diff --git a/TESTS/mbed_hal/flash/functional_tests/main.cpp b/TESTS/mbed_hal/flash/functional_tests/main.cpp index c8bb7fdd105..d9b4b0121c8 100644 --- a/TESTS/mbed_hal/flash/functional_tests/main.cpp +++ b/TESTS/mbed_hal/flash/functional_tests/main.cpp @@ -49,6 +49,7 @@ static void erase_range(flash_t *flash, uint32_t addr, uint32_t size) TEST_ASSERT_NOT_EQUAL(0, sector_size); int32_t ret = flash_erase_sector(flash, addr); TEST_ASSERT_EQUAL_INT32(0, ret); + addr += sector_size; size = size > sector_size ? size - sector_size : 0; } } diff --git a/drivers/I2C.h b/drivers/I2C.h index 84f1d89880d..69561dd0399 100644 --- a/drivers/I2C.h +++ b/drivers/I2C.h @@ -117,8 +117,8 @@ class I2C { * @param repeated Repeated start, true - do not send stop at end * * @returns - * 0 or non-zero - written number of bytes, - * negative - I2C_ERROR_XXX status + * 0 on success (ack), + * non-0 on failure (nack) */ int write(int address, const char *data, int length, bool repeated = false); diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md b/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md index b2e282fe540..9b2c59ed471 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md +++ b/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md @@ -1,5 +1,17 @@ # Change Log +## [v4.0.3](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.0.3) + +-[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.0.2...v4.0.3) + + **New feature** + + - CoAP Protocol Confirmable resend fix and minor memory optimization (IOTMAC-328) + + **Closed issues:** + + - IOTCLT-1439 - stuck in while loop + ## [v4.0.0](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.0.2) **New feature** diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h b/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h index 2fee18e1c8d..b9fbdc63ac0 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h +++ b/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h @@ -83,7 +83,8 @@ extern int8_t sn_coap_protocol_destroy(struct coap_s *handle); * In failure cases:\n * -1 = Failure in CoAP header structure\n * -2 = Failure in given pointer (= NULL)\n - * -3 = Failure in Reset message\ŋ + * -3 = Failure in Reset message\n + * -4 = Failure in Resending message store\n * If there is not enough memory (or User given limit exceeded) for storing * resending messages, situation is ignored. */ diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/module.json b/features/FEATURE_COMMON_PAL/mbed-coap/module.json index c03d51e4cf3..b581d6bac6f 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/module.json +++ b/features/FEATURE_COMMON_PAL/mbed-coap/module.json @@ -1,6 +1,6 @@ { "name": "mbed-coap", - "version": "4.0.2", + "version": "4.0.3", "description": "COAP library", "keywords": [ "coap", diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_header_internal.h b/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_header_internal.h index 0a6d5936cb5..f00dd7d7cd8 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_header_internal.h +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_header_internal.h @@ -64,8 +64,6 @@ typedef struct sn_nsdl_transmit_ { uint16_t packet_len; uint8_t *packet_ptr; - uint8_t *uri_path_ptr; - uint8_t uri_path_len; } sn_nsdl_transmit_s; /* * * * * * * * * * * * * * * * * * * * * * */ diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_builder.c b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_builder.c index 5a530122a48..0901fd00861 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_builder.c +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_builder.c @@ -174,21 +174,16 @@ uint16_t sn_coap_builder_calc_needed_packet_data_size_2(sn_coap_hdr_s *src_coap_ returned_byte_count += src_coap_msg_ptr->token_len; } /* URI PATH - Repeatable option. Length of one option is 0-255 */ - /* Do not add uri-path for notification message. - * Uri-path is needed for cancelling observation with RESET message */ - if (!src_coap_msg_ptr->options_list_ptr || - (src_coap_msg_ptr->options_list_ptr && - COAP_OBSERVE_NONE == src_coap_msg_ptr->options_list_ptr->observe)) { - if (src_coap_msg_ptr->uri_path_ptr != NULL) { - repeatable_option_size = sn_coap_builder_options_calc_option_size(src_coap_msg_ptr->uri_path_len, - src_coap_msg_ptr->uri_path_ptr, COAP_OPTION_URI_PATH); - if (repeatable_option_size) { - returned_byte_count += repeatable_option_size; - } else { - return 0; - } + if (src_coap_msg_ptr->uri_path_ptr != NULL) { + repeatable_option_size = sn_coap_builder_options_calc_option_size(src_coap_msg_ptr->uri_path_len, + src_coap_msg_ptr->uri_path_ptr, COAP_OPTION_URI_PATH); + if (repeatable_option_size) { + returned_byte_count += repeatable_option_size; + } else { + return 0; } } + uint16_t tempInt = 0; /* CONTENT FORMAT - An integer option, up to 2 bytes */ if (src_coap_msg_ptr->content_format != COAP_CT_NONE) { @@ -574,13 +569,8 @@ static int8_t sn_coap_builder_options_build(uint8_t **dst_packet_data_pptr, sn_c &src_coap_msg_ptr->options_list_ptr->location_path_len, COAP_OPTION_LOCATION_PATH, &previous_option_number); } /* * * * Build Uri-Path option * * * */ - /* Do not add uri-path for notification message. - * Uri-path is needed for cancelling observation with RESET message */ - if (!src_coap_msg_ptr->options_list_ptr || - (src_coap_msg_ptr->options_list_ptr && - COAP_OBSERVE_NONE == src_coap_msg_ptr->options_list_ptr->observe)) - sn_coap_builder_options_build_add_multiple_option(dst_packet_data_pptr, &src_coap_msg_ptr->uri_path_ptr, - &src_coap_msg_ptr->uri_path_len, COAP_OPTION_URI_PATH, &previous_option_number); + sn_coap_builder_options_build_add_multiple_option(dst_packet_data_pptr, &src_coap_msg_ptr->uri_path_ptr, + &src_coap_msg_ptr->uri_path_len, COAP_OPTION_URI_PATH, &previous_option_number); /* * * * Build Content-Type option * * * */ if (src_coap_msg_ptr->content_format != COAP_CT_NONE) { diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_parser.c b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_parser.c index 6ec7c68de49..8f63f736d70 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_parser.c +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_parser.c @@ -35,7 +35,6 @@ #include "mbed-coap/sn_coap_protocol.h" #include "sn_coap_header_internal.h" #include "sn_coap_protocol_internal.h" - /* * * * * * * * * * * * * * * * * * * * */ /* * * * LOCAL FUNCTION PROTOTYPES * * * */ /* * * * * * * * * * * * * * * * * * * * */ @@ -315,6 +314,7 @@ static int8_t sn_coap_parser_options_parse(struct coap_s *handle, uint8_t **pack (*packet_data_pptr) += 2; } + message_left = packet_len - (*packet_data_pptr - packet_data_start_ptr); /* * * Parse option itself * * */ /* Some options are handled independently in own functions */ @@ -655,7 +655,7 @@ static int16_t sn_coap_parser_options_count_needed_memory_multiple_option(uint8_ uint16_t i = 1; /* Loop all Uri-Query options */ - while (i < packet_left_len) { + while (i <= packet_left_len) { if (option == COAP_OPTION_LOCATION_PATH && option_number_len > 255) { return -1; } @@ -677,14 +677,13 @@ static int16_t sn_coap_parser_options_count_needed_memory_multiple_option(uint8_ i += option_number_len; ret_value += option_number_len + 1; /* + 1 is for separator */ - if(ret_value >= packet_left_len) - break; - - if(ret_value >= packet_left_len) - break; - if( i == packet_left_len ) + if( i == packet_left_len ) { break; + } + else if( i > packet_left_len ) { + return -1; + } if ((*(packet_data_ptr + i) >> COAP_OPTIONS_OPTION_NUMBER_SHIFT) != 0) { return (ret_value - 1); /* -1 because last Part path does not include separator */ @@ -693,9 +692,19 @@ static int16_t sn_coap_parser_options_count_needed_memory_multiple_option(uint8_ option_number_len = (*(packet_data_ptr + i) & 0x0F); if (option_number_len == 13) { + + if(i + 1 >= packet_left_len) { + return -1; + } + i++; option_number_len = *(packet_data_ptr + i) + 13; } else if (option_number_len == 14) { + + if(i + 2 >= packet_left_len) { + return -1; + } + option_number_len = *(packet_data_ptr + i + 2); option_number_len += (*(packet_data_ptr + i + 1) << 8) + 269; i += 2; @@ -750,3 +759,4 @@ static int8_t sn_coap_parser_payload_parse(uint16_t packet_data_len, uint8_t *pa } return 0; } + diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c index 0612d16b25c..2df34e3dd36 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c @@ -67,7 +67,7 @@ static int8_t sn_coap_convert_block_size(uint16_t block_size); static sn_coap_hdr_s *sn_coap_protocol_copy_header(struct coap_s *handle, sn_coap_hdr_s *source_header_ptr); #endif #if ENABLE_RESENDINGS -static void sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, uint8_t *send_packet_data_ptr, uint32_t sending_time, void *param, uint8_t *uri_path_ptr, uint8_t uri_path_len); +static uint8_t sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, uint8_t *send_packet_data_ptr, uint32_t sending_time, void *param); static sn_nsdl_transmit_s *sn_coap_protocol_linked_list_send_msg_search(struct coap_s *handle,sn_nsdl_addr_s *src_addr_ptr, uint16_t msg_id); static void sn_coap_protocol_linked_list_send_msg_remove(struct coap_s *handle, sn_nsdl_addr_s *src_addr_ptr, uint16_t msg_id); static coap_send_msg_s *sn_coap_protocol_allocate_mem_for_msg(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t packet_data_len); @@ -300,30 +300,9 @@ void sn_coap_protocol_clear_retransmission_buffer(struct coap_s *handle) return; } ns_list_foreach_safe(coap_send_msg_s, tmp, &handle->linked_list_resent_msgs) { - if (tmp->send_msg_ptr) { - if (tmp->send_msg_ptr->dst_addr_ptr) { - if (tmp->send_msg_ptr->dst_addr_ptr->addr_ptr) { - handle->sn_coap_protocol_free(tmp->send_msg_ptr->dst_addr_ptr->addr_ptr); - tmp->send_msg_ptr->dst_addr_ptr->addr_ptr = 0; - } - handle->sn_coap_protocol_free(tmp->send_msg_ptr->dst_addr_ptr); - tmp->send_msg_ptr->dst_addr_ptr = 0; - } - if (tmp->send_msg_ptr->packet_ptr) { - handle->sn_coap_protocol_free(tmp->send_msg_ptr->packet_ptr); - tmp->send_msg_ptr->packet_ptr = 0; - } - if (tmp->send_msg_ptr->uri_path_ptr) { - handle->sn_coap_protocol_free(tmp->send_msg_ptr->uri_path_ptr); - tmp->send_msg_ptr->uri_path_ptr = 0; - } - handle->sn_coap_protocol_free(tmp->send_msg_ptr); - tmp->send_msg_ptr = 0; - } ns_list_remove(&handle->linked_list_resent_msgs, tmp); + sn_coap_protocol_release_allocated_send_msg_mem(handle, tmp); --handle->count_resent_msgs; - handle->sn_coap_protocol_free(tmp); - tmp = 0; } #endif } @@ -445,9 +424,11 @@ int16_t sn_coap_protocol_build(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_p /* Check if built Message type was confirmable, only these messages are resent */ if (src_coap_msg_ptr->msg_type == COAP_MSG_TYPE_CONFIRMABLE) { /* Store message to Linked list for resending purposes */ - sn_coap_protocol_linked_list_send_msg_store(handle, dst_addr_ptr, byte_count_built, dst_packet_data_ptr, + if (sn_coap_protocol_linked_list_send_msg_store(handle, dst_addr_ptr, byte_count_built, dst_packet_data_ptr, handle->system_time + (uint32_t)(handle->sn_coap_resending_intervall * RESPONSE_RANDOM_FACTOR), - param, src_coap_msg_ptr->uri_path_ptr, src_coap_msg_ptr->uri_path_len); + param) == 0) { + return -4; + } } #endif /* ENABLE_RESENDINGS */ @@ -702,15 +683,6 @@ sn_coap_hdr_s *sn_coap_protocol_parse(struct coap_s *handle, sn_nsdl_addr_s *src removed_msg_ptr = sn_coap_protocol_linked_list_send_msg_search(handle, src_addr_ptr, returned_dst_coap_msg_ptr->msg_id); if (removed_msg_ptr != NULL) { - if (returned_dst_coap_msg_ptr->msg_type == COAP_MSG_TYPE_RESET) { - if(removed_msg_ptr->uri_path_len) { - returned_dst_coap_msg_ptr->uri_path_ptr = handle->sn_coap_protocol_malloc(removed_msg_ptr->uri_path_len); - if (returned_dst_coap_msg_ptr->uri_path_ptr != NULL) { - memcpy(returned_dst_coap_msg_ptr->uri_path_ptr, removed_msg_ptr->uri_path_ptr, removed_msg_ptr->uri_path_len); - returned_dst_coap_msg_ptr->uri_path_len = removed_msg_ptr->uri_path_len; - } - } - } /* Remove resending message from active message resending Linked list */ sn_coap_protocol_linked_list_send_msg_remove(handle, src_addr_ptr, returned_dst_coap_msg_ptr->msg_id); } @@ -799,7 +771,7 @@ int8_t sn_coap_protocol_exec(struct coap_s *handle, uint32_t current_time) #if ENABLE_RESENDINGS /* If Message resending is not used at all, this part of code will not be compiled */ /**************************************************************************//** - * \fn static void sn_coap_protocol_linked_list_send_msg_store(sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, uint8_t *send_packet_data_ptr, uint32_t sending_time) + * \fn static uint8_t sn_coap_protocol_linked_list_send_msg_store(sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, uint8_t *send_packet_data_ptr, uint32_t sending_time) * * \brief Stores message to Linked list for sending purposes. @@ -810,29 +782,33 @@ int8_t sn_coap_protocol_exec(struct coap_s *handle, uint32_t current_time) * \param *send_packet_data_ptr is Packet data to be stored * * \param sending_time is stored sending time + * + * \return 0 Allocation or buffer limit reached + * + * \return 1 Msg stored properly *****************************************************************************/ -static void sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, - uint8_t *send_packet_data_ptr, uint32_t sending_time, void *param, uint8_t *uri_path_ptr, uint8_t uri_path_len) +static uint8_t sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, + uint8_t *send_packet_data_ptr, uint32_t sending_time, void *param) { coap_send_msg_s *stored_msg_ptr = NULL; /* If both queue parameters are "0" or resending count is "0", then re-sending is disabled */ if (((handle->sn_coap_resending_queue_msgs == 0) && (handle->sn_coap_resending_queue_bytes == 0)) || (handle->sn_coap_resending_count == 0)) { - return; + return 1; } if (handle->sn_coap_resending_queue_msgs > 0) { if (handle->count_resent_msgs >= handle->sn_coap_resending_queue_msgs) { - return; + return 0; } } /* Count resending queue size, if buffer size is defined */ if (handle->sn_coap_resending_queue_bytes > 0) { if ((sn_coap_count_linked_list_size(&handle->linked_list_resent_msgs) + send_packet_data_len) > handle->sn_coap_resending_queue_bytes) { - return; + return 0; } } @@ -840,7 +816,7 @@ static void sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, s stored_msg_ptr = sn_coap_protocol_allocate_mem_for_msg(handle, dst_addr_ptr, send_packet_data_len); if (stored_msg_ptr == 0) { - return; + return 0; } /* Filling of coap_send_msg_s with initialization values */ @@ -861,19 +837,10 @@ static void sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, s stored_msg_ptr->coap = handle; stored_msg_ptr->param = param; - if (uri_path_len) { - stored_msg_ptr->send_msg_ptr->uri_path_ptr = handle->sn_coap_protocol_malloc(uri_path_len); - if (stored_msg_ptr->send_msg_ptr->uri_path_ptr == NULL){ - return; - } - stored_msg_ptr->send_msg_ptr->uri_path_len = uri_path_len; - memcpy(stored_msg_ptr->send_msg_ptr->uri_path_ptr, uri_path_ptr, uri_path_len); - } - - /* Storing Resending message to Linked list */ ns_list_add_to_end(&handle->linked_list_resent_msgs, stored_msg_ptr); ++handle->count_resent_msgs; + return 1; } /**************************************************************************//** @@ -1367,6 +1334,7 @@ static void sn_coap_protocol_linked_list_blockwise_remove_old_data(struct coap_s * * \param *dst_addr_ptr is pointer to destination address where message will be sent * \param packet_data_len is length of allocated Packet data + * \param uri_path_len is length of messages path url * * \return pointer to allocated struct *****************************************************************************/ @@ -1377,45 +1345,35 @@ coap_send_msg_s *sn_coap_protocol_allocate_mem_for_msg(struct coap_s *handle, sn coap_send_msg_s *msg_ptr = handle->sn_coap_protocol_malloc(sizeof(coap_send_msg_s)); if (msg_ptr == NULL) { - return 0; - } - - memset(msg_ptr, 0, sizeof(coap_send_msg_s)); - - msg_ptr->send_msg_ptr = handle->sn_coap_protocol_malloc(sizeof(sn_nsdl_transmit_s)); - - if (msg_ptr->send_msg_ptr == NULL) { - sn_coap_protocol_release_allocated_send_msg_mem(handle, msg_ptr); - return 0; - } - - memset(msg_ptr->send_msg_ptr, 0 , sizeof(sn_nsdl_transmit_s)); - - msg_ptr->send_msg_ptr->dst_addr_ptr = handle->sn_coap_protocol_malloc(sizeof(sn_nsdl_addr_s)); - - if (msg_ptr->send_msg_ptr->dst_addr_ptr == NULL) { - sn_coap_protocol_release_allocated_send_msg_mem(handle, msg_ptr); - return 0; + return NULL; } - memset(msg_ptr->send_msg_ptr->dst_addr_ptr, 0, sizeof(sn_nsdl_addr_s)); + //Locall structure for 1 malloc for send msg + struct + { + sn_nsdl_transmit_s transmit; + sn_nsdl_addr_s addr; + uint8_t trail_data[]; + } *m; + int trail_size = dst_addr_ptr->addr_len + packet_data_len; - msg_ptr->send_msg_ptr->packet_ptr = handle->sn_coap_protocol_malloc(packet_data_len); - - if (msg_ptr->send_msg_ptr->packet_ptr == NULL) { - sn_coap_protocol_release_allocated_send_msg_mem(handle, msg_ptr); - return 0; + m = handle->sn_coap_protocol_malloc(sizeof *m + trail_size); + if (!m) { + handle->sn_coap_protocol_free(msg_ptr); + return NULL; } + //Init data + memset(m, 0, sizeof(*m) + trail_size); + memset(msg_ptr, 0, sizeof(coap_send_msg_s)); - msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr = handle->sn_coap_protocol_malloc(dst_addr_ptr->addr_len); + msg_ptr->send_msg_ptr = &m->transmit; + msg_ptr->send_msg_ptr->dst_addr_ptr = &m->addr; - if (msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr == NULL) { - sn_coap_protocol_release_allocated_send_msg_mem(handle, msg_ptr); - return 0; + msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr = m->trail_data; + if (packet_data_len) { + msg_ptr->send_msg_ptr->packet_ptr = m->trail_data + dst_addr_ptr->addr_len; } - memset(msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr, 0, dst_addr_ptr->addr_len); - return msg_ptr; } @@ -1431,33 +1389,10 @@ coap_send_msg_s *sn_coap_protocol_allocate_mem_for_msg(struct coap_s *handle, sn static void sn_coap_protocol_release_allocated_send_msg_mem(struct coap_s *handle, coap_send_msg_s *freed_send_msg_ptr) { if (freed_send_msg_ptr != NULL) { - if (freed_send_msg_ptr->send_msg_ptr != NULL) { - if (freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr != NULL) { - if (freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr != NULL) { - handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr); - freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr = 0; - } - - handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr); - freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr = 0; - } - - if (freed_send_msg_ptr->send_msg_ptr->packet_ptr != NULL) { - handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr->packet_ptr); - freed_send_msg_ptr->send_msg_ptr->packet_ptr = 0; - } - - if (freed_send_msg_ptr->send_msg_ptr->uri_path_ptr != NULL) { - handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr->uri_path_ptr); - freed_send_msg_ptr->send_msg_ptr->uri_path_ptr = 0; - } - - handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr); - freed_send_msg_ptr->send_msg_ptr = 0; - } - + handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr); + freed_send_msg_ptr->send_msg_ptr = NULL; handle->sn_coap_protocol_free(freed_send_msg_ptr); - freed_send_msg_ptr = 0; + freed_send_msg_ptr = NULL; } } @@ -1877,7 +1812,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn sn_coap_protocol_linked_list_send_msg_store(handle, src_addr_ptr, dst_packed_data_needed_mem, dst_ack_packet_data_ptr, - handle->system_time + (uint32_t)(handle->sn_coap_resending_intervall * RESPONSE_RANDOM_FACTOR), param, NULL, 0); + handle->system_time + (uint32_t)(handle->sn_coap_resending_intervall * RESPONSE_RANDOM_FACTOR), param); #endif handle->sn_coap_protocol_free(dst_ack_packet_data_ptr); dst_ack_packet_data_ptr = 0; diff --git a/features/FEATURE_COMMON_PAL/mbed-trace/.yotta_ignore b/features/FEATURE_COMMON_PAL/mbed-trace/.yotta_ignore index e69de29bb2d..cc6371fe0cb 100644 --- a/features/FEATURE_COMMON_PAL/mbed-trace/.yotta_ignore +++ b/features/FEATURE_COMMON_PAL/mbed-trace/.yotta_ignore @@ -0,0 +1 @@ +/*CMakeLists.txt diff --git a/features/FEATURE_COMMON_PAL/mbed-trace/CMakeLists.txt b/features/FEATURE_COMMON_PAL/mbed-trace/CMakeLists.txt new file mode 100755 index 00000000000..84a887c547f --- /dev/null +++ b/features/FEATURE_COMMON_PAL/mbed-trace/CMakeLists.txt @@ -0,0 +1,17 @@ +INCLUDE(CMakeForceCompiler) + +cmake_minimum_required (VERSION 2.8) +SET(CMAKE_SYSTEM_NAME Generic) + +project(mbedTrace) + + +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/mbed-trace/) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../nanostack-libservice/mbed-client-libservice/) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../nanostack-libservice/) + +set (MBED_TRACE_SRC ${CMAKE_CURRENT_SOURCE_DIR}/source/mbed_trace.c) + + +CREATE_LIBRARY(mbedTrace "${MBED_TRACE_SRC}" "") + diff --git a/features/FEATURE_COMMON_PAL/mbed-trace/README.md b/features/FEATURE_COMMON_PAL/mbed-trace/README.md index 695b65795ec..b719ed83a0c 100644 --- a/features/FEATURE_COMMON_PAL/mbed-trace/README.md +++ b/features/FEATURE_COMMON_PAL/mbed-trace/README.md @@ -33,9 +33,9 @@ The purpose of the library is to provide a light, simple and general tracing sol ``` [DBG ][abc ]: This is a debug message from module abc -[ERR ][abc ]: Something goes wrong in module abc -[WARN][br ]: Oh no, br warning occurs! [INFO][br ]: Hi there. +[WARN][br ]: Oh no, br warning occurs! +[ERR ][abc ]: Something goes wrong in module abc ``` ## Usage @@ -47,8 +47,10 @@ The purpose of the library is to provide a light, simple and general tracing sol * To enable the tracing API: * With yotta: set `YOTTA_CFG_MBED_TRACE` to 1 or true. Setting the flag to 0 or false disables tracing. * [With mbed OS 5](#enabling-the-tracing-api-in-mbed-os-5) -* By default, trace uses 1024 bytes buffer for trace lines, but you can change it by yotta with: `YOTTA_CFG_MBED_TRACE_LINE_LENGTH`. -* To disable the IPv6 conversion, set `YOTTA_CFG_MBED_TRACE_FEA_IPV6 = 0`. +* By default, trace uses 1024 bytes buffer for trace lines, but you can change it by setting the configuration macro `MBED_TRACE_LINE_LENGTH` to the desired value. +* To disable the IPv6 conversion: + * With yotta: set `YOTTA_CFG_MBED_TRACE_FEA_IPV6 = 0`. + * With mbed OS 5: set `MBED_CONF_MBED_TRACE_FEA_IPV6 = 0`. * If thread safety is needed, configure the wait and release callback functions before initialization to enable the protection. Usually, this needs to be done only once in the application's lifetime. * Call the trace initialization (`mbed_trace_init`) once before using any other APIs. It allocates the trace buffer and initializes the internal variables. * Define `TRACE_GROUP` in your source code (not in the header!) to use traces. It is a 1-4 characters long char-array (for example `#define TRACE_GROUP "APPL"`). This will be printed on every trace line. @@ -82,9 +84,9 @@ When you want to print traces, use the `tr_` macros. The macros behave li Available levels: * debug +* info * warning * error -* info * cmdline (special behavior, should not be used) For the thread safety, set the mutex wait and release functions. You need do this before the initialization to have the functions available right away: @@ -128,7 +130,7 @@ See more in [mbed_trace.h](https://github.com/ARMmbed/mbed-trace/blob/master/mbe ## Usage example: ```c++ -#define YOTTA_CFG_MBED_TRACE 1 //this can be defined also in the yotta configuration file config.json +#define MBED_CONF_MBED_TRACE_ENABLE 1 //this could be defined also in the mbed-cli configuration file mbed_app.json #include "mbed-trace/mbed_trace.h" #define TRACE_GROUP "main" @@ -148,9 +150,9 @@ int main(void){ mbed_trace_mutex_release_function_set( my_mutex_release ); // only if thread safety is needed mbed_trace_init(); // initialize the trace library tr_debug("this is debug msg"); //-> "[DBG ][main]: this is a debug msg" - tr_err("this is error msg"); //-> "[ERR ][main]: this is an error msg" - tr_warn("this is warning msg"); //-> "[WARN][main]: this is a warning msg" tr_info("this is info msg"); //-> "[INFO][main]: this is an info msg" + tr_warn("this is warning msg"); //-> "[WARN][main]: this is a warning msg" + tr_err("this is error msg"); //-> "[ERR ][main]: this is an error msg" char arr[] = {30, 31, 32}; tr_debug("printing array: %s", mbed_trace_array(arr, 3)); //-> "[DBG ][main]: printing array: 01:02:03" return 0; diff --git a/features/FEATURE_COMMON_PAL/mbed-trace/mbed-trace/mbed_trace.h b/features/FEATURE_COMMON_PAL/mbed-trace/mbed-trace/mbed_trace.h index 61aeb4d5e05..6309055ae72 100644 --- a/features/FEATURE_COMMON_PAL/mbed-trace/mbed-trace/mbed_trace.h +++ b/features/FEATURE_COMMON_PAL/mbed-trace/mbed-trace/mbed_trace.h @@ -18,8 +18,8 @@ * \file mbed_trace.h * Trace interface for MbedOS applications. * This file provide simple but flexible way to handle software traces. - * Trace library are abstract layer, which use stdout (printf) by default, - * but outputs can be easily redirect to custom function, for example to + * Trace library are abstract layer, which use stdout (printf) by default, + * but outputs can be easily redirect to custom function, for example to * store traces to memory or other interfaces. * * usage example: @@ -30,14 +30,15 @@ * int main(void){ * mbed_trace_init(); // initialize trace library * tr_debug("this is debug msg"); //print debug message to stdout: "[DBG] - * tr_err("this is error msg"); - * tr_warn("this is warning msg"); * tr_info("this is info msg"); + * tr_warn("this is warning msg"); + * tr_err("this is error msg"); * return 0; * } * \endcode * Activate with compiler flag: YOTTA_CFG_MBED_TRACE * Configure trace line buffer size with compiler flag: YOTTA_CFG_MBED_TRACE_LINE_LENGTH. Default length: 1024. + * Limit the size of flash by setting MBED_TRACE_MAX_LEVEL value. Default is TRACE_LEVEL_DEBUG (all included) * */ #ifndef MBED_TRACE_H_ @@ -63,12 +64,19 @@ extern "C" { #ifndef YOTTA_CFG_MBED_TRACE_FEA_IPV6 #define YOTTA_CFG_MBED_TRACE_FEA_IPV6 1 +#else +#warning YOTTA_CFG_MBED_TRACE_FEA_IPV6 is deprecated and will be removed in the future! Use MBED_CONF_MBED_TRACE_FEA_IPV6 instead. +#define MBED_CONF_MBED_TRACE_FEA_IPV6 YOTTA_CFG_MBED_TRACE_FEA_IPV6 #endif #ifndef MBED_CONF_MBED_TRACE_ENABLE #define MBED_CONF_MBED_TRACE_ENABLE 0 #endif +#ifndef MBED_CONF_MBED_TRACE_FEA_IPV6 +#define MBED_CONF_MBED_TRACE_FEA_IPV6 1 +#endif + /** 3 upper bits are trace modes related, and 5 lower bits are trace level configuration */ @@ -110,13 +118,39 @@ extern "C" { /** special level for cmdline. Behaviours like "plain mode" */ #define TRACE_LEVEL_CMD 0x01 +#ifndef MBED_TRACE_MAX_LEVEL +#define MBED_TRACE_MAX_LEVEL TRACE_LEVEL_DEBUG +#endif + //usage macros: -#define tr_info(...) mbed_tracef(TRACE_LEVEL_INFO, TRACE_GROUP, __VA_ARGS__) //!< Print info message +#if MBED_TRACE_MAX_LEVEL >= TRACE_LEVEL_DEBUG #define tr_debug(...) mbed_tracef(TRACE_LEVEL_DEBUG, TRACE_GROUP, __VA_ARGS__) //!< Print debug message +#else +#define tr_debug(...) +#endif + +#if MBED_TRACE_MAX_LEVEL >= TRACE_LEVEL_INFO +#define tr_info(...) mbed_tracef(TRACE_LEVEL_INFO, TRACE_GROUP, __VA_ARGS__) //!< Print info message +#else +#define tr_info(...) +#endif + +#if MBED_TRACE_MAX_LEVEL >= TRACE_LEVEL_WARN #define tr_warning(...) mbed_tracef(TRACE_LEVEL_WARN, TRACE_GROUP, __VA_ARGS__) //!< Print warning message #define tr_warn(...) mbed_tracef(TRACE_LEVEL_WARN, TRACE_GROUP, __VA_ARGS__) //!< Alternative warning message +#else +#define tr_warning(...) +#define tr_warn(...) +#endif + +#if MBED_TRACE_MAX_LEVEL >= TRACE_LEVEL_ERROR #define tr_error(...) mbed_tracef(TRACE_LEVEL_ERROR, TRACE_GROUP, __VA_ARGS__) //!< Print Error Message #define tr_err(...) mbed_tracef(TRACE_LEVEL_ERROR, TRACE_GROUP, __VA_ARGS__) //!< Alternative error message +#else +#define tr_error(...) +#define tr_err(...) +#endif + #define tr_cmdline(...) mbed_tracef(TRACE_LEVEL_CMD, TRACE_GROUP, __VA_ARGS__) //!< Special print for cmdline. See more from TRACE_LEVEL_CMD -level //aliases for the most commonly used functions and the helper functions @@ -180,7 +214,7 @@ void mbed_trace_buffer_sizes(int lineLength, int tmpLength); * @endcode */ void mbed_trace_config_set(uint8_t config); -/** get trace configurations +/** get trace configurations * @return trace configuration byte */ uint8_t mbed_trace_config_get(void); @@ -232,7 +266,7 @@ void mbed_trace_mutex_release_function_set(void (*mutex_release_f)(void)); /** * When trace group contains text in filters, * trace print will be ignored. - * e.g.: + * e.g.: * mbed_trace_exclude_filters_set("mygr"); * mbed_tracef(TRACE_ACTIVE_LEVEL_DEBUG, "ougr", "This is not printed"); */ @@ -294,7 +328,7 @@ void mbed_vtracef(uint8_t dlevel, const char* grp, const char *fmt, va_list ap); * Get last trace from buffer */ const char* mbed_trace_last(void); -#if YOTTA_CFG_MBED_TRACE_FEA_IPV6 == 1 +#if MBED_CONF_MBED_TRACE_FEA_IPV6 == 1 /** * mbed_tracef helping function for convert ipv6 * table to human readable string. @@ -327,7 +361,7 @@ char* mbed_trace_ipv6_prefix(const uint8_t *prefix, uint8_t prefix_len); * @param buf hex array pointer * @param len buffer length * @return temporary buffer where string copied - * if array as string not fit to temp buffer, this function write '*' as last character, + * if array as string not fit to temp buffer, this function write '*' as last character, * which indicate that buffer is too small for array. */ char* mbed_trace_array(const uint8_t* buf, uint16_t len); diff --git a/features/FEATURE_COMMON_PAL/mbed-trace/mbed_lib.json b/features/FEATURE_COMMON_PAL/mbed-trace/mbed_lib.json index 568cb0d4dfe..f51343717f4 100644 --- a/features/FEATURE_COMMON_PAL/mbed-trace/mbed_lib.json +++ b/features/FEATURE_COMMON_PAL/mbed-trace/mbed_lib.json @@ -4,6 +4,11 @@ "enable": { "help": "Used to globally enable traces.", "value": null + }, + "fea-ipv6": { + "help": "Used to globally disable ipv6 tracing features.", + "value": null } + } } \ No newline at end of file diff --git a/features/FEATURE_COMMON_PAL/mbed-trace/source/mbed_trace.c b/features/FEATURE_COMMON_PAL/mbed-trace/source/mbed_trace.c index 31cd66dfa60..9f648415aa8 100644 --- a/features/FEATURE_COMMON_PAL/mbed-trace/source/mbed_trace.c +++ b/features/FEATURE_COMMON_PAL/mbed-trace/source/mbed_trace.c @@ -17,13 +17,16 @@ #include #include -#ifndef YOTTA_CFG_MBED_TRACE -#define YOTTA_CFG_MBED_TRACE 1 -#define YOTTA_CFG_MBED_TRACE_FEA_IPV6 1 +#ifdef MBED_CONF_MBED_TRACE_ENABLE +#undef MBED_CONF_MBED_TRACE_ENABLE +#endif +#define MBED_CONF_MBED_TRACE_ENABLE 1 +#ifndef MBED_CONF_MBED_TRACE_FEA_IPV6 +#define MBED_CONF_MBED_TRACE_FEA_IPV6 1 #endif #include "mbed-trace/mbed_trace.h" -#if YOTTA_CFG_MBED_TRACE_FEA_IPV6 == 1 +#if MBED_CONF_MBED_TRACE_FEA_IPV6 == 1 #include "mbed-client-libservice/ip6string.h" #include "mbed-client-libservice/common_functions.h" #endif @@ -52,23 +55,42 @@ #define VT100_COLOR_DEBUG "\x1b[90m" /** default max trace line size in bytes */ -#ifdef YOTTA_CFG_MBED_TRACE_LINE_LENGTH +#ifdef MBED_TRACE_LINE_LENGTH +#define DEFAULT_TRACE_LINE_LENGTH MBED_TRACE_LINE_LENGTH +#elif defined YOTTA_CFG_MBED_TRACE_LINE_LENGTH +#warning YOTTA_CFG_MBED_TRACE_LINE_LENGTH is deprecated and will be removed in the future! Use MBED_TRACE_LINE_LENGTH instead. #define DEFAULT_TRACE_LINE_LENGTH YOTTA_CFG_MBED_TRACE_LINE_LENGTH #else #define DEFAULT_TRACE_LINE_LENGTH 1024 #endif + /** default max temporary buffer size in bytes, used in trace_ipv6, trace_ipv6_prefix and trace_array */ -#ifdef YOTTA_CFG_MBED_TRACE_TMP_LINE_LEN +#ifdef MBED_TRACE_TMP_LINE_LENGTH +#define DEFAULT_TRACE_TMP_LINE_LEN MBED_TRACE_TMP_LINE_LENGTH +#elif defined YOTTA_CFG_MBED_TRACE_TMP_LINE_LEN +#warning The YOTTA_CFG_MBED_TRACE_TMP_LINE_LEN flag is deprecated and will be removed in the future! Use MBED_TRACE_TMP_LINE_LENGTH instead. #define DEFAULT_TRACE_TMP_LINE_LEN YOTTA_CFG_MBED_TRACE_TMP_LINE_LEN #elif defined YOTTA_CFG_MTRACE_TMP_LINE_LEN -#warning The YOTTA_CFG_MTRACE_TMP_LINE_LEN flag is deprecated! Use YOTTA_CFG_MBED_TRACE_TMP_LINE_LEN instead. +#warning The YOTTA_CFG_MTRACE_TMP_LINE_LEN flag is deprecated and will be removed in the future! Use MBED_TRACE_TMP_LINE_LENGTH instead. #define DEFAULT_TRACE_TMP_LINE_LEN YOTTA_CFG_MTRACE_TMP_LINE_LEN #else #define DEFAULT_TRACE_TMP_LINE_LEN 128 #endif + /** default max filters (include/exclude) length in bytes */ +#ifdef MBED_TRACE_FILTER_LENGTH +#define DEFAULT_TRACE_FILTER_LENGTH MBED_TRACE_FILTER_LENGTH +#else #define DEFAULT_TRACE_FILTER_LENGTH 24 +#endif + +/** default trace configuration bitmask */ +#ifdef MBED_TRACE_CONFIG +#define DEFAULT_TRACE_CONFIG MBED_TRACE_CONFIG +#else +#define DEFAULT_TRACE_CONFIG TRACE_MODE_COLOR | TRACE_ACTIVE_LEVEL_ALL | TRACE_CARRIAGE_RETURN +#endif /** default print function, just redirect str to printf */ static void mbed_trace_realloc( char **buffer, int *length_ptr, int new_length); @@ -112,13 +134,17 @@ typedef struct trace_s { } trace_t; static trace_t m_trace = { + .trace_config = DEFAULT_TRACE_CONFIG, .filters_exclude = 0, .filters_include = 0, + .filters_length = DEFAULT_TRACE_FILTER_LENGTH, .line = 0, + .line_length = DEFAULT_TRACE_LINE_LENGTH, .tmp_data = 0, + .tmp_data_length = DEFAULT_TRACE_TMP_LINE_LEN, .prefix_f = 0, .suffix_f = 0, - .printf = 0, + .printf = mbed_trace_default_print, .cmd_printf = 0, .mutex_wait_f = 0, .mutex_release_f = 0, @@ -127,17 +153,15 @@ static trace_t m_trace = { int mbed_trace_init(void) { - m_trace.trace_config = TRACE_MODE_COLOR | TRACE_ACTIVE_LEVEL_ALL | TRACE_CARRIAGE_RETURN; - m_trace.line_length = DEFAULT_TRACE_LINE_LENGTH; if (m_trace.line == NULL) { m_trace.line = MBED_TRACE_MEM_ALLOC(m_trace.line_length); } - m_trace.tmp_data_length = DEFAULT_TRACE_TMP_LINE_LEN; + if (m_trace.tmp_data == NULL) { m_trace.tmp_data = MBED_TRACE_MEM_ALLOC(m_trace.tmp_data_length); } m_trace.tmp_data_ptr = m_trace.tmp_data; - m_trace.filters_length = DEFAULT_TRACE_FILTER_LENGTH; + if (m_trace.filters_exclude == NULL) { m_trace.filters_exclude = MBED_TRACE_MEM_ALLOC(m_trace.filters_length); } @@ -158,29 +182,28 @@ int mbed_trace_init(void) memset(m_trace.filters_include, 0, m_trace.filters_length); memset(m_trace.line, 0, m_trace.line_length); - m_trace.prefix_f = 0; - m_trace.suffix_f = 0; - m_trace.printf = mbed_trace_default_print; - m_trace.cmd_printf = 0; - return 0; } void mbed_trace_free(void) { + // release memory MBED_TRACE_MEM_FREE(m_trace.line); - m_trace.line_length = 0; - m_trace.line = 0; MBED_TRACE_MEM_FREE(m_trace.tmp_data); - m_trace.tmp_data = 0; - m_trace.tmp_data_ptr = 0; MBED_TRACE_MEM_FREE(m_trace.filters_exclude); - m_trace.filters_exclude = 0; MBED_TRACE_MEM_FREE(m_trace.filters_include); + + // reset to default values + m_trace.trace_config = DEFAULT_TRACE_CONFIG; + m_trace.filters_exclude = 0; m_trace.filters_include = 0; - m_trace.filters_length = 0; + m_trace.filters_length = DEFAULT_TRACE_FILTER_LENGTH; + m_trace.line = 0; + m_trace.line_length = DEFAULT_TRACE_LINE_LENGTH; + m_trace.tmp_data = 0; + m_trace.tmp_data_length = DEFAULT_TRACE_TMP_LINE_LEN; m_trace.prefix_f = 0; m_trace.suffix_f = 0; - m_trace.printf = mbed_trace_default_print; + m_trace.printf = mbed_trace_default_print; m_trace.cmd_printf = 0; m_trace.mutex_wait_f = 0; m_trace.mutex_release_f = 0; @@ -480,7 +503,7 @@ const char *mbed_trace_last(void) } /* Helping functions */ #define tmp_data_left() m_trace.tmp_data_length-(m_trace.tmp_data_ptr-m_trace.tmp_data) -#if YOTTA_CFG_MBED_TRACE_FEA_IPV6 == 1 +#if MBED_CONF_MBED_TRACE_FEA_IPV6 == 1 char *mbed_trace_ipv6(const void *addr_ptr) { /** Acquire mutex. It is released before returning from mbed_vtracef. */ @@ -524,7 +547,7 @@ char *mbed_trace_ipv6_prefix(const uint8_t *prefix, uint8_t prefix_len) m_trace.tmp_data_ptr += ip6_prefix_tos(prefix, prefix_len, str) + 1; return str; } -#endif //YOTTA_CFG_MBED_TRACE_FEA_IPV6 +#endif //MBED_CONF_MBED_TRACE_FEA_IPV6 char *mbed_trace_array(const uint8_t *buf, uint16_t len) { /** Acquire mutex. It is released before returning from mbed_vtracef. */ diff --git a/features/FEATURE_COMMON_PAL/mbed-trace/test/Test.cpp b/features/FEATURE_COMMON_PAL/mbed-trace/test/Test.cpp index 0541240ecab..90b7a9343dc 100644 --- a/features/FEATURE_COMMON_PAL/mbed-trace/test/Test.cpp +++ b/features/FEATURE_COMMON_PAL/mbed-trace/test/Test.cpp @@ -14,8 +14,8 @@ #include "mbed-cpputest/CppUTest/SimpleString.h" #include "mbed-cpputest/CppUTest/CommandLineTestRunner.h" -#define YOTTA_CFG_MBED_TRACE 1 -#define YOTTA_CFG_MBED_TRACE_FEA_IPV6 1 +#define MBED_CONF_MBED_TRACE_ENABLE 1 +#define MBED_CONF_MBED_TRACE_FEA_IPV6 1 #include "mbed-trace/mbed_trace.h" #include "ip6tos_stub.h" @@ -118,6 +118,7 @@ TEST(trace, BufferResize) { uint8_t arr[20] = {0}; memset(arr, '0', 20); + mbed_trace_buffer_sizes(0, 10); STRCMP_EQUAL("30:30:30*", mbed_trace_array(arr, 20)); mbed_trace_buffer_sizes(0, 15); @@ -125,7 +126,38 @@ TEST(trace, BufferResize) mbed_trace_buffer_sizes(0, 15); STRCMP_EQUAL("30:30:30:30", mbed_trace_array(arr, 4)); - mbed_tracef(TRACE_LEVEL_DEBUG, "mygr", "flush buffers and locks"); + const char * expectedStr = "0123456789"; + mbed_trace_buffer_sizes(11, 0); + mbed_tracef(TRACE_LEVEL_DEBUG, "mygr", "01234567890123456789"); + STRCMP_EQUAL(expectedStr, buf); + expectedStr = "012345678901234"; + mbed_trace_buffer_sizes(16, 0); + mbed_tracef(TRACE_LEVEL_DEBUG, "mygr", "01234567890123456789"); + STRCMP_EQUAL(expectedStr, buf); + expectedStr = "012345678901234"; + mbed_trace_buffer_sizes(16, 0); + mbed_tracef(TRACE_LEVEL_DEBUG, "mygr", "012345678901234"); + STRCMP_EQUAL(expectedStr, buf); +} + +TEST(trace, PreInitConfiguration) +{ + uint8_t arr[20] = {0}; + memset(arr, '0', 20); + + mbed_trace_free(); + mbed_trace_config_set(TRACE_MODE_PLAIN|TRACE_ACTIVE_LEVEL_ALL); + mbed_trace_print_function_set( myprint ); + mbed_trace_buffer_sizes(11, 10); + mbed_trace_mutex_wait_function_set( my_mutex_wait ); + mbed_trace_mutex_release_function_set( my_mutex_release ); + mbed_trace_init(); + + STRCMP_EQUAL("30:30:30*", mbed_trace_array(arr, 20)); + + const char * expectedStr = "0123456789"; + mbed_tracef(TRACE_LEVEL_DEBUG, "mygr", "01234567890123456789"); + STRCMP_EQUAL(expectedStr, buf); } #if YOTTA_CFG_MBED_TRACE_FEA_IPV6 == 1 diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_netif.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_netif.c index 148c2e285ba..7cdb7a9a604 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_netif.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_netif.c @@ -100,36 +100,43 @@ struct ethernetif { // Override mbed_mac_address of mbed_interface.c to provide ethernet devices with a semi-unique MAC address void mbed_mac_address(char *mac) { - unsigned char my_mac_addr[6] = {0x02, 0x00, 0xac, 0x55, 0x66, 0x77}; // default mac adderss + uint32_t uID1; // Fetch word 0 - uint32_t word0 = *(uint32_t *)0x7FFFC; + uint32_t word0 = *(uint32_t *)0x7F804; // 2KB Data Flash at 0x7F800 // Fetch word 1 // we only want bottom 16 bits of word1 (MAC bits 32-47) // and bit 9 forced to 1, bit 8 forced to 0 // Locally administered MAC, reduced conflicts // http://en.wikipedia.org/wiki/MAC_address - uint32_t word1 = *(uint32_t *)0x7FFF8; - if( word0 == 0xFFFFFFFF ) // Not burn any mac address at the last 2 words of flash + uint32_t word1 = *(uint32_t *)0x7F800; // 2KB Data Flash at 0x7F800 + + if( word0 == 0xFFFFFFFF ) // Not burn any mac address at 1st 2 words of Data Flash { - mac[0] = my_mac_addr[0]; - mac[1] = my_mac_addr[1]; - mac[2] = my_mac_addr[2]; - mac[3] = my_mac_addr[3]; - mac[4] = my_mac_addr[4]; - mac[5] = my_mac_addr[5]; - return; + // with a semi-unique MAC address from the UUID + /* Enable FMC ISP function */ + SYS_UnlockReg(); + FMC_Open(); + // = FMC_ReadUID(0); + uID1 = FMC_ReadUID(1); + word1 = (uID1 & 0x003FFFFF) | ((uID1 & 0x030000) << 6) >> 8; + word0 = ((FMC_ReadUID(0) >> 4) << 20) | ((uID1 & 0xFF)<<12) | (FMC_ReadUID(2) & 0xFFF); + /* Disable FMC ISP function */ + FMC_Close(); + /* Lock protected registers */ + SYS_LockReg(); } word1 |= 0x00000200; word1 &= 0x0000FEFF; - - mac[0] = (word1 & 0x000000ff); - mac[1] = (word1 & 0x0000ff00) >> 8; + + mac[0] = (word1 & 0x0000ff00) >> 8; + mac[1] = (word1 & 0x000000ff); mac[2] = (word0 & 0xff000000) >> 24; mac[3] = (word0 & 0x00ff0000) >> 16; mac[4] = (word0 & 0x0000ff00) >> 8; mac[5] = (word0 & 0x000000ff); - + + LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING|LWIP_DBG_ON, ("mac address %02x-%02x-%02x-%02x-%02x-%02x \r\n", mac[0], mac[1],mac[2],mac[3],mac[4],mac[5])); } /** @@ -350,7 +357,7 @@ ethernetif_loopback_input(struct pbuf *p) // TODO: make sure packet no { /* pass all packets to ethernet_input, which decides what packets it supports */ if (netif->input(p, netif) != ERR_OK) { - LWIP_DEBUGF(NETIF_DEBUG, ("k64f_enetif_input: input error\n")); + LWIP_DEBUGF(NETIF_DEBUG, ("netif_input: input error\n")); /* Free buffer */ pbuf_free(p); } diff --git a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c index ff36b3e7877..dffc1610fb7 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c @@ -691,6 +691,7 @@ static nsapi_error_t mbed_lwip_socket_close(nsapi_stack_t *stack, nsapi_socket_t { struct lwip_socket *s = (struct lwip_socket *)handle; + netbuf_delete(s->buf); err_t err = netconn_delete(s->conn); mbed_lwip_arena_dealloc(s); return mbed_lwip_err_remap(err); diff --git a/features/TESTS/filesystem/heap_block_device/main.cpp b/features/TESTS/filesystem/heap_block_device/main.cpp index eb057fef8e0..8d337ed73e2 100644 --- a/features/TESTS/filesystem/heap_block_device/main.cpp +++ b/features/TESTS/filesystem/heap_block_device/main.cpp @@ -23,71 +23,124 @@ using namespace utest::v1; -/* It is not possible to build a KL25Z image with IAR including the file system if - * stack tracking statistics are enabled. If this is the case, build dummy - * tests. - */ -#if ! defined(__ICCARM__) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED) +#define TEST_BLOCK_SIZE 512 +#define TEST_BLOCK_DEVICE_SIZE 16*TEST_BLOCK_SIZE +#define TEST_BLOCK_COUNT 10 +#define TEST_ERROR_MASK 16 + +const struct { + const char *name; + bd_size_t (BlockDevice::*method)() const; +} ATTRS[] = { + {"read size", &BlockDevice::get_read_size}, + {"program size", &BlockDevice::get_program_size}, + {"erase size", &BlockDevice::get_erase_size}, + {"total size", &BlockDevice::size}, +}; -#define BLOCK_SIZE 512 -#define HEAP_BLOCK_DEVICE_TEST_01 test_read_write -uint8_t write_block[BLOCK_SIZE]; -uint8_t read_block[BLOCK_SIZE]; -// Simple test which reads and writes a block +// Simple test that read/writes random set of blocks void test_read_write() { - HeapBlockDevice bd(16*BLOCK_SIZE, BLOCK_SIZE); + HeapBlockDevice bd(TEST_BLOCK_DEVICE_SIZE, TEST_BLOCK_SIZE); int err = bd.init(); TEST_ASSERT_EQUAL(0, err); - // Fill with random sequence - srand(1); - for (int i = 0; i < BLOCK_SIZE; i++) { - write_block[i] = 0xff & rand(); + for (unsigned a = 0; a < sizeof(ATTRS)/sizeof(ATTRS[0]); a++) { + static const char *prefixes[] = {"", "k", "M", "G"}; + for (int i = 3; i >= 0; i--) { + bd_size_t size = (bd.*ATTRS[a].method)(); + if (size >= (1ULL << 10*i)) { + printf("%s: %llu%sbytes (%llubytes)\n", + ATTRS[a].name, size >> 10*i, prefixes[i], size); + break; + } + } } - // Write, sync, and read the block - err = bd.program(write_block, 0, BLOCK_SIZE); - TEST_ASSERT_EQUAL(0, err); - - err = bd.read(read_block, 0, BLOCK_SIZE); - TEST_ASSERT_EQUAL(0, err); - - // Check that the data was unmodified - srand(1); - for (int i = 0; i < BLOCK_SIZE; i++) { - TEST_ASSERT_EQUAL(0xff & rand(), read_block[i]); + bd_size_t block_size = bd.get_erase_size(); + uint8_t *write_block = new uint8_t[block_size]; + uint8_t *read_block = new uint8_t[block_size]; + uint8_t *error_mask = new uint8_t[TEST_ERROR_MASK]; + unsigned addrwidth = ceil(log(float(bd.size()-1)) / log(float(16)))+1; + + for (int b = 0; b < TEST_BLOCK_COUNT; b++) { + // Find a random block + bd_addr_t block = (rand()*block_size) % bd.size(); + + // Use next random number as temporary seed to keep + // the address progressing in the pseudorandom sequence + unsigned seed = rand(); + + // Fill with random sequence + srand(seed); + for (bd_size_t i = 0; i < block_size; i++) { + write_block[i] = 0xff & rand(); + } + + // erase, program, and read the block + printf("test %0*llx:%llu...\n", addrwidth, block, block_size); + + err = bd.erase(block, block_size); + TEST_ASSERT_EQUAL(0, err); + + err = bd.program(write_block, block, block_size); + TEST_ASSERT_EQUAL(0, err); + + printf("write %0*llx:%llu ", addrwidth, block, block_size); + for (int i = 0; i < 16; i++) { + printf("%02x", write_block[i]); + } + printf("...\n"); + + err = bd.read(read_block, block, block_size); + TEST_ASSERT_EQUAL(0, err); + + printf("read %0*llx:%llu ", addrwidth, block, block_size); + for (int i = 0; i < 16; i++) { + printf("%02x", read_block[i]); + } + printf("...\n"); + + // Find error mask for debugging + memset(error_mask, 0, TEST_ERROR_MASK); + bd_size_t error_scale = block_size / (TEST_ERROR_MASK*8); + + srand(seed); + for (bd_size_t i = 0; i < TEST_ERROR_MASK*8; i++) { + for (bd_size_t j = 0; j < error_scale; j++) { + if ((0xff & rand()) != read_block[i*error_scale + j]) { + error_mask[i/8] |= 1 << (i%8); + } + } + } + + printf("error %0*llx:%llu ", addrwidth, block, block_size); + for (int i = 0; i < 16; i++) { + printf("%02x", error_mask[i]); + } + printf("\n"); + + // Check that the data was unmodified + srand(seed); + for (bd_size_t i = 0; i < block_size; i++) { + TEST_ASSERT_EQUAL(0xff & rand(), read_block[i]); + } } - + err = bd.deinit(); TEST_ASSERT_EQUAL(0, err); } -#else /* ! defined(__ICCARM__) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED) */ - -#define HEAP_BLOCK_DEVICE_TEST_01 heap_block_device_test_dummy - -/** @brief heap_block_device_test_dummy Dummy test case for testing when KL25Z being built with stack statistics enabled. - * - * @return success always - */ -static control_t heap_block_device_test_dummy() -{ - printf("Null test\n"); - return CaseNext; -} - -#endif /* ! defined(__ICCARM__) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED) */ // Test setup utest::v1::status_t test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(10, "default_auto"); + GREENTEA_SETUP(30, "default_auto"); return verbose_test_setup_handler(number_of_cases); } Case cases[] = { - Case("Testing read write of a block", HEAP_BLOCK_DEVICE_TEST_01), + Case("Testing read write random blocks", test_read_write), }; Specification specification(test_setup, cases); diff --git a/features/TESTS/filesystem/util_block_device/main.cpp b/features/TESTS/filesystem/util_block_device/main.cpp index 98933c14c13..50867568ac8 100644 --- a/features/TESTS/filesystem/util_block_device/main.cpp +++ b/features/TESTS/filesystem/util_block_device/main.cpp @@ -25,23 +25,15 @@ using namespace utest::v1; -/* It is not possible to build a KL25Z image with IAR including the file system if - * stack tracking statistics are enabled. If this is the case, build dummy - * tests. - */ -#if ! defined(TOOLCHAIN_IAR) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED) - #define BLOCK_COUNT 16 #define BLOCK_SIZE 512 -#define UTIL_BLOCK_DEVICE_TEST_01 test_slicing -#define UTIL_BLOCK_DEVICE_TEST_02 test_chaining -uint8_t write_block[BLOCK_SIZE]; -uint8_t read_block[BLOCK_SIZE]; // Simple test which read/writes blocks on a sliced block device void test_slicing() { HeapBlockDevice bd(BLOCK_COUNT*BLOCK_SIZE, BLOCK_SIZE); + uint8_t *write_block = new uint8_t[BLOCK_SIZE]; + uint8_t *read_block = new uint8_t[BLOCK_SIZE]; // Test with first slice of block device SlicingBlockDevice slice1(&bd, 0, (BLOCK_COUNT/2)*BLOCK_SIZE); @@ -123,6 +115,8 @@ void test_slicing() { TEST_ASSERT_EQUAL(0xff & rand(), read_block[i]); } + delete[] write_block; + delete[] read_block; err = slice2.deinit(); TEST_ASSERT_EQUAL(0, err); } @@ -131,6 +125,8 @@ void test_slicing() { void test_chaining() { HeapBlockDevice bd1((BLOCK_COUNT/2)*BLOCK_SIZE, BLOCK_SIZE); HeapBlockDevice bd2((BLOCK_COUNT/2)*BLOCK_SIZE, BLOCK_SIZE); + uint8_t *write_block = new uint8_t[BLOCK_SIZE]; + uint8_t *read_block = new uint8_t[BLOCK_SIZE]; // Test with chain of block device BlockDevice *bds[] = {&bd1, &bd2}; @@ -174,26 +170,12 @@ void test_chaining() { TEST_ASSERT_EQUAL(0xff & rand(), read_block[i]); } + delete[] write_block; + delete[] read_block; err = chain.deinit(); TEST_ASSERT_EQUAL(0, err); } -#else /* ! defined(TOOLCHAIN_IAR) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED) */ - -#define UTIL_BLOCK_DEVICE_TEST_01 util_block_device_test_dummy -#define UTIL_BLOCK_DEVICE_TEST_02 util_block_device_test_dummy - -/** @brief util_block_device_test_dummy Dummy test case for testing when KL25Z being built with stack statistics enabled. - * - * @return success always - */ -static control_t util_block_device_test_dummy() -{ - printf("Null test\n"); - return CaseNext; -} - -#endif /* ! defined(TOOLCHAIN_IAR) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED) */ // Test setup utest::v1::status_t test_setup(const size_t number_of_cases) { @@ -202,8 +184,8 @@ utest::v1::status_t test_setup(const size_t number_of_cases) { } Case cases[] = { - Case("Testing slicing of a block device", UTIL_BLOCK_DEVICE_TEST_01), - Case("Testing chaining of block devices", UTIL_BLOCK_DEVICE_TEST_02), + Case("Testing slicing of a block device", test_slicing), + Case("Testing chaining of block devices", test_chaining), }; Specification specification(test_setup, cases); diff --git a/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/mbedtls_device.h b/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/mbedtls_device.h new file mode 100644 index 00000000000..9a06a1cba55 --- /dev/null +++ b/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/mbedtls_device.h @@ -0,0 +1,26 @@ +/* + * mbedtls_device.h + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +#ifndef MBEDTLS_DEVICE_H +#define MBEDTLS_DEVICE_H + +#define MBEDTLS_AES_ALT + + +#endif /* MBEDTLS_DEVICE_H */ diff --git a/features/mbedtls/targets/TARGET_STM/aes_alt.c b/features/mbedtls/targets/TARGET_STM/aes_alt.c new file mode 100644 index 00000000000..a5a8fa4dce2 --- /dev/null +++ b/features/mbedtls/targets/TARGET_STM/aes_alt.c @@ -0,0 +1,295 @@ +/* + * Hardware aes collector for the STM32F4 family + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#include +#include "mbedtls/aes.h" + +#if defined(MBEDTLS_AES_ALT) + +static int aes_set_key( mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits ) +{ + switch( keybits ) + { + case 128: + ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_128B; + memcpy(ctx->aes_key, key, 16); + break; + case 192: + ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_192B; + memcpy(ctx->aes_key, key, 24); + break; + case 256: + ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_256B; + memcpy(ctx->aes_key, key, 32); + break; + default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + + /* Deinitializes the CRYP peripheral */ + if (HAL_CRYP_DeInit(&ctx->hcryp_aes) == HAL_ERROR) + return (HAL_ERROR); + + ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B; + ctx->hcryp_aes.Instance = CRYP; + /* Enable CRYP clock */ + __HAL_RCC_CRYP_CLK_ENABLE(); + + ctx->hcryp_aes.Init.pKey = ctx->aes_key; + if (HAL_CRYP_Init(&ctx->hcryp_aes) == HAL_ERROR) + return (HAL_ERROR); + + /* allow multi-instance of CRYP use: save context for CRYP HW module CR */ + ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR; + return(0); + +} + +/* Implementation that should never be optimized out by the compiler */ +static void mbedtls_zeroize( void *v, size_t n ) { + volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +} + + +void mbedtls_aes_init( mbedtls_aes_context *ctx ) +{ + memset( ctx, 0, sizeof( mbedtls_aes_context ) ); + +} + + +void mbedtls_aes_free( mbedtls_aes_context *ctx ) +{ + if( ctx == NULL ) + return; + /* Force the CRYP Periheral Clock Reset */ + __HAL_RCC_CRYP_FORCE_RESET(); + + /* Release the CRYP Periheral Clock Reset */ + __HAL_RCC_CRYP_RELEASE_RESET(); + + mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) ); +} + + +int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ) +{ + int ret_val = 0; + ret_val = aes_set_key(ctx, key, keybits); + return(ret_val); +} + +int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ) +{ + int ret_val = 0; + ret_val = aes_set_key(ctx, key, keybits); + return( ret_val ); +} + + +int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ) +{ + + /* allow multi-instance of CRYP use: restore context for CRYP hw module */ + ctx->hcryp_aes.Instance->CR = ctx->ctx_save_cr; + + if(mode == MBEDTLS_AES_DECRYPT) /* AES decryption */ + { + ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B; + ctx->hcryp_aes.Init.pKey = ctx->aes_key; + mbedtls_aes_decrypt( ctx, input, output ); + } + else /* AES encryption */ + { + ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B; + ctx->hcryp_aes.Init.pKey = ctx->aes_key; + mbedtls_aes_encrypt( ctx, input, output ); + } + /* allow multi-instance of CRYP use: save context for CRYP HW module CR */ + ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR; + + return( 0 ); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + +int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int status=0; + if( length % 16 ) + return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + + if( mode == MBEDTLS_AES_DECRYPT ) + { + ctx->hcryp_aes.Init.pInitVect = &iv[0]; // used in process, not in the init + + status = HAL_CRYP_AESCBC_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10); + } + else + { + ctx->hcryp_aes.Init.pInitVect = &iv[0]; // used in process, not in the init + + status = HAL_CRYP_AESCBC_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10); + } + return( status ); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int c; + size_t n = *iv_off; + + if( mode == MBEDTLS_AES_DECRYPT ) + { + while( length-- ) + { + if( n == 0 ) + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + + n = ( n + 1 ) & 0x0F; + } + } + else + { + while( length-- ) + { + if( n == 0 ) + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + + n = ( n + 1 ) & 0x0F; + } + } + + *iv_off = n; + + return( 0 ); +} + + +int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + unsigned char c; + unsigned char ov[17]; + + while( length-- ) + { + memcpy( ov, iv, 16 ); + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + if( mode == MBEDTLS_AES_DECRYPT ) + ov[16] = *input; + + c = *output++ = (unsigned char)( iv[0] ^ *input++ ); + + if( mode == MBEDTLS_AES_ENCRYPT ) + ov[16] = c; + + memcpy( iv, ov + 1, 16 ); + } + + return( 0 ); +} + +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) +{ + int c, i; + size_t n = *nc_off; + + while( length-- ) + { + if( n == 0 ) { + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ); + + for( i = 16; i > 0; i-- ) + if( ++nonce_counter[i - 1] != 0 ) + break; + } + c = *input++; + *output++ = (unsigned char)( c ^ stream_block[n] ); + + n = ( n + 1 ) & 0x0F; + } + + *nc_off = n; + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + + if (HAL_CRYP_AESECB_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10) !=0) { + // error found to be returned + } + +} + +void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + + if(HAL_CRYP_AESECB_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10)) { + // error found to be returned + } +} + + +#endif /*MBEDTLS_AES_ALT*/ diff --git a/features/mbedtls/targets/TARGET_STM/aes_alt.h b/features/mbedtls/targets/TARGET_STM/aes_alt.h new file mode 100644 index 00000000000..dbe4fdeec30 --- /dev/null +++ b/features/mbedtls/targets/TARGET_STM/aes_alt.h @@ -0,0 +1,264 @@ +/* + * aes_alt.h AES block cipher + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +#ifndef MBEDTLS_AES_ALT_H +#define MBEDTLS_AES_ALT_H + + +#if defined(MBEDTLS_AES_ALT) +#include "mbedtls/platform.h" +#include "mbedtls/config.h" + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief AES context structure + * + * \note buf is able to hold 32 extra bytes, which can be used: + * - for alignment purposes if VIA padlock is used, and/or + * - to simplify key expansion in the 256-bit case by + * generating an extra round key + */ +typedef struct +{ + unsigned char aes_key[32]; /* Decryption key */ + CRYP_HandleTypeDef hcryp_aes; + uint32_t ctx_save_cr; /* save context for multi-instance */ +} +mbedtls_aes_context; + +/** + * \brief Initialize AES context + * + * \param ctx AES context to be initialized + */ +void mbedtls_aes_init( mbedtls_aes_context *ctx ); + +/** + * \brief Clear AES context + * + * \param ctx AES context to be cleared + */ +void mbedtls_aes_free( mbedtls_aes_context *ctx ); + +/** + * \brief AES key schedule (encryption) + * + * \param ctx AES context to be initialized + * \param key encryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH + */ +int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ); + +/** + * \brief AES key schedule (decryption) + * + * \param ctx AES context to be initialized + * \param key decryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH + */ +int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ); + +/** + * \brief AES-ECB block encryption/decryption + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param input 16-byte input block + * \param output 16-byte output block + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/** + * \brief AES-CBC buffer encryption/decryption + * Length should be a multiple of the block + * size (16 bytes) + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH + */ +int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/** + * \brief AES-CFB128 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param length length of the input data + * \param iv_off offset in IV (updated after use) + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CFB8 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/** + * \brief AES-CTR buffer encryption/decryption + * + * Warning: You have to keep the maximum use of your counter in mind! + * + * Note: Due to the nature of CTR you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT. + * + * \param ctx AES context + * \param length The length of the data + * \param nc_off The offset in the current stream_block (for resuming + * within current cipher stream). The offset pointer to + * should be 0 at the start of a stream. + * \param nonce_counter The 128-bit nonce and counter. + * \param stream_block The saved stream-block for resuming. Is overwritten + * by the function. + * \param input The input data stream + * \param output The output data stream + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see MBEDTLS_AES_ENCRYPT_ALT) + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + */ +void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ); + +/** + * \brief Internal AES block decryption function + * (Only exposed to allow overriding it, + * see MBEDTLS_AES_DECRYPT_ALT) + * + * \param ctx AES context + * \param input Ciphertext block + * \param output Output (plaintext) block + */ +void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ); + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_AES_ALT */ + +#endif /* MBEDTLS_AES_ALT_H */ + diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp index e4a7dfb4cd3..875abbb48a7 100644 --- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp @@ -67,6 +67,8 @@ static const RAIL_CsmaConfig_t csma_config = RAIL_CSMA_CONFIG_802_15_4_2003_2p4_ #if defined(TARGET_EFR32MG1) #include "ieee802154_subg_efr32xg1_configurator_out.h" #include "ieee802154_efr32xg1_configurator_out.h" +#elif defined(TARGET_EFR32MG12) +#include "ieee802154_efr32xg12_configurator_out.h" #else #error "Not a valid target." #endif @@ -78,7 +80,7 @@ static const RAIL_ChannelConfigEntry_t entry[] = { }; #if MBED_CONF_SL_RAIL_BAND == 868 -#ifndef DEVICE_RF_SUBGHZ +#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG #error "Sub-Gigahertz band is not supported on this target." #endif static const RAIL_ChannelConfig_t channels = { @@ -86,7 +88,7 @@ static const RAIL_ChannelConfig_t channels = { 1 }; #elif MBED_CONF_SL_RAIL_BAND == 915 -#ifndef DEVICE_RF_SUBGHZ +#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG #error "Sub-Gigahertz band is not supported on this target." #endif static const RAIL_ChannelConfig_t channels = { @@ -94,7 +96,7 @@ static const RAIL_ChannelConfig_t channels = { 1 }; #elif MBED_CONF_SL_RAIL_BAND == 2400 -#ifndef DEVICE_RF_2P4GHZ +#ifndef MBED_CONF_SL_RAIL_HAS_2P4 #error "2.4GHz band is not supported on this target." #endif static const RAIL_ChannelConfig_t channels = { @@ -111,7 +113,7 @@ static const RAIL_IEEE802154_Config_t config = { false, false, static const RAIL_Init_t railInitParams = { 140, 38400000, RAIL_CAL_ALL_PENDING }; -#if defined (DEVICE_RF_2P4GHZ) +#if defined (MBED_CONF_SL_RAIL_HAS_2P4) // Set up the PA for 2.4 GHz operation static const RADIO_PAInit_t paInit2p4 = { PA_SEL_2P4_HP, /* Power Amplifier mode */ @@ -122,7 +124,7 @@ static const RADIO_PAInit_t paInit2p4 = { }; #endif -#if defined (DEVICE_RF_SUBGHZ) +#if defined (MBED_CONF_SL_RAIL_HAS_SUBGIG) // Set up the PA for sub-GHz operation static const RADIO_PAInit_t paInitSubGhz = { PA_SEL_SUBGIG, /* Power Amplifier mode */ @@ -173,21 +175,19 @@ static int8_t rf_device_register(void) #endif // Set up PTI since it makes life so much easier -#if defined(DEVICE_SL_PTI) +#if defined(MBED_CONF_SL_RAIL_PTI) && (MBED_CONF_SL_RAIL_PTI == 1) RADIO_PTIInit_t ptiInit = { - RADIO_PTI_MODE_UART, - 1600000, - 6, - // TODO: Configure PTI pinout using config system. - // Not very urgent, since all boards use the same pins now. - gpioPortB, - 12, - 6, - gpioPortB, - 11, - 6, - gpioPortB, - 13, + MBED_CONF_SL_RAIL_PTI_MODE, + MBED_CONF_SL_RAIL_PTI_BAUDRATE, + MBED_CONF_SL_RAIL_PTI_DOUT_LOCATION, + MBED_CONF_SL_RAIL_PTI_DOUT_PORT, + MBED_CONF_SL_RAIL_PTI_DOUT_PIN, + MBED_CONF_SL_RAIL_PTI_DCLK_LOCATION, + MBED_CONF_SL_RAIL_PTI_DCLK_PORT, + MBED_CONF_SL_RAIL_PTI_DCLK_PIN, + MBED_CONF_SL_RAIL_PTI_DFRAME_LOCATION, + MBED_CONF_SL_RAIL_PTI_DFRAME_PORT, + MBED_CONF_SL_RAIL_PTI_DFRAME_PIN }; RADIO_PTI_Init(&ptiInit); @@ -196,13 +196,13 @@ static int8_t rf_device_register(void) // Set up RAIL RAIL_RfInit(&railInitParams); RAIL_ChannelConfig(&channels); -#if MBED_CONF_SL_RAIL_BAND == 2400 +#if (MBED_CONF_SL_RAIL_BAND == 2400) RAIL_RadioConfig((void*) ieee802154_config_base); channel = 11; #elif (MBED_CONF_SL_RAIL_BAND == 915) RAIL_RadioConfig((void*) ieee802154_config_915); channel = 1; -#elif MBED_CONF_SL_RAIL_BAND == 868 +#elif (MBED_CONF_SL_RAIL_BAND == 868) RAIL_RadioConfig((void*) ieee802154_config_863); channel = 0; #endif @@ -286,8 +286,6 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h data_length + 3 }; - tr_debug("Called TX, len %d, chan %d\n", data_length, channel); - switch(radio_state) { case RADIO_UNINIT: tr_debug("Radio uninit\n"); @@ -327,6 +325,8 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h txOpt.waitForAck = false; } + //tr_debug("Called TX, len %d, chan %d, ack %d\n", data_length, channel, waiting_for_ack ? 1 : 0); + if(RAIL_TxStartWithOptions(channel, &txOpt, &RAIL_CcaCsma, (RAIL_CsmaConfig_t*) &csma_config) == 0) { //Save packet number and sequence current_tx_handle = tx_handle; @@ -612,7 +612,6 @@ void RAILCb_RfReady(void) { * @param[in] status A bit field that defines what event caused the callback */ void RAILCb_TxRadioStatus(uint8_t status) { - tr_debug("Packet TX error %d\n", status); if(device_driver.phy_tx_done_cb != NULL) { if(status == RAIL_TX_CONFIG_BUFFER_UNDERFLOW || status == RAIL_TX_CONFIG_CHANNEL_BUSY || @@ -624,6 +623,8 @@ void RAILCb_TxRadioStatus(uint8_t status) { PHY_LINK_CCA_FAIL, 8, 1); + } else { + tr_debug("Packet TX error %d\n", status); } } radio_state = RADIO_RX; @@ -643,7 +644,13 @@ void RAILCb_TxRadioStatus(uint8_t status) { * @param[in] status The event that triggered this callback */ void RAILCb_RxRadioStatus(uint8_t status) { - tr_debug("RXE %d\n", status); + switch(status) { + case RAIL_RX_CONFIG_ADDRESS_FILTERED: + break; + default: + tr_debug("RXE %d\n", status); + break; + } } /** @@ -724,10 +731,10 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) { /* Save the pending bit */ last_ack_pending_bit = (rxPacketInfo->dataPtr[1] & (1 << 4)) != 0; /* Tell the stack we got an ACK */ - tr_debug("rACK\n"); + //tr_debug("rACK\n"); device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, - PHY_LINK_TX_DONE, + last_ack_pending_bit ? PHY_LINK_TX_DONE_PENDING : PHY_LINK_TX_DONE, 1, 1); } else { @@ -745,7 +752,7 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) { RAIL_AutoAckCancelAck(); } - tr_debug("rPKT %d\n", rxPacketInfo->dataLength); + //tr_debug("rPKT %d\n", rxPacketInfo->dataLength); /* Feed the received packet into the stack */ device_driver.phy_rx_cb(rxPacketInfo->dataPtr + 1, rxPacketInfo->dataLength - 1, @@ -785,6 +792,7 @@ void RAILCb_IEEE802154_DataRequestCommand(RAIL_IEEE802154_Address_t *address) { */ void RAILCb_RxAckTimeout(void) { if(waiting_for_ack) { + tr_debug("nACK\n"); waiting_for_ack = false; device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, @@ -824,4 +832,59 @@ static bool rail_checkAndSwitchChannel(uint8_t newChannel) { } else { return false; } +} + +/** + * Callback that fires when the receive fifo exceeds the configured threshold + * value + * + * @param[in] bytesAvailable Number of bytes available in the receive fifo at + * the time of the callback dispatch + * + * @return void + * @warning You must implement a stub for this in your RAIL application. + * + * Callback that fires when the receive fifo exceeds the configured threshold + * value. Provides the number of bytes available in the receive fifo at the + * time of the callback dispatch. + */ +void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable) { + tr_debug("RX near full (%d)\n", bytesAvailable); +} + +/** + * Callback that fires when the transmit fifo falls under the configured + * threshold value + * + * @param[in] spaceAvailable Number of bytes open in the transmit fifo at the + * time of the callback dispatch + * + * @return void + * @warning You must implement a stub for this in your RAIL application. + * + * Callback that fires when the transmit fifo falls under the configured + * threshold value. It only fires if a rising edge occurs across this + * threshold. This callback will not fire on initailization nor after resetting + * the transmit fifo with RAIL_ResetFifo(). + * + * Provides the number of bytes open in the transmit fifo at the time of the + * callback dispatch. + */ +void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable) { + tr_debug("TX near empty (%d)\n", spaceAvailable); +} + +/** + * Callback for when AGC averaged RSSI is done + * + * @param avgRssi Contains the the RSSI in quarter dBm (dbm*4) on success and + * returns \ref RAIL_RSSI_INVALID if there was a problem computing the result. + * + * Called in response to RAIL_StartAverageRSSI() to indicate that the hardware + * has completed averaging. If you would like you can instead use the + * RAIL_AverageRSSIReady() to wait for completion and RAIL_GetAverageRSSI() to + * get the result. + */ +void RAILCb_RssiAverageDone(int16_t avgRssi) { + tr_debug("RSSI done (%d)\n", avgRssi); } \ No newline at end of file diff --git a/features/unsupported/tests/mbed/digitalin_digitalout/main.cpp b/features/unsupported/tests/mbed/digitalin_digitalout/main.cpp index 1e1de891bb7..eb5ffd9b7df 100644 --- a/features/unsupported/tests/mbed/digitalin_digitalout/main.cpp +++ b/features/unsupported/tests/mbed/digitalin_digitalout/main.cpp @@ -9,11 +9,12 @@ DigitalIn in(dp2); // port pin), D1 is used as USBTX DigitalOut out(D7); DigitalIn in(D2); + #elif defined(TARGET_STM) && defined(TARGET_FF_ARDUINO) // TARGET_FF_ARDUINO cannot be used // D0 is used as USBRX for some NUCLEO64 // D7 is not used for some NUCLEO32 -DigitalOut out(D9); +DigitalOut out(D3); DigitalIn in(D2); #elif defined(TARGET_DISCO_L053C8) || \ diff --git a/features/unsupported/tests/mbed/digitalinout/main.cpp b/features/unsupported/tests/mbed/digitalinout/main.cpp index 22a1fad2af7..9cfa01a1f95 100644 --- a/features/unsupported/tests/mbed/digitalinout/main.cpp +++ b/features/unsupported/tests/mbed/digitalinout/main.cpp @@ -14,7 +14,7 @@ DigitalInOut d2(D7); // TARGET_FF_ARDUINO cannot be used // D0 is used as USBRX for some NUCLEO64 // D7 is not used for some NUCLEO32 -DigitalInOut d1(D9); +DigitalInOut d1(D3); DigitalInOut d2(D2); #elif defined(TARGET_DISCO_L053C8) || \ diff --git a/features/unsupported/tests/mbed/interruptin/main.cpp b/features/unsupported/tests/mbed/interruptin/main.cpp index cf49d86653a..8792c878902 100644 --- a/features/unsupported/tests/mbed/interruptin/main.cpp +++ b/features/unsupported/tests/mbed/interruptin/main.cpp @@ -44,7 +44,7 @@ void in_handler() { // D0 is used as USBRX for some NUCLEO64 // D7 is not used for some NUCLEO32 #define PIN_OUT D2 -#define PIN_IN D9 +#define PIN_IN D3 #elif defined(TARGET_DISCO_L053C8) || \ defined(TARGET_DISCO_F334C8) diff --git a/features/unsupported/tests/mbed/portinout/main.cpp b/features/unsupported/tests/mbed/portinout/main.cpp index bdc09e3369a..06a1fc27927 100644 --- a/features/unsupported/tests/mbed/portinout/main.cpp +++ b/features/unsupported/tests/mbed/portinout/main.cpp @@ -1,5 +1,9 @@ #include "test_env.h" +#if !DEVICE_PORTINOUT + #error [NOT_SUPPORTED] PortInOut is not supported +#endif + #if defined(TARGET_K64F) #define P1_1 (1 << 16) #define P1_2 (1 << 17) @@ -103,14 +107,28 @@ defined(TARGET_NUCLEO_F411RE) || \ defined(TARGET_NUCLEO_L053R8) || \ defined(TARGET_NUCLEO_L073RZ) || \ + defined(TARGET_NUCLEO_L476RG) || \ + defined(TARGET_NUCLEO_F446RE) || \ defined(TARGET_NUCLEO_L152RE) -#define P1_1 (1 << 6) // PC_6 -#define P1_2 (1 << 5) // PC_5 -#define PORT_1 PortC +#define P1_1 (1 << 3) // PB_3 (D3) +#define P1_2 (1 << 10) // PB_10 (D6) +#define PORT_1 PortB -#define P2_1 (1 << 8) // PB_8 -#define P2_2 (1 << 9) // PB_9 -#define PORT_2 PortB +#define P2_1 (1 << 10) // PA_10 (D2) +#define P2_2 (1 << 8) // PA_8 (D7) +#define PORT_2 PortA + +#elif defined(TARGET_NUCLEO_F767ZI) || \ + defined(TARGET_NUCLEO_F303ZE) || \ + defined(TARGET_NUCLEO_F207ZG) || \ + defined(TARGET_NUCLEO_F746ZG) +#define P1_1 (1 << 13) // PE_13 (D3) +#define P1_2 (1 << 11) // PE_11 (D5) +#define PORT_1 PortE + +#define P2_1 (1 << 15) // PF_15 (D2) +#define P2_2 (1 << 14) // PF_14 (D4) +#define PORT_2 PortF #elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800) #define P1_1 (1 << 0) // PD0 @@ -193,6 +211,8 @@ #define P2_2 (1 << 1) /*P5_1*/ #define PORT_2 Port5 +#else +#error [NOT_SUPPORTED] This test is not defined on this target #endif #define MASK_1 (P1_1 | P1_2) diff --git a/features/unsupported/tests/mbed/portout_portin/main.cpp b/features/unsupported/tests/mbed/portout_portin/main.cpp index b2336d0820a..83b5d8ad58c 100644 --- a/features/unsupported/tests/mbed/portout_portin/main.cpp +++ b/features/unsupported/tests/mbed/portout_portin/main.cpp @@ -121,14 +121,28 @@ defined(TARGET_NUCLEO_F411RE) || \ defined(TARGET_NUCLEO_L053R8) || \ defined(TARGET_NUCLEO_L073RZ) || \ + defined(TARGET_NUCLEO_L476RG) || \ + defined(TARGET_NUCLEO_F446RE) || \ defined(TARGET_NUCLEO_L152RE) -#define P1_1 (1 << 6) // PC_6 -#define P1_2 (1 << 5) // PC_5 -#define PORT_1 PortC +#define P1_1 (1 << 3) // PB_3 (D3) +#define P1_2 (1 << 10) // PB_10 (D6) +#define PORT_1 PortB -#define P2_1 (1 << 8) // PB_8 -#define P2_2 (1 << 9) // PB_9 -#define PORT_2 PortB +#define P2_1 (1 << 10) // PA_10 (D2) +#define P2_2 (1 << 8) // PA_8 (D7) +#define PORT_2 PortA + +#elif defined(TARGET_NUCLEO_F767ZI) || \ + defined(TARGET_NUCLEO_F303ZE) || \ + defined(TARGET_NUCLEO_F207ZG) || \ + defined(TARGET_NUCLEO_F746ZG) +#define P1_1 (1 << 13) // PE_13 (D3) +#define P1_2 (1 << 11) // PE_11 (D5) +#define PORT_1 PortE + +#define P2_1 (1 << 15) // PF_15 (D2) +#define P2_2 (1 << 14) // PF_14 (D4) +#define PORT_2 PortF #elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800) #define P1_1 (1 << 0) // PD0 @@ -212,7 +226,7 @@ #define PORT_2 Port5 #else -#error [NOT_SUPPORTED] This test is not supported on this target +#error [NOT_SUPPORTED] This test is not defined on this target #endif #define MASK_1 (P1_1 | P1_2) diff --git a/mbed.h b/mbed.h index 4f6d1b1c689..137bd3a7df5 100644 --- a/mbed.h +++ b/mbed.h @@ -16,13 +16,13 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 138 +#define MBED_LIBRARY_VERSION 139 #if MBED_CONF_RTOS_PRESENT // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 #define MBED_MINOR_VERSION 4 -#define MBED_PATCH_VERSION 1 +#define MBED_PATCH_VERSION 2 #else // mbed 2 diff --git a/platform/mbed_retarget.h b/platform/mbed_retarget.h index 8d3b74cebfd..87510590898 100644 --- a/platform/mbed_retarget.h +++ b/platform/mbed_retarget.h @@ -50,8 +50,13 @@ typedef int mode_t; ///< Mode for opening files #if __cplusplus namespace mbed { class Dir; } typedef mbed::Dir DIR; +#else +typedef struct Dir DIR; +#endif +#if __cplusplus extern "C" { +#endif DIR *opendir(const char*); struct dirent *readdir(DIR *); int closedir(DIR*); @@ -59,6 +64,7 @@ extern "C" { long telldir(DIR*); void seekdir(DIR*, long); int mkdir(const char *name, mode_t n); +#if __cplusplus }; #endif diff --git a/rtos/Thread.cpp b/rtos/Thread.cpp index 61bfe964c66..9969e096704 100644 --- a/rtos/Thread.cpp +++ b/rtos/Thread.cpp @@ -44,6 +44,7 @@ namespace rtos { void Thread::constructor(osPriority priority, uint32_t stack_size, unsigned char *stack_pointer) { _tid = 0; + _finished = false; _dynamic_stack = (stack_pointer == NULL); #if defined(__MBED_CMSIS_RTOS_CA9) || defined(__MBED_CMSIS_RTOS_CM) @@ -74,7 +75,7 @@ void Thread::constructor(Callback task, osStatus Thread::start(Callback task) { _mutex.lock(); - if (_tid != 0) { + if ((_tid != 0) || _finished) { _mutex.unlock(); return osErrorParameter; } @@ -117,6 +118,7 @@ osStatus Thread::terminate() { osThreadId local_id = _tid; _join_sem.release(); _tid = (osThreadId)NULL; + _finished = true; ret = osThreadTerminate(local_id); @@ -177,11 +179,15 @@ int32_t Thread::signal_clr(int32_t signals) { Thread::State Thread::get_state() { #if !defined(__MBED_CMSIS_RTOS_CA9) && !defined(__MBED_CMSIS_RTOS_CM) #ifdef CMSIS_OS_RTX - State status = Deleted; + State status; _mutex.lock(); if (_tid != NULL) { status = (State)_thread_def.tcb.state; + } else if (_finished) { + status = Deleted; + } else { + status = Inactive; } _mutex.unlock(); @@ -367,6 +373,7 @@ void Thread::_thunk(const void * thread_ptr) t->_task(); t->_mutex.lock(); t->_tid = (osThreadId)NULL; + t->_finished = true; t->_join_sem.release(); // rtos will release the mutex automatically } diff --git a/rtos/Thread.h b/rtos/Thread.h index 6c480d74b78..d2bae4fb012 100644 --- a/rtos/Thread.h +++ b/rtos/Thread.h @@ -197,6 +197,7 @@ class Thread { /** Starts a thread executing the specified function. @param task function to be executed by this thread. @return status code that indicates the execution status of the function. + @note a thread can only be started once */ osStatus start(mbed::Callback task); @@ -251,7 +252,7 @@ class Thread { /** State of the Thread */ enum State { - Inactive, /**< Not created or terminated */ + Inactive, /**< Not created */ Ready, /**< Ready to run */ Running, /**< Running */ WaitingDelay, /**< Waiting for a delay to occur */ @@ -330,6 +331,10 @@ class Thread { virtual ~Thread(); private: + /* disallow copy constructor and assignment operators */ + Thread(const Thread&); + Thread& operator=(const Thread&); + // Required to share definitions without // delegated constructors void constructor(osPriority priority=osPriorityNormal, @@ -344,9 +349,10 @@ class Thread { mbed::Callback _task; osThreadId _tid; osThreadDef_t _thread_def; - bool _dynamic_stack; Semaphore _join_sem; Mutex _mutex; + bool _dynamic_stack; + bool _finished; }; } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/mbed_overrides.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/mbed_overrides.c index b1ff3e2fde8..fd32a743297 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/mbed_overrides.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/mbed_overrides.c @@ -16,6 +16,7 @@ void mbed_sdk_init() { - printf("", __TIME__, __DATE__); - + char* debug_date = __DATE__; + char* debug_time = __TIME__; + } diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h index 17f54002997..7988f18af54 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h +++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h @@ -23,95 +23,101 @@ extern "C" { #endif -// NOTE: TIMER0_BASE=(APBPERIPH_BASE + 0x10000) -// TIMER1_BASE=(APBPERIPH_BASE + 0x10020) -#define NU_MODNAME(MODBASE, SUBINDEX) ((MODBASE) | (SUBINDEX)) -#define NU_MODBASE(MODNAME) ((MODNAME) & 0xFFFFFFE0) -#define NU_MODSUBINDEX(MODNAME) ((MODNAME) & 0x0000001F) +// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name +// which encodes module base address and module index/subindex. +#define NU_MODSUBINDEX_Pos 0 +#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos) +#define NU_MODINDEX_Pos 20 +#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos) + +#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos)) +#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk)) +#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos) +#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos) #if 0 typedef enum { - GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0), - GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 0), - GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 0), - GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 0), - GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 0), - GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 0) + GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0), + GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0), + GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0), + GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0), + GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0), + GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0) } GPIOName; #endif typedef enum { - ADC_0_0 = (int) NU_MODNAME(EADC0_BASE, 0), - ADC_0_1 = (int) NU_MODNAME(EADC0_BASE, 1), - ADC_0_2 = (int) NU_MODNAME(EADC0_BASE, 2), - ADC_0_3 = (int) NU_MODNAME(EADC0_BASE, 3), - ADC_0_4 = (int) NU_MODNAME(EADC0_BASE, 4), - ADC_0_5 = (int) NU_MODNAME(EADC0_BASE, 5), - ADC_0_6 = (int) NU_MODNAME(EADC0_BASE, 6), - ADC_0_7 = (int) NU_MODNAME(EADC0_BASE, 7), - ADC_0_8 = (int) NU_MODNAME(EADC0_BASE, 8), - ADC_0_9 = (int) NU_MODNAME(EADC0_BASE, 9), - ADC_0_10 = (int) NU_MODNAME(EADC0_BASE, 10), - ADC_0_11 = (int) NU_MODNAME(EADC0_BASE, 11), - ADC_0_12 = (int) NU_MODNAME(EADC0_BASE, 12), - ADC_0_13 = (int) NU_MODNAME(EADC0_BASE, 13), - ADC_0_14 = (int) NU_MODNAME(EADC0_BASE, 14), - ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 15) + ADC_0_0 = (int) NU_MODNAME(EADC0_BASE, 0, 0), + ADC_0_1 = (int) NU_MODNAME(EADC0_BASE, 0, 1), + ADC_0_2 = (int) NU_MODNAME(EADC0_BASE, 0, 2), + ADC_0_3 = (int) NU_MODNAME(EADC0_BASE, 0, 3), + ADC_0_4 = (int) NU_MODNAME(EADC0_BASE, 0, 4), + ADC_0_5 = (int) NU_MODNAME(EADC0_BASE, 0, 5), + ADC_0_6 = (int) NU_MODNAME(EADC0_BASE, 0, 6), + ADC_0_7 = (int) NU_MODNAME(EADC0_BASE, 0, 7), + ADC_0_8 = (int) NU_MODNAME(EADC0_BASE, 0, 8), + ADC_0_9 = (int) NU_MODNAME(EADC0_BASE, 0, 9), + ADC_0_10 = (int) NU_MODNAME(EADC0_BASE, 0, 10), + ADC_0_11 = (int) NU_MODNAME(EADC0_BASE, 0, 11), + ADC_0_12 = (int) NU_MODNAME(EADC0_BASE, 0, 12), + ADC_0_13 = (int) NU_MODNAME(EADC0_BASE, 0, 13), + ADC_0_14 = (int) NU_MODNAME(EADC0_BASE, 0, 14), + ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 0, 15) } ADCName; typedef enum { - UART_0 = (int) NU_MODNAME(UART0_BASE, 0), - UART_1 = (int) NU_MODNAME(UART1_BASE, 0), - UART_2 = (int) NU_MODNAME(UART2_BASE, 0), - UART_3 = (int) NU_MODNAME(UART3_BASE, 0), + UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0), + UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0), + UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0), + UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0), // FIXME: board-specific STDIO_UART = UART_3 } UARTName; typedef enum { - SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0), - SPI_1 = (int) NU_MODNAME(SPI1_BASE, 0), - SPI_2 = (int) NU_MODNAME(SPI2_BASE, 0) + SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0), + SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0), + SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0) } SPIName; typedef enum { - I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0), - I2C_1 = (int) NU_MODNAME(I2C1_BASE, 0) + I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0), + I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0) } I2CName; typedef enum { - PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0), - PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 1), - PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 2), - PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 3), - PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 4), - PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 5), + PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0, 0), + PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 0, 1), + PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 0, 2), + PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 0, 3), + PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 0, 4), + PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 0, 5), - PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 0), - PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1), - PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 2), - PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 3), - PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 4), - PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 5) + PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 1, 0), + PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1, 1), + PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 1, 2), + PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 1, 3), + PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 1, 4), + PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 1, 5) } PWMName; typedef enum { - TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0), - TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x20, 0), - TIMER_2 = (int) NU_MODNAME(TMR23_BASE, 0), - TIMER_3 = (int) NU_MODNAME(TMR23_BASE + 0x20, 0), + TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0, 0), + TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x20, 1, 0), + TIMER_2 = (int) NU_MODNAME(TMR23_BASE, 2, 0), + TIMER_3 = (int) NU_MODNAME(TMR23_BASE + 0x20, 3, 0), } TIMERName; typedef enum { - RTC_0 = (int) NU_MODNAME(RTC_BASE, 0) + RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0) } RTCName; typedef enum { - DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0) + DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0, 0) } DMAName; typedef enum { - CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0) + CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0, 0) } CANName; #ifdef __cplusplus diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h index a9964c135c3..dd10d034cfe 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h +++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h @@ -22,13 +22,32 @@ extern "C" { #endif -#define NU_PORT_SHIFT 12 -#define NU_PINNAME_TO_PORT(name) ((unsigned int)(name) >> NU_PORT_SHIFT) -#define NU_PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << NU_PORT_SHIFT)) -#define NU_PORT_N_PIN_TO_PINNAME(port, pin) ((((unsigned int) (port)) << (NU_PORT_SHIFT)) | ((unsigned int) (pin))) -#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port)) -#define NU_MFP_POS(pin) ((pin % 8) * 4) -#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin)) +#define NU_PININDEX_Pos 0 +#define NU_PININDEX_Msk (0xFFul << NU_PININDEX_Pos) +#define NU_PINPORT_Pos 8 +#define NU_PINPORT_Msk (0xFul << NU_PINPORT_Pos) +#define NU_PIN_MODINDEX_Pos 12 +#define NU_PIN_MODINDEX_Msk (0xFul << NU_PIN_MODINDEX_Pos) +#define NU_PIN_BIND_Pos 16 +#define NU_PIN_BIND_Msk (0x1ul << NU_PIN_BIND_Pos) + +#define NU_PININDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos) +#define NU_PINPORT(PINNAME) (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos) +#define NU_PIN_BIND(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos) +#define NU_PIN_MODINDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos) +#define NU_PINNAME(PORT, PIN) ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos)) +#define NU_PINNAME_BIND(PINNAME, modname) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname) +#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk) + +#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port)) +#define NU_MFP_POS(pin) ((pin % 8) * 4) +#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin)) + +// LEGACY +#define NU_PINNAME_TO_PIN(PINNAME) NU_PININDEX(PINNAME) +#define NU_PINNAME_TO_PORT(PINNAME) NU_PINPORT(PINNAME) +#define NU_PINNAME_TO_MODSUBINDEX(PINNAME) NU_PIN_MODINDEX(PINNAME) +#define NU_PORT_N_PIN_TO_PINNAME(PORT, PIN) NU_PINNAME((PORT), (PIN)) typedef enum { PIN_INPUT, diff --git a/targets/TARGET_NUVOTON/TARGET_M451/can_api.c b/targets/TARGET_NUVOTON/TARGET_M451/can_api.c index ba43d93b0b1..2625298a781 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/can_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/can_api.c @@ -69,7 +69,7 @@ PA0 = 0x00; PA1 = 0x00; - CAN_Open((CAN_T *)obj->can, 500000, CAN_NORMAL_MODE); + CAN_Open((CAN_T *)NU_MODBASE(obj->can), 500000, CAN_NORMAL_MODE); can_filter(obj, 0, 0, CANStandard, 0); } @@ -91,9 +91,9 @@ void can_free(can_t *obj) int can_frequency(can_t *obj, int hz) { - CAN_SetBaudRate((CAN_T *)obj->can, hz); + CAN_SetBaudRate((CAN_T *)NU_MODBASE(obj->can), hz); - return CAN_GetCANBitRate((CAN_T *)obj->can); + return CAN_GetCANBitRate((CAN_T *)NU_MODBASE(obj->can)); } static void can_irq(CANName name, int id) @@ -154,7 +154,7 @@ void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) void can_irq_free(can_t *obj) { - CAN_DisableInt((CAN_T *)obj->can, (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk)); + CAN_DisableInt((CAN_T *)NU_MODBASE(obj->can), (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk)); can_irq_ids[obj->index] = 0; @@ -163,8 +163,9 @@ void can_irq_free(can_t *obj) void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable) { + CAN_T *can_base = (CAN_T *) NU_MODBASE(obj->can); - CAN_EnterInitMode((CAN_T*)obj->can, ((enable != 0 )? CAN_CON_IE_Msk :0) ); + CAN_EnterInitMode(can_base, ((enable != 0 )? CAN_CON_IE_Msk :0) ); switch (irq) @@ -172,15 +173,15 @@ void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable) case IRQ_ERROR: case IRQ_BUS: case IRQ_PASSIVE: - ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_EIE_Msk; - ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk; + can_base->CON = can_base->CON |CAN_CON_EIE_Msk; + can_base->CON = can_base->CON |CAN_CON_SIE_Msk; break; case IRQ_RX: case IRQ_TX: case IRQ_OVERRUN: case IRQ_WAKEUP: - ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk; + can_base->CON = can_base->CON |CAN_CON_SIE_Msk; break; default: @@ -188,7 +189,7 @@ void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable) } - CAN_LeaveInitMode((CAN_T*)obj->can); + CAN_LeaveInitMode(can_base); NVIC_SetVector(CAN0_IRQn, (uint32_t)&CAN0_IRQHandler); NVIC_EnableIRQ(CAN0_IRQn); @@ -205,14 +206,14 @@ int can_write(can_t *obj, CAN_Message msg, int cc) CMsg.DLC = msg.len; memcpy((void *)&CMsg.Data[0],(const void *)&msg.data[0], (unsigned int)8); - return CAN_Transmit((CAN_T *)(obj->can), cc, &CMsg); + return CAN_Transmit((CAN_T *)NU_MODBASE(obj->can), cc, &CMsg); } int can_read(can_t *obj, CAN_Message *msg, int handle) { STR_CANMSG_T CMsg; - if(!CAN_Receive((CAN_T *)(obj->can), handle, &CMsg)) + if(!CAN_Receive((CAN_T *)NU_MODBASE(obj->can), handle, &CMsg)) return 0; msg->format = (CANFormat)CMsg.IdType; @@ -226,32 +227,34 @@ int can_read(can_t *obj, CAN_Message *msg, int handle) int can_mode(can_t *obj, CanMode mode) { + CAN_T *can_base = (CAN_T *) NU_MODBASE(obj->can); + int success = 0; switch (mode) { case MODE_RESET: - CAN_LeaveTestMode((CAN_T*)obj->can); + CAN_LeaveTestMode(can_base); success = 1; break; case MODE_NORMAL: - CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_BASIC_Msk); + CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk); success = 1; break; case MODE_SILENT: - CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk); + CAN_EnterTestMode(can_base, CAN_TEST_SILENT_Msk); success = 1; break; case MODE_TEST_LOCAL: case MODE_TEST_GLOBAL: - CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_LBACK_Msk); + CAN_EnterTestMode(can_base, CAN_TEST_LBACK_Msk); success = 1; break; case MODE_TEST_SILENT: - CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk); + CAN_EnterTestMode(can_base, CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk); success = 1; break; @@ -267,7 +270,7 @@ int can_mode(can_t *obj, CanMode mode) int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) { - return CAN_SetRxMsg((CAN_T *)(obj->can), handle , (uint32_t)format, id); + return CAN_SetRxMsg((CAN_T *)NU_MODBASE(obj->can), handle , (uint32_t)format, id); } @@ -285,19 +288,19 @@ void can_reset(can_t *obj) unsigned char can_rderror(can_t *obj) { - CAN_T *can = (CAN_T *)(obj->can); + CAN_T *can = (CAN_T *)NU_MODBASE(obj->can); return ((can->ERR>>8)&0xFF); } unsigned char can_tderror(can_t *obj) { - CAN_T *can = (CAN_T *)(obj->can); + CAN_T *can = (CAN_T *)NU_MODBASE(obj->can); return ((can->ERR)&0xFF); } void can_monitor(can_t *obj, int silent) { - CAN_EnterTestMode((CAN_T *)(obj->can), CAN_TEST_SILENT_Msk); + CAN_EnterTestMode((CAN_T *)NU_MODBASE(obj->can), CAN_TEST_SILENT_Msk); } #endif // DEVICE_CAN diff --git a/targets/TARGET_NUVOTON/TARGET_M451/dma.h b/targets/TARGET_NUVOTON/TARGET_M451/dma.h index 1faf3c05813..465003246ba 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/dma.h +++ b/targets/TARGET_NUVOTON/TARGET_M451/dma.h @@ -32,6 +32,7 @@ extern "C" { #define DMA_EVENT_MASK DMA_EVENT_ALL void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event); +PDMA_T *dma_modbase(void); #ifdef __cplusplus } diff --git a/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c b/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c index ddecc9ca634..0bfc53f4855 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c @@ -111,6 +111,11 @@ void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t even NVIC_EnableIRQ(dma_modinit.irq_n); } +PDMA_T *dma_modbase(void) +{ + return (PDMA_T *) NU_MODBASE(dma_modinit.modname); +} + static void pdma_vec(void) { uint32_t intsts = PDMA_GET_INT_STATUS(); @@ -165,7 +170,7 @@ static void pdma_vec(void) PDMA->INTSTS = reqto; while (reqto) { - int chn_id = nu_ctz(reqto) >> PDMA_INTSTS_REQTOFn_Pos; + int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFn_Pos; if (dma_chn_mask & (1 << chn_id)) { struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) { diff --git a/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c index f89dc4f6a00..f04d1b8b057 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c @@ -99,9 +99,11 @@ void pwmout_init(pwmout_t* obj, PinName pin) ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn; - // Mark this module to be inited. - int i = modinit - pwm_modinit_tab; - pwm_modinit_mask |= 1 << i; + if (((struct nu_pwm_var *) modinit->var)->en_msk) { + // Mark this module to be inited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask |= 1 << i; + } } void pwmout_free(pwmout_t* obj) @@ -120,9 +122,11 @@ void pwmout_free(pwmout_t* obj) CLK_DisableModuleClock(modinit->clkidx); } - // Mark this module to be deinited. - int i = modinit - pwm_modinit_tab; - pwm_modinit_mask &= ~(1 << i); + if (((struct nu_pwm_var *) modinit->var)->en_msk == 0) { + // Mark this module to be deinited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask &= ~(1 << i); + } } void pwmout_write(pwmout_t* obj, float value) diff --git a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c index 93c9df8a1ba..30eb950285f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c @@ -255,7 +255,7 @@ void serial_free(serial_t *obj) void serial_baud(serial_t *obj, int baudrate) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. - while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); + while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)))); obj->serial.baudrate = baudrate; UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate); @@ -263,7 +263,7 @@ void serial_baud(serial_t *obj, int baudrate) { void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. - while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); + while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)))); // TODO: Assert for not supported parity and data bits obj->serial.databits = data_bits; @@ -325,7 +325,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. - while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); + while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)))); const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); @@ -502,7 +502,9 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == obj->serial.uart); - PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel + PDMA_T *pdma_base = dma_modbase(); + + pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel PDMA_SetTransferMode(obj->serial.dma_chn_id_tx, ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA 0, // Scatter-gather disabled @@ -515,7 +517,7 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx // NUC472: End of source address // M451: Start of source address PDMA_SAR_INC, // Source address incremental - (uint32_t) obj->serial.uart, // Destination address + (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address PDMA_DAR_FIX); // Destination address fixed PDMA_SetBurstType(obj->serial.dma_chn_id_tx, PDMA_REQ_SINGLE, // Single mode @@ -563,7 +565,9 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == obj->serial.uart); - PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel + PDMA_T *pdma_base = dma_modbase(); + + pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel PDMA_SetTransferMode(obj->serial.dma_chn_id_rx, ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA 0, // Scatter-gather disabled @@ -572,7 +576,7 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, rx_length); PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx, - (uint32_t) obj->serial.uart, // Source address + (uint32_t) NU_MODBASE(obj->serial.uart), // Source address PDMA_SAR_FIX, // Source address fixed (uint32_t) rx, // NOTE: // NUC472: End of destination address @@ -593,14 +597,16 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt void serial_tx_abort_asynch(serial_t *obj) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. - while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); + while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)))); if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) { + PDMA_T *pdma_base = dma_modbase(); + if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE); // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. //PDMA_STOP(obj->serial.dma_chn_id_tx); - PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx); + pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx); } UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk); } @@ -615,11 +621,13 @@ void serial_tx_abort_asynch(serial_t *obj) void serial_rx_abort_asynch(serial_t *obj) { if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) { + PDMA_T *pdma_base = dma_modbase(); + if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE); // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. //PDMA_STOP(obj->serial.dma_chn_id_rx); - PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx); + pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx); } UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk); } diff --git a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c index feda823720b..f024bbc3f20 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c @@ -314,8 +314,10 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == obj->spi.spi); + PDMA_T *pdma_base = dma_modbase(); + // Configure tx DMA - PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel + pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel PDMA_SetTransferMode(obj->spi.dma_chn_id_tx, ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA 0, // Scatter-gather disabled @@ -339,7 +341,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); // Configure rx DMA - PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel + pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel PDMA_SetTransferMode(obj->spi.dma_chn_id_rx, ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA 0, // Scatter-gather disabled @@ -380,6 +382,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, void spi_abort_asynch(spi_t *obj) { SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + PDMA_T *pdma_base = dma_modbase(); if (obj->spi.dma_usage != DMA_USAGE_NEVER) { // Receive FIFO Overrun in case of tx length > rx length on DMA way @@ -388,18 +391,18 @@ void spi_abort_asynch(spi_t *obj) } if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { - PDMA_DisableInt(obj->spi.dma_chn_id_tx, 0); + PDMA_DisableInt(obj->spi.dma_chn_id_tx, PDMA_INT_TRANS_DONE); // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. //PDMA_STOP(obj->spi.dma_chn_id_tx); - PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx); + pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx); } SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { - PDMA_DisableInt(obj->spi.dma_chn_id_rx, 0); + PDMA_DisableInt(obj->spi.dma_chn_id_rx, PDMA_INT_TRANS_DONE); // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. //PDMA_STOP(obj->spi.dma_chn_id_rx); - PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx); + pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx); } SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h index 217d66d9019..475bd62678f 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h @@ -23,111 +23,117 @@ extern "C" { #endif -// NOTE: TIMER0_BASE=(APBPERIPH_BASE + 0x10000) -// TIMER1_BASE=(APBPERIPH_BASE + 0x10020) -#define NU_MODNAME(MODBASE, SUBINDEX) ((MODBASE) | (SUBINDEX)) -#define NU_MODBASE(MODNAME) ((MODNAME) & 0xFFFFFFE0) -#define NU_MODSUBINDEX(MODNAME) ((MODNAME) & 0x0000001F) +// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name +// which encodes module base address and module index/subindex. +#define NU_MODSUBINDEX_Pos 0 +#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos) +#define NU_MODINDEX_Pos 20 +#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos) + +#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos)) +#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk)) +#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos) +#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos) #if 0 typedef enum { - GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0), - GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 0), - GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 0), - GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 0), - GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 0), - GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 0), - GPIO_G = (int) NU_MODNAME(GPIOG_BASE, 0), - GPIO_H = (int) NU_MODNAME(GPIOH_BASE, 0), - GPIO_I = (int) NU_MODNAME(GPIOI_BASE, 0) + GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0), + GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0), + GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0), + GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0), + GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0), + GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0), + GPIO_G = (int) NU_MODNAME(GPIOG_BASE, 6, 0), + GPIO_H = (int) NU_MODNAME(GPIOH_BASE, 7, 0), + GPIO_I = (int) NU_MODNAME(GPIOI_BASE, 8, 0) } GPIOName; #endif typedef enum { - ADC_0_0 = (int) NU_MODNAME(EADC_BASE, 0), - ADC_0_1 = (int) NU_MODNAME(EADC_BASE, 1), - ADC_0_2 = (int) NU_MODNAME(EADC_BASE, 2), - ADC_0_3 = (int) NU_MODNAME(EADC_BASE, 3), - ADC_0_4 = (int) NU_MODNAME(EADC_BASE, 4), - ADC_0_5 = (int) NU_MODNAME(EADC_BASE, 5), - ADC_0_6 = (int) NU_MODNAME(EADC_BASE, 6), - ADC_0_7 = (int) NU_MODNAME(EADC_BASE, 7), + ADC_0_0 = (int) NU_MODNAME(EADC_BASE, 0, 0), + ADC_0_1 = (int) NU_MODNAME(EADC_BASE, 0, 1), + ADC_0_2 = (int) NU_MODNAME(EADC_BASE, 0, 2), + ADC_0_3 = (int) NU_MODNAME(EADC_BASE, 0, 3), + ADC_0_4 = (int) NU_MODNAME(EADC_BASE, 0, 4), + ADC_0_5 = (int) NU_MODNAME(EADC_BASE, 0, 5), + ADC_0_6 = (int) NU_MODNAME(EADC_BASE, 0, 6), + ADC_0_7 = (int) NU_MODNAME(EADC_BASE, 0, 7), - ADC_1_0 = (int) NU_MODNAME(EADC_BASE, 8), - ADC_1_1 = (int) NU_MODNAME(EADC_BASE, 9), - ADC_1_2 = (int) NU_MODNAME(EADC_BASE, 10), - ADC_1_3 = (int) NU_MODNAME(EADC_BASE, 11), - ADC_1_4 = (int) NU_MODNAME(EADC_BASE, 12), - ADC_1_5 = (int) NU_MODNAME(EADC_BASE, 13), - ADC_1_6 = (int) NU_MODNAME(EADC_BASE, 14), - ADC_1_7 = (int) NU_MODNAME(EADC_BASE, 15), + ADC_1_0 = (int) NU_MODNAME(EADC_BASE, 1, 0), + ADC_1_1 = (int) NU_MODNAME(EADC_BASE, 1, 1), + ADC_1_2 = (int) NU_MODNAME(EADC_BASE, 1, 2), + ADC_1_3 = (int) NU_MODNAME(EADC_BASE, 1, 3), + ADC_1_4 = (int) NU_MODNAME(EADC_BASE, 1, 4), + ADC_1_5 = (int) NU_MODNAME(EADC_BASE, 1, 5), + ADC_1_6 = (int) NU_MODNAME(EADC_BASE, 1, 6), + ADC_1_7 = (int) NU_MODNAME(EADC_BASE, 1, 7), } ADCName; typedef enum { - UART_0 = (int) NU_MODNAME(UART0_BASE, 0), - UART_1 = (int) NU_MODNAME(UART1_BASE, 0), - UART_2 = (int) NU_MODNAME(UART2_BASE, 0), - UART_3 = (int) NU_MODNAME(UART3_BASE, 0), - UART_4 = (int) NU_MODNAME(UART4_BASE, 0), - UART_5 = (int) NU_MODNAME(UART5_BASE, 0), + UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0), + UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0), + UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0), + UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0), + UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0), + UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0), // FIXME: board-specific STDIO_UART = UART_3 } UARTName; typedef enum { - SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0), - SPI_1 = (int) NU_MODNAME(SPI1_BASE, 0), - SPI_2 = (int) NU_MODNAME(SPI2_BASE, 0), - SPI_3 = (int) NU_MODNAME(SPI3_BASE, 0) + SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0), + SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0), + SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0), + SPI_3 = (int) NU_MODNAME(SPI3_BASE, 3, 0) } SPIName; typedef enum { - I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0), - I2C_1 = (int) NU_MODNAME(I2C1_BASE, 0), - I2C_2 = (int) NU_MODNAME(I2C2_BASE, 0), - I2C_3 = (int) NU_MODNAME(I2C3_BASE, 0), - I2C_4 = (int) NU_MODNAME(I2C4_BASE, 0) + I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0), + I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0), + I2C_2 = (int) NU_MODNAME(I2C2_BASE, 2, 0), + I2C_3 = (int) NU_MODNAME(I2C3_BASE, 3, 0), + I2C_4 = (int) NU_MODNAME(I2C4_BASE, 4, 0) } I2CName; typedef enum { - PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0), - PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 1), - PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 2), - PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 3), - PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 4), - PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 5), + PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0, 0), + PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 0, 1), + PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 0, 2), + PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 0, 3), + PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 0, 4), + PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 0, 5), - PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 0), - PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1), - PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 2), - PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 3), - PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 4), - PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 5) + PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 1, 0), + PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1, 1), + PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 1, 2), + PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 1, 3), + PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 1, 4), + PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 1, 5) } PWMName; typedef enum { - TIMER_0 = (int) NU_MODNAME(TIMER0_BASE, 0), - TIMER_1 = (int) NU_MODNAME(TIMER1_BASE, 0), - TIMER_2 = (int) NU_MODNAME(TIMER2_BASE, 0), - TIMER_3 = (int) NU_MODNAME(TIMER3_BASE, 0) + TIMER_0 = (int) NU_MODNAME(TIMER0_BASE, 0, 0), + TIMER_1 = (int) NU_MODNAME(TIMER1_BASE, 1, 0), + TIMER_2 = (int) NU_MODNAME(TIMER2_BASE, 2, 0), + TIMER_3 = (int) NU_MODNAME(TIMER3_BASE, 3, 0) } TIMERName; typedef enum { - RTC_0 = (int) NU_MODNAME(RTC_BASE, 0) + RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0) } RTCName; typedef enum { - DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0) + DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0, 0) } DMAName; typedef enum { - SD_0_0 = (int) NU_MODNAME(SD_BASE, 0), - SD_0_1 = (int) NU_MODNAME(SD_BASE, 1) + SD_0_0 = (int) NU_MODNAME(SD_BASE, 0, 0), + SD_0_1 = (int) NU_MODNAME(SD_BASE, 0, 1) } SDName; typedef enum { - CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0), - CAN_1 = (int) NU_MODNAME(CAN1_BASE, 0) + CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0, 0), + CAN_1 = (int) NU_MODNAME(CAN1_BASE, 1, 0) } CANName; #ifdef __cplusplus diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h index 6bba3511ce4..7e874f327ba 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h @@ -22,13 +22,32 @@ extern "C" { #endif -#define NU_PORT_SHIFT 12 -#define NU_PINNAME_TO_PORT(name) ((unsigned int)(name) >> NU_PORT_SHIFT) -#define NU_PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << NU_PORT_SHIFT)) -#define NU_PORT_N_PIN_TO_PINNAME(port, pin) ((((unsigned int) (port)) << (NU_PORT_SHIFT)) | ((unsigned int) (pin))) -#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port)) -#define NU_MFP_POS(pin) ((pin % 8) * 4) -#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin)) +#define NU_PININDEX_Pos 0 +#define NU_PININDEX_Msk (0xFFul << NU_PININDEX_Pos) +#define NU_PINPORT_Pos 8 +#define NU_PINPORT_Msk (0xFul << NU_PINPORT_Pos) +#define NU_PIN_MODINDEX_Pos 12 +#define NU_PIN_MODINDEX_Msk (0xFul << NU_PIN_MODINDEX_Pos) +#define NU_PIN_BIND_Pos 16 +#define NU_PIN_BIND_Msk (0x1ul << NU_PIN_BIND_Pos) + +#define NU_PININDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos) +#define NU_PINPORT(PINNAME) (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos) +#define NU_PIN_BIND(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos) +#define NU_PIN_MODINDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos) +#define NU_PINNAME(PORT, PIN) ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos)) +#define NU_PINNAME_BIND(PINNAME, modname) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname) +#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk) + +#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port)) +#define NU_MFP_POS(pin) ((pin % 8) * 4) +#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin)) + +// LEGACY +#define NU_PINNAME_TO_PIN(PINNAME) NU_PININDEX(PINNAME) +#define NU_PINNAME_TO_PORT(PINNAME) NU_PINPORT(PINNAME) +#define NU_PINNAME_TO_MODSUBINDEX(PINNAME) NU_PIN_MODINDEX(PINNAME) +#define NU_PORT_N_PIN_TO_PINNAME(PORT, PIN) NU_PINNAME((PORT), (PIN)) typedef enum { PIN_INPUT, diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/analogin_api.c index a3039cb1509..73ac4fa4372 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/analogin_api.c @@ -70,25 +70,27 @@ void analogin_init(analogin_t *obj, PinName pin) EADC_Open(eadc_base, 0); } - uint32_t chn = NU_MODSUBINDEX(obj->adc); + uint32_t smp_chn = NU_MODSUBINDEX(obj->adc); + uint32_t smp_mod = NU_MODINDEX(obj->adc) * 8 + smp_chn; // Wire pinout pinmap_pinout(pin, PinMap_ADC); // Configure the sample module Nmod for analog input channel Nch and software trigger source - EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn % 8); + EADC_ConfigSampleModule(eadc_base, smp_mod, EADC_SOFTWARE_TRIGGER, smp_chn); - eadc_modinit_mask |= 1 << chn; + eadc_modinit_mask |= 1 << smp_mod; } uint16_t analogin_read_u16(analogin_t *obj) { EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc); - uint32_t chn = NU_MODSUBINDEX(obj->adc); + uint32_t smp_chn = NU_MODSUBINDEX(obj->adc); + uint32_t smp_mod = NU_MODINDEX(obj->adc) * 8 + smp_chn; - EADC_START_CONV(eadc_base, 1 << chn); - while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != (1 << chn)); - uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn); + EADC_START_CONV(eadc_base, 1 << smp_mod); + while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << smp_mod) != (1 << smp_mod)); + uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, smp_mod); // Just 12 bits are effective. Convert to 16 bits. // conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0 // conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8 diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c index 0f8fd1c295c..ad4d30582b0 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c @@ -75,7 +75,7 @@ PA2 = 0x00; PA3 = 0x00; - CAN_Open((CAN_T *)obj->can, 500000, CAN_NORMAL_MODE); + CAN_Open((CAN_T *)NU_MODBASE(obj->can), 500000, CAN_NORMAL_MODE); can_filter(obj, 0, 0, CANStandard, 0); } @@ -97,9 +97,9 @@ void can_free(can_t *obj) int can_frequency(can_t *obj, int hz) { - CAN_SetBaudRate((CAN_T *)obj->can, hz); + CAN_SetBaudRate((CAN_T *)NU_MODBASE(obj->can), hz); - return CAN_GetCANBitRate((CAN_T *)obj->can); + return CAN_GetCANBitRate((CAN_T *)NU_MODBASE(obj->can)); } static void can_irq(CANName name, int id) @@ -188,7 +188,7 @@ void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) void can_irq_free(can_t *obj) { - CAN_DisableInt((CAN_T *)obj->can, (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk)); + CAN_DisableInt((CAN_T *)NU_MODBASE(obj->can), (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk)); can_irq_ids[obj->index] = 0; @@ -202,25 +202,26 @@ void can_irq_free(can_t *obj) void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable) { + CAN_T *can_base = (CAN_T *) NU_MODBASE(obj->can); - CAN_EnterInitMode((CAN_T*)obj->can); + CAN_EnterInitMode((CAN_T*)can_base); - ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON ) | ((enable != 0 )? CAN_CON_IE_Msk :0); + ((CAN_T *)can_base)->CON = (((CAN_T *)can_base)->CON ) | ((enable != 0 )? CAN_CON_IE_Msk :0); switch (irq) { case IRQ_ERROR: case IRQ_BUS: case IRQ_PASSIVE: - ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_EIE_Msk; - ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk; + can_base->CON = can_base->CON |CAN_CON_EIE_Msk; + can_base->CON = can_base->CON |CAN_CON_SIE_Msk; break; case IRQ_RX: case IRQ_TX: case IRQ_OVERRUN: case IRQ_WAKEUP: - ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk; + can_base->CON = can_base->CON |CAN_CON_SIE_Msk; break; default: @@ -228,7 +229,7 @@ void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable) } - CAN_LeaveInitMode((CAN_T*)obj->can); + CAN_LeaveInitMode(can_base); if(!obj->index) { @@ -253,14 +254,14 @@ int can_write(can_t *obj, CAN_Message msg, int cc) CMsg.DLC = msg.len; memcpy((void *)&CMsg.Data[0],(const void *)&msg.data[0], (unsigned int)8); - return CAN_Transmit((CAN_T *)(obj->can), cc, &CMsg); + return CAN_Transmit((CAN_T *)NU_MODBASE(obj->can), cc, &CMsg); } int can_read(can_t *obj, CAN_Message *msg, int handle) { STR_CANMSG_T CMsg; - if(!CAN_Receive((CAN_T *)(obj->can), handle, &CMsg)) + if(!CAN_Receive((CAN_T *)NU_MODBASE(obj->can), handle, &CMsg)) return 0; msg->format = (CANFormat)CMsg.IdType; @@ -274,32 +275,34 @@ int can_read(can_t *obj, CAN_Message *msg, int handle) int can_mode(can_t *obj, CanMode mode) { + CAN_T *can_base = (CAN_T *) NU_MODBASE(obj->can); + int success = 0; switch (mode) { case MODE_RESET: - CAN_LeaveTestMode((CAN_T*)obj->can); + CAN_LeaveTestMode(can_base); success = 1; break; case MODE_NORMAL: - CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_BASIC_Msk); + CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk); success = 1; break; case MODE_SILENT: - CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk); + CAN_EnterTestMode(can_base, CAN_TEST_SILENT_Msk); success = 1; break; case MODE_TEST_LOCAL: case MODE_TEST_GLOBAL: - CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_LBACK_Msk); + CAN_EnterTestMode(can_base, CAN_TEST_LBACK_Msk); success = 1; break; case MODE_TEST_SILENT: - CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk); + CAN_EnterTestMode(can_base, CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk); success = 1; break; @@ -315,7 +318,7 @@ int can_mode(can_t *obj, CanMode mode) int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) { - return CAN_SetRxMsg((CAN_T *)(obj->can), handle , (uint32_t)format, id); + return CAN_SetRxMsg((CAN_T *)NU_MODBASE(obj->can), handle , (uint32_t)format, id); } @@ -333,19 +336,19 @@ void can_reset(can_t *obj) unsigned char can_rderror(can_t *obj) { - CAN_T *can = (CAN_T *)(obj->can); + CAN_T *can = (CAN_T *)NU_MODBASE(obj->can); return ((can->ERR>>8)&0xFF); } unsigned char can_tderror(can_t *obj) { - CAN_T *can = (CAN_T *)(obj->can); + CAN_T *can = (CAN_T *)NU_MODBASE(obj->can); return ((can->ERR)&0xFF); } void can_monitor(can_t *obj, int silent) { - CAN_EnterTestMode((CAN_T *)(obj->can), CAN_TEST_SILENT_Msk); + CAN_EnterTestMode((CAN_T *)NU_MODBASE(obj->can), CAN_TEST_SILENT_Msk); } #endif // DEVICE_CAN diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/dma.h b/targets/TARGET_NUVOTON/TARGET_NUC472/dma.h index 1faf3c05813..465003246ba 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/dma.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/dma.h @@ -32,6 +32,7 @@ extern "C" { #define DMA_EVENT_MASK DMA_EVENT_ALL void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event); +PDMA_T *dma_modbase(void); #ifdef __cplusplus } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/dma_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/dma_api.c index 11c0f52b8ed..1b789090f3c 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/dma_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/dma_api.c @@ -111,6 +111,11 @@ void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t even NVIC_EnableIRQ(dma_modinit.irq_n); } +PDMA_T *dma_modbase(void) +{ + return (PDMA_T *) NU_MODBASE(dma_modinit.modname); +} + static void pdma_vec(void) { uint32_t intsts = PDMA_GET_INT_STATUS(); @@ -165,7 +170,7 @@ static void pdma_vec(void) PDMA->INTSTS = reqto; while (reqto) { - int chn_id = nu_ctz(reqto) >> PDMA_INTSTS_REQTOFX_Pos; + int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFX_Pos; if (dma_chn_mask & (1 << chn_id)) { struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) { diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c index 90165697c63..2ca1cd49cd3 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c @@ -105,9 +105,11 @@ void pwmout_init(pwmout_t* obj, PinName pin) ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn; - // Mark this module to be inited. - int i = modinit - pwm_modinit_tab; - pwm_modinit_mask |= 1 << i; + if (((struct nu_pwm_var *) modinit->var)->en_msk) { + // Mark this module to be inited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask |= 1 << i; + } } void pwmout_free(pwmout_t* obj) @@ -143,9 +145,11 @@ void pwmout_free(pwmout_t* obj) } } - // Mark this module to be deinited. - int i = modinit - pwm_modinit_tab; - pwm_modinit_mask &= ~(1 << i); + if (((struct nu_pwm_var *) modinit->var)->en_msk == 0) { + // Mark this module to be deinited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask &= ~(1 << i); + } } void pwmout_write(pwmout_t* obj, float value) diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c index e18938aafe8..13bae2a9665 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c @@ -285,7 +285,7 @@ void serial_free(serial_t *obj) void serial_baud(serial_t *obj, int baudrate) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. - while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); + while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)))); obj->serial.baudrate = baudrate; UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate); @@ -293,7 +293,7 @@ void serial_baud(serial_t *obj, int baudrate) { void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. - while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); + while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)))); // TODO: Assert for not supported parity and data bits obj->serial.databits = data_bits; @@ -357,7 +357,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. - while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); + while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)))); const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); @@ -544,7 +544,9 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == obj->serial.uart); - PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel + PDMA_T *pdma_base = dma_modbase(); + + pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel PDMA_SetTransferMode(obj->serial.dma_chn_id_tx, ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA 0, // Scatter-gather disabled @@ -555,7 +557,7 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx, ((uint32_t) tx) + (tx_width / 8) * tx_length, // NOTE: End of source address PDMA_SAR_INC, // Source address incremental - (uint32_t) obj->serial.uart, // Destination address + (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address PDMA_DAR_FIX); // Destination address fixed PDMA_SetBurstType(obj->serial.dma_chn_id_tx, PDMA_REQ_SINGLE, // Single mode @@ -603,7 +605,9 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == obj->serial.uart); - PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel + PDMA_T *pdma_base = dma_modbase(); + + pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel PDMA_SetTransferMode(obj->serial.dma_chn_id_rx, ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA 0, // Scatter-gather disabled @@ -612,7 +616,7 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, rx_length); PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx, - (uint32_t) obj->serial.uart, // Source address + (uint32_t) NU_MODBASE(obj->serial.uart), // Source address PDMA_SAR_FIX, // Source address fixed ((uint32_t) rx) + (rx_width / 8) * rx_length, // NOTE: End of destination address PDMA_DAR_INC); // Destination address incremental @@ -631,14 +635,16 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt void serial_tx_abort_asynch(serial_t *obj) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. - while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart))); + while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)))); if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) { + PDMA_T *pdma_base = dma_modbase(); + if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { PDMA_DisableInt(obj->serial.dma_chn_id_tx, 0); // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. //PDMA_STOP(obj->serial.dma_chn_id_tx); - PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx); + pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx); } UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk); } @@ -653,11 +659,13 @@ void serial_tx_abort_asynch(serial_t *obj) void serial_rx_abort_asynch(serial_t *obj) { if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) { + PDMA_T *pdma_base = dma_modbase(); + if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { PDMA_DisableInt(obj->serial.dma_chn_id_rx, 0); // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. //PDMA_STOP(obj->serial.dma_chn_id_rx); - PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx); + pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx); } UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk); } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c index 368e4ca5131..2a9cf5d77cd 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c @@ -317,8 +317,10 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == obj->spi.spi); + PDMA_T *pdma_base = dma_modbase(); + // Configure tx DMA - PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel + pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel PDMA_SetTransferMode(obj->spi.dma_chn_id_tx, ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA 0, // Scatter-gather disabled @@ -340,7 +342,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); // Configure rx DMA - PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel + pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel PDMA_SetTransferMode(obj->spi.dma_chn_id_rx, ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA 0, // Scatter-gather disabled @@ -379,6 +381,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, void spi_abort_asynch(spi_t *obj) { SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + PDMA_T *pdma_base = dma_modbase(); if (obj->spi.dma_usage != DMA_USAGE_NEVER) { // Receive FIFO Overrun in case of tx length > rx length on DMA way @@ -390,7 +393,7 @@ void spi_abort_asynch(spi_t *obj) PDMA_DisableInt(obj->spi.dma_chn_id_tx, 0); // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. //PDMA_STOP(obj->spi.dma_chn_id_tx); - PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx); + pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx); } SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); @@ -398,7 +401,7 @@ void spi_abort_asynch(spi_t *obj) PDMA_DisableInt(obj->spi.dma_chn_id_rx, 0); // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. //PDMA_STOP(obj->spi.dma_chn_id_rx); - PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx); + pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx); } SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); } diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h index 41b0f6b4f8c..61305788c75 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h @@ -37,6 +37,7 @@ extern "C" { #endif typedef enum { + NC = (int)0xFFFFFFFF, GPIO0 = 0, GPIO1, GPIO2, @@ -59,6 +60,8 @@ typedef enum { A1, A2, A3, + A4 = NC, + A5 = NC, UART1_TX = GPIO0, UART1_RX = GPIO1, UART2_TX = GPIO8, @@ -146,8 +149,7 @@ typedef enum { D12 = GPIO16, D13 = GPIO14, D14 = GPIO3, - D15 = GPIO2, - NC = (int)0xFFFFFFFF + D15 = GPIO2 } PinName; typedef enum { diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c index 5a01b365b6a..29ab895021c 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c @@ -88,7 +88,7 @@ void analogin_init(analogin_t *obj, PinName pin) /* Single sample, absolute conversion, scale = 1 */ obj->adcReg->CONTROL.WORD = ((0 << ADC_CONTROL_MODE_BIT_POS) | (1 << ADC_CONTROL_MEASTYPE_BIT_POS) | - (1 << ADC_CONTROL_INPUTSCALE_BIT_POS) | + (6 << ADC_CONTROL_INPUTSCALE_BIT_POS) | (((uint8_t)adc_pin) << ADC_CONTROL_MEAS_CH_BIT_POS)); /* Prescaler enabled; set to 7 */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c index e312a058c9e..3dff1c42d83 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c @@ -398,10 +398,11 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b break; } - obj->serial.uart->SCSMR = data_bits << 6 - | parity_enable << 5 - | parity_select << 4 - | stop_bits << 3; + obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0078) + | (data_bits << 6) + | (parity_enable << 5) + | (parity_select << 4) + | (stop_bits << 3); } /****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralPins.c index ee6d564faa5..1f99dd21f92 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralPins.c @@ -226,13 +226,13 @@ const PinMap PinMap_SPI_SSEL[] = { }; const PinMap PinMap_CAN_RD[] = { -// {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, // Not available in 32 pins package + {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, {NC, NC, 0} }; const PinMap PinMap_CAN_TD[] = { -// {PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, // Not available in 32 pins package + {PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf index c2b9d0d7f88..94c7d061c01 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf @@ -15,9 +15,9 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF; /*-Sizes-*/ -/*Heap 1/2 of ram and stack 1/8*/ +/*Heap 64K and stack 24K */ define symbol __ICFEDIT_size_cstack__ = 0x6000; -define symbol __ICFEDIT_size_heap__ = 0x18000; +define symbol __ICFEDIT_size_heap__ = 0x10000; /**** End of ICF editor section. ###ICF###*/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/TOOLCHAIN_IAR/stm32f439xx_flash.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/TOOLCHAIN_IAR/stm32f439xx_flash.icf index c2b9d0d7f88..9a41a3c0c50 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/TOOLCHAIN_IAR/stm32f439xx_flash.icf +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/TOOLCHAIN_IAR/stm32f439xx_flash.icf @@ -15,9 +15,9 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF; /*-Sizes-*/ -/*Heap 1/2 of ram and stack 1/8*/ +/*Heap 64kB and stack 24kB */ define symbol __ICFEDIT_size_cstack__ = 0x6000; -define symbol __ICFEDIT_size_heap__ = 0x18000; +define symbol __ICFEDIT_size_heap__ = 0x10000; /**** End of ICF editor section. ###ICF###*/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_stm32f7xx.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_stm32f7xx.c index d3e86e4039a..f46b2607417 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_stm32f7xx.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_stm32f7xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f7xx.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c index ae2c75da2d6..e72f2632009 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f7xx.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h index c981d2a6124..01fa1b8f61f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f746xx.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. * * This file contains: @@ -48,21 +48,21 @@ /** @addtogroup stm32f746xx * @{ */ - + #ifndef __STM32F746xx_H #define __STM32F746xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ - + /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** - * @brief STM32F7xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section + * @brief STM32F7xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section */ typedef enum { @@ -110,7 +110,7 @@ typedef enum I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ @@ -118,7 +118,7 @@ typedef enum USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ @@ -180,7 +180,7 @@ typedef enum */ /** - * @brief Configuration of the Cortex-M7 Processor and Core Peripherals + * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */ #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ @@ -190,23 +190,23 @@ typedef enum #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ - - + + #include "system_stm32f7xx.h" #include /** @addtogroup Peripheral_registers_structures * @{ - */ + */ -/** - * @brief Analog to Digital Converter +/** + * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ @@ -236,8 +236,8 @@ typedef struct } ADC_Common_TypeDef; -/** - * @brief Controller Area Network TxMailBox +/** + * @brief Controller Area Network TxMailBox */ typedef struct @@ -248,10 +248,10 @@ typedef struct __IO uint32_t TDHR; /*!< CAN mailbox data high register */ } CAN_TxMailBox_TypeDef; -/** - * @brief Controller Area Network FIFOMailBox +/** + * @brief Controller Area Network FIFOMailBox */ - + typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ @@ -260,20 +260,20 @@ typedef struct __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox_TypeDef; -/** - * @brief Controller Area Network FilterRegister +/** + * @brief Controller Area Network FilterRegister */ - + typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ } CAN_FilterRegister_TypeDef; -/** - * @brief Controller Area Network +/** + * @brief Controller Area Network */ - + typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ @@ -296,12 +296,12 @@ typedef struct __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; -/** - * @brief HDMI-CEC +/** + * @brief HDMI-CEC */ typedef struct @@ -314,8 +314,8 @@ typedef struct __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ }CEC_TypeDef; -/** - * @brief CRC calculation unit +/** + * @brief CRC calculation unit */ typedef struct @@ -330,7 +330,7 @@ typedef struct __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; -/** +/** * @brief Digital to Analog Converter */ @@ -353,7 +353,7 @@ typedef struct } DAC_TypeDef; -/** +/** * @brief Debug MCU */ @@ -365,7 +365,7 @@ typedef struct __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; -/** +/** * @brief DCMI */ @@ -384,7 +384,7 @@ typedef struct __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; -/** +/** * @brief DMA Controller */ @@ -406,7 +406,7 @@ typedef struct __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; -/** +/** * @brief DMA2D Controller */ @@ -438,7 +438,7 @@ typedef struct } DMA2D_TypeDef; -/** +/** * @brief Ethernet MAC */ @@ -455,7 +455,8 @@ typedef struct uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; /* 11 */ __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; + uint32_t RESERVED1; + __IO uint32_t MACDBGR; __IO uint32_t MACSR; /* 15 */ __IO uint32_t MACIMR; __IO uint32_t MACA0HR; @@ -512,7 +513,7 @@ typedef struct __IO uint32_t DMACHRBAR; } ETH_TypeDef; -/** +/** * @brief External Interrupt/Event Controller */ @@ -526,7 +527,7 @@ typedef struct __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ } EXTI_TypeDef; -/** +/** * @brief FLASH Registers */ @@ -543,28 +544,28 @@ typedef struct -/** +/** * @brief Flexible Memory Controller */ typedef struct { - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; -/** +/** * @brief Flexible Memory Controller Bank1E */ - + typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FMC_Bank1E_TypeDef; -/** +/** * @brief Flexible Memory Controller Bank3 */ - + typedef struct { __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ @@ -574,11 +575,11 @@ typedef struct uint32_t RESERVED0; /*!< Reserved, 0x90 */ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ } FMC_Bank3_TypeDef; - -/** + +/** * @brief Flexible Memory Controller Bank5_6 */ - + typedef struct { __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ @@ -586,10 +587,10 @@ typedef struct __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ -} FMC_Bank5_6_TypeDef; +} FMC_Bank5_6_TypeDef; -/** +/** * @brief General Purpose I/O */ @@ -606,10 +607,10 @@ typedef struct __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ } GPIO_TypeDef; -/** +/** * @brief System configuration controller */ - + typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ @@ -619,14 +620,14 @@ typedef struct __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ } SYSCFG_TypeDef; -/** +/** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ @@ -635,10 +636,10 @@ typedef struct __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; -/** +/** * @brief Independent WATCHDOG */ @@ -652,10 +653,10 @@ typedef struct } IWDG_TypeDef; -/** +/** * @brief LCD-TFT Display Controller */ - + typedef struct { uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ @@ -675,14 +676,14 @@ typedef struct __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ -} LTDC_TypeDef; +} LTDC_TypeDef; -/** +/** * @brief LCD-TFT Display layer x Controller */ - + typedef struct -{ +{ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ @@ -700,7 +701,7 @@ typedef struct } LTDC_Layer_TypeDef; -/** +/** * @brief Power Control */ @@ -713,7 +714,7 @@ typedef struct } PWR_TypeDef; -/** +/** * @brief Reset and Clock Control */ @@ -755,7 +756,7 @@ typedef struct } RCC_TypeDef; -/** +/** * @brief Real-Time Clock */ @@ -763,7 +764,7 @@ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ @@ -816,10 +817,10 @@ typedef struct } RTC_TypeDef; -/** +/** * @brief Serial Audio Interface */ - + typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ @@ -837,22 +838,22 @@ typedef struct __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; -/** +/** * @brief SPDIF-RX Interface */ typedef struct { __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ - __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ - __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ } SPDIFRX_TypeDef; -/** +/** * @brief SD host Interface */ @@ -880,7 +881,7 @@ typedef struct __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ } SDMMC_TypeDef; -/** +/** * @brief Serial Peripheral Interface */ @@ -897,7 +898,7 @@ typedef struct __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; -/** +/** * @brief QUAD Serial Peripheral Interface */ @@ -913,12 +914,12 @@ typedef struct __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ - __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ - __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ } QUADSPI_TypeDef; -/** +/** * @brief TIM */ @@ -951,7 +952,7 @@ typedef struct } TIM_TypeDef; -/** +/** * @brief LPTIMIMER */ typedef struct @@ -967,18 +968,18 @@ typedef struct } LPTIM_TypeDef; -/** +/** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ - + typedef struct { - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ @@ -987,7 +988,7 @@ typedef struct } USART_TypeDef; -/** +/** * @brief Window WATCHDOG */ @@ -999,11 +1000,11 @@ typedef struct } WWDG_TypeDef; -/** +/** * @brief RNG */ - -typedef struct + +typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ @@ -1014,7 +1015,7 @@ typedef struct * @} */ -/** +/** * @brief USB_OTG_Core_Registers */ typedef struct @@ -1036,7 +1037,7 @@ typedef struct __IO uint32_t CID; /*!< User ID Register 03Ch */ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ - uint32_t Reserved6; /*!< Reserved 050h */ + uint32_t Reserved6; /*!< Reserved 050h */ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ @@ -1047,10 +1048,10 @@ typedef struct } USB_OTG_GlobalTypeDef; -/** +/** * @brief USB_OTG_device_Registers */ -typedef struct +typedef struct { __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ __IO uint32_t DCTL; /*!< dev Control Register 804h */ @@ -1067,18 +1068,18 @@ typedef struct __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ uint32_t Reserved40; /*!< dedicated EP mask 840h */ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ } USB_OTG_DeviceTypeDef; -/** +/** * @brief USB_OTG_IN_Endpoint-Specific_Register */ -typedef struct +typedef struct { __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ @@ -1091,10 +1092,10 @@ typedef struct } USB_OTG_INEndpointTypeDef; -/** +/** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ -typedef struct +typedef struct { __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ @@ -1106,10 +1107,10 @@ typedef struct } USB_OTG_OUTEndpointTypeDef; -/** +/** * @brief USB_OTG_Host_Mode_Register_Structures */ -typedef struct +typedef struct { __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ @@ -1120,7 +1121,7 @@ typedef struct __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ } USB_OTG_HostTypeDef; -/** +/** * @brief USB_OTG_Host_Channel_Specific_Registers */ typedef struct @@ -1144,8 +1145,8 @@ typedef struct * @{ */ #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ -#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */ -#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ +#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */ #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */ #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */ @@ -1155,6 +1156,8 @@ typedef struct #define SRAM1_BASE 0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */ #define SRAM2_BASE 0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ #define FLASH_END 0x080FFFFFU /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */ /* Legacy define */ #define FLASH_BASE FLASHAXI_BASE @@ -1243,7 +1246,10 @@ typedef struct #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */ #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */ -#define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +/* Legacy define */ +#define PACKAGESIZE_BASE PACKAGE_BASE + #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) @@ -1300,10 +1306,10 @@ typedef struct /** * @} */ - + /** @addtogroup Peripheral_declaration * @{ - */ + */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) @@ -1332,7 +1338,8 @@ typedef struct #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define CEC ((CEC_TypeDef *) CEC_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ #define UART7 ((USART_TypeDef *) UART7_BASE) #define UART8 ((USART_TypeDef *) UART8_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) @@ -1343,8 +1350,9 @@ typedef struct #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) @@ -1394,7 +1402,7 @@ typedef struct #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) #define DCMI ((DCMI_TypeDef *) DCMI_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) @@ -1414,11 +1422,11 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ - + /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ @@ -1429,334 +1437,532 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD 0x00000001U /*! /** @addtogroup Peripheral_registers_structures * @{ - */ + */ -/** - * @brief Analog to Digital Converter +/** + * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ @@ -237,8 +237,8 @@ typedef struct } ADC_Common_TypeDef; -/** - * @brief Controller Area Network TxMailBox +/** + * @brief Controller Area Network TxMailBox */ typedef struct @@ -249,10 +249,10 @@ typedef struct __IO uint32_t TDHR; /*!< CAN mailbox data high register */ } CAN_TxMailBox_TypeDef; -/** - * @brief Controller Area Network FIFOMailBox +/** + * @brief Controller Area Network FIFOMailBox */ - + typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ @@ -261,20 +261,20 @@ typedef struct __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox_TypeDef; -/** - * @brief Controller Area Network FilterRegister +/** + * @brief Controller Area Network FilterRegister */ - + typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ } CAN_FilterRegister_TypeDef; -/** - * @brief Controller Area Network +/** + * @brief Controller Area Network */ - + typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ @@ -297,12 +297,12 @@ typedef struct __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; -/** - * @brief HDMI-CEC +/** + * @brief HDMI-CEC */ typedef struct @@ -315,8 +315,8 @@ typedef struct __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ }CEC_TypeDef; -/** - * @brief CRC calculation unit +/** + * @brief CRC calculation unit */ typedef struct @@ -331,7 +331,7 @@ typedef struct __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; -/** +/** * @brief Digital to Analog Converter */ @@ -354,7 +354,7 @@ typedef struct } DAC_TypeDef; -/** +/** * @brief Debug MCU */ @@ -366,7 +366,7 @@ typedef struct __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; -/** +/** * @brief DCMI */ @@ -385,7 +385,7 @@ typedef struct __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; -/** +/** * @brief DMA Controller */ @@ -407,7 +407,7 @@ typedef struct __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; -/** +/** * @brief DMA2D Controller */ @@ -439,7 +439,7 @@ typedef struct } DMA2D_TypeDef; -/** +/** * @brief Ethernet MAC */ @@ -456,7 +456,8 @@ typedef struct uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; /* 11 */ __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; + uint32_t RESERVED1; + __IO uint32_t MACDBGR; __IO uint32_t MACSR; /* 15 */ __IO uint32_t MACIMR; __IO uint32_t MACA0HR; @@ -513,7 +514,7 @@ typedef struct __IO uint32_t DMACHRBAR; } ETH_TypeDef; -/** +/** * @brief External Interrupt/Event Controller */ @@ -527,7 +528,7 @@ typedef struct __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ } EXTI_TypeDef; -/** +/** * @brief FLASH Registers */ @@ -544,28 +545,28 @@ typedef struct -/** +/** * @brief Flexible Memory Controller */ typedef struct { - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; -/** +/** * @brief Flexible Memory Controller Bank1E */ - + typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FMC_Bank1E_TypeDef; -/** +/** * @brief Flexible Memory Controller Bank3 */ - + typedef struct { __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ @@ -575,11 +576,11 @@ typedef struct uint32_t RESERVED0; /*!< Reserved, 0x90 */ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ } FMC_Bank3_TypeDef; - -/** + +/** * @brief Flexible Memory Controller Bank5_6 */ - + typedef struct { __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ @@ -587,10 +588,10 @@ typedef struct __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ -} FMC_Bank5_6_TypeDef; +} FMC_Bank5_6_TypeDef; -/** +/** * @brief General Purpose I/O */ @@ -607,10 +608,10 @@ typedef struct __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ } GPIO_TypeDef; -/** +/** * @brief System configuration controller */ - + typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ @@ -620,14 +621,14 @@ typedef struct __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ } SYSCFG_TypeDef; -/** +/** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ @@ -636,10 +637,10 @@ typedef struct __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; -/** +/** * @brief Independent WATCHDOG */ @@ -653,10 +654,10 @@ typedef struct } IWDG_TypeDef; -/** +/** * @brief LCD-TFT Display Controller */ - + typedef struct { uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ @@ -676,14 +677,14 @@ typedef struct __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ -} LTDC_TypeDef; +} LTDC_TypeDef; -/** +/** * @brief LCD-TFT Display layer x Controller */ - + typedef struct -{ +{ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ @@ -701,7 +702,7 @@ typedef struct } LTDC_Layer_TypeDef; -/** +/** * @brief Power Control */ @@ -714,7 +715,7 @@ typedef struct } PWR_TypeDef; -/** +/** * @brief Reset and Clock Control */ @@ -756,7 +757,7 @@ typedef struct } RCC_TypeDef; -/** +/** * @brief Real-Time Clock */ @@ -764,7 +765,7 @@ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ @@ -817,10 +818,10 @@ typedef struct } RTC_TypeDef; -/** +/** * @brief Serial Audio Interface */ - + typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ @@ -838,22 +839,22 @@ typedef struct __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; -/** +/** * @brief SPDIF-RX Interface */ typedef struct { __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ - __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ - __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ } SPDIFRX_TypeDef; -/** +/** * @brief SD host Interface */ @@ -881,7 +882,7 @@ typedef struct __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ } SDMMC_TypeDef; -/** +/** * @brief Serial Peripheral Interface */ @@ -898,7 +899,7 @@ typedef struct __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; -/** +/** * @brief QUAD Serial Peripheral Interface */ @@ -914,12 +915,12 @@ typedef struct __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ - __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ - __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ } QUADSPI_TypeDef; -/** +/** * @brief TIM */ @@ -952,7 +953,7 @@ typedef struct } TIM_TypeDef; -/** +/** * @brief LPTIMIMER */ typedef struct @@ -968,18 +969,18 @@ typedef struct } LPTIM_TypeDef; -/** +/** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ - + typedef struct { - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ @@ -988,7 +989,7 @@ typedef struct } USART_TypeDef; -/** +/** * @brief Window WATCHDOG */ @@ -999,7 +1000,7 @@ typedef struct __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; -/** +/** * @brief Crypto Processor */ @@ -1043,11 +1044,11 @@ typedef struct __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ } CRYP_TypeDef; -/** +/** * @brief HASH */ - -typedef struct + +typedef struct { __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ @@ -1059,20 +1060,20 @@ typedef struct __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ } HASH_TypeDef; -/** +/** * @brief HASH_DIGEST */ - -typedef struct + +typedef struct { - __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ } HASH_DIGEST_TypeDef; -/** +/** * @brief RNG */ - -typedef struct + +typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ @@ -1083,7 +1084,7 @@ typedef struct * @} */ -/** +/** * @brief USB_OTG_Core_Registers */ typedef struct @@ -1105,7 +1106,7 @@ typedef struct __IO uint32_t CID; /*!< User ID Register 03Ch */ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ - uint32_t Reserved6; /*!< Reserved 050h */ + uint32_t Reserved6; /*!< Reserved 050h */ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ @@ -1116,10 +1117,10 @@ typedef struct } USB_OTG_GlobalTypeDef; -/** +/** * @brief USB_OTG_device_Registers */ -typedef struct +typedef struct { __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ __IO uint32_t DCTL; /*!< dev Control Register 804h */ @@ -1136,18 +1137,18 @@ typedef struct __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ uint32_t Reserved40; /*!< dedicated EP mask 840h */ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ } USB_OTG_DeviceTypeDef; -/** +/** * @brief USB_OTG_IN_Endpoint-Specific_Register */ -typedef struct +typedef struct { __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ @@ -1160,10 +1161,10 @@ typedef struct } USB_OTG_INEndpointTypeDef; -/** +/** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ -typedef struct +typedef struct { __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ @@ -1175,10 +1176,10 @@ typedef struct } USB_OTG_OUTEndpointTypeDef; -/** +/** * @brief USB_OTG_Host_Mode_Register_Structures */ -typedef struct +typedef struct { __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ @@ -1189,7 +1190,7 @@ typedef struct __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ } USB_OTG_HostTypeDef; -/** +/** * @brief USB_OTG_Host_Channel_Specific_Registers */ typedef struct @@ -1213,8 +1214,8 @@ typedef struct * @{ */ #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ -#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */ -#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ +#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */ #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */ #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */ @@ -1224,6 +1225,8 @@ typedef struct #define SRAM1_BASE 0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */ #define SRAM2_BASE 0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ #define FLASH_END 0x080FFFFFU /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */ /* Legacy define */ #define FLASH_BASE FLASHAXI_BASE @@ -1312,7 +1315,10 @@ typedef struct #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */ #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */ -#define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +/* Legacy define */ +#define PACKAGESIZE_BASE PACKAGE_BASE + #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) @@ -1372,10 +1378,10 @@ typedef struct /** * @} */ - + /** @addtogroup Peripheral_declaration * @{ - */ + */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) @@ -1404,7 +1410,8 @@ typedef struct #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define CEC ((CEC_TypeDef *) CEC_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ #define UART7 ((USART_TypeDef *) UART7_BASE) #define UART8 ((USART_TypeDef *) UART8_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) @@ -1415,8 +1422,9 @@ typedef struct #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) @@ -1466,7 +1474,7 @@ typedef struct #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) #define DCMI ((DCMI_TypeDef *) DCMI_BASE) #define CRYP ((CRYP_TypeDef *) CRYP_BASE) @@ -1489,11 +1497,11 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ - + /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ @@ -1504,334 +1512,532 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD 0x00000001U /*! /** @addtogroup Peripheral_registers_structures * @{ - */ + */ -/** - * @brief Analog to Digital Converter +/** + * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ @@ -247,8 +247,8 @@ typedef struct } ADC_Common_TypeDef; -/** - * @brief Controller Area Network TxMailBox +/** + * @brief Controller Area Network TxMailBox */ typedef struct @@ -259,10 +259,10 @@ typedef struct __IO uint32_t TDHR; /*!< CAN mailbox data high register */ } CAN_TxMailBox_TypeDef; -/** - * @brief Controller Area Network FIFOMailBox +/** + * @brief Controller Area Network FIFOMailBox */ - + typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ @@ -271,20 +271,20 @@ typedef struct __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox_TypeDef; -/** - * @brief Controller Area Network FilterRegister +/** + * @brief Controller Area Network FilterRegister */ - + typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ } CAN_FilterRegister_TypeDef; -/** - * @brief Controller Area Network +/** + * @brief Controller Area Network */ - + typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ @@ -307,12 +307,12 @@ typedef struct __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; -/** - * @brief HDMI-CEC +/** + * @brief HDMI-CEC */ typedef struct @@ -325,8 +325,8 @@ typedef struct __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ }CEC_TypeDef; -/** - * @brief CRC calculation unit +/** + * @brief CRC calculation unit */ typedef struct @@ -341,7 +341,7 @@ typedef struct __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; -/** +/** * @brief Digital to Analog Converter */ @@ -398,7 +398,7 @@ typedef struct __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ } DFSDM_Channel_TypeDef; -/** +/** * @brief Debug MCU */ @@ -410,7 +410,7 @@ typedef struct __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; -/** +/** * @brief DCMI */ @@ -429,7 +429,7 @@ typedef struct __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; -/** +/** * @brief DMA Controller */ @@ -451,7 +451,7 @@ typedef struct __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; -/** +/** * @brief DMA2D Controller */ @@ -483,7 +483,7 @@ typedef struct } DMA2D_TypeDef; -/** +/** * @brief Ethernet MAC */ @@ -500,7 +500,8 @@ typedef struct uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; /* 11 */ __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; + uint32_t RESERVED1; + __IO uint32_t MACDBGR; __IO uint32_t MACSR; /* 15 */ __IO uint32_t MACIMR; __IO uint32_t MACA0HR; @@ -557,7 +558,7 @@ typedef struct __IO uint32_t DMACHRBAR; } ETH_TypeDef; -/** +/** * @brief External Interrupt/Event Controller */ @@ -571,7 +572,7 @@ typedef struct __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ } EXTI_TypeDef; -/** +/** * @brief FLASH Registers */ @@ -588,28 +589,28 @@ typedef struct -/** +/** * @brief Flexible Memory Controller */ typedef struct { - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; -/** +/** * @brief Flexible Memory Controller Bank1E */ - + typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FMC_Bank1E_TypeDef; -/** +/** * @brief Flexible Memory Controller Bank3 */ - + typedef struct { __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ @@ -619,11 +620,11 @@ typedef struct uint32_t RESERVED0; /*!< Reserved, 0x90 */ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ } FMC_Bank3_TypeDef; - -/** + +/** * @brief Flexible Memory Controller Bank5_6 */ - + typedef struct { __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ @@ -631,10 +632,10 @@ typedef struct __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ -} FMC_Bank5_6_TypeDef; +} FMC_Bank5_6_TypeDef; -/** +/** * @brief General Purpose I/O */ @@ -651,10 +652,10 @@ typedef struct __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ } GPIO_TypeDef; -/** +/** * @brief System configuration controller */ - + typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ @@ -665,14 +666,14 @@ typedef struct __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ } SYSCFG_TypeDef; -/** +/** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ @@ -681,10 +682,10 @@ typedef struct __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; -/** +/** * @brief Independent WATCHDOG */ @@ -698,10 +699,10 @@ typedef struct } IWDG_TypeDef; -/** +/** * @brief LCD-TFT Display Controller */ - + typedef struct { uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ @@ -721,14 +722,14 @@ typedef struct __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ -} LTDC_TypeDef; +} LTDC_TypeDef; -/** +/** * @brief LCD-TFT Display layer x Controller */ - + typedef struct -{ +{ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ @@ -746,7 +747,7 @@ typedef struct } LTDC_Layer_TypeDef; -/** +/** * @brief Power Control */ @@ -759,7 +760,7 @@ typedef struct } PWR_TypeDef; -/** +/** * @brief Reset and Clock Control */ @@ -801,7 +802,7 @@ typedef struct } RCC_TypeDef; -/** +/** * @brief Real-Time Clock */ @@ -809,7 +810,7 @@ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ @@ -862,10 +863,10 @@ typedef struct } RTC_TypeDef; -/** +/** * @brief Serial Audio Interface */ - + typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ @@ -883,22 +884,22 @@ typedef struct __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; -/** +/** * @brief SPDIF-RX Interface */ typedef struct { __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ - __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ - __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ } SPDIFRX_TypeDef; -/** +/** * @brief SD host Interface */ @@ -926,7 +927,7 @@ typedef struct __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ } SDMMC_TypeDef; -/** +/** * @brief Serial Peripheral Interface */ @@ -943,7 +944,7 @@ typedef struct __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; -/** +/** * @brief QUAD Serial Peripheral Interface */ @@ -959,12 +960,12 @@ typedef struct __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ - __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ - __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ } QUADSPI_TypeDef; -/** +/** * @brief TIM */ @@ -999,7 +1000,7 @@ typedef struct } TIM_TypeDef; -/** +/** * @brief LPTIMIMER */ typedef struct @@ -1015,18 +1016,18 @@ typedef struct } LPTIM_TypeDef; -/** +/** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ - + typedef struct { - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ @@ -1035,7 +1036,7 @@ typedef struct } USART_TypeDef; -/** +/** * @brief Window WATCHDOG */ @@ -1047,11 +1048,11 @@ typedef struct } WWDG_TypeDef; -/** +/** * @brief RNG */ - -typedef struct + +typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ @@ -1062,7 +1063,7 @@ typedef struct * @} */ -/** +/** * @brief USB_OTG_Core_Registers */ typedef struct @@ -1084,7 +1085,7 @@ typedef struct __IO uint32_t CID; /*!< User ID Register 03Ch */ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ - uint32_t Reserved6; /*!< Reserved 050h */ + uint32_t Reserved6; /*!< Reserved 050h */ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ @@ -1095,10 +1096,10 @@ typedef struct } USB_OTG_GlobalTypeDef; -/** +/** * @brief USB_OTG_device_Registers */ -typedef struct +typedef struct { __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ __IO uint32_t DCTL; /*!< dev Control Register 804h */ @@ -1115,18 +1116,18 @@ typedef struct __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ uint32_t Reserved40; /*!< dedicated EP mask 840h */ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ } USB_OTG_DeviceTypeDef; -/** +/** * @brief USB_OTG_IN_Endpoint-Specific_Register */ -typedef struct +typedef struct { __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ @@ -1139,10 +1140,10 @@ typedef struct } USB_OTG_INEndpointTypeDef; -/** +/** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ -typedef struct +typedef struct { __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ @@ -1154,10 +1155,10 @@ typedef struct } USB_OTG_OUTEndpointTypeDef; -/** +/** * @brief USB_OTG_Host_Mode_Register_Structures */ -typedef struct +typedef struct { __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ @@ -1168,7 +1169,7 @@ typedef struct __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ } USB_OTG_HostTypeDef; -/** +/** * @brief USB_OTG_Host_Channel_Specific_Registers */ typedef struct @@ -1193,15 +1194,15 @@ typedef struct __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ - __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ - __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ - __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ - __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ - __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ - __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ - __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ @@ -1231,50 +1232,50 @@ typedef struct __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */ __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */ __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */ - __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */ - __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */ + __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */ + __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */ __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */ - __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */ - uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */ - __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */ - __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */ - __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */ - __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */ - __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */ - __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */ - __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */ - __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */ - __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */ - __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */ - __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */ - __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */ - __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */ - __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */ - __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */ - __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */ - __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */ - __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */ - __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */ - __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */ - __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */ - __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */ - __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */ - __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */ - __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */ - __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */ - __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */ - __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */ - __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */ - __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */ - __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */ - __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */ - __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */ - __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */ - __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */ - __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */ - __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */ - __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */ - __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */ + __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */ + uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */ + __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */ + __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */ + __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */ + __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */ + __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */ + __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */ + __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */ + __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */ + __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */ + __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */ + __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */ + __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */ + __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */ + __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */ + __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */ + __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */ + __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */ + __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */ + __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */ + __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */ + __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */ + __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */ + __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */ + __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */ + __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */ + __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */ + __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */ + __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */ + __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */ + __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */ + __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */ + __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */ + __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */ + __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */ + __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */ + __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */ + __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */ + __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */ + __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */ __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */ __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */ __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */ @@ -1307,8 +1308,8 @@ typedef struct * @{ */ #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ -#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */ -#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ +#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */ #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */ #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */ @@ -1318,6 +1319,8 @@ typedef struct #define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */ #define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ #define FLASH_END 0x081FFFFFU /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */ /* Legacy define */ #define FLASH_BASE FLASHAXI_BASE @@ -1422,7 +1425,10 @@ typedef struct #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */ #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */ -#define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +/* Legacy define */ +#define PACKAGESIZE_BASE PACKAGE_BASE + #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) @@ -1480,10 +1486,10 @@ typedef struct /** * @} */ - + /** @addtogroup Peripheral_declaration * @{ - */ + */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) @@ -1512,7 +1518,8 @@ typedef struct #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define CEC ((CEC_TypeDef *) CEC_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ #define UART7 ((USART_TypeDef *) UART7_BASE) #define UART8 ((USART_TypeDef *) UART8_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) @@ -1523,8 +1530,9 @@ typedef struct #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) @@ -1574,7 +1582,7 @@ typedef struct #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) #define DCMI ((DCMI_TypeDef *) DCMI_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) @@ -1610,11 +1618,11 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ - + /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ @@ -1625,334 +1633,532 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD 0x00000001U /*! /** @addtogroup Peripheral_registers_structures * @{ - */ + */ -/** - * @brief Analog to Digital Converter +/** + * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ @@ -248,8 +248,8 @@ typedef struct } ADC_Common_TypeDef; -/** - * @brief Controller Area Network TxMailBox +/** + * @brief Controller Area Network TxMailBox */ typedef struct @@ -260,10 +260,10 @@ typedef struct __IO uint32_t TDHR; /*!< CAN mailbox data high register */ } CAN_TxMailBox_TypeDef; -/** - * @brief Controller Area Network FIFOMailBox +/** + * @brief Controller Area Network FIFOMailBox */ - + typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ @@ -272,20 +272,20 @@ typedef struct __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox_TypeDef; -/** - * @brief Controller Area Network FilterRegister +/** + * @brief Controller Area Network FilterRegister */ - + typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ } CAN_FilterRegister_TypeDef; -/** - * @brief Controller Area Network +/** + * @brief Controller Area Network */ - + typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ @@ -308,12 +308,12 @@ typedef struct __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; -/** - * @brief HDMI-CEC +/** + * @brief HDMI-CEC */ typedef struct @@ -326,8 +326,8 @@ typedef struct __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ }CEC_TypeDef; -/** - * @brief CRC calculation unit +/** + * @brief CRC calculation unit */ typedef struct @@ -342,7 +342,7 @@ typedef struct __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; -/** +/** * @brief Digital to Analog Converter */ @@ -399,7 +399,7 @@ typedef struct __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ } DFSDM_Channel_TypeDef; -/** +/** * @brief Debug MCU */ @@ -411,7 +411,7 @@ typedef struct __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; -/** +/** * @brief DCMI */ @@ -430,7 +430,7 @@ typedef struct __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; -/** +/** * @brief DMA Controller */ @@ -452,7 +452,7 @@ typedef struct __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; -/** +/** * @brief DMA2D Controller */ @@ -484,7 +484,7 @@ typedef struct } DMA2D_TypeDef; -/** +/** * @brief Ethernet MAC */ @@ -501,7 +501,8 @@ typedef struct uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; /* 11 */ __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; + uint32_t RESERVED1; + __IO uint32_t MACDBGR; __IO uint32_t MACSR; /* 15 */ __IO uint32_t MACIMR; __IO uint32_t MACA0HR; @@ -558,7 +559,7 @@ typedef struct __IO uint32_t DMACHRBAR; } ETH_TypeDef; -/** +/** * @brief External Interrupt/Event Controller */ @@ -572,7 +573,7 @@ typedef struct __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ } EXTI_TypeDef; -/** +/** * @brief FLASH Registers */ @@ -589,28 +590,28 @@ typedef struct -/** +/** * @brief Flexible Memory Controller */ typedef struct { - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; -/** +/** * @brief Flexible Memory Controller Bank1E */ - + typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FMC_Bank1E_TypeDef; -/** +/** * @brief Flexible Memory Controller Bank3 */ - + typedef struct { __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ @@ -620,11 +621,11 @@ typedef struct uint32_t RESERVED0; /*!< Reserved, 0x90 */ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ } FMC_Bank3_TypeDef; - -/** + +/** * @brief Flexible Memory Controller Bank5_6 */ - + typedef struct { __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ @@ -632,10 +633,10 @@ typedef struct __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ -} FMC_Bank5_6_TypeDef; +} FMC_Bank5_6_TypeDef; -/** +/** * @brief General Purpose I/O */ @@ -652,10 +653,10 @@ typedef struct __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ } GPIO_TypeDef; -/** +/** * @brief System configuration controller */ - + typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ @@ -666,14 +667,14 @@ typedef struct __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ } SYSCFG_TypeDef; -/** +/** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ @@ -682,10 +683,10 @@ typedef struct __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; -/** +/** * @brief Independent WATCHDOG */ @@ -699,10 +700,10 @@ typedef struct } IWDG_TypeDef; -/** +/** * @brief LCD-TFT Display Controller */ - + typedef struct { uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ @@ -722,14 +723,14 @@ typedef struct __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ -} LTDC_TypeDef; +} LTDC_TypeDef; -/** +/** * @brief LCD-TFT Display layer x Controller */ - + typedef struct -{ +{ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ @@ -747,7 +748,7 @@ typedef struct } LTDC_Layer_TypeDef; -/** +/** * @brief Power Control */ @@ -760,7 +761,7 @@ typedef struct } PWR_TypeDef; -/** +/** * @brief Reset and Clock Control */ @@ -802,7 +803,7 @@ typedef struct } RCC_TypeDef; -/** +/** * @brief Real-Time Clock */ @@ -810,7 +811,7 @@ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ @@ -863,10 +864,10 @@ typedef struct } RTC_TypeDef; -/** +/** * @brief Serial Audio Interface */ - + typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ @@ -884,22 +885,22 @@ typedef struct __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; -/** +/** * @brief SPDIF-RX Interface */ typedef struct { __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ - __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ - __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ } SPDIFRX_TypeDef; -/** +/** * @brief SD host Interface */ @@ -927,7 +928,7 @@ typedef struct __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ } SDMMC_TypeDef; -/** +/** * @brief Serial Peripheral Interface */ @@ -944,7 +945,7 @@ typedef struct __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; -/** +/** * @brief QUAD Serial Peripheral Interface */ @@ -960,12 +961,12 @@ typedef struct __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ - __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ - __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ } QUADSPI_TypeDef; -/** +/** * @brief TIM */ @@ -1000,7 +1001,7 @@ typedef struct } TIM_TypeDef; -/** +/** * @brief LPTIMIMER */ typedef struct @@ -1016,18 +1017,18 @@ typedef struct } LPTIM_TypeDef; -/** +/** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ - + typedef struct { - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ @@ -1036,7 +1037,7 @@ typedef struct } USART_TypeDef; -/** +/** * @brief Window WATCHDOG */ @@ -1048,11 +1049,11 @@ typedef struct } WWDG_TypeDef; -/** +/** * @brief RNG */ - -typedef struct + +typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ @@ -1063,7 +1064,7 @@ typedef struct * @} */ -/** +/** * @brief USB_OTG_Core_Registers */ typedef struct @@ -1085,7 +1086,7 @@ typedef struct __IO uint32_t CID; /*!< User ID Register 03Ch */ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ - uint32_t Reserved6; /*!< Reserved 050h */ + uint32_t Reserved6; /*!< Reserved 050h */ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ @@ -1096,10 +1097,10 @@ typedef struct } USB_OTG_GlobalTypeDef; -/** +/** * @brief USB_OTG_device_Registers */ -typedef struct +typedef struct { __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ __IO uint32_t DCTL; /*!< dev Control Register 804h */ @@ -1116,18 +1117,18 @@ typedef struct __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ uint32_t Reserved40; /*!< dedicated EP mask 840h */ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ } USB_OTG_DeviceTypeDef; -/** +/** * @brief USB_OTG_IN_Endpoint-Specific_Register */ -typedef struct +typedef struct { __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ @@ -1140,10 +1141,10 @@ typedef struct } USB_OTG_INEndpointTypeDef; -/** +/** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ -typedef struct +typedef struct { __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ @@ -1155,10 +1156,10 @@ typedef struct } USB_OTG_OUTEndpointTypeDef; -/** +/** * @brief USB_OTG_Host_Mode_Register_Structures */ -typedef struct +typedef struct { __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ @@ -1169,7 +1170,7 @@ typedef struct __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ } USB_OTG_HostTypeDef; -/** +/** * @brief USB_OTG_Host_Channel_Specific_Registers */ typedef struct @@ -1194,15 +1195,15 @@ typedef struct __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ - __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ - __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ - __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ - __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ - __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ - __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ - __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ @@ -1232,50 +1233,50 @@ typedef struct __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */ __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */ __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */ - __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */ - __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */ + __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */ + __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */ __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */ - __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */ - uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */ - __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */ - __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */ - __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */ - __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */ - __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */ - __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */ - __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */ - __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */ - __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */ - __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */ - __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */ - __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */ - __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */ - __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */ - __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */ - __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */ - __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */ - __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */ - __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */ - __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */ - __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */ - __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */ - __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */ - __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */ - __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */ - __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */ - __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */ - __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */ - __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */ - __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */ - __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */ - __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */ - __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */ - __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */ - __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */ - __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */ - __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */ - __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */ - __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */ + __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */ + uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */ + __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */ + __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */ + __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */ + __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */ + __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */ + __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */ + __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */ + __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */ + __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */ + __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */ + __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */ + __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */ + __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */ + __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */ + __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */ + __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */ + __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */ + __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */ + __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */ + __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */ + __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */ + __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */ + __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */ + __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */ + __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */ + __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */ + __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */ + __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */ + __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */ + __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */ + __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */ + __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */ + __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */ + __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */ + __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */ + __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */ + __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */ + __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */ + __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */ __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */ __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */ __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */ @@ -1303,7 +1304,7 @@ typedef struct __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */ } MDIOS_TypeDef; -/** +/** * @brief DSI Controller */ @@ -1313,11 +1314,11 @@ typedef struct __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ - __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ - __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ @@ -1331,18 +1332,18 @@ typedef struct __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ - __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ - __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ - __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ - __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ @@ -1366,12 +1367,12 @@ typedef struct __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ - __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ - __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ @@ -1388,8 +1389,8 @@ typedef struct * @{ */ #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ -#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */ -#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ +#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */ #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */ #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */ @@ -1399,6 +1400,8 @@ typedef struct #define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */ #define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ #define FLASH_END 0x081FFFFFU /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */ /* Legacy define */ #define FLASH_BASE FLASHAXI_BASE @@ -1504,7 +1507,10 @@ typedef struct #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */ #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */ -#define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +/* Legacy define */ +#define PACKAGESIZE_BASE PACKAGE_BASE + #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) @@ -1562,10 +1568,10 @@ typedef struct /** * @} */ - + /** @addtogroup Peripheral_declaration * @{ - */ + */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) @@ -1594,7 +1600,8 @@ typedef struct #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define CEC ((CEC_TypeDef *) CEC_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ #define UART7 ((USART_TypeDef *) UART7_BASE) #define UART8 ((USART_TypeDef *) UART8_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) @@ -1605,8 +1612,9 @@ typedef struct #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) @@ -1656,7 +1664,7 @@ typedef struct #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) #define DCMI ((DCMI_TypeDef *) DCMI_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) @@ -1693,11 +1701,11 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ - + /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ @@ -1708,334 +1716,532 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD 0x00000001U /*! -

Update History

-

V1.1.2 / 23-September-2016

+

Update History

V1.2.0 / 30-December-2016

Main -Changes

  • General updates -to fix known defects and enhancements implementation
  • HAL - Cortex update
    • Move HAL_MPU_Disable() and - HAL_MPU_Enable() from stm32f7xx_hal_cortex.h to stm32f7xx_hal_cortex.c
    • Clear the whole MPU control - register in HAL_MPU_Disable() API
  • HAL - CRC update
    • Update HAL_CRC_DeInit() - function to reset IDR register
  • HAL - DMA update
    • Add a check on DMA stream - instance in HAL_DMA_DeInit() API
- -
  • HAL - DSI update
    • Update - HAL_DSI_ConfigHostTimeouts() and HAL_DSI_Init() functions to avoid - scratch in DSI_CCR register
  • HAL ETH update 
    • Fix wrong definitions in driver header file stm32f7_hal_eth.h
  • HAL FLASH update 
    • Update the clearing of error flags
  • HAL - GPIO update 
    • Add GPIO_AF14_LTDC definition
  • HAL - I2C update 
    • Add I2C_FIRST_AND_NEXT_FRAME - for I2C Sequential Transfer Options
  • HAL IRDA update
    • Add IRDA_CLOCKSOURCE_UNDEFINED - define
    • Add - __HAL_IRDA_FLUSH_DRREGISTER() macro for IRDA DR register flush
    • Add macros for specific flag - clear
      • __HAL_IRDA_CLEAR_FLAG()
      • __HAL_IRDA_CLEAR_PEFLAG()
      • __HAL_IRDA_CLEAR_FEFLAG()
      • __HAL_IRDA_CLEAR_NEFLAG()
      • __HAL_IRDA_CLEAR_OREFLAG()
      • __HAL_IRDA_CLEAR_IDLEFLAG()
    • Add new functions and call - backs for Transfer Abort
      • HAL_IRDA_Abort()
      • HAL_IRDA_AbortTransmit()
      • HAL_IRDA_AbortReceive()
      • HAL_IRDA_Abort_IT()
      • HAL_IRDA_AbortTransmit_IT()
      • HAL_IRDA_AbortReceive_IT()
      • HAL_IRDA_AbortCpltCallback()
      • HAL_IRDA_AbortTransmitCpltCallback()
-
      • HAL_IRDA_AbortReceiveCpltCallback()
-
  • HAL - JPEG update 
    • Update the output data - management when HAL_JPEG_Pause() is performed during the last data - sending
    • Update JPEG_FIFO_SIZE - definition
  • HAL - RCC update
    • Enable PWR only if necessary - for LSE configuration in HAL_RCC_OscConfig() API
  • HAL RTC update
    • Update - HAL_RTCEx_SetTimeStamp_IT() function implementation to clear RTC - Timestamp flag
    • Update - HAL_RTCEx_SetTamper_IT() function implementation for better management of - different RTC tampers flags
    • Update - HAL_RTCEx_SetWakeUpTimer_IT() function implementation to clear wake up - timer flag
  • HAL SMARTCARD update
    • Rename NACKState to NACKEnable - in the SMARTCARD_InitTypeDef structure
    • Add macros for specific flag - clear
      • __HAL_SMARTCARD_CLEAR_FLAG()
      • __HAL_SMARTCARD_CLEAR_PEFLAG()
      • __HAL_SMARTCARD_CLEAR_FEFLAG()
      • __HAL_SMARTCARD_CLEAR_NEFLAG() -
      • __HAL_ SMARTCARD_CLEAR_OREFLAG()
      • __HAL_ SMARTCARD_CLEAR_IDLEFLAG()
    • Add new functions and call backs - for Transfer Abort
      • HAL_ SMARTCARD_Abort()
      • HAL_ SMARTCARD_AbortTransmit()
      • HAL_ SMARTCARD_AbortReceive()
      • HAL_ SMARTCARD_Abort_IT()
      • HAL_ SMARTCARD_AbortTransmit_IT()
      • HAL_ SMARTCARD_AbortReceive_IT()
      • HAL_ SMARTCARD_AbortCpltCallback()
      • HAL_ SMARTCARD_AbortTransmitCpltCallback()
      • HAL_ SMARTCARD_AbortReceiveCpltCallback()
  • HAL SPI update
    • Update SPI_EndRxTxTransaction() function to RX FiFo at the end of each transaction
    • Add HAL_SPI_STATE_ABORT in the - HAL_SPI_StateTypeDef enum
    • Add new functions and call - backs for Transfer Abort
      • HAL_SPI_Abort ()
      • HAL_SPI_Abort_IT()
      • HAL_SPI_AbortCpltCallback()
- - - -
  • HAL - UART update
    • Update HAL_UART_Receive_IT() - and HAL_UART_DMAStop() functions implementations to manage Parity error - interrupt
  • HAL - USART update
    • Update HAL_USART_Init() function by removing the clear of CLKEN bit
    • Update HAL_USART_Receive_IT() - and HAL_USART_DMAStop() functions implementations to manage Parity error - interrupt
-
  • HAL USB update
    • Update PENA bit clearing in - OTG_HPRT0 register
-

V1.1.1 / 01-July-2016

+Changes

  • Official release to add the support of STM32F722xx, STM32F723xx, STM32F732xx and STM32F733xx devices
  • Add Low Layer drivers allowing performance and footprint optimization
    • Low +Layer drivers APIs provide register level programming: require deep +knowledge of peripherals described in STM32F7xx Reference Manuals
    • Low +Layer drivers are available for: ADC, Cortex, CRC, DAC, DMA, +DMA2D, EXTI, GPIO, I2C, IWDG, LPTIM, PWR, RCC, RNG, RTC, SPI, TIM, +USART, WWDG peripherals and additionnal Low Level Bus, System and +Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f7xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32f7xx_ll_ppp.h file must be included in user code.
  • General updates +to fix known defects and enhancements implementation
  • Add new HAL MMC and SMBUS drivers
  • HAL Cortex update
    • Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f7xx_hal_cortex.h to stm32f7xx_hal_cortex.c
    • Clear the whole MPU control register in HAL_MPU_Disable() API
  • HAL CRYP update
    • Add support of AES
  • HAL DMA update
    • Add a check on DMA stream instance in HAL_DMA_DeInit() API
  • HAL ETH update 
    • Fix wrong definitions in driver header file stm32f7_hal_eth.h
  • HAL FLASH update
    • Support OTP program operation
    • Add the support of PCROP feature
    • Update the clearing of error flags
  • HAL I2C update
    • Align driver source code with other STM32 families
  • HAL JPEG update 
    • Update the output data management when HAL_JPEG_Pause() is performed during the last data sending
  • HAL RCC update
    • Enable PWR only if necessary for LSE configuration in HAL_RCC_OscConfig() API
    • Rename RCC_LPTIM1CLKSOURCE_PCLK define to RCC_LPTIM1CLKSOURCE_PCLK1
    • Rename RCC_DFSDM1CLKSOURCE_PCLK define to RCC_DFSDM1CLKSOURCE_PCLK2
  • HAL SPI update
    • Clear RX FIFO at the end of each transaction
  • HAL UART update
    • Remove USART_CR2_LINEN bit clearing when initializing in synchronous mode
  • HAL USB update
    • Add support of embedded USB PHY Controller
    • Add support of Battery Charging Detector (BCD) feature
  • LL SDMMC update
    • Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions
  • LL USB update
    • Update PENA bit clearing in OTG_HPRT0 register
  • The following changes done on the HAL drivers require an update on the +application code based on older HAL versions
    • HAL SD update
      • Overall rework of the driver for a more efficient implementation
        • Modify initialization API and structures
        • Modify Read / Write sequences: separate transfer process and SD Cards state management 
        • Adding interrupt mode for Read / Write operations
        • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
      • Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application
    • HAL TIM update
      • Add new AutoReloadPreload field in TIM_Base_InitTypeDef structure
      • Refer to the TIM examples to identify the changes 
    • HAL NAND update
      • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
      • Add new HAL_NAND_ConfigDevice API

V1.1.1 / 01-July-2016

Main Changes

  • HAL DMA update 
    • Update HAL_DMA_PollForTransfer() function implementation to avoid early TIMEOUT error.
  • HAL JPEG update
    • Update HAL_JPEG_ConfigEncoding() function to properly set the ImageHeight and ImageWidth
  • HAL SPI update
    • Update SPI_DMATransmitReceiveCplt() function to properly handle the CRC and avoid conditional statement duplication

V1.1.0 / 22-April-2016

Main @@ -1012,8 +966,8 @@

V1.0.0 / 12-May-2015

Main -Changes

  • First official release for STM32F756xx/746xx/745xx -devices
+Changes

  • First official release for STM32F756xx/746xx/745xx +devices

License

diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h index 8e0d3967bcd..112662abd72 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** @@ -241,9 +241,9 @@ #define DAC1_CHANNEL_1 DAC_CHANNEL_1 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE ((uint32_t)0x00000000U) -#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE @@ -917,48 +917,45 @@ #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK -#define ETH_MMCCR ((uint32_t)0x00000100U) -#define ETH_MMCRIR ((uint32_t)0x00000104U) -#define ETH_MMCTIR ((uint32_t)0x00000108U) -#define ETH_MMCRIMR ((uint32_t)0x0000010CU) -#define ETH_MMCTIMR ((uint32_t)0x00000110U) -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) -#define ETH_MMCTGFCR ((uint32_t)0x00000168U) -#define ETH_MMCRFCECR ((uint32_t)0x00000194U) -#define ETH_MMCRFAECR ((uint32_t)0x00000198U) -#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U -#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ /** * @} @@ -2231,26 +2228,26 @@ #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET @@ -2784,11 +2781,14 @@ #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED #define DfsdmClockSelection Dfsdm1ClockSelection #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE - +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 /** * @} */ @@ -2918,6 +2918,14 @@ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler #endif + +#if defined(STM32F7) || defined(STM32F4) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.c index 9d917614bdb..f4e49eb2fa4 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -68,11 +68,11 @@ * @{ */ /** - * @brief STM32F7xx HAL Driver version number V1.1.2 + * @brief STM32F7xx HAL Driver version number V1.2.0 */ #define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F7xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ -#define __STM32F7xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.h index 9ccadf14cc2..1636e610db2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.c index 2bf59480f7c..953debb17d7 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions @@ -270,7 +270,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h index 84b30b50a78..73ba1ee2e80 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention @@ -88,6 +88,7 @@ typedef struct Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'. + This parameter can be a value of @ref ADC_Scan_mode. This parameter can be set to ENABLE or DISABLE */ uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. This parameter can be a value of @ref ADC_EOCSelection. @@ -135,7 +136,8 @@ typedef struct uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. This parameter can be a value of @ref ADC_channels */ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ + This parameter must be a number between Min_Data = 1 and Max_Data = 16 + This parameter can be a value of @ref ADC_regular_rank */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). @@ -337,6 +339,38 @@ typedef struct * @} */ +/** @defgroup ADC_Scan_mode ADC sequencer scan mode + * @{ + */ +#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */ +#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */ +/** + * @} + */ + +/** @defgroup ADC_regular_rank ADC group regular sequencer rank + * @{ + */ +#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */ +#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */ +#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */ +#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */ +#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */ +#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */ +#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */ +#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */ +#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */ +#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */ +#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */ +#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */ +#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */ +#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */ +#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */ +#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */ +/** + * @} + */ + /** @defgroup ADC_channels ADC Common Channels * @{ */ @@ -705,7 +739,8 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((__REGTRIG__) == ADC_SOFTWARE_START)) #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ - ((__ALIGN__) == ADC_DATAALIGN_LEFT)) + ((__ALIGN__) == ADC_DATAALIGN_LEFT)) + #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \ ((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \ @@ -730,9 +765,29 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) + +#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_2 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_3 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_4 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_5 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_6 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_7 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_8 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_9 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_10) || \ + ((__RANK__) == ADC_REGULAR_RANK_11) || \ + ((__RANK__) == ADC_REGULAR_RANK_12) || \ + ((__RANK__) == ADC_REGULAR_RANK_13) || \ + ((__RANK__) == ADC_REGULAR_RANK_14) || \ + ((__RANK__) == ADC_REGULAR_RANK_15) || \ + ((__RANK__) == ADC_REGULAR_RANK_16)) + +#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ + ((__SCAN_MODE__) == ADC_SCAN_ENABLE)) + #define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF)) #define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16))) -#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16))) #define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8))) #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.c index 6924d019908..605a0bb0b9d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.h index de4bf51c18b..0bd8dd1451b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention @@ -217,7 +217,7 @@ typedef struct * @} */ -/** @defgroup ADCEx_injected_rank ADC Injected Rank +/** @defgroup ADCEx_injected_rank ADC Injected Channel Rank * @{ */ #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U) @@ -333,9 +333,12 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ - ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)) + ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)) +#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) == ADC_INJECTED_RANK_1) || \ + ((__RANK__) == ADC_INJECTED_RANK_2) || \ + ((__RANK__) == ADC_INJECTED_RANK_3) || \ + ((__RANK__) == ADC_INJECTED_RANK_4)) #define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4))) -#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4))) /** * @brief Set the selected injected Channel rank. diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.c index 101d1c09f5b..a074f0c852a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_can.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief CAN HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.h index 2c2ad21b0b9..eef7f1a684e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_can.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention @@ -232,8 +232,8 @@ typedef struct HAL_LockTypeDef Lock; /*!< CAN locking object */ - __IO uint32_t ErrorCode; /*!< CAN Error code */ - + __IO uint32_t ErrorCode; /*!< CAN Error code + This parameter can be a value of @ref CAN_Error_Code */ }CAN_HandleTypeDef; /** @@ -245,7 +245,7 @@ typedef struct * @{ */ -/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code +/** @defgroup CAN_Error_Code CAN Error Code * @{ */ #define HAL_CAN_ERROR_NONE 0x00U /*!< No error */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.c index 1214d723b2b..cdc9743d2ea 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cec.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.h index b542c522505..79fee5fe269 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cec.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention @@ -43,11 +43,11 @@ extern "C" { #endif -#if defined (CEC) - /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" +#if defined (CEC) + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h index dd26352919d..d4a4bdf4795 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_conf.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -95,6 +95,8 @@ #define HAL_DSI_MODULE_ENABLED #define HAL_JPEG_MODULE_ENABLED #define HAL_MDIOS_MODULE_ENABLED +#define HAL_SMBUS_MODULE_ENABLED +#define HAL_MMC_MODULE_ENABLED /* ########################## HSE/HSI Values adaptation ##################### */ @@ -103,7 +105,6 @@ * This value is used by the RCC HAL module to compute the system frequency * (when HSE is used as system clock source, directly or through the PLL). */ -//#if !defined (HSE_VALUE) #if defined(TARGET_DISCO_F746NG) || defined(TARGET_DISCO_F769NI) #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ #else @@ -427,6 +428,14 @@ #include "stm32f7xx_hal_mdios.h" #endif /* HAL_MDIOS_MODULE_ENABLED */ +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.c index e4e9c472093..0c9b5a89656 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cortex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.h index 8cbffabdd9d..381b94f8a27 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cortex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.c index df41c2b6806..bf73da55d47 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.h index 7b276565b5d..bc813d4ec22 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.c index 85e7d0ee3e5..dad16247400 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Extended CRC HAL module driver. * * This file provides firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.h index cff90c2ec6b..2d91fa88ca6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.c index affe5040d32..024e51b027e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief CRYP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: @@ -3815,6 +3815,1367 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) * @} */ #endif /* CRYP */ + +#if defined (AES) + + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup AES AES + * @brief AES HAL module driver. + * @{ + */ + + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private functions --------------------------------------------------------*/ + +/** @defgroup CRYP_Private_Functions CRYP Private Functions + * @{ + */ + +static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CRYP_Exported_Functions CRYP Exported Functions + * @{ + */ + +/** @defgroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and deinitialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRYP according to the specified parameters + in the CRYP_InitTypeDef and creates the associated handle + (+) DeInitialize the CRYP peripheral + (+) Initialize the CRYP MSP (MCU Specific Package) + (+) De-Initialize the CRYP MSP + + [..] + (@) Specific care must be taken to format the key and the Initialization Vector IV! + + [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where + b127 is the MSB and b0 the LSB, the key must be stored in MCU memory + (+) as a sequence of words where the MSB word comes first (occupies the + lowest memory address) + (+) where each word is byte-swapped: + (++) address n+0 : 0b b103 .. b96 b111 .. b104 b119 .. b112 b127 .. b120 + (++) address n+4 : 0b b71 .. b64 b79 .. b72 b87 .. b80 b95 .. b88 + (++) address n+8 : 0b b39 .. b32 b47 .. b40 b55 .. b48 b63 .. b56 + (++) address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24 + [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}. + The 4 32-bit words that make the key must be stored as follows in MCU memory: + (+) address n+0 : 0x B12 B13 B14 B15 + (+) address n+4 : 0x B8 B9 B10 B11 + (+) address n+8 : 0x B4 B5 B6 B7 + (+) address n+C : 0x B0 B1 B2 B3 + [..] which leads to the expected setting + (+) AES_KEYR3 = 0x B15 B14 B13 B12 + (+) AES_KEYR2 = 0x B11 B10 B9 B8 + (+) AES_KEYR1 = 0x B7 B6 B5 B4 + (+) AES_KEYR0 = 0x B3 B2 B1 B0 + + [..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}. + The 8 32-bit words that make the key must be stored as follows in MCU memory: + (+) address n+00 : 0x B28 B29 B30 B31 + (+) address n+04 : 0x B24 B25 B26 B27 + (+) address n+08 : 0x B20 B21 B22 B23 + (+) address n+0C : 0x B16 B17 B18 B19 + (+) address n+10 : 0x B12 B13 B14 B15 + (+) address n+14 : 0x B8 B9 B10 B11 + (+) address n+18 : 0x B4 B5 B6 B7 + (+) address n+1C : 0x B0 B1 B2 B3 + [..] which leads to the expected setting + (+) AES_KEYR7 = 0x B31 B30 B29 B28 + (+) AES_KEYR6 = 0x B27 B26 B25 B24 + (+) AES_KEYR5 = 0x B23 B22 B21 B20 + (+) AES_KEYR4 = 0x B19 B18 B17 B16 + (+) AES_KEYR3 = 0x B15 B14 B13 B12 + (+) AES_KEYR2 = 0x B11 B10 B9 B8 + (+) AES_KEYR1 = 0x B7 B6 B5 B4 + (+) AES_KEYR0 = 0x B3 B2 B1 B0 + + [..] Initialization Vector IV (4 32-bit words) format must follow the same as + that of a 128-bit long key. + + [..] + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CRYP according to the specified + * parameters in the CRYP_InitTypeDef and initialize the associated handle. + * @note Specific care must be taken to format the key and the Initialization Vector IV + * stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations + * hereabove. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) +{ + /* Check the CRYP handle allocation */ + if(hcryp == NULL) + { + return HAL_ERROR; + } + + /* Check the instance */ + assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance)); + + /* Check the parameters */ + assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize)); + assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); + assert_param(IS_CRYP_ALGOMODE(hcryp->Init.OperatingMode)); + /* ChainingMode parameter is irrelevant when mode is set to Key derivation */ + if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION) + { + assert_param(IS_CRYP_CHAINMODE(hcryp->Init.ChainingMode)); + } + assert_param(IS_CRYP_WRITE(hcryp->Init.KeyWriteFlag)); + + /*========================================================*/ + /* Check the proper operating/chaining modes combinations */ + /*========================================================*/ + /* Check the proper chaining when the operating mode is key derivation and decryption */ +#if defined(AES_CR_NPBLB) + if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\ + ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \ + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \ + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))) +#else + if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\ + ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \ + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \ + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))) +#endif + { + return HAL_ERROR; + } + /* Check that key derivation is not set in CMAC mode or CCM mode when applicable */ +#if defined(AES_CR_NPBLB) + if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) + && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)) +#else + if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) + && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) +#endif + { + return HAL_ERROR; + } + + + /*================*/ + /* Initialization */ + /*================*/ + /* Initialization start */ + if(hcryp->State == HAL_CRYP_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcryp->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_CRYP_MspInit(hcryp); + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_CRYP_DISABLE(); + + /*=============================================================*/ + /* AES initialization common to all operating modes */ + /*=============================================================*/ + /* Set the Key size selection */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KEYSIZE, hcryp->Init.KeySize); + + /* Set the default CRYP phase when this parameter is not used. + Phase is updated below in case of GCM/GMAC/CMAC(/CCM) setting. */ + hcryp->Phase = HAL_CRYP_PHASE_NOT_USED; + + + + /*=============================================================*/ + /* Carry on the initialization based on the AES operating mode */ + /*=============================================================*/ + /* Key derivation */ + if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_ALGOMODE_KEYDERIVATION); + + /* Configure the Key registers */ + if (CRYP_SetKey(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + } + else + /* Encryption / Decryption (with or without key derivation) / authentication */ + { + /* Set data type, operating and chaining modes. + In case of GCM or GMAC, data type is forced to 0b00 */ + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode); + } + else + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.DataType|hcryp->Init.OperatingMode|hcryp->Init.ChainingMode); + } + + + /* Specify the encryption/decryption phase in case of Galois counter mode (GCM), + Galois message authentication code (GMAC), cipher message authentication code (CMAC) + or Counter with Cipher Mode (CCM) when applicable */ +#if defined(AES_CR_NPBLB) + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)) +#else + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) +#endif + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, hcryp->Init.GCMCMACPhase); + hcryp->Phase = HAL_CRYP_PHASE_START; + } + + + /* Configure the Key registers if no need to bypass this step */ + if (hcryp->Init.KeyWriteFlag == CRYP_KEY_WRITE_ENABLE) + { + if (CRYP_SetKey(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* If applicable, configure the Initialization Vector */ + if (hcryp->Init.ChainingMode != CRYP_CHAINMODE_AES_ECB) + { + if (CRYP_SetInitVector(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + } + } + +#if defined(AES_CR_NPBLB) + /* Clear NPBLB field */ + CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB); +#endif + + /* Reset CrypInCount and CrypOutCount */ + hcryp->CrypInCount = 0; + hcryp->CrypOutCount = 0; + + /* Reset ErrorCode field */ + hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; + + /* Reset Mode suspension request */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Enable the Peripheral */ + __HAL_CRYP_ENABLE(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CRYP peripheral. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) +{ + /* Check the CRYP handle allocation */ + if(hcryp == NULL) + { + return HAL_ERROR; + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Set the default CRYP phase */ + hcryp->Phase = HAL_CRYP_PHASE_READY; + + /* Reset CrypInCount and CrypOutCount */ + hcryp->CrypInCount = 0; + hcryp->CrypOutCount = 0; + + /* Disable the CRYP Peripheral Clock */ + __HAL_CRYP_DISABLE(); + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_CRYP_MspDeInit(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the CRYP MSP. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize CRYP MSP. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions + * @brief Processing functions. + * +@verbatim + ============================================================================== + ##### AES processing functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Encrypt plaintext using AES algorithm in different chaining modes + (+) Decrypt cyphertext using AES algorithm in different chaining modes + [..] Three processing functions are available: + (+) Polling mode + (+) Interrupt mode + (+) DMA mode + +@endverbatim + * @{ + */ + + +/** + * @brief Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer + * @param Timeout: Specify Timeout value + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout); +} + + +/** + * @brief Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer + * @param Timeout: Specify Timeout value + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout); +} + + +/** + * @brief Encrypt pPlainData in AES CTR encryption mode. The cypher data are available in pCypherData + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer + * @param Timeout: Specify Timeout value + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout); +} + +/** + * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, + * the decyphered data are available in pPlainData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer + * @param Timeout: Specify Timeout value + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout); +} + +/** + * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, + * the decyphered data are available in pPlainData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer + * @param Timeout: Specify Timeout value + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout); +} + +/** + * @brief Decrypt pCypherData in AES CTR decryption mode, + * the decyphered data are available in pPlainData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer + * @param Timeout: Specify Timeout value + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout); +} + +/** + * @brief Encrypt pPlainData in AES ECB encryption mode using Interrupt, + * the cypher data are available in pCypherData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData); +} + +/** + * @brief Encrypt pPlainData in AES CBC encryption mode using Interrupt, + * the cypher data are available in pCypherData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData); +} + + +/** + * @brief Encrypt pPlainData in AES CTR encryption mode using Interrupt, + * the cypher data are available in pCypherData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData); +} + +/** + * @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt, + * the decyphered data are available in pPlainData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer. + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData); +} + +/** + * @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt, + * the decyphered data are available in pPlainData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData); +} + +/** + * @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt, + * the decyphered data are available in pPlainData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData); +} + +/** + * @brief Encrypt pPlainData in AES ECB encryption mode using DMA, + * the cypher data are available in pCypherData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData); +} + + + +/** + * @brief Encrypt pPlainData in AES CBC encryption mode using DMA, + * the cypher data are available in pCypherData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer + * @param Size: Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData); +} + +/** + * @brief Encrypt pPlainData in AES CTR encryption mode using DMA, + * the cypher data are available in pCypherData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer. + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData); +} + +/** + * @brief Decrypt pCypherData in AES ECB decryption mode using DMA, + * the decyphered data are available in pPlainData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData); +} + +/** + * @brief Decrypt pCypherData in AES CBC decryption mode using DMA, + * the decyphered data are available in pPlainData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData); +} + +/** + * @brief Decrypt pCypherData in AES CTR decryption mode using DMA, + * the decyphered data are available in pPlainData. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer + * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer + * @note This API is provided only to maintain compatibility with legacy software. Users should directly + * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + /* Re-initialize AES IP with proper parameters */ + if (HAL_CRYP_DeInit(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT; + hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR; + hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; + if (HAL_CRYP_Init(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData); +} + + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group3 Callback functions + * @brief Callback functions. + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] This section provides Interruption and DMA callback functions: + (+) DMA Input data transfer complete + (+) DMA Output data transfer complete + (+) DMA or Interrupt error + +@endverbatim + * @{ + */ + +/** + * @brief CRYP error callback. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief Input DMA transfer complete callback. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_InCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Output DMA transfer complete callback. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_OutCpltCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler + * @brief AES IRQ handler. + * +@verbatim + ============================================================================== + ##### AES IRQ handler management ##### + ============================================================================== +[..] This section provides AES IRQ handler function. + +@endverbatim + * @{ + */ + +/** + * @brief Handle AES interrupt request. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) +{ + /* Check if error occurred */ + if (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_ERRIE) != RESET) + { + /* If Write Error occurred */ + if (__HAL_CRYP_GET_FLAG(CRYP_IT_WRERR) != RESET) + { + hcryp->ErrorCode |= HAL_CRYP_WRITE_ERROR; + hcryp->State = HAL_CRYP_STATE_ERROR; + } + /* If Read Error occurred */ + if (__HAL_CRYP_GET_FLAG(CRYP_IT_RDERR) != RESET) + { + hcryp->ErrorCode |= HAL_CRYP_READ_ERROR; + hcryp->State = HAL_CRYP_STATE_ERROR; + } + + /* If an error has been reported */ + if (hcryp->State == HAL_CRYP_STATE_ERROR) + { + /* Disable Error and Computation Complete Interrupts */ + __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + /* Clear all Interrupt flags */ + __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR|CRYP_CCF_CLEAR); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + HAL_CRYP_ErrorCallback(hcryp); + + return; + } + } + + /* Check if computation complete interrupt is enabled + and if the computation complete flag is raised */ + if((__HAL_CRYP_GET_FLAG(CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_CCFIE) != RESET)) + { +#if defined(AES_CR_NPBLB) + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)) +#else + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) +#endif + { + /* To ensure proper suspension requests management, CCF flag + is reset in CRYP_AES_Auth_IT() according to the current + phase under handling */ + CRYP_AES_Auth_IT(hcryp); + } + else + { + /* Clear Computation Complete Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + CRYP_AES_IT(hcryp); + } + } +} + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CRYP handle state. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL state + */ +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) +{ + /* Return CRYP handle state */ + return hcryp->State; +} + +/** + * @brief Return the CRYP peripheral error. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @note The returned error is a bit-map combination of possible errors + * @retval Error bit-map + */ +uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) +{ + return hcryp->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CRYP_Private_Functions + * @{ + */ + + +/** + * @brief Write the Key in KeyRx registers. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp) +{ + uint32_t keyaddr = 0x0; + + if ((uint32_t)(hcryp->Init.pKey == NULL)) + { + return HAL_ERROR; + } + + + keyaddr = (uint32_t)(hcryp->Init.pKey); + + if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) + { + hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + } + + hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); + + return HAL_OK; +} + +/** + * @brief Write the InitVector/InitCounter in IVRx registers. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) +{ + uint32_t ivaddr = 0x0; + +#if !defined(AES_CR_NPBLB) + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) + { + hcryp->Instance->IVR3 = 0; + hcryp->Instance->IVR2 = 0; + hcryp->Instance->IVR1 = 0; + hcryp->Instance->IVR0 = 0; + } + else +#endif + { + if (hcryp->Init.pInitVect == NULL) + { + return HAL_ERROR; + } + + ivaddr = (uint32_t)(hcryp->Init.pInitVect); + + hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr)); + } + return HAL_OK; +} + + + +/** + * @brief Handle CRYP block input/output data handling under interruption. + * @note The function is called under interruption only, once + * interruptions have been enabled by HAL_CRYPEx_AES_IT(). + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t inputaddr = 0; + uint32_t outputaddr = 0; + + if(hcryp->State == HAL_CRYP_STATE_BUSY) + { + if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION) + { + /* Get the output data address */ + outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; + + /* Read the last available output block from the Data Output Register */ + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + hcryp->pCrypOutBuffPtr += 16; + hcryp->CrypOutCount -= 16; + + } + else + { + /* Read the derived key from the Key registers */ + if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) + { + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4); + outputaddr+=4; + } + + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0); + } + + /* In case of ciphering or deciphering, check if all output text has been retrieved; + In case of key derivation, stop right there */ + if ((hcryp->CrypOutCount == 0) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)) + { + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Call computation complete callback */ + HAL_CRYPEx_ComputationCpltCallback(hcryp); + + return HAL_OK; + } + /* If suspension flag has been raised, suspend processing */ + else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) + { + /* reset ModeSuspend */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return HAL_OK; + } + else /* Process the rest of input data */ + { + /* Get the Intput data address */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Increment/decrement instance pointer/counter */ + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + + /* Write the next input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + + + + +/** + * @} + */ + + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* AES */ #endif /* HAL_CRYP_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.h index 33ae4893f21..6ab89b00224 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of CRYP HAL module. ****************************************************************************** * @attention @@ -527,6 +527,638 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); * @} */ +#if defined (AES) + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRYP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CRYP_Exported_Types CRYP Exported Types + * @{ + */ + +/** + * @brief CRYP Configuration Structure definition + */ +typedef struct +{ + uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. + This parameter can be a value of @ref CRYP_Data_Type */ + + uint32_t KeySize; /*!< 128 or 256-bit key length. + This parameter can be a value of @ref CRYP_Key_Size */ + + uint32_t OperatingMode; /*!< AES operating mode. + This parameter can be a value of @ref CRYP_AES_OperatingMode */ + + uint32_t ChainingMode; /*!< AES chaining mode. + This parameter can be a value of @ref CRYP_AES_ChainingMode */ + + uint32_t KeyWriteFlag; /*!< Allows to bypass or not key write-up before decryption. + This parameter can be a value of @ref CRYP_Key_Write */ + + uint32_t GCMCMACPhase; /*!< Indicates the processing phase of the Galois Counter Mode (GCM), + Galois Message Authentication Code (GMAC) or Cipher Message + Authentication Code (CMAC) or Counter with Cipher Mode (CCM) when + the latter is applicable. + This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */ + + uint8_t* pKey; /*!< Encryption/Decryption Key */ + + uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC, + (and CCM when applicable) modes */ + + uint8_t* Header; /*!< Header used in GCM/GMAC, CMAC (and CCM when applicable) modes */ + + uint64_t HeaderSize; /*!< Header size in bytes */ + +}CRYP_InitTypeDef; + +/** + * @brief HAL CRYP State structures definition + */ +typedef enum +{ + HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */ + HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */ + HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */ + HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */ + HAL_CRYP_STATE_ERROR = 0x04, /*!< CRYP error state */ + HAL_CRYP_STATE_SUSPENDED = 0x05 /*!< CRYP suspended */ +}HAL_CRYP_STATETypeDef; + +/** + * @brief HAL CRYP phase structures definition + */ +typedef enum +{ + HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */ + HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */ + HAL_CRYP_PHASE_START = 0x03, /*!< CRYP peripheral has been initialized but + GCM/GMAC/CMAC(/CCM) initialization phase has not started */ + HAL_CRYP_PHASE_INIT_OVER = 0x04, /*!< GCM/GMAC/CMAC(/CCM) init phase has been carried out */ + HAL_CRYP_PHASE_HEADER_OVER = 0x05, /*!< GCM/GMAC/CMAC(/CCM) header phase has been carried out */ + HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, /*!< GCM(/CCM) payload phase has been carried out */ + HAL_CRYP_PHASE_FINAL_OVER = 0x07, /*!< GCM/GMAC/CMAC(/CCM) final phase has been carried out */ + HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08, /*!< GCM/GMAC/CMAC(/CCM) header phase has been suspended */ + HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, /*!< GCM(/CCM) payload phase has been suspended */ + HAL_CRYP_PHASE_NOT_USED = 0x0a /*!< Phase is irrelevant to the current chaining mode */ +}HAL_PhaseTypeDef; + +/** + * @brief HAL CRYP mode suspend definitions + */ +typedef enum +{ + HAL_CRYP_SUSPEND_NONE = 0x00, /*!< CRYP peripheral suspension not requested */ + HAL_CRYP_SUSPEND = 0x01 /*!< CRYP peripheral suspension requested */ +}HAL_SuspendTypeDef; + + +/** + * @brief HAL CRYP Error Codes definition + */ +#define HAL_CRYP_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_CRYP_WRITE_ERROR ((uint32_t)0x00000001) /*!< Write error */ +#define HAL_CRYP_READ_ERROR ((uint32_t)0x00000002) /*!< Read error */ +#define HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004) /*!< DMA error */ +#define HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008) /*!< Busy flag error */ + +/** + * @brief CRYP handle Structure definition + */ +typedef struct +{ + AES_TypeDef *Instance; /*!< Register base address */ + + CRYP_InitTypeDef Init; /*!< CRYP initialization parameters */ + + uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) input buffer */ + + uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */ + + uint32_t CrypInCount; /*!< Input data size in bytes or, after suspension, the remaining + number of bytes to process */ + + uint32_t CrypOutCount; /*!< Output data size in bytes */ + + HAL_PhaseTypeDef Phase; /*!< CRYP peripheral processing phase for GCM, GMAC, CMAC + (or CCM when applicable) modes. + Indicates the last phase carried out to ease + phase transitions */ + + DMA_HandleTypeDef *hdmain; /*!< CRYP peripheral Input DMA handle parameters */ + + DMA_HandleTypeDef *hdmaout; /*!< CRYP peripheral Output DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< CRYP locking object */ + + __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ + + __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ + + HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */ +}CRYP_HandleTypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRYP_Exported_Constants CRYP Exported Constants + * @{ + */ + +/** @defgroup CRYP_Key_Size Key size selection + * @{ + */ +#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000) /*!< 128-bit long key */ +#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */ +/** + * @} + */ + +/** @defgroup CRYP_Data_Type AES Data Type selection + * @{ + */ +#define CRYP_DATATYPE_32B ((uint32_t)0x00000000) /*!< 32-bit data type (no swapping) */ +#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */ +#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */ +#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */ +/** + * @} + */ + + /** @defgroup CRYP_AES_State AES Enable state + * @{ + */ +#define CRYP_AES_DISABLE ((uint32_t)0x00000000) /*!< Disable AES */ +#define CRYP_AES_ENABLE AES_CR_EN /*!< Enable AES */ +/** + * @} + */ + +/** @defgroup CRYP_AES_OperatingMode AES operating mode + * @{ + */ +#define CRYP_ALGOMODE_ENCRYPT ((uint32_t)0x00000000) /*!< Encryption mode */ +#define CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode */ +#define CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */ +#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption */ +#define CRYP_ALGOMODE_TAG_GENERATION ((uint32_t)0x00000000) /*!< GMAC or CMAC authentication tag generation */ +/** + * @} + */ + +/** @defgroup CRYP_AES_ChainingMode AES chaining mode + * @{ + */ +#define CRYP_CHAINMODE_AES_ECB ((uint32_t)0x00000000) /*!< Electronic codebook chaining algorithm */ +#define CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */ +#define CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */ +#define CRYP_CHAINMODE_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */ +#define CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2 /*!< Cipher message authentication code */ +#if defined(AES_CR_NPBLB) +#define CRYP_CHAINMODE_AES_CCM_CMAC AES_CR_CHMOD_2 /*!< Counter with Cipher Mode - Cipher message authentication code */ +#endif +/** + * @} + */ + +/** @defgroup CRYP_Key_Write AES decryption key write-up flag + * @{ + */ +#define CRYP_KEY_WRITE_ENABLE ((uint32_t)0x00000000) /*!< Enable decryption key writing */ +#define CRYP_KEY_WRITE_DISABLE ((uint32_t)0x00000001) /*!< Disable decryption key writing */ +/** + * @} + */ + +/** @defgroup CRYP_DMAIN DMA Input phase management enable state + * @{ + */ +#define CRYP_DMAIN_DISABLE ((uint32_t)0x00000000) /*!< Disable DMA Input phase management */ +#define CRYP_DMAIN_ENABLE AES_CR_DMAINEN /*!< Enable DMA Input phase management */ +/** + * @} + */ + +/** @defgroup CRYP_DMAOUT DMA Output phase management enable state + * @{ + */ +#define CRYP_DMAOUT_DISABLE ((uint32_t)0x00000000) /*!< Disable DMA Output phase management */ +#define CRYP_DMAOUT_ENABLE AES_CR_DMAOUTEN /*!< Enable DMA Output phase management */ +/** + * @} + */ + + +/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CMAC processing phase selection + * @{ + */ +#define CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000) /*!< GCM/GMAC (or CCM) init phase */ +#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC or (CCM/)CMAC header phase */ +#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ +#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC or (CCM/)CMAC final phase */ +/* Definitions duplication for code readibility's sake: + supported or not supported chain modes are not specified for each phase */ +#define CRYP_INIT_PHASE ((uint32_t)0x00000000) /*!< Init phase */ +#define CRYP_HEADER_PHASE AES_CR_GCMPH_0 /*!< Header phase */ +#define CRYP_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< Payload phase */ +#define CRYP_FINAL_PHASE AES_CR_GCMPH /*!< Final phase */ +/** + * @} + */ + +/** @defgroup CRYP_Flags AES status flags + * @{ + */ + +#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */ +#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */ +#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */ +#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */ +/** + * @} + */ + +/** @defgroup CRYP_Clear_Flags AES clearing flags + * @{ + */ + +#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */ +#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */ +/** + * @} + */ + +/** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits + * @{ + */ +#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */ +#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup CRYP_Interrupts_Flags AES Interrupts flags + * @{ + */ +#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */ +#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */ +#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CRYP_Exported_Macros CRYP Exported Macros + * @{ + */ + +/** @brief Reset CRYP handle state. + * @param __HANDLE__: specifies the CRYP handle. + * @retval None + */ +#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) + +/** + * @brief Enable the CRYP AES peripheral. + * @retval None + */ +#define __HAL_CRYP_ENABLE() (AES->CR |= AES_CR_EN) + +/** + * @brief Disable the CRYP AES peripheral. + * @retval None + */ +#define __HAL_CRYP_DISABLE() (AES->CR &= ~AES_CR_EN) + +/** + * @brief Set the algorithm operating mode. + * @param __OPERATING_MODE__: specifies the operating mode + * This parameter can be one of the following values: + * @arg @ref CRYP_ALGOMODE_ENCRYPT encryption + * @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation + * @arg @ref CRYP_ALGOMODE_DECRYPT decryption + * @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption + * @retval None + */ +#define __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__)) + + +/** + * @brief Set the algorithm chaining mode. + * @param __CHAINING_MODE__: specifies the chaining mode + * This parameter can be one of the following values: + * @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook + * @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining + * @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode + * @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code + * @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable) + * @retval None + */ +#define __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__)) + + + +/** @brief Check whether the specified CRYP status flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden + * @arg @ref CRYP_IT_WRERR Write Error + * @arg @ref CRYP_IT_RDERR Read Error + * @arg @ref CRYP_IT_CCF Computation Complete + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__)) + + +/** @brief Clear the CRYP pending status flag. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear + * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear + * @retval None + */ +#define __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__)) + + + +/** @brief Check whether the specified CRYP interrupt source is enabled or not. + * @param __INTERRUPT__: CRYP interrupt source to check + * This parameter can be one of the following values: + * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @retval State of interruption (TRUE or FALSE). + */ +#define __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__)) + + +/** @brief Check whether the specified CRYP interrupt is set or not. + * @param __INTERRUPT__: specifies the interrupt to check. + * This parameter can be one of the following values: + * @arg @ref CRYP_IT_WRERR Write Error + * @arg @ref CRYP_IT_RDERR Read Error + * @arg @ref CRYP_IT_CCF Computation Complete + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__)) + + + +/** @brief Clear the CRYP pending interrupt. + * @param __INTERRUPT__: specifies the IT to clear. + * This parameter can be one of the following values: + * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear + * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear + * @retval None + */ +#define __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__)) + + +/** + * @brief Enable the CRYP interrupt. + * @param __INTERRUPT__: CRYP Interrupt. + * This parameter can be one of the following values: + * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @retval None + */ +#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__)) + + +/** + * @brief Disable the CRYP interrupt. + * @param __INTERRUPT__: CRYP Interrupt. + * This parameter can be one of the following values: + * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @retval None + */ +#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__)) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @addtogroup CRYP_Private_Macros CRYP Private Macros + * @{ + */ + +/** + * @brief Verify the key size length. + * @param __KEYSIZE__: Ciphering/deciphering algorithm key size. + * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid) + */ +#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \ + ((__KEYSIZE__) == CRYP_KEYSIZE_256B)) + +/** + * @brief Verify the input data type. + * @param __DATATYPE__: Ciphering/deciphering algorithm input data type. + * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) + */ +#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \ + ((__DATATYPE__) == CRYP_DATATYPE_16B) || \ + ((__DATATYPE__) == CRYP_DATATYPE_8B) || \ + ((__DATATYPE__) == CRYP_DATATYPE_1B)) + +/** + * @brief Verify the CRYP AES IP running mode. + * @param __MODE__: CRYP AES IP running mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \ + ((__MODE__) == CRYP_AES_ENABLE)) + +/** + * @brief Verify the selected CRYP algorithm. + * @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter). + * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid) + */ +#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \ + ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION) || \ + ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT) || \ + ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \ + ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT)) + +/** + * @brief Verify the selected CRYP chaining algorithm. + * @param __CHAINMODE__: Selected CRYP chaining algorithm. + * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid) + */ +#if defined(AES_CR_NPBLB) +#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \ + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \ + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \ + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \ + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM_CMAC)) +#else +#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \ + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \ + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \ + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \ + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC)) +#endif + +/** + * @brief Verify the deciphering key write option. + * @param __WRITE__: deciphering key write option. + * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid) + */ +#define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \ + ((__WRITE__) == CRYP_KEY_WRITE_DISABLE)) + +/** + * @brief Verify the CRYP input data DMA mode. + * @param __MODE__: CRYP input data DMA mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \ + ((__MODE__) == CRYP_DMAIN_ENABLE)) + +/** + * @brief Verify the CRYP output data DMA mode. + * @param __MODE__: CRYP output data DMA mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \ + ((__MODE__) == CRYP_DMAOUT_ENABLE)) + +/** + * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase. + * @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase. + * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid) + */ +#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE) || \ + ((__PHASE__) == CRYP_GCMCMAC_HEADER_PHASE) || \ + ((__PHASE__) == CRYP_GCM_PAYLOAD_PHASE) || \ + ((__PHASE__) == CRYP_GCMCMAC_FINAL_PHASE)) + +/** + * @} + */ + +/* Include CRYP HAL Extended module */ +#include "stm32f7xx_hal_cryp_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRYP_Exported_Functions CRYP Exported Functions + * @{ + */ + +/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); + +/* MSP initialization/de-initialization functions ****************************/ +void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions + * @{ + */ + +/* AES encryption/decryption processing functions ****************************/ + +/* AES encryption/decryption using polling ***********************************/ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); + +/* AES encryption/decryption using interrupt *********************************/ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); + +/* AES encryption/decryption using DMA ***************************************/ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group3 Callback functions + * @{ + */ +/* CallBack functions ********************************************************/ +void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler + * @{ + */ + +/* AES interrupt handling function *******************************************/ +void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions + * @{ + */ + +/* Peripheral State functions ************************************************/ +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); +uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* AES */ + + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.c index d13c6907870..2fd0d8e6a36 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Extended CRYP HAL module driver * This file provides firmware functions to manage the following * functionalities of CRYP extension peripheral: @@ -3031,6 +3031,3001 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp) #endif /* CRYP */ +#if defined (AES) + +/** @defgroup AESEx AESEx + * @brief CRYP Extended HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants + * @{ + */ +#define CRYP_CCF_TIMEOUTVALUE 22000 /*!< CCF flag raising time-out value */ +#define CRYP_BUSY_TIMEOUTVALUE 22000 /*!< BUSY flag reset time-out value */ + +#define CRYP_POLLING_OFF 0x0 /*!< No polling when padding */ +#define CRYP_POLLING_ON 0x1 /*!< Polling when padding */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions + * @{ + */ +static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout); +static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); +static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); +static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma); +static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma); +static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); +static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); +static void CRYP_DMAError(DMA_HandleTypeDef *hdma); +static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions + * @{ + */ + + +/** @defgroup CRYPEx_Exported_Functions_Group1 Extended callback function + * @brief Extended callback functions. + * +@verbatim + =============================================================================== + ##### Extended callback functions ##### + =============================================================================== + [..] This section provides callback function: + (+) Computation completed. + +@endverbatim + * @{ + */ + + +/** + * @brief Computation completed callbacks. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYPEx_ComputationCpltCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRYPEx_Exported_Functions_Group2 AES extended processing functions + * @brief Extended processing functions. + * +@verbatim + ============================================================================== + ##### AES extended processing functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Encrypt plaintext or decrypt cipher text using AES algorithm in different chaining modes. + Functions are generic (handles ECB, CBC and CTR and all modes) and are only differentiated + based on the processing type. Three processing types are available: + (++) Polling mode + (++) Interrupt mode + (++) DMA mode + (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES + algorithm in different chaining modes. + Functions are generic (handles GCM, GMAC, CMAC and CCM when applicable) and process only one phase + so that steps can be skipped if so required. Functions are only differentiated based on the processing type. + Three processing types are available: + (++) Polling mode + (++) Interrupt mode + (++) DMA mode + +@endverbatim + * @{ + */ + +/** + * @brief Carry out in polling mode the ciphering or deciphering operation according to + * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and + * chaining modes ECB, CBC and CTR are managed by this function in polling mode. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * or key derivation+decryption. + * Parameter is meaningless in case of key derivation. + * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. + * Parameter is meaningless in case of key derivation. + * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * decryption/key derivation+decryption, or pointer to the derivative keys in + * case of key derivation only. + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout) +{ + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Check parameters setting */ + if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) + { + if (pOutputData == NULL) + { + return HAL_ERROR; + } + } + else + { + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + } + + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Call CRYP_ReadKey() API if the operating mode is set to + key derivation, CRYP_ProcessData() otherwise */ + if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) + { + if(CRYP_ReadKey(hcryp, pOutputData, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + else + { + if(CRYP_ProcessData(hcryp, pInputData, Size, pOutputData, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + + /* If the state has not been set to SUSPENDED, set it to + READY, otherwise keep it as it is */ + if (hcryp->State != HAL_CRYP_STATE_SUSPENDED) + { + hcryp->State = HAL_CRYP_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + + +/** + * @brief Carry out in interrupt mode the ciphering or deciphering operation according to + * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and + * chaining modes ECB, CBC and CTR are managed by this function in interrupt mode. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * or key derivation+decryption. + * Parameter is meaningless in case of key derivation. + * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. + * Parameter is meaningless in case of key derivation. + * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * decryption/key derivation+decryption, or pointer to the derivative keys in + * case of key derivation only. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData) +{ + uint32_t inputaddr = 0; + + if(hcryp->State == HAL_CRYP_STATE_READY) + { + /* Check parameters setting */ + if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) + { + if (pOutputData == NULL) + { + return HAL_ERROR; + } + } + else + { + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + } + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* If operating mode is not limited to key derivation only, + get the buffers addresses and sizes */ + if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION) + { + + hcryp->CrypInCount = Size; + hcryp->pCrypInBuffPtr = pInputData; + hcryp->pCrypOutBuffPtr = pOutputData; + hcryp->CrypOutCount = Size; + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Enable Computation Complete Flag and Error Interrupts */ + __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + + + /* If operating mode is key derivation only, the input data have + already been entered during the initialization process. For + the other operating modes, they are fed to the CRYP hardware + block at this point. */ + if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION) + { + /* Initiate the processing under interrupt in entering + the first input data */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + /* Increment/decrement instance pointer/counter */ + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + /* Write the first input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + } + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + + + + +/** + * @brief Carry out in DMA mode the ciphering or deciphering operation according to + * hcryp->Init structure fields. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * or key derivation+decryption. + * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. + * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * decryption/key derivation+decryption. + * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode. + * @note Supported operating modes are encryption, decryption and key derivation with decryption. + * @note No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx + * registers must be done by software. + * @note This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx + * registers must be done by software thru HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs. + * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData) +{ + uint32_t inputaddr = 0; + uint32_t outputaddr = 0; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Check parameters setting */ + if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) + { + /* no DMA channel is provided for key derivation operating mode, + access to AES_KEYRx registers must be done by software */ + return HAL_ERROR; + } + else + { + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + } + + + /* Process Locked */ + __HAL_LOCK(hcryp); + + inputaddr = (uint32_t)pInputData; + outputaddr = (uint32_t)pOutputData; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Set the input and output addresses and start DMA transfer */ + CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + + + + + +/** + * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering + * operation according to hcryp->Init structure fields. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInputData: + * - pointer to payload data in GCM payload phase, + * - pointer to B0 block in CMAC header phase, + * - pointer to C block in CMAC final phase. + * - Parameter is meaningless in case of GCM/GMAC init, header and final phases. + * @param Size: + * - length of the input payload data buffer in bytes, + * - length of B0 block (in bytes) in CMAC header phase, + * - length of C block (in bytes) in CMAC final phase. + * - Parameter is meaningless in case of GCM/GMAC init and header phases. + * @param pOutputData: + * - pointer to plain or cipher text in GCM payload phase, + * - pointer to authentication tag in GCM/GMAC and CMAC final phases. + * - Parameter is meaningless in case of GCM/GMAC init and header phases + * and in case of CMAC header phase. + * @param Timeout: Specify Timeout value + * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable. + * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes + * can be skipped by the user if so required. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout) +{ + uint32_t index = 0; + uint32_t inputaddr = 0; + uint32_t outputaddr = 0; + uint32_t tagaddr = 0; + uint64_t headerlength = 0; + uint64_t inputlength = 0; + uint64_t payloadlength = 0; + uint32_t difflength = 0; + uint32_t addhoc_process = 0; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* input/output parameters check */ + if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + { + if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0)) + { + return HAL_ERROR; + } +#if defined(AES_CR_NPBLB) + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) +#else + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) +#endif + { + /* In case of CMAC (or CCM) header phase resumption, we can have pInputData = NULL and Size = 0 */ + if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) + { + return HAL_ERROR; + } + } + } + else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) + { + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + } + else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + { + if (pOutputData == NULL) + { + return HAL_ERROR; + } +#if defined(AES_CR_NPBLB) + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL)) +#else + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) +#endif + { + return HAL_ERROR; + } + } + + + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /*==============================================*/ + /* GCM/GMAC (or CCM when applicable) init phase */ + /*==============================================*/ + /* In case of init phase, the input data (Key and Initialization Vector) have + already been entered during the initialization process. Therefore, the + API just waits for the CCF flag to be set. */ + if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) + { + /* just wait for hash computation */ + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + /* Mark that the initialization phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER; + } + /*=====================================*/ + /* GCM/GMAC or (CCM/)CMAC header phase */ + /*=====================================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + { + /* Set header phase; for GCM or GMAC, set data-byte at this point */ + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType); + } + else + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE); + } + + /* Enable the Peripheral */ + __HAL_CRYP_ENABLE(); + +#if !defined(AES_CR_NPBLB) + /* in case of CMAC, enter B0 block in header phase, before the header itself. */ + /* If Size = 0 (possible case of resumption after CMAC header phase suspension), + skip these steps and go directly to header buffer feeding to the HW */ + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0)) + { + inputaddr = (uint32_t)pInputData; + + for(index=0; (index < Size); index += 16) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + + /* If the suspension flag has been raised and if the processing is not about + to end, suspend processing */ + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Size)) + { + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + /* Mark that the header phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; + + /* Save current reading and writing locations of Input and Output buffers */ + hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; + /* Save the total number of bytes (B blocks + header) that remain to be + processed at this point */ + hcryp->CrypInCount = hcryp->Init.HeaderSize + Size - (index+16); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return HAL_OK; + } + } /* for(index=0; (index < Size); index += 16) */ + } +#endif /* !defined(AES_CR_NPBLB) */ + + /* Enter header */ + inputaddr = (uint32_t)hcryp->Init.Header; + /* Local variable headerlength is a number of bytes multiple of 128 bits, + remaining header data (if any) are handled after this loop */ + headerlength = (((hcryp->Init.HeaderSize)/16)*16) ; + if ((hcryp->Init.HeaderSize % 16) != 0) + { + difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength); + } + for(index=0; index < headerlength; index += 16) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + + /* If the suspension flag has been raised and if the processing is not about + to end, suspend processing */ + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < headerlength)) + { + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + /* Mark that the header phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; + + /* Save current reading and writing locations of Input and Output buffers */ + hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; + /* Save the total number of bytes that remain to be processed at this point */ + hcryp->CrypInCount = hcryp->Init.HeaderSize - (index+16); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return HAL_OK; + } + } + + /* Case header length is not a multiple of 16 bytes */ + if (difflength != 0) + { + hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; + CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); + } + + /* Mark that the header phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; + } + /*============================================*/ + /* GCM (or CCM when applicable) payload phase */ + /*============================================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) + { + + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE); + + /* if the header phase has been bypassed, AES must be enabled again */ + if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) + { + __HAL_CRYP_ENABLE(); + } + + inputaddr = (uint32_t)pInputData; + outputaddr = (uint32_t)pOutputData; + + /* Enter payload */ + /* Specific handling to manage payload last block size less than 128 bits */ + if ((Size % 16) != 0) + { + payloadlength = (Size/16) * 16; + difflength = (uint32_t) (Size - payloadlength); + addhoc_process = 1; + } + else + { + payloadlength = Size; + addhoc_process = 0; + } + + /* Feed payload */ + for(index=0; index < payloadlength; index += 16) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + + /* Retrieve output data: read the output block + from the Data Output Register */ + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + + /* If the suspension flag has been raised and if the processing is not about + to end, suspend processing */ + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < payloadlength)) + { + /* no flag waiting under IRQ handling */ + if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) + { + /* Ensure that Busy flag is reset */ + if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + } + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + /* Mark that the header phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; + + /* Save current reading and writing locations of Input and Output buffers */ + hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; + hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; + /* Save the number of bytes that remain to be processed at this point */ + hcryp->CrypInCount = Size - (index+16); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return HAL_OK; + } + + } + + /* Additional processing to manage GCM(/CCM) encryption and decryption cases when + payload last block size less than 128 bits */ + if (addhoc_process == 1) + { + + hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; + hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; + CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); + + } /* (addhoc_process == 1) */ + + /* Mark that the payload phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + } + /*====================================*/ + /* GCM/GMAC or (CCM/)CMAC final phase */ + /*====================================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + { + tagaddr = (uint32_t)pOutputData; + +#if defined(AES_CR_NPBLB) + /* By default, clear NPBLB field */ + CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB); +#endif + + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); + + /* if the header and payload phases have been bypassed, AES must be enabled again */ + if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) + { + __HAL_CRYP_ENABLE(); + } + + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + { + headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ + inputlength = Size * 8; /* input length in bits */ + + + if(hcryp->Init.DataType == CRYP_DATATYPE_1B) + { + hcryp->Instance->DINR = __RBIT((headerlength)>>32); + hcryp->Instance->DINR = __RBIT(headerlength); + hcryp->Instance->DINR = __RBIT((inputlength)>>32); + hcryp->Instance->DINR = __RBIT(inputlength); + } + else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) + { + hcryp->Instance->DINR = __REV((headerlength)>>32); + hcryp->Instance->DINR = __REV(headerlength); + hcryp->Instance->DINR = __REV((inputlength)>>32); + hcryp->Instance->DINR = __REV(inputlength); + } + else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) + { + hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); + hcryp->Instance->DINR = __ROR(headerlength, 16); + hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); + hcryp->Instance->DINR = __ROR(inputlength, 16); + } + else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) + { + hcryp->Instance->DINR = (uint32_t)(headerlength>>32); + hcryp->Instance->DINR = (uint32_t)(headerlength); + hcryp->Instance->DINR = (uint32_t)(inputlength>>32); + hcryp->Instance->DINR = (uint32_t)(inputlength); + } + } +#if !defined(AES_CR_NPBLB) + else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) + { + inputaddr = (uint32_t)pInputData; + /* Enter the last block made of a 128-bit value formatted + from the original B0 packet. */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + } +#endif + + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + + /* Read the Auth TAG in the Data Out register */ + *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr+=4; + *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr+=4; + *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr+=4; + *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + /* Mark that the final phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER; + /* Disable the Peripheral */ + __HAL_CRYP_DISABLE(); + } + /*=================================================*/ + /* case incorrect hcryp->Init.GCMCMACPhase setting */ + /*=================================================*/ + else + { + hcryp->State = HAL_CRYP_STATE_ERROR; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + + + +/** + * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering + * operation according to hcryp->Init structure fields. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInputData: + * - pointer to payload data in GCM payload phase, + * - pointer to B0 block in CMAC header phase, + * - pointer to C block in CMAC final phase. + * Parameter is meaningless in case of GCM/GMAC init, header and final phases. + * @param Size: + * - length of the input payload data buffer in bytes, + * - length of B0 block (in bytes) in CMAC header phase, + * - length of C block (in bytes) in CMAC final phase. + * - Parameter is meaningless in case of GCM/GMAC init and header phases. + * @param pOutputData: + * - pointer to plain or cipher text in GCM payload phase, + * - pointer to authentication tag in GCM/GMAC and CMAC final phases. + * - Parameter is meaningless in case of GCM/GMAC init and header phases + * and in case of CMAC header phase. + * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC. + * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes + * can be skipped by the user if so required. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData) +{ + + uint32_t inputaddr = 0; + uint64_t headerlength = 0; + uint64_t inputlength = 0; + uint32_t index = 0; + uint32_t addhoc_process = 0; + uint32_t difflength = 0; + uint32_t difflengthmod4 = 0; + uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF}; + + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* input/output parameters check */ + if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + { + if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0)) + { + return HAL_ERROR; + } +#if defined(AES_CR_NPBLB) + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) +#else + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) +#endif + { + /* In case of CMAC header phase resumption, we can have pInputData = NULL and Size = 0 */ + if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) + { + return HAL_ERROR; + } + } + } + else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) + { + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + } + else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + { + if (pOutputData == NULL) + { + return HAL_ERROR; + } +#if defined(AES_CR_NPBLB) + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL)) +#else + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) +#endif + { + return HAL_ERROR; + } + } + + + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Enable Computation Complete Flag and Error Interrupts */ + __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + + + + /*==============================================*/ + /* GCM/GMAC (or CCM when applicable) init phase */ + /*==============================================*/ + if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) + { + /* In case of init phase, the input data (Key and Initialization Vector) have + already been entered during the initialization process. Therefore, the + software just waits for the CCF interrupt to be raised and which will + be handled by CRYP_AES_Auth_IT() API. */ + } + /*=====================================*/ + /* GCM/GMAC or (CCM/)CMAC header phase */ + /*=====================================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + { + +#if defined(AES_CR_NPBLB) + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) +#else + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) +#endif + { + /* In case of CMAC, B blocks are first entered, before the header. + Therefore, B blocks and the header are entered back-to-back + as if it was only one single block. + However, in case of resumption after suspension, if all the + B blocks have been entered (in that case, Size = 0), only the + remainder of the non-processed header bytes are entered. */ + if (Size != 0) + { + hcryp->CrypInCount = Size + hcryp->Init.HeaderSize; + hcryp->pCrypInBuffPtr = pInputData; + } + else + { + hcryp->CrypInCount = hcryp->Init.HeaderSize; + hcryp->pCrypInBuffPtr = hcryp->Init.Header; + } + } + else + { + /* Get the header addresses and sizes */ + hcryp->CrypInCount = hcryp->Init.HeaderSize; + hcryp->pCrypInBuffPtr = hcryp->Init.Header; + } + + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Set header phase; for GCM or GMAC, set data-byte at this point */ + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType); + } + else + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE); + } + + /* Enable the Peripheral */ + __HAL_CRYP_ENABLE(); + + /* Increment/decrement instance pointer/counter */ + if (hcryp->CrypInCount == 0) + { + /* Case of no header */ + hcryp->State = HAL_CRYP_STATE_READY; + return HAL_OK; + } + else if (hcryp->CrypInCount < 16) + { + hcryp->CrypInCount = 0; + addhoc_process = 1; + difflength = (uint32_t) (hcryp->Init.HeaderSize); + difflengthmod4 = difflength%4; + } + else + { + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + } + + +#if defined(AES_CR_NPBLB) + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) +#else + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) +#endif + { + if (hcryp->CrypInCount == hcryp->Init.HeaderSize) + { + /* All B blocks will have been entered after the next + four DINR writing, so point at header buffer for + the next iteration */ + hcryp->pCrypInBuffPtr = hcryp->Init.Header; + } + } + + /* Enter header first block to initiate the process + in the Data Input register */ + if (addhoc_process == 0) + { + /* Header has size equal or larger than 128 bits */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + } + else + { + /* Header has size less than 128 bits */ + /* Enter complete words when possible */ + for(index=0; index < (difflength/4); index ++) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + } + /* Enter incomplete word padded with zeroes if applicable + (case of header length not a multiple of 32-bits) */ + if (difflengthmod4 != 0) + { + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + } + /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ + for(index=0; index < (4 - ((difflength+3)/4)); index ++) + { + hcryp->Instance->DINR = 0; + } + + } + } + /*============================================*/ + /* GCM (or CCM when applicable) payload phase */ + /*============================================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) + { + /* Get the buffer addresses and sizes */ + hcryp->CrypInCount = Size; + hcryp->pCrypInBuffPtr = pInputData; + hcryp->pCrypOutBuffPtr = pOutputData; + hcryp->CrypOutCount = Size; + + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCM_PAYLOAD_PHASE); + + /* if the header phase has been bypassed, AES must be enabled again */ + if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) + { + __HAL_CRYP_ENABLE(); + } + + /* Specific handling to manage payload size less than 128 bits */ + if (Size < 16) + { +#if defined(AES_CR_NPBLB) + /* In case of GCM encryption or CCM decryption, specify the number of padding + bytes in last block of payload */ + if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE) + { + if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) + && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) + || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC) + && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) + { + /* Set NPBLB field in writing the number of padding bytes + for the last block of payload */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16 - difflength); + } + } +#else + /* Software workaround applied to GCM encryption only */ + if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) + { + /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ + __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR); + } +#endif + + + /* Set hcryp->CrypInCount to 0 (no more data to enter) */ + hcryp->CrypInCount = 0; + + /* Insert the last block (which size is inferior to 128 bits) padded with zeroes, + to have a complete block of 128 bits */ + difflength = (uint32_t) (Size); + difflengthmod4 = difflength%4; + /* Insert the last block (which size is inferior to 128 bits) padded with zeroes + to have a complete block of 128 bits */ + for(index=0; index < (difflength/4); index ++) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + } + /* If required, manage input data size not multiple of 32 bits */ + if (difflengthmod4 != 0) + { + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + } + /* Wrap-up in padding with zero-words if applicable */ + for(index=0; index < (4 - ((difflength+3)/4)); index ++) + { + hcryp->Instance->DINR = 0; + } + } + else + { + /* Increment/decrement instance pointer/counter */ + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + + /* Enter payload first block to initiate the process + in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + } + } + /*====================================*/ + /* GCM/GMAC or (CCM/)CMAC final phase */ + /*====================================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + { + hcryp->pCrypOutBuffPtr = pOutputData; + +#if defined(AES_CR_NPBLB) + /* By default, clear NPBLB field */ + CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB); +#endif + + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); + + /* if the header and payload phases have been bypassed, AES must be enabled again */ + if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) + { + __HAL_CRYP_ENABLE(); + } + + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + { + headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ + inputlength = Size * 8; /* Input length in bits */ + /* Write the number of bits in the header on 64 bits followed by the number + of bits in the payload on 64 bits as well */ + if(hcryp->Init.DataType == CRYP_DATATYPE_1B) + { + hcryp->Instance->DINR = __RBIT((headerlength)>>32); + hcryp->Instance->DINR = __RBIT(headerlength); + hcryp->Instance->DINR = __RBIT((inputlength)>>32); + hcryp->Instance->DINR = __RBIT(inputlength); + } + else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) + { + hcryp->Instance->DINR = __REV((headerlength)>>32); + hcryp->Instance->DINR = __REV(headerlength); + hcryp->Instance->DINR = __REV((inputlength)>>32); + hcryp->Instance->DINR = __REV(inputlength); + } + else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) + { + hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); + hcryp->Instance->DINR = __ROR(headerlength, 16); + hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); + hcryp->Instance->DINR = __ROR(inputlength, 16); + } + else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) + { + hcryp->Instance->DINR = (uint32_t)(headerlength>>32); + hcryp->Instance->DINR = (uint32_t)(headerlength); + hcryp->Instance->DINR = (uint32_t)(inputlength>>32); + hcryp->Instance->DINR = (uint32_t)(inputlength); + } + } +#if !defined(AES_CR_NPBLB) + else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) + { + inputaddr = (uint32_t)pInputData; + /* Enter the last block made of a 128-bit value formatted + from the original B0 packet. */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + } +#endif + } + /*=================================================*/ + /* case incorrect hcryp->Init.GCMCMACPhase setting */ + /*=================================================*/ + else + { + hcryp->State = HAL_CRYP_STATE_ERROR; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + + + +/** + * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering + * operation according to hcryp->Init structure fields. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInputData: + * - pointer to payload data in GCM payload phase, + * - pointer to B0 block in CMAC header phase, + * - pointer to C block in CMAC final phase. + * - Parameter is meaningless in case of GCM/GMAC init, header and final phases. + * @param Size: + * - length of the input payload data buffer in bytes, + * - length of B block (in bytes) in CMAC header phase, + * - length of C block (in bytes) in CMAC final phase. + * - Parameter is meaningless in case of GCM/GMAC init and header phases. + * @param pOutputData: + * - pointer to plain or cipher text in GCM payload phase, + * - pointer to authentication tag in GCM/GMAC and CMAC final phases. + * - Parameter is meaningless in case of GCM/GMAC init and header phases + * and in case of CMAC header phase. + * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC. + * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes + * can be skipped by the user if so required. + * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData) +{ + uint32_t inputaddr = 0; + uint32_t outputaddr = 0; + uint32_t tagaddr = 0; + uint64_t headerlength = 0; + uint64_t inputlength = 0; + uint64_t payloadlength = 0; + + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* input/output parameters check */ + if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + { + if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0)) + { + return HAL_ERROR; + } +#if defined(AES_CR_NPBLB) + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) +#else + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) +#endif + { + if ((pInputData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + } + } + else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) + { + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + } + else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + { + if (pOutputData == NULL) + { + return HAL_ERROR; + } +#if defined(AES_CR_NPBLB) + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL)) +#else + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) +#endif + { + return HAL_ERROR; + } + } + + + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /*==============================================*/ + /* GCM/GMAC (or CCM when applicable) init phase */ + /*==============================================*/ + /* In case of init phase, the input data (Key and Initialization Vector) have + already been entered during the initialization process. No DMA transfer is + required at that point therefore, the software just waits for the CCF flag + to be raised. */ + if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) + { + /* just wait for hash computation */ + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + /* Mark that the initialization phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER; + hcryp->State = HAL_CRYP_STATE_READY; + } + /*===============================*/ + /* GCM/GMAC or CMAC header phase */ + /*===============================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE) + { + /* Set header phase; for GCM or GMAC, set data-byte at this point */ + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_GCMCMAC_HEADER_PHASE|hcryp->Init.DataType); + } + else + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_HEADER_PHASE); + } + +#if !defined(AES_CR_NPBLB) + /* enter first B0 block in polling mode (no DMA transfer for B0) */ + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) + { + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(); + + inputaddr = (uint32_t)pInputData; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + } +#endif + + /* No header case */ + if (hcryp->Init.Header == NULL) + { + hcryp->State = HAL_CRYP_STATE_READY; + /* Mark that the header phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return HAL_OK; + } + + inputaddr = (uint32_t)hcryp->Init.Header; + if ((hcryp->Init.HeaderSize % 16) != 0) + { + + if (hcryp->Init.HeaderSize < 16) + { + CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF); + + hcryp->State = HAL_CRYP_STATE_READY; + /* Mark that the header phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; + + /* CCF flag indicating header phase AES processing completion + will be checked at the start of the next phase: + - payload phase (GCM / CCM when applicable) + - final phase (GMAC or CMAC). */ + } + else + { + /* Local variable headerlength is a number of bytes multiple of 128 bits, + remaining header data (if any) are handled after this loop */ + headerlength = (((hcryp->Init.HeaderSize)/16)*16) ; + /* Store the ending transfer point */ + hcryp->pCrypInBuffPtr = hcryp->Init.Header + headerlength; + hcryp->CrypInCount = (uint32_t)(hcryp->Init.HeaderSize - headerlength); /* remainder */ + + /* Set the input and output addresses and start DMA transfer */ + /* (incomplete DMA transfer, will be wrapped up after completion of + the first one (initiated here) with data padding */ + CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, headerlength, 0); + } + } + else + { + hcryp->CrypInCount = 0; + /* Set the input address and start DMA transfer */ + CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, hcryp->Init.HeaderSize, 0); + } + + + } + /*============================================*/ + /* GCM (or CCM when applicable) payload phase */ + /*============================================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) + { + /* Coming from header phase, wait for CCF flag to be raised + if header present and fed to the IP in the previous phase */ + if (hcryp->Init.Header != NULL) + { + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + } + else + { + /* Enable the Peripheral since wasn't in header phase (no header case) */ + __HAL_CRYP_ENABLE(); + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE); + + /* Specific handling to manage payload size less than 128 bits */ + if ((Size % 16) != 0) + { + inputaddr = (uint32_t)pInputData; + outputaddr = (uint32_t)pOutputData; + if (Size < 16) + { + /* Block is now entered in polling mode, no actual gain in resorting to DMA */ + hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; + hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; + + CRYP_Padding(hcryp, (uint32_t)Size, CRYP_POLLING_ON); + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Mark that the payload phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + + /* Call output data transfer complete callback */ + HAL_CRYP_OutCpltCallback(hcryp); + } + else + { + payloadlength = (Size/16) * 16; + + /* Store the ending transfer points */ + hcryp->pCrypInBuffPtr = pInputData + payloadlength; + hcryp->pCrypOutBuffPtr = pOutputData + payloadlength; + hcryp->CrypInCount = (uint32_t)(Size - payloadlength); /* remainder */ + + /* Set the input and output addresses and start DMA transfer */ + /* (incomplete DMA transfer, will be wrapped up with data padding + after completion of the one initiated here) */ + CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, payloadlength, outputaddr); + } + } + else + { + hcryp->CrypInCount = 0; + inputaddr = (uint32_t)pInputData; + outputaddr = (uint32_t)pOutputData; + + /* Set the input and output addresses and start DMA transfer */ + CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); + } + } + /*====================================*/ + /* GCM/GMAC or (CCM/)CMAC final phase */ + /*====================================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + { + /* If coming from header phase (GMAC or CMAC case), + wait for CCF flag to be raised */ + if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_HEADER_PHASE) + { + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + } + + tagaddr = (uint32_t)pOutputData; + + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); + + /* if the header and payload phases have been bypassed, AES must be enabled again */ + if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) + { + __HAL_CRYP_ENABLE(); + } + + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + { + headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ + inputlength = Size * 8; /* input length in bits */ + /* Write the number of bits in the header on 64 bits followed by the number + of bits in the payload on 64 bits as well */ + if(hcryp->Init.DataType == CRYP_DATATYPE_1B) + { + hcryp->Instance->DINR = __RBIT((headerlength)>>32); + hcryp->Instance->DINR = __RBIT(headerlength); + hcryp->Instance->DINR = __RBIT((inputlength)>>32); + hcryp->Instance->DINR = __RBIT(inputlength); + } + else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) + { + hcryp->Instance->DINR = __REV((headerlength)>>32); + hcryp->Instance->DINR = __REV(headerlength); + hcryp->Instance->DINR = __REV((inputlength)>>32); + hcryp->Instance->DINR = __REV(inputlength); + } + else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) + { + hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); + hcryp->Instance->DINR = __ROR(headerlength, 16); + hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); + hcryp->Instance->DINR = __ROR(inputlength, 16); + } + else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) + { + hcryp->Instance->DINR = (uint32_t)(headerlength>>32); + hcryp->Instance->DINR = (uint32_t)(headerlength); + hcryp->Instance->DINR = (uint32_t)(inputlength>>32); + hcryp->Instance->DINR = (uint32_t)(inputlength); + } + } +#if !defined(AES_CR_NPBLB) + else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) + { + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + + inputaddr = (uint32_t)pInputData; + /* Enter the last block made of a 128-bit value formatted + from the original B0 packet. */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + } +#endif + + /* No DMA transfer is required at that point therefore, the software + just waits for the CCF flag to be raised. */ + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + /* Read the Auth TAG in the IN FIFO */ + *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr+=4; + *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr+=4; + *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr+=4; + *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + + /* Mark that the final phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER; + hcryp->State = HAL_CRYP_STATE_READY; + /* Disable the Peripheral */ + __HAL_CRYP_DISABLE(); + } + /*=================================================*/ + /* case incorrect hcryp->Init.GCMCMACPhase setting */ + /*=================================================*/ + else + { + hcryp->State = HAL_CRYP_STATE_ERROR; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** @defgroup CRYPEx_Exported_Functions_Group3 AES suspension/resumption functions + * @brief Extended processing functions. + * +@verbatim + ============================================================================== + ##### AES extended suspension and resumption functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) save in memory the Initialization Vector, the Key registers, the Control register or + the Suspend registers when a process is suspended by a higher priority message + (+) write back in CRYP hardware block the saved values listed above when the suspended + lower priority message processing is resumed. + +@endverbatim + * @{ + */ + + +/** + * @brief In case of message processing suspension, read the Initialization Vector. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Output: Pointer to the buffer containing the saved Initialization Vector. + * @note This value has to be stored for reuse by writing the AES_IVRx registers + * as soon as the interrupted processing has to be resumed. + * Applicable to all chaining modes. + * @note AES must be disabled when reading or resetting the IV values. + * @retval None + */ +void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output) +{ + uint32_t outputaddr = (uint32_t)Output; + + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR3); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR2); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR1); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR0); +} + +/** + * @brief In case of message processing resumption, rewrite the Initialization + * Vector in the AES_IVRx registers. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Input: Pointer to the buffer containing the saved Initialization Vector to + * write back in the CRYP hardware block. + * @note Applicable to all chaining modes. + * @note AES must be disabled when reading or resetting the IV values. + * @retval None + */ +void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input) +{ + uint32_t ivaddr = (uint32_t)Input; + + hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr)); +} + + +/** + * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Output: Pointer to the buffer containing the saved Suspend Registers. + * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers + * as soon as the interrupted processing has to be resumed. + * @retval None + */ +void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output) +{ + uint32_t outputaddr = (uint32_t)Output; + + /* In case of GCM payload phase encryption, check that suspension can be carried out */ + if (READ_BIT(hcryp->Instance->CR, (AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_GCM_PAYLOAD_PHASE|CRYP_ALGOMODE_ENCRYPT)) + { + /* Ensure that Busy flag is reset */ + if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK) + { + hcryp->ErrorCode |= HAL_CRYP_BUSY_ERROR; + hcryp->State = HAL_CRYP_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + HAL_CRYP_ErrorCallback(hcryp); + return ; + } + } + + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP7R); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP6R); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP5R); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP4R); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP3R); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP2R); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R); +} + +/** + * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend + * Registers in the AES_SUSPxR registers. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Input: Pointer to the buffer containing the saved suspend registers to + * write back in the CRYP hardware block. + * @retval None + */ +void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input) +{ + uint32_t ivaddr = (uint32_t)Input; + + hcryp->Instance->SUSP7R = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->SUSP6R = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->SUSP5R = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->SUSP4R = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->SUSP3R = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->SUSP2R = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->SUSP1R = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr)); +} + + +/** + * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Output: Pointer to the buffer containing the saved Key Registers. + * @param KeySize: Indicates the key size (128 or 256 bits). + * @note These values have to be stored for reuse by writing back the AES_KEYRx registers + * as soon as the interrupted processing has to be resumed. + * @retval None + */ +void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize) +{ + uint32_t keyaddr = (uint32_t)Output; + + if (KeySize == CRYP_KEYSIZE_256B) + { + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR7); + keyaddr+=4; + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR6); + keyaddr+=4; + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR5); + keyaddr+=4; + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR4); + keyaddr+=4; + } + + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR3); + keyaddr+=4; + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR2); + keyaddr+=4; + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR1); + keyaddr+=4; + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0); +} + +/** + * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key + * Registers in the AES_KEYRx registers. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Input: Pointer to the buffer containing the saved key registers to + * write back in the CRYP hardware block. + * @param KeySize: Indicates the key size (128 or 256 bits) + * @retval None + */ +void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize) +{ + uint32_t keyaddr = (uint32_t)Input; + + if (KeySize == CRYP_KEYSIZE_256B) + { + hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + } + + hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); +} + + +/** + * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Control Register. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Output: Pointer to the buffer containing the saved Control Register. + * @note This values has to be stored for reuse by writing back the AES_CR register + * as soon as the interrupted processing has to be resumed. + * @retval None + */ +void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output) +{ + *(uint32_t*)(Output) = hcryp->Instance->CR; +} + +/** + * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control + * Registers in the AES_CR register. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Input: Pointer to the buffer containing the saved Control Register to + * write back in the CRYP hardware block. + * @retval None + */ +void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input) +{ + hcryp->Instance->CR = *(uint32_t*)(Input); + /* At the same time, set handle state back to READY to be able to resume the AES calculations + without the processing APIs returning HAL_BUSY when called. */ + hcryp->State = HAL_CRYP_STATE_READY; +} + +/** + * @brief Request CRYP processing suspension when in polling or interruption mode. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @note Set the handle field SuspendRequest to the appropriate value so that + * the on-going CRYP processing is suspended as soon as the required + * conditions are met. + * @note It is advised not to suspend the CRYP processing when the DMA controller + * is managing the data transfer + * @retval None + */ +void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp) +{ + /* Set Handle Suspend Request field */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CRYPEx_Private_Functions + * @{ + */ + +/** + * @brief DMA CRYP Input Data process complete callback + * for GCM, GMAC or CMAC chainging modes. + * @note Specific setting of hcryp fields are required only + * in the case of header phase where no output data DMA + * transfer is on-going (only input data transfer is enabled + * in such a case). + * @param hdma: DMA handle. + * @retval None + */ +static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma) +{ + uint32_t difflength = 0; + + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable the DMA transfer for input request */ + CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); + + if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + { + + if (hcryp->CrypInCount != 0) + { + /* Last block is now entered in polling mode, no actual gain in resorting to DMA */ + difflength = hcryp->CrypInCount; + hcryp->CrypInCount = 0; + + CRYP_Padding(hcryp, difflength, CRYP_POLLING_OFF); + } + hcryp->State = HAL_CRYP_STATE_READY; + /* Mark that the header phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; + } + /* CCF flag indicating header phase AES processing completion + will be checked at the start of the next phase: + - payload phase (GCM or CCM when applicable) + - final phase (GMAC or CMAC). + This allows to avoid the Wait on Flag within the IRQ handling. */ + + /* Call input data transfer complete callback */ + HAL_CRYP_InCpltCallback(hcryp); +} + +/** + * @brief DMA CRYP Output Data process complete callback + * for GCM, GMAC or CMAC chainging modes. + * @note This callback is called only in the payload phase. + * @param hdma: DMA handle. + * @retval None + */ +static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma) +{ + uint32_t difflength = 0; + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable the DMA transfer for output request */ + CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + + /* Initiate additional transfer to wrap-up data feeding to the IP */ + if (hcryp->CrypInCount != 0) + { + /* Last block is now entered in polling mode, no actual gain in resorting to DMA */ + difflength = hcryp->CrypInCount; + hcryp->CrypInCount = 0; + + CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); + } + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Mark that the payload phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + + /* Call output data transfer complete callback */ + HAL_CRYP_OutCpltCallback(hcryp); +} + +/** + * @brief DMA CRYP communication error callback + * for GCM, GMAC or CMAC chainging modes. + * @param hdma: DMA handle + * @retval None + */ +static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma) +{ + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + hcryp->State= HAL_CRYP_STATE_ERROR; + hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; + HAL_CRYP_ErrorCallback(hcryp); + /* Clear Error Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR); +} + + + +/** + * @brief Handle CRYP block input/output data handling under interruption + * for GCM, GMAC or CMAC chaining modes. + * @note The function is called under interruption only, once + * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT(). + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t inputaddr = 0x0; + uint32_t outputaddr = 0x0; + uint32_t index = 0x0; + uint32_t addhoc_process = 0; + uint32_t difflength = 0; + uint32_t difflengthmod4 = 0; + uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF}; + uint32_t intermediate_data[4] = {0}; + + if(hcryp->State == HAL_CRYP_STATE_BUSY) + { + /*===========================*/ + /* GCM/GMAC(/CCM) init phase */ + /*===========================*/ + if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) + { + /* Clear Computation Complete Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Mark that the initialization phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + /* Call computation complete callback */ + HAL_CRYPEx_ComputationCpltCallback(hcryp); + return HAL_OK; + } + /*=====================================*/ + /* GCM/GMAC or (CCM/)CMAC header phase */ + /*=====================================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + { + /* Check if all input header data have been entered */ + if (hcryp->CrypInCount == 0) + { + /* Clear Computation Complete Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Mark that the header phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Call computation complete callback */ + HAL_CRYPEx_ComputationCpltCallback(hcryp); + + return HAL_OK; + } + /* If suspension flag has been raised, suspend processing */ + else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) + { + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + /* Mark that the header phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return HAL_OK; + } + else /* Carry on feeding input data to the CRYP hardware block */ + { + /* Clear Computation Complete Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + /* Get the last Input data address */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Increment/decrement instance pointer/counter */ + if (hcryp->CrypInCount < 16) + { + difflength = hcryp->CrypInCount; + hcryp->CrypInCount = 0; + addhoc_process = 1; + difflengthmod4 = difflength%4; + } + else + { + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + } + +#if defined(AES_CR_NPBLB) + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) +#else + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) +#endif + { + if (hcryp->CrypInCount == hcryp->Init.HeaderSize) + { + /* All B blocks will have been entered after the next + four DINR writing, so point at header buffer for + the next iteration */ + hcryp->pCrypInBuffPtr = hcryp->Init.Header; + } + } + + /* Write the Input block in the Data Input register */ + if (addhoc_process == 0) + { + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + } + else + { + /* Header remainder has size less than 128 bits */ + /* Enter complete words when possible */ + for(index=0; index < (difflength/4); index ++) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + } + /* Enter incomplete word padded with zeroes if applicable + (case of header length not a multiple of 32-bits) */ + if (difflengthmod4 != 0) + { + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + } + /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ + for(index=0; index < (4 - ((difflength+3)/4)); index ++) + { + hcryp->Instance->DINR = 0; + } + } + + return HAL_OK; + } + } + /*=======================*/ + /* GCM/CCM payload phase */ + /*=======================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) + { + /* Get the last output data address */ + outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; + + /* Specific handling to manage payload size less than 128 bits + when GCM (or CCM when applicable) encryption or decryption is selected. + Check here if the last block output data are read */ +#if defined(AES_CR_NPBLB) + if ((hcryp->CrypOutCount < 16) && \ + (hcryp->CrypOutCount > 0)) +#else + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \ + (hcryp->CrypOutCount < 16) && \ + (hcryp->CrypOutCount > 0)) +#endif + { + addhoc_process = 1; + difflength = hcryp->CrypOutCount; + difflengthmod4 = difflength%4; + hcryp->CrypOutCount = 0; /* mark that no more output data will be needed */ + /* Retrieve intermediate data */ + for(index=0; index < 4; index ++) + { + intermediate_data[index] = hcryp->Instance->DOUTR; + } + /* Retrieve last words of cyphered data */ + /* First, retrieve complete output words */ + for(index=0; index < (difflength/4); index ++) + { + *(uint32_t*)(outputaddr) = intermediate_data[index]; + outputaddr+=4; + } + /* Next, retrieve partial output word if applicable; + at the same time, start masking intermediate data + with a mask of zeros of same size than the padding + applied to the last block of payload */ + if (difflengthmod4 != 0) + { + intermediate_data[difflength/4] &= mask[difflengthmod4-1]; + *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; + } + +#if !defined(AES_CR_NPBLB) + if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) + { + /* Change again CHMOD configuration to GCM mode */ + __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC); + + /* Select FINAL phase */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE); + + /* Before inserting the intermediate data, carry on masking operation + with a mask of zeros of same size than the padding applied to the last block of payload */ + for(index=0; index < (4 - ((difflength+3)/4)); index ++) + { + intermediate_data[(difflength+3)/4+index] = 0; + } + + /* Insert intermediate data to trigger an additional DOUTR reading round */ + /* Clear Computation Complete Flag before entering new block */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + for(index=0; index < 4; index ++) + { + hcryp->Instance->DINR = intermediate_data[index]; + } + } + else +#endif + { + /* Payload phase is now over */ + /* Clear Computation Complete Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Mark that the payload phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Call computation complete callback */ + HAL_CRYPEx_ComputationCpltCallback(hcryp); + } + return HAL_OK; + } + else + { + if (hcryp->CrypOutCount != 0) + { + /* Usual case (different than GCM/CCM last block < 128 bits ciphering) */ + /* Retrieve the last block available from the CRYP hardware block: + read the output block from the Data Output Register */ + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + + /* Increment/decrement instance pointer/counter */ + hcryp->pCrypOutBuffPtr += 16; + hcryp->CrypOutCount -= 16; + } +#if !defined(AES_CR_NPBLB) + else + { + /* Software work-around: additional DOUTR reading round to discard the data */ + for(index=0; index < 4; index ++) + { + intermediate_data[index] = hcryp->Instance->DOUTR; + } + } +#endif + } + + /* Check if all output text has been retrieved */ + if (hcryp->CrypOutCount == 0) + { +#if !defined(AES_CR_NPBLB) + /* Make sure that software-work around is not running before disabling + the interruptions (indeed, if software work-around is running, the + interruptions must not be disabled to allow the additional DOUTR + reading round */ + if (addhoc_process == 0) +#endif + { + /* Clear Computation Complete Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Mark that the payload phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Call computation complete callback */ + HAL_CRYPEx_ComputationCpltCallback(hcryp); + } + + return HAL_OK; + } + /* If suspension flag has been raised, suspend processing */ + else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) + { + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + /* Mark that the header phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return HAL_OK; + } + else /* Output data are still expected, carry on feeding the CRYP + hardware block with input data */ + { + /* Clear Computation Complete Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + /* Get the last Input data address */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Usual input data feeding case */ + if (hcryp->CrypInCount < 16) + { + difflength = (uint32_t) (hcryp->CrypInCount); + difflengthmod4 = difflength%4; + hcryp->CrypInCount = 0; + +#if defined(AES_CR_NPBLB) + /* In case of GCM encryption or CCM decryption, specify the number of padding + bytes in last block of payload */ + if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) + && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) + || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC) + && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) + { + /* Set NPBLB field in writing the number of padding bytes + for the last block of payload */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16 - difflength); + } +#else + /* Software workaround applied to GCM encryption only */ + if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) + { + /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ + __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR); + } +#endif + + /* Insert the last block (which size is inferior to 128 bits) padded with zeroes + to have a complete block of 128 bits */ + for(index=0; index < (difflength/4); index ++) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + } + /* If required, manage input data size not multiple of 32 bits */ + if (difflengthmod4 != 0) + { + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + } + /* Wrap-up in padding with zero-words if applicable */ + for(index=0; index < (4 - ((difflength+3)/4)); index ++) + { + hcryp->Instance->DINR = 0; + } + + } + else + { + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + } + + + return HAL_OK; + } + } + /*====================================*/ + /* GCM/GMAC or (CCM/)CMAC final phase */ + /*====================================*/ + else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + { + /* Clear Computation Complete Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + + /* Get the last output data address */ + outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; + + /* Retrieve the last expected data from the CRYP hardware block: + read the output block from the Data Output Register */ + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Mark that the header phase is over */ + hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER; + + /* Disable the Peripheral */ + __HAL_CRYP_DISABLE(); + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Call computation complete callback */ + HAL_CRYPEx_ComputationCpltCallback(hcryp); + + return HAL_OK; + } + else + { + /* Clear Computation Complete Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + hcryp->State = HAL_CRYP_STATE_ERROR; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + + + +/** + * @brief Set the DMA configuration and start the DMA transfer + * for GCM, GMAC or CMAC chainging modes. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param inputaddr: Address of the Input buffer. + * @param Size: Size of the Input buffer un bytes, must be a multiple of 16. + * @param outputaddr: Address of the Output buffer, null pointer when no output DMA stream + * has to be configured. + * @retval None + */ +static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) +{ + + /* Set the input CRYP DMA transfer complete callback */ + hcryp->hdmain->XferCpltCallback = CRYP_GCMCMAC_DMAInCplt; + /* Set the DMA error callback */ + hcryp->hdmain->XferErrorCallback = CRYP_GCMCMAC_DMAError; + + if (outputaddr != 0) + { + /* Set the output CRYP DMA transfer complete callback */ + hcryp->hdmaout->XferCpltCallback = CRYP_GCMCMAC_DMAOutCplt; + /* Set the DMA error callback */ + hcryp->hdmaout->XferErrorCallback = CRYP_GCMCMAC_DMAError; + } + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(); + + /* Enable the DMA input stream */ + HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4); + + /* Enable the DMA input request */ + SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); + + + if (outputaddr != 0) + { + /* Enable the DMA output stream */ + HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4); + + /* Enable the DMA output request */ + SET_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); + } +} + + + +/** + * @brief Write/read input/output data in polling mode. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Input: Pointer to the Input buffer. + * @param Ilength: Length of the Input buffer in bytes, must be a multiple of 16. + * @param Output: Pointer to the returned buffer. + * @param Timeout: Specify Timeout value. + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) +{ + uint32_t index = 0; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + + + for(index=0; (index < Ilength); index += 16) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + + /* Wait for CCF flag to be raised */ + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + + /* Read the Output block from the Data Output Register */ + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + + /* If the suspension flag has been raised and if the processing is not about + to end, suspend processing */ + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Ilength)) + { + /* Reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + + /* Save current reading and writing locations of Input and Output buffers */ + hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; + hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; + /* Save the number of bytes that remain to be processed at this point */ + hcryp->CrypInCount = Ilength - (index+16); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + + return HAL_OK; + } + + + } + /* Return function status */ + return HAL_OK; + +} + + + + + +/** + * @brief Read derivative key in polling mode when CRYP hardware block is set + * in key derivation operating mode (mode 2). + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Output: Pointer to the returned buffer. + * @param Timeout: Specify Timeout value. + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout) +{ + uint32_t outputaddr = (uint32_t)Output; + + /* Wait for CCF flag to be raised */ + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_TIMEOUT; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG( CRYP_CCF_CLEAR); + + /* Read the derivative key from the AES_KEYRx registers */ + if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) + { + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4); + outputaddr+=4; + } + + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1); + outputaddr+=4; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0); + + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the DMA configuration and start the DMA transfer. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param inputaddr: Address of the Input buffer. + * @param Size: Size of the Input buffer in bytes, must be a multiple of 16. + * @param outputaddr: Address of the Output buffer. + * @retval None + */ +static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) +{ + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; + /* Set the DMA error callback */ + hcryp->hdmain->XferErrorCallback = CRYP_DMAError; + + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt; + /* Set the DMA error callback */ + hcryp->hdmaout->XferErrorCallback = CRYP_DMAError; + + /* Enable the DMA input stream */ + HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4); + + /* Enable the DMA output stream */ + HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4); + + /* Enable In and Out DMA requests */ + SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(); +} + + +/** + * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((HAL_GetTick() - tickstart ) > Timeout) + { + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY)) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((HAL_GetTick() - tickstart ) > Timeout) + { + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + + +/** + * @brief DMA CRYP Input Data process complete callback. + * @param hdma: DMA handle. + * @retval None + */ +static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) +{ + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable the DMA transfer for input request */ + CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); + + /* Call input data transfer complete callback */ + HAL_CRYP_InCpltCallback(hcryp); +} + +/** + * @brief DMA CRYP Output Data process complete callback. + * @param hdma: DMA handle. + * @retval None + */ +static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) +{ + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable the DMA transfer for output request */ + CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(); + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Call output data transfer complete callback */ + HAL_CRYP_OutCpltCallback(hcryp); +} + +/** + * @brief DMA CRYP communication error callback. + * @param hdma: DMA handle. + * @retval None + */ +static void CRYP_DMAError(DMA_HandleTypeDef *hdma) +{ + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + hcryp->State= HAL_CRYP_STATE_ERROR; + hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; + HAL_CRYP_ErrorCallback(hcryp); + /* Clear Error Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR); +} + +/** + * @brief Last header or payload block padding when size is not a multiple of 128 bits. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param difflength: size remainder after having fed all complete 128-bit blocks. + * @param polling: specifies whether or not polling on CCF must be done after having + * entered a complete block. + * @retval None + */ +static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling) +{ + uint32_t index = 0; + uint32_t difflengthmod4 = difflength%4; + uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; + uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF}; + uint32_t intermediate_data[4] = {0}; + +#if defined(AES_CR_NPBLB) + /* In case of GCM encryption or CCM decryption, specify the number of padding + bytes in last block of payload */ + if (READ_BIT(hcryp->Instance->CR,AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE) + { + if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) + && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) + || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC) + && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) + { + /* Set NPBLB field in writing the number of padding bytes + for the last block of payload */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16 - difflength); + } + } +#else + /* Software workaround applied to GCM encryption only */ + if ((hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) && + (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)) + { + /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ + __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR); + } +#endif + + /* Wrap-up entering header or payload data */ + /* Enter complete words when possible */ + for(index=0; index < (difflength/4); index ++) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + } + /* Enter incomplete word padded with zeroes if applicable + (case of header length not a multiple of 32-bits) */ + if (difflengthmod4 != 0) + { + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + } + /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ + for(index=0; index < (4 - ((difflength+3)/4)); index ++) + { + hcryp->Instance->DINR = 0; + } + + if (polling == CRYP_POLLING_ON) + { + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + HAL_CRYP_ErrorCallback(hcryp); + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + } + + /* if payload */ + if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) + { + + /* Retrieve intermediate data */ + for(index=0; index < 4; index ++) + { + intermediate_data[index] = hcryp->Instance->DOUTR; + } + /* Retrieve last words of cyphered data */ + /* First, retrieve complete output words */ + for(index=0; index < (difflength/4); index ++) + { + *(uint32_t*)(outputaddr) = intermediate_data[index]; + outputaddr+=4; + } + /* Next, retrieve partial output word if applicable; + at the same time, start masking intermediate data + with a mask of zeros of same size than the padding + applied to the last block of payload */ + if (difflengthmod4 != 0) + { + intermediate_data[difflength/4] &= mask[difflengthmod4-1]; + *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; + } + + +#if !defined(AES_CR_NPBLB) + /* Software workaround applied to GCM encryption only, + applicable for AES IP v2 version (where NPBLB is not defined) */ + if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) + { + /* Change again CHMOD configuration to GCM mode */ + __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC); + + /* Select FINAL phase */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE); + + /* Before inserting the intermediate data, carry on masking operation + with a mask of zeros of same size than the padding applied to the last block of payload */ + for(index=0; index < (4 - ((difflength+3)/4)); index ++) + { + intermediate_data[(difflength+3)/4+index] = 0; + } + /* Insert intermediate data */ + for(index=0; index < 4; index ++) + { + hcryp->Instance->DINR = intermediate_data[index]; + } + + /* Wait for completion, and read data on DOUT. This data is to discard. */ + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + HAL_CRYP_ErrorCallback(hcryp); + } + + /* Read data to discard */ + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); + for(index=0; index < 4; index ++) + { + intermediate_data[index] = hcryp->Instance->DOUTR; + } + + } /* if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) */ +#endif /* !defined(AES_CR_NPBLB) */ + } /* if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) */ + +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* AES */ + #endif /* HAL_CRYP_MODULE_ENABLED */ /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.h index b57efa4abad..b4e2e16440e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of CRYP HAL Extension module. ****************************************************************************** * @attention @@ -209,6 +209,76 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp); #endif /* CRYP */ +#if defined (AES) + +/** @addtogroup CRYPEx_Exported_Functions + * @{ + */ + +/** @addtogroup CRYPEx_Exported_Functions_Group1 + * @{ + */ + +/* CallBack functions ********************************************************/ +void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** @addtogroup CRYPEx_Exported_Functions_Group2 + * @{ + */ + +/* AES encryption/decryption processing functions ****************************/ +HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData); +HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData); + +/* AES encryption/decryption/authentication processing functions *************/ +HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData); +HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData); + +/** + * @} + */ + +/** @addtogroup CRYPEx_Exported_Functions_Group3 + * @{ + */ + +/* AES suspension/resumption functions ***************************************/ +void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output); +void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input); +void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output); +void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input); +void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize); +void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize); +void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output); +void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input); +void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions + * @{ + */ +HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +#endif /* AES */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.c index 45623d94f5a..aa73c6d6474 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.h index 073b38ce103..c080d6c9eb7 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.c index dadf2cbf97f..1edb4c85dfd 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Extended DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.h index 29d118fd347..7a72f44816a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.c index e00732de96e..aef1928bf95 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief DCMI HAL module driver * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.h index a96fc9bd8aa..56f5dc35e45 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of DCMI HAL module. ****************************************************************************** * @attention @@ -43,10 +43,10 @@ extern "C" { #endif -#if defined (DCMI) - /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" + +#if defined (DCMI) /** @addtogroup STM32F7xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.c index 4a956bb5cb1..f75061702f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Empty file; This file is no longer used to handle the Black&White * feature. Its content is now moved to common files * (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7 diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.h index 914dab5d8f0..c43b1887fa3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of DCMI Extension HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h index f7843f84a27..b41b409bf6c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_def.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.c index ce18015f381..553758ca5e6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dfsdm.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Digital Filter for Sigma-Delta Modulators * (DFSDM) peripherals: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.h index 9c913f52432..ab120d1db89 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dfsdm.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of DFSDM HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.c index cbe50bceced..ee8aea7bbbe 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.h index 7e9e4a54f2c..d739e35800f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.c index 084a23e6fda..91ea3a1d91e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma2d.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief DMA2D HAL module driver. * This file provides firmware functions to manage the following * functionalities of the DMA2D peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.h index 1e4a1396228..8d6befe0d45 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma2d.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of DMA2D HAL module. ****************************************************************************** * @attention @@ -43,11 +43,11 @@ extern "C" { #endif -#if defined (DMA2D) - /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" +#if defined (DMA2D) + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.c index 4fcaf507014..4035d0bc937 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.h index f2f3a4f9b62..cace40a181f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention @@ -93,7 +93,9 @@ typedef enum #define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */ #define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */ #define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) #define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */ #define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */ #define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10*/ @@ -102,7 +104,8 @@ typedef enum #define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13*/ #define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14*/ #define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15*/ -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} @@ -140,7 +143,9 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre * @brief DMAEx private macros * @{ */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ ((CHANNEL) == DMA_CHANNEL_1) || \ ((CHANNEL) == DMA_CHANNEL_2) || \ @@ -166,7 +171,8 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre ((CHANNEL) == DMA_CHANNEL_5) || \ ((CHANNEL) == DMA_CHANNEL_6) || \ ((CHANNEL) == DMA_CHANNEL_7)) -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.c index d60ec186d39..5eae306b3e8 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dsi.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief DSI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the DSI peripheral: @@ -605,11 +605,7 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) @verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) - (+) - (+) + =============================================================================== @endverbatim * @{ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.h index 3d304374021..4eaf8ac13a2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dsi.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of DSI HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c index f250a989924..e24adf81df3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_eth.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief ETH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.h index 970b4152c70..367cafbbb53 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_eth.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of ETH HAL module. ****************************************************************************** * @attention @@ -43,11 +43,11 @@ extern "C" { #endif -#if defined (ETH) - /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" +#if defined (ETH) + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.c index 7ac109eb6de..6d2ede12e89 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -801,6 +801,13 @@ static void FLASH_SetErrorCode(void) pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS; } +#if defined (FLASH_OPTCR2_PCROP) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + } +#endif /* FLASH_OPTCR2_PCROP */ + /* Clear error programming flags */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); } diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.h index acb2afa98d6..26d03da06ae 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention @@ -111,6 +111,7 @@ typedef struct #define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */ #define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */ #define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */ +#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000040U) /*!< Read Protection Error */ /** * @} */ @@ -138,9 +139,14 @@ typedef struct #define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */ #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ - +#if defined (FLASH_OPTCR2_PCROP) +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protection error flag */ +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR) +#else #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR) +#endif /* FLASH_OPTCR2_PCROP */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.c index 47d0a6c9eef..73481562130 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extension peripheral: @@ -131,6 +131,13 @@ static void FLASH_MassErase(uint8_t VoltageRange); static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby); #endif /* FLASH_OPTCR_nDBANK */ +#if defined (FLASH_OPTCR2_PCROP) +static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector); +static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp); +static uint32_t FLASH_OB_GetPCROP(void); +static uint32_t FLASH_OB_GetPCROPRDP(void); +#endif /* FLASH_OPTCR2_PCROP */ + extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @} @@ -366,6 +373,20 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1); } + +#if defined (FLASH_OPTCR2_PCROP) + /* PCROP configuration */ + if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + { + status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector); + } + + /* PCROP_RDP configuration */ + if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP) + { + status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp); + } +#endif /* FLASH_OPTCR2_PCROP */ /* Process Unlocked */ __HAL_UNLOCK(&pFlash); @@ -402,6 +423,14 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) /*Get Boot Address when Boot pin = 1 */ pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1); + +#if defined (FLASH_OPTCR2_PCROP) + /*Get PCROP Sectors */ + pOBInit->PCROPSector = FLASH_OB_GetPCROP(); + + /*Get PCROP_RDP Value */ + pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP(); +#endif /* FLASH_OPTCR2_PCROP */ } /** * @} @@ -1021,6 +1050,79 @@ static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption) return Address; } +#if defined (FLASH_OPTCR2_PCROP) +/** + * @brief Set the PCROP protection for sectors. + * @param PCROPSector: specifies the sector(s) to be PCROP protected. + * This parameter can be one of the following values: + * @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7 + * @arg OB_PCROP_SECTOR_ALL + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_SECTOR(PCROPSector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP, PCROPSector); + } + + return status; +} + +/** + * @brief Set the PCROP_RDP value + * @param Pcrop_Rdp: specifies the PCROP_RDP bit value. + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_RDP_VALUE(Pcrop_Rdp)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP_RDP, Pcrop_Rdp); + } + + return status; +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @retval uint32_t FLASH PCROP Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetPCROP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP)); +} + +/** + * @brief Return the FLASH PCROP_RDP option byte value. + * @retval uint32_t FLASH PCROP_RDP option byte value + */ +static uint32_t FLASH_OB_GetPCROPRDP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP_RDP)); +} +#endif /* FLASH_OPTCR2_PCROP */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.h index 213dcde793e..d28b8880dd7 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of FLASH HAL Extension module. ****************************************************************************** * @attention @@ -113,6 +113,14 @@ typedef struct uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1. This parameter can be a value of @ref FLASHEx_Boot_Address */ +#if defined (FLASH_OPTCR2_PCROP) + uint32_t PCROPSector; /*!< Set the PCROP sector. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */ + + uint32_t PCROPRdp; /*!< Set the PCROP_RDP option. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */ +#endif /* FLASH_OPTCR2_PCROP */ + } FLASH_OBProgramInitTypeDef; /** @@ -162,6 +170,10 @@ typedef struct #define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */ #define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */ #define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */ +#if defined (FLASH_OPTCR2_PCROP) +#define OPTIONBYTE_PCROP ((uint32_t)0x40U) /*!< PCROP configuration */ +#define OPTIONBYTE_PCROP_RDP ((uint32_t)0x80U) /*!< PCROP_RDP configuration */ +#endif /* FLASH_OPTCR2_PCROP */ /** * @} */ @@ -275,7 +287,11 @@ typedef struct #define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */ #define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */ #define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */ +#if (SRAM2_BASE == 0x2003C000U) +#define OB_BOOTADDR_SRAM2 ((uint32_t)0x800FU) /*!< Boot from SRAM2 (0x2003C000) */ +#else #define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */ +#endif /* SRAM2_BASE == 0x2003C000U */ /** * @} */ @@ -426,6 +442,33 @@ typedef struct */ #endif /* FLASH_SECTOR_TOTAL == 8 */ +#if defined (FLASH_OPTCR2_PCROP) +/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors + * @{ + */ +#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ +#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ +#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ +#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ +#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4 */ +#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5 */ +#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6 */ +#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7 */ +#define OB_PCROP_SECTOR_All ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit + * @{ + */ +#define OB_PCROP_RDP_ENABLE ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable */ +#define OB_PCROP_RDP_DISABLE ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable */ +/** + * @} + */ +#endif /* FLASH_OPTCR2_PCROP */ + /** * @} */ @@ -489,8 +532,14 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); #define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \ ((VALUE) == OB_WRPSTATE_ENABLE)) +#if defined (FLASH_OPTCR2_PCROP) +#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\ + OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP))) +#else #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1))) +#endif /* FLASH_OPTCR2_PCROP */ #define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013) @@ -530,8 +579,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); ((LATENCY) == FLASH_LATENCY_14) || \ ((LATENCY) == FLASH_LATENCY_15)) -#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) - +#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ + (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END))) #define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) #if (FLASH_SECTOR_TOTAL == 8) @@ -574,6 +623,12 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); ((VALUE) == OB_DUAL_BOOT_ENABLE)) #endif /* FLASH_OPTCR_nDBOOT */ +#if defined (FLASH_OPTCR2_PCROP) +#define IS_OB_PCROP_SECTOR(SECTOR) (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U) +#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \ + ((VALUE) == OB_PCROP_RDP_ENABLE)) +#endif /* FLASH_OPTCR2_PCROP */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.c index 90d33c040fc..a9461563f35 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.h index fb8748d3294..39910925e8d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio_ex.h index c0b07ae68a0..c4ad1b89aee 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention @@ -237,6 +237,122 @@ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /*----------------------------------------------------------------------------*/ +/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/ +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) + /** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_RNG ((uint8_t)0x0DU) /* RNG Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ +/*----------------------------------------------------------------------------*/ + /** * @} */ @@ -309,6 +425,16 @@ ((__GPIOx__) == (GPIOJ))? 9U : 10U) #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ /** * @} */ @@ -487,6 +613,33 @@ ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ ((AF) == GPIO_AF10_OTG_FS)) +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI3) || \ + ((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF9_QUADSPI) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QUADSPI) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ + ((AF) == GPIO_AF10_OTG_FS)) #endif /* STM32F756xx || STM32F746xx */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.c index dc6882c6318..1599992c8e2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.h index bbeee618650..73f1caef585 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of HASH HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.c index 5328b8351c9..07fc57be1c8 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief HASH HAL Extension module driver. * This file provides firmware functions to manage the following * functionalities of HASH peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.h index 5109158a774..96b17c0d2c8 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of HASH HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c index 52c73f1f2d8..860708d4a2b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hcd.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief HCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.h index 4653ef8a4d9..568bcc259bd 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hcd.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.c index 8734d31f1a6..708fd8666d8 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -17,7 +17,7 @@ ============================================================================== [..] The I2C HAL driver can be used as follows: - + (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; @@ -81,24 +81,24 @@ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2C_ErrorCallback() (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO sequential operation *** - =================================== + ============================================== [..] (@) These interfaces allow to manage a sequential transfer with a repeated start condition when a direction change during transfer [..] (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition, an then permit a call the same master sequential interface several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address @@ -118,8 +118,6 @@ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit - (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). @@ -175,8 +173,8 @@ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2C_ErrorCallback() (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -262,16 +260,16 @@ /** @defgroup I2C_Private_Define I2C Private Define * @{ */ -#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ -#define I2C_TIMEOUT_ADDR ((uint32_t)10000U) /*!< 10 s */ -#define I2C_TIMEOUT_BUSY ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_DIR ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_RXNE ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_STOPF ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TC ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TCR ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TXIS ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_FLAG ((uint32_t)25U) /*!< 25 ms */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ #define MAX_NBYTE_SIZE 255U #define SlaveAddr_SHIFT 7U @@ -287,17 +285,18 @@ #define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ #define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT ((uint32_t)0x00000001U) -#define I2C_XFER_RX_IT ((uint32_t)0x00000002U) -#define I2C_XFER_LISTEN_IT ((uint32_t)0x00000004U) +#define I2C_XFER_TX_IT (0x00000001U) +#define I2C_XFER_RX_IT (0x00000002U) +#define I2C_XFER_LISTEN_IT (0x00000004U) -#define I2C_XFER_ERROR_IT ((uint32_t)0x00000011U) -#define I2C_XFER_CPLT_IT ((uint32_t)0x00000012U) -#define I2C_XFER_RELOAD_IT ((uint32_t)0x00000012U) +#define I2C_XFER_ERROR_IT (0x00000011U) +#define I2C_XFER_CPLT_IT (0x00000012U) +#define I2C_XFER_RELOAD_IT (0x00000012U) /* Private define Sequential Transfer Options default/reset value */ -#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U) +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) /** * @} */ @@ -400,8 +399,8 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui /** * @brief Initializes the I2C according to the specified parameters * in the I2C_InitTypeDef and initialize the associated handle. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) @@ -476,19 +475,19 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); - + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; - + return HAL_OK; } /** * @brief DeInitialize the I2C peripheral. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) @@ -498,23 +497,23 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - + hi2c->State = HAL_I2C_STATE_BUSY; - + /* Disable the I2C Peripheral Clock */ __HAL_I2C_DISABLE(hi2c); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_I2C_MspDeInit(hi2c); - + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_RESET; hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Release Lock */ __HAL_UNLOCK(hi2c); @@ -523,15 +522,15 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /** * @brief Initialize the I2C MSP. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspInit could be implemented in the user file */ @@ -539,15 +538,15 @@ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) /** * @brief DeInitialize the I2C MSP. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspDeInit could be implemented in the user file */ @@ -618,32 +617,32 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) /** * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address. The device 7 bits address value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shift at right before call interface - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -652,7 +651,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; - + /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if(hi2c->XferCount > MAX_NBYTE_SIZE) @@ -665,8 +664,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } - - while(hi2c->XferSize > 0) + + while(hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) @@ -684,15 +683,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferCount--; hi2c->XferSize--; - - if((hi2c->XferSize == 0) && (hi2c->XferCount!=0)) + + if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; @@ -705,7 +704,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA } } } - + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) @@ -719,19 +718,19 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA return HAL_TIMEOUT; } } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -742,41 +741,41 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /** * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address. The device 7 bits address value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shift at right before call interface - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) - { + { /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; - + /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if(hi2c->XferCount > MAX_NBYTE_SIZE) @@ -789,8 +788,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } - - while(hi2c->XferSize > 0) + + while(hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) @@ -804,20 +803,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd return HAL_TIMEOUT; } } - + /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferSize--; hi2c->XferCount--; - - if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) + + if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; @@ -830,7 +829,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } } } - + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) @@ -844,19 +843,19 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd return HAL_TIMEOUT; } } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -867,41 +866,41 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /** * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; - + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - + /* Wait until ADDR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { @@ -909,10 +908,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - + /* If 10bit addressing mode is selected */ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { @@ -923,11 +922,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); } - + /* Wait until DIR flag is set Transmitter mode */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) { @@ -935,15 +934,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - - while(hi2c->XferCount > 0) + + while(hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; @@ -953,18 +952,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData return HAL_TIMEOUT; } } - + /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferCount--; } - + /* Wait until STOP flag is set */ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Normal use case for Transmitter mode */ @@ -976,10 +975,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData return HAL_TIMEOUT; } } - + /* Clear STOP flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); - + /* Wait until BUSY flag is reset */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { @@ -987,16 +986,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - + /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1007,41 +1006,41 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /** * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL ) || (Size == 0)) + { + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; - + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - + /* Wait until ADDR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { @@ -1049,10 +1048,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - + /* Wait until DIR flag is reset Receiver mode */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) { @@ -1060,15 +1059,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - - while(hi2c->XferCount > 0) + + while(hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + /* Store Last receive data if any */ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) { @@ -1086,18 +1085,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, return HAL_ERROR; } } - + /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferCount--; } - + /* Wait until STOP flag is set */ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; @@ -1107,10 +1106,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, return HAL_TIMEOUT; } } - + /* Clear STOP flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); - + /* Wait until BUSY flag is reset */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { @@ -1118,16 +1117,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - + /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1138,32 +1137,32 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /** * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address. The device 7 bits address value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shift at right before call interface - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0; - + uint32_t xfermode = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } - + /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -1180,23 +1179,23 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } - + /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - + return HAL_OK; } else @@ -1207,32 +1206,32 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /** * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address. The device 7 bits address value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shift at right before call interface - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0; - + uint32_t xfermode = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } - + /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -1249,7 +1248,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } - + /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); @@ -1260,12 +1259,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - + return HAL_OK; } else @@ -1276,10 +1275,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /** * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) @@ -1288,33 +1287,33 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD { /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_IT; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - + return HAL_OK; } else @@ -1325,10 +1324,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /** * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) @@ -1337,33 +1336,33 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa { /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_IT; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - + return HAL_OK; } else @@ -1374,32 +1373,32 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa /** * @brief Transmit in master mode an amount of data in non-blocking mode with DMA - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address. The device 7 bits address value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shift at right before call interface - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0; - + uint32_t xfermode = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } - + /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -1416,39 +1415,62 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + return HAL_OK; } else @@ -1459,32 +1481,32 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /** * @brief Receive in master mode an amount of data in non-blocking mode with DMA - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address. The device 7 bits address value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shift at right before call interface - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0; - + uint32_t xfermode = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } - + /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -1501,48 +1523,60 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } - - if(hi2c->XferSize > 0) + + if(hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - + /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - + /* Set the unused DMA callbacks to NULL */ hi2c->hdmarx->XferHalfCpltCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; - + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - + /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - + /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR and NACK interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - + /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } else { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + /* Process Unlocked */ __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } return HAL_OK; } @@ -1554,62 +1588,62 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /** * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; - + /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - + /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - + /* Set the unused DMA callbacks to NULL */ hi2c->hdmatx->XferHalfCpltCallback = NULL; hi2c->hdmatx->XferAbortCallback = NULL; - + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - + /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - + return HAL_OK; } else @@ -1620,62 +1654,62 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p /** * @brief Receive in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; - } + } /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; - + /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - + /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - + /* Set the unused DMA callbacks to NULL */ hi2c->hdmarx->XferHalfCpltCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; - + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - + /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - + return HAL_OK; } else @@ -1685,50 +1719,51 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; - + /* Send Slave Address and Memory Address */ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { @@ -1745,7 +1780,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress return HAL_TIMEOUT; } } - + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ if(hi2c->XferCount > MAX_NBYTE_SIZE) { @@ -1757,7 +1792,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } - + do { /* Wait until TXIS flag is set */ @@ -1772,20 +1807,20 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress return HAL_TIMEOUT; } } - + /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferCount--; hi2c->XferSize--; - - if((hi2c->XferSize == 0) && (hi2c->XferCount!=0)) + + if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; @@ -1797,9 +1832,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - - }while(hi2c->XferCount > 0); - + + }while(hi2c->XferCount > 0U); + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) @@ -1813,19 +1848,19 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress return HAL_TIMEOUT; } } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1836,50 +1871,51 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /** * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; - + /* Send Slave Address and Memory Address */ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { @@ -1896,7 +1932,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, return HAL_TIMEOUT; } } - + /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if(hi2c->XferCount > MAX_NBYTE_SIZE) @@ -1909,7 +1945,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } - + do { /* Wait until RXNE flag is set */ @@ -1917,20 +1953,20 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, { return HAL_TIMEOUT; } - + /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferSize--; hi2c->XferCount--; - - if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) + + if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; @@ -1942,8 +1978,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - }while(hi2c->XferCount > 0); - + }while(hi2c->XferCount > 0U); + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) @@ -1957,19 +1993,19 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, return HAL_TIMEOUT; } } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1979,26 +2015,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } /** * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0; - uint32_t xfermode = 0; - + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2007,17 +2044,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr { return HAL_BUSY; } - + /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -2034,7 +2071,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } - + /* Send Slave Address and Memory Address */ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { @@ -2051,22 +2088,22 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr return HAL_TIMEOUT; } } - + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - + return HAL_OK; } else @@ -2077,26 +2114,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /** * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0; - uint32_t xfermode = 0; - + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2105,17 +2143,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre { return HAL_BUSY; } - + /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -2132,7 +2170,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } - + /* Send Slave Address and Memory Address */ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { @@ -2149,70 +2187,71 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre return HAL_TIMEOUT; } } - + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - + return HAL_OK; } else { return HAL_BUSY; - } + } } /** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0; - uint32_t xfermode = 0; - + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } - + /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -2229,7 +2268,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } - + /* Send Slave Address and Memory Address */ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { @@ -2246,39 +2285,39 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd return HAL_TIMEOUT; } } - + /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - + /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - + /* Set the unused DMA callbacks to NULL */ hi2c->hdmatx->XferHalfCpltCallback = NULL; hi2c->hdmatx->XferAbortCallback = NULL; - + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - + /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - + /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR and NACK interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - + /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - + return HAL_OK; } else @@ -2289,51 +2328,52 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /** * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be read + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0; - uint32_t xfermode = 0; - + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } - + /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; @@ -2344,7 +2384,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } - + /* Send Slave Address and Memory Address */ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { @@ -2361,38 +2401,38 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr return HAL_TIMEOUT; } } - + /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - + /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - + /* Set the unused DMA callbacks to NULL */ hi2c->hdmarx->XferHalfCpltCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; - + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - + /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR and NACK interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - + return HAL_OK; } else @@ -2404,37 +2444,38 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /** * @brief Checks if target device is ready for communication. * @note This function is used with Memory devices - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param Trials: Number of trials - * @param Timeout: Timeout duration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param Trials Number of trials + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - __IO uint32_t I2C_Trials = 0; - +{ + uint32_t tickstart = 0U; + + __IO uint32_t I2C_Trials = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } - + /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + do { /* Generate Start */ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); - + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); @@ -2442,7 +2483,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; @@ -2452,7 +2493,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } } } - + /* Check if the NACKF flag has not been set */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) { @@ -2461,55 +2502,55 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else { - /* Wait until STOPF flag is reset */ + /* Wait until STOPF flag is reset */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Clear STOP Flag, auto generated with autoend*/ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - + /* Check if the maximum allowed number of trials has been reached */ if (I2C_Trials++ == Trials) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; - + /* Wait until STOPF flag is reset */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } }while(I2C_Trials < Trials); - + hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_TIMEOUT; } else @@ -2521,32 +2562,32 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address. The device 7 bits address value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shift at right before call interface - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { - uint32_t xfermode = 0; + uint32_t xfermode = 0U; uint32_t xferrequest = I2C_GENERATE_START_WRITE; - + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - + if(hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -2564,7 +2605,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferSize = hi2c->XferCount; xfermode = hi2c->XferOptions; } - + /* Send Slave Address and set NBYTES to write */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); @@ -2575,7 +2616,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, to avoid the risk of I2C interrupt handle execution before current process unlock */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - + return HAL_OK; } else @@ -2587,38 +2628,38 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address. The device 7 bits address value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shift at right before call interface - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { - uint32_t xfermode = 0; + uint32_t xfermode = 0U; uint32_t xferrequest = I2C_GENERATE_START_READ; - + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - + if(hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); hi2c->XferISR = I2C_Master_ISR_IT; - + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ if(hi2c->XferCount > MAX_NBYTE_SIZE) { @@ -2629,19 +2670,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, { hi2c->XferSize = hi2c->XferCount; xfermode = hi2c->XferOptions; + } - + /* Send Slave Address and set NBYTES to read */ I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest); - + /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - + __HAL_UNLOCK(hi2c); + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - + return HAL_OK; } else @@ -2653,61 +2695,69 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if(hi2c->State == HAL_I2C_STATE_LISTEN) + + if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - + /* Process Locked */ __HAL_LOCK(hi2c); + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + } + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - + if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); } - + /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - + __HAL_UNLOCK(hi2c); + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - + return HAL_OK; } else @@ -2719,61 +2769,69 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if(hi2c->State == HAL_I2C_STATE_LISTEN) + + if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - + /* Process Locked */ __HAL_LOCK(hi2c); + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + } + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - + if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); } - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - + return HAL_OK; } else @@ -2784,8 +2842,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /** * @brief Enable the Address listen mode with Interrupt. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) @@ -2794,10 +2852,10 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) { hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->XferISR = I2C_Slave_ISR_IT; - + /* Enable the Address Match interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - + return HAL_OK; } else @@ -2808,15 +2866,15 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) /** * @brief Disable the Address listen mode with Interrupt. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) { /* Declaration of tmp to prevent undefined behavior of volatile usage */ uint32_t tmp; - + /* Disable Address listen mode only if a transfer is not ongoing */ if(hi2c->State == HAL_I2C_STATE_LISTEN) { @@ -2825,10 +2883,10 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; - + /* Disable the Address Match interrupt */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - + return HAL_OK; } else @@ -2839,8 +2897,8 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) /** * @brief Abort a master I2C IT or DMA process communication with Interrupt. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shift at right before call interface * @retval HAL status @@ -2851,26 +2909,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA { /* Process Locked */ __HAL_LOCK(hi2c); - + /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - + /* Set State at HAL_I2C_STATE_ABORT */ hi2c->State = HAL_I2C_STATE_ABORT; - + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - I2C_TransferConfig(hi2c, 0, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); - + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - + return HAL_OK; } else @@ -2891,8 +2949,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /** * @brief This function handles I2C event interrupt request. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) @@ -2900,7 +2958,7 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hi2c->Instance->ISR); uint32_t itsources = READ_REG(hi2c->Instance->CR1); - + /* I2C events treatment -------------------------------------*/ if(hi2c->XferISR != NULL) { @@ -2910,42 +2968,42 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /** * @brief This function handles I2C error interrupt request. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { uint32_t itflags = READ_REG(hi2c->Instance->ISR); uint32_t itsources = READ_REG(hi2c->Instance->CR1); - + /* I2C Bus error interrupt occurred ------------------------------------*/ if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; - + /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); } - + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; - + /* Clear OVR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); } - + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; - + /* Clear ARLO flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); } - + /* Call the Error Callback in case of Error detected */ if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { @@ -2955,15 +3013,15 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) /** * @brief Master Tx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterTxCpltCallback could be implemented in the user file */ @@ -2971,30 +3029,30 @@ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief Master Rx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterRxCpltCallback could be implemented in the user file */ } /** @brief Slave Tx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file */ @@ -3002,15 +3060,15 @@ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief Slave Rx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file */ @@ -3018,9 +3076,9 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief Slave Address Match callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION * @param AddrMatchCode: Address Match Code * @retval None */ @@ -3030,7 +3088,7 @@ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirect UNUSED(hi2c); UNUSED(TransferDirection); UNUSED(AddrMatchCode); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AddrCallback() could be implemented in the user file */ @@ -3038,15 +3096,15 @@ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirect /** * @brief Listen Complete callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ListenCpltCallback() could be implemented in the user file */ @@ -3054,15 +3112,15 @@ __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief Memory Tx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MemTxCpltCallback could be implemented in the user file */ @@ -3070,15 +3128,15 @@ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief Memory Rx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MemRxCpltCallback could be implemented in the user file */ @@ -3086,15 +3144,15 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief I2C error callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ErrorCallback could be implemented in the user file */ @@ -3102,15 +3160,15 @@ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) /** * @brief I2C abort callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AbortCpltCallback could be implemented in the user file */ @@ -3137,8 +3195,8 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief Return the I2C handle state. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL state */ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) @@ -3149,7 +3207,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) /** * @brief Returns the I2C Master, Slave, Memory or no mode. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL mode */ @@ -3160,7 +3218,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) /** * @brief Return the I2C error code. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval I2C Error Code */ @@ -3183,29 +3241,29 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags: Interrupt flags to handle. - * @param ITSources: Interrupt sources enabled. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t devaddress = 0; + uint16_t devaddress = 0U; /* Process Locked */ __HAL_LOCK(hi2c); - + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Set corresponding Error Code */ /* No need to generate STOP, it is automatically done */ /* Error callback will be send during stop flag treatment */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - + /* Flush TX register */ I2C_Flush_TXDR(hi2c); } @@ -3221,11 +3279,11 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferSize--; - hi2c->XferCount--; + hi2c->XferCount--; } else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) + if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); @@ -3250,7 +3308,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { /* Call TxCpltCallback() if no stop mode is set */ - if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER)) + if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Call I2C Master Sequential complete process */ I2C_ITMasterSequentialCplt(hi2c); @@ -3265,12 +3323,21 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if(hi2c->XferCount == 0) + if(hi2c->XferCount == 0U) { - if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER)) + if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); + /* Generate a stop condition in case of no transfer option */ + if(hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } } } else @@ -3280,25 +3347,25 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - + if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); } - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags: Interrupt flags to handle. - * @param ITSources: Interrupt sources enabled. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) @@ -3312,7 +3379,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hi2c->XferCount == 0) + if(hi2c->XferCount == 0U) { if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ (hi2c->State == HAL_I2C_STATE_LISTEN)) @@ -3324,10 +3391,10 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - + /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSequentialCplt(hi2c); @@ -3343,22 +3410,22 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { - if(hi2c->XferCount > 0) + if(hi2c->XferCount > 0U) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferSize--; hi2c->XferCount--; } - - if((hi2c->XferCount == 0) && \ + + if((hi2c->XferCount == 0U) && \ (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ @@ -3375,7 +3442,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* A TXIS flag can be set, during STOP treatment */ /* Check if all Datas have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hi2c->XferCount > 0) + if(hi2c->XferCount > 0U) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); @@ -3392,14 +3459,14 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } } } - + /* Check if STOPF is set */ if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3408,25 +3475,25 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags: Interrupt flags to handle. - * @param ITSources: Interrupt sources enabled. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t devaddress = 0; - uint32_t xfermode = 0; - + uint16_t devaddress = 0U; + uint32_t xfermode = 0U; + /* Process Locked */ __HAL_LOCK(hi2c); - + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; @@ -3434,7 +3501,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - + /* Flush TX register */ I2C_Flush_TXDR(hi2c); } @@ -3443,7 +3510,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - if(hi2c->XferCount != 0) + if(hi2c->XferCount != 0U) { /* Recover Slave address */ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); @@ -3459,13 +3526,13 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } - + /* Set the new XferSize in Nbytes register */ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - + /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; - + /* Enable DMA Request */ if(hi2c->State == HAL_I2C_STATE_BUSY_RX) { @@ -3488,7 +3555,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); } - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3497,10 +3564,10 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags: Interrupt flags to handle. - * @param ITSources: Interrupt sources enabled. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) @@ -3514,7 +3581,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ - if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0) + if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3542,25 +3609,26 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } /** * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param Timeout: Timeout duration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - + /* Wait until TXIS flag is set */ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { @@ -3573,7 +3641,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ return HAL_TIMEOUT; } } - + /* If Memory address size is 8Bit */ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) { @@ -3585,7 +3653,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ { /* Send MSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - + /* Wait until TXIS flag is set */ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { @@ -3602,31 +3670,32 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } - + /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + return HAL_OK; } /** * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param Timeout: Timeout duration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - + /* Wait until TXIS flag is set */ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { @@ -3639,7 +3708,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t return HAL_TIMEOUT; } } - + /* If Memory address size is 8Bit */ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) { @@ -3651,7 +3720,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t { /* Send MSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - + /* Wait until TXIS flag is set */ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { @@ -3668,7 +3737,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } - + /* Wait until TC flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { @@ -3680,17 +3749,20 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /** * @brief I2C Address complete process callback. - * @param hi2c: I2C handle. - * @param ITFlags: Interrupt flags to handle. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { - uint8_t transferdirection = 0; - uint16_t slaveaddrcode = 0; - uint16_t ownadd1code = 0; - uint16_t ownadd2code = 0; - + uint8_t transferdirection = 0U; + uint16_t slaveaddrcode = 0U; + uint16_t ownadd1code = 0U; + uint16_t ownadd2code = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + /* In case of Listen state, need to inform upper layer of address match code event */ if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { @@ -3698,7 +3770,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); - + /* If 10bits addressing mode is selected */ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { @@ -3706,17 +3778,17 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { slaveaddrcode = ownadd1code; hi2c->AddrEventCount++; - if(hi2c->AddrEventCount == 2) + if(hi2c->AddrEventCount == 2U) { - /* Reset Address Event counter */ - hi2c->AddrEventCount = 0; - + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call Slave Addr callback */ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); } @@ -3724,13 +3796,13 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else { slaveaddrcode = ownadd2code; - + /* Disable ADDR Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call Slave Addr callback */ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); } @@ -3740,10 +3812,10 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { /* Disable ADDR Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call Slave Addr callback */ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); } @@ -3753,7 +3825,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); } @@ -3761,14 +3833,14 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /** * @brief I2C Master sequential complete process. - * @param hi2c: I2C handle. + * @param hi2c I2C handle. * @retval None */ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) { /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; - + /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) @@ -3776,13 +3848,13 @@ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) hi2c->State = HAL_I2C_STATE_READY; hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; hi2c->XferISR = NULL; - + /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_MasterTxCpltCallback(hi2c); } @@ -3792,13 +3864,13 @@ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) hi2c->State = HAL_I2C_STATE_READY; hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; hi2c->XferISR = NULL; - + /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_MasterRxCpltCallback(hi2c); } @@ -3806,42 +3878,42 @@ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) /** * @brief I2C Slave sequential complete process. - * @param hi2c: I2C handle. + * @param hi2c I2C handle. * @retval None */ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) { /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; - + if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - + /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the Tx complete callback to inform upper layer of the end of transmit process */ HAL_I2C_SlaveTxCpltCallback(hi2c); } - + else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - + /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the Rx complete callback to inform upper layer of the end of receive process */ HAL_I2C_SlaveRxCpltCallback(hi2c); } @@ -3849,40 +3921,40 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) /** * @brief I2C Master complete process. - * @param hi2c: I2C handle. - * @param ITFlags: Interrupt flags to handle. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - + /* Reset handle parameters */ hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - + if((ITFlags & I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Set acknowledge error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - + /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT); - + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); @@ -3891,24 +3963,24 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; - + if (hi2c->Mode == HAL_I2C_MODE_MEM) { hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_MemTxCpltCallback(hi2c); } else { hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_MasterTxCpltCallback(hi2c); } @@ -3917,23 +3989,23 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; - + if (hi2c->Mode == HAL_I2C_MODE_MEM) { hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + HAL_I2C_MemRxCpltCallback(hi2c); } else { hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + HAL_I2C_MasterRxCpltCallback(hi2c); } } @@ -3941,80 +4013,84 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /** * @brief I2C Slave complete process. - * @param hi2c: I2C handle. - * @param ITFlags: Interrupt flags to handle. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - + /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); - + /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - + /* If a DMA is ongoing, Update handle size context */ if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) { - if((hi2c->XferSize - I2C_GET_DMA_REMAIN_DATA(hi2c)) != hi2c->XferSize) - { - hi2c->XferSize = I2C_GET_DMA_REMAIN_DATA(hi2c); - hi2c->XferCount += hi2c->XferSize; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } + hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); } - + + /* All data are not transferred, so set error code accordingly */ + if(hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + /* Store Last receive data if any */ if(((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if((hi2c->XferSize > 0)) + + if((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - + hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; - + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) { - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->State = HAL_I2C_STATE_READY; - /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } } else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) { hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ HAL_I2C_ListenCpltCallback(hi2c); } @@ -4022,20 +4098,20 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the Slave Rx Complete callback */ HAL_I2C_SlaveRxCpltCallback(hi2c); } else { hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the Slave Tx Complete callback */ HAL_I2C_SlaveTxCpltCallback(hi2c); } @@ -4043,8 +4119,8 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /** * @brief I2C Listen complete process. - * @param hi2c: I2C handle. - * @param ITFlags: Interrupt flags to handle. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) @@ -4055,40 +4131,40 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; - + /* Store Last receive data if any */ if(((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if((hi2c->XferSize > 0)) + + if((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - + /* Disable all Interrupts*/ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - + /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ HAL_I2C_ListenCpltCallback(hi2c); } /** * @brief I2C interrupts error process. - * @param hi2c: I2C handle. - * @param ErrorCode: Error code to handle. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. * @retval None */ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) @@ -4096,11 +4172,11 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferCount = 0; - + hi2c->XferCount = 0U; + /* Set new error code */ hi2c->ErrorCode |= ErrorCode; - + /* Disable Interrupts */ if((hi2c->State == HAL_I2C_STATE_LISTEN) || (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || @@ -4108,7 +4184,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); - + /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->PreviousState = I2C_STATE_NONE; @@ -4119,24 +4195,29 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - /* Set HAL_I2C_STATE_READY */ - hi2c->State = HAL_I2C_STATE_READY; + /* If state is an abort treatment on goind, don't change state */ + /* This change will be do later */ + if(hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + } hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; } - + /* Abort DMA TX transfer if any */ if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Set the I2C DMA Abort callback : + + /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Abort DMA TX */ if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) { @@ -4148,14 +4229,14 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Set the I2C DMA Abort callback : + + /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Abort DMA RX */ if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) { @@ -4163,13 +4244,13 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } - else if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT) + else if(hi2c->State == HAL_I2C_STATE_ABORT) { - hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT; + hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_AbortCpltCallback(hi2c); } @@ -4177,7 +4258,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_ErrorCallback(hi2c); } @@ -4185,7 +4266,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /** * @brief I2C Tx data register flush process. - * @param hi2c: I2C handle. + * @param hi2c I2C handle. * @retval None */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) @@ -4194,9 +4275,9 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) /* Write a dummy data in TXDR to clear it */ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) { - hi2c->Instance->TXDR = 0x00; + hi2c->Instance->TXDR = 0x00U; } - + /* Flush TX register if not empty */ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) { @@ -4206,18 +4287,18 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) /** * @brief DMA I2C master transmit process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - + /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0) + if(hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4227,7 +4308,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { /* Update Buffer pointer */ hi2c->pBuffPtr += hi2c->XferSize; - + /* Set the XferSize to transfer */ if(hi2c->XferCount > MAX_NBYTE_SIZE) { @@ -4237,10 +4318,10 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { hi2c->XferSize = hi2c->XferCount; } - + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - + /* Enable TC interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } @@ -4248,11 +4329,14 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C slave transmit process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* No specific action, Master fully manage the generation of STOP condition */ /* Mean that this generation can arrive at any time, at the end or during DMA process */ /* So STOP condition should be manage through Interrupt treatment */ @@ -4260,18 +4344,18 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C master receive process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - + /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0) + if(hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4281,7 +4365,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { /* Update Buffer pointer */ hi2c->pBuffPtr += hi2c->XferSize; - + /* Set the XferSize to transfer */ if(hi2c->XferCount > MAX_NBYTE_SIZE) { @@ -4291,10 +4375,10 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { hi2c->XferSize = hi2c->XferCount; } - + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - + /* Enable TC interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } @@ -4302,11 +4386,14 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C slave receive process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* No specific action, Master fully manage the generation of STOP condition */ /* Mean that this generation can arrive at any time, at the end or during DMA process */ /* So STOP condition should be manage through Interrupt treatment */ @@ -4314,16 +4401,16 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); } @@ -4337,18 +4424,18 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + /* Reset AbortCpltCallback */ hi2c->hdmatx->XferAbortCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; - + /* Check if come from abort from user */ - if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT) + if(hi2c->State == HAL_I2C_STATE_ABORT) { - hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT; + hi2c->State = HAL_I2C_STATE_READY; /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_AbortCpltCallback(hi2c); @@ -4362,26 +4449,26 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) /** * @brief This function handles I2C Communication Timeout. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag: Specifies the I2C flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration - * @param Tickstart: Tick start value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { - while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) + while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) { hi2c->State= HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; @@ -4393,10 +4480,10 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin /** * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout: Timeout duration - * @param Tickstart: Tick start value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) @@ -4408,19 +4495,19 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { return HAL_ERROR; } - + /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_TIMEOUT; } } @@ -4430,10 +4517,10 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /** * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout: Timeout duration - * @param Tickstart: Tick start value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) @@ -4445,17 +4532,17 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { return HAL_ERROR; } - + /* Check for the Timeout */ - if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_TIMEOUT; } } @@ -4464,10 +4551,10 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /** * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout: Timeout duration - * @param Tickstart: Tick start value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) @@ -4479,35 +4566,35 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { return HAL_ERROR; } - + /* Check if a STOPF is detected */ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) { /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State= HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_ERROR; } - + /* Check for the Timeout */ - if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_TIMEOUT; } } @@ -4516,10 +4603,10 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /** * @brief This function handles Acknowledge failed detection during an I2C Communication. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout: Timeout duration - * @param Tickstart: Tick start value + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) @@ -4533,37 +4620,37 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->State= HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } } - + /* Clear NACKF Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - + hi2c->ErrorCode = HAL_I2C_ERROR_AF; hi2c->State= HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_ERROR; } return HAL_OK; @@ -4571,50 +4658,57 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /** * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param hi2c: I2C handle. - * @param DevAddress: Specifies the slave address to be programmed. - * @param Size: Specifies the number of bytes to be programmed. + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. * This parameter must be a value between 0 and 255. - * @param Mode: New state of the I2C START condition generation. - * This parameter can be a value of @ref I2C_RELOAD_END_MODE. - * @param Request: New state of the I2C START condition generation. - * This parameter can be a value of I2C_START_STOP_MODE. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0; - + uint32_t tmpreg = 0U; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); - + /* Get the CR2 register value */ tmpreg = hi2c->Instance->CR2; - + /* clear tmpreg specific bits */ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - + /* update tmpreg */ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ (uint32_t)Mode | (uint32_t)Request); - + /* update CR2 register */ hi2c->Instance->CR2 = tmpreg; } /** * @brief Manage the enabling of Interrupts. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval HAL status */ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { - uint32_t tmpisr = 0; - + uint32_t tmpisr = 0U; + if((hi2c->XferISR == I2C_Master_ISR_DMA) || \ (hi2c->XferISR == I2C_Slave_ISR_DMA)) { @@ -4623,13 +4717,13 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - + if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ @@ -4649,19 +4743,19 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr /* Enable ERR, STOP, NACK, and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - + if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } - + if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ @@ -4673,57 +4767,57 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ __HAL_I2C_ENABLE_IT(hi2c, tmpisr); - + return HAL_OK; } /** * @brief Manage the disabling of Interrupts. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval HAL status */ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { - uint32_t tmpisr = 0; - + uint32_t tmpisr = 0U; + if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - + if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - + if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - + if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - + if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - + if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ @@ -4735,12 +4829,12 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; } - + /* Disable interrupts only at the end */ /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_I2C_DISABLE_IT(hi2c, tmpisr); - + return HAL_OK; } diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.h index 52bc36ac79a..11590555fcf 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -98,47 +98,46 @@ typedef struct /** @defgroup HAL_state_structure_definition HAL state structure definition * @brief HAL State structure definition - * @note HAL I2C State value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : Abort (Abort user request on going) - * 10 : Timeout - * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) - * b4 (not used) - * x : Should be set to 0 - * b3 - * 0 : Ready or Busy (No Listen mode ongoing) - * 1 : Listen (IP in Address Listen Mode) - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 IP initilisation status\n + * 0 : Reset (IP not initialized)\n + * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (IP in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (IP busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n * 1 : Busy (Tx operation ongoing) * @{ */ - typedef enum { HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission - process is ongoing */ + process is ongoing */ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception - process is ongoing */ - HAL_I2C_STATE_ABORT = 0x60, /*!< Abort user request ongoing */ + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ }HAL_I2C_StateTypeDef; @@ -148,19 +147,19 @@ typedef enum /** @defgroup HAL_mode_structure_definition HAL mode structure definition * @brief HAL Mode structure definition - * @note HAL I2C Mode value coding follow below described bitmap : - * b7 (not used) - * x : Should be set to 0 - * b6 - * 0 : None - * 1 : Memory (HAL I2C communication is in Memory Mode) - * b5 - * 0 : None - * 1 : Slave (HAL I2C communication is in Slave Mode) - * b4 - * 0 : None - * 1 : Master (HAL I2C communication is in Master Mode) - * b3-b2-b1-b0 (not used) + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n * xxxx : Should be set to 0000 * @{ */ @@ -178,24 +177,23 @@ typedef enum */ /** @defgroup I2C_Error_Code_definition I2C Error Code definition - * @brief I2C Error Code definition + * @brief I2C Error Code definition * @{ */ -#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040U) /*!< Size Management error */ -#define HAL_I2C_ERROR_ABORT ((uint32_t)0x00000080U) /*!< Abort user request */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ /** * @} */ /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition - * @brief I2C handle Structure definition + * @brief I2C handle Structure definition * @{ */ typedef struct __I2C_HandleTypeDef @@ -237,7 +235,7 @@ typedef struct __I2C_HandleTypeDef /** * @} - */ + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup I2C_Exported_Constants I2C Exported Constants @@ -259,8 +257,8 @@ typedef struct __I2C_HandleTypeDef /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode * @{ */ -#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U) -#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U) +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) /** * @} */ @@ -268,7 +266,7 @@ typedef struct __I2C_HandleTypeDef /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode * @{ */ -#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U) +#define I2C_DUALADDRESS_DISABLE (0x00000000U) #define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN /** * @} @@ -292,7 +290,7 @@ typedef struct __I2C_HandleTypeDef /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode * @{ */ -#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U) +#define I2C_GENERALCALL_DISABLE (0x00000000U) #define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN /** * @} @@ -301,7 +299,7 @@ typedef struct __I2C_HandleTypeDef /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode * @{ */ -#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U) +#define I2C_NOSTRETCH_DISABLE (0x00000000U) #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} @@ -310,17 +308,17 @@ typedef struct __I2C_HandleTypeDef /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size * @{ */ -#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U) -#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U) +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) /** * @} */ -/** @defgroup I2C_XferDirection I2C Transfer Direction +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View * @{ */ -#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000000U) -#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000001U) +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) /** * @} */ @@ -330,7 +328,7 @@ typedef struct __I2C_HandleTypeDef */ #define I2C_RELOAD_MODE I2C_CR2_RELOAD #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE ((uint32_t)0x00000000U) +#define I2C_SOFTEND_MODE (0x00000000U) /** * @} */ @@ -338,7 +336,7 @@ typedef struct __I2C_HandleTypeDef /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode * @{ */ -#define I2C_NO_STARTSTOP ((uint32_t)0x00000000U) +#define I2C_NO_STARTSTOP (0x00000000U) #define I2C_GENERATE_STOP I2C_CR2_STOP #define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) #define I2C_GENERATE_START_WRITE I2C_CR2_START @@ -365,7 +363,7 @@ typedef struct __I2C_HandleTypeDef /** @defgroup I2C_Flag_definition I2C Flag definition * @{ - */ + */ #define I2C_FLAG_TXE I2C_ISR_TXE #define I2C_FLAG_TXIS I2C_ISR_TXIS #define I2C_FLAG_RXNE I2C_ISR_RXNE @@ -391,7 +389,7 @@ typedef struct __I2C_HandleTypeDef */ /* Exported macros -----------------------------------------------------------*/ - + /** @defgroup I2C_Exported_Macros I2C Exported Macros * @{ */ @@ -429,7 +427,7 @@ typedef struct __I2C_HandleTypeDef * @arg @ref I2C_IT_ADDRI Address match interrupt enable * @arg @ref I2C_IT_RXI RX interrupt enable * @arg @ref I2C_IT_TXI TX interrupt enable - * + * * @retval None */ #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) @@ -485,16 +483,16 @@ typedef struct __I2C_HandleTypeDef * @arg @ref I2C_FLAG_STOPF STOP detection flag * @arg @ref I2C_FLAG_BERR Bus error * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_OVR Overrun/Underrun * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref I2C_FLAG_ALERT SMBus alert * * @retval None */ #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ : ((__HANDLE__)->Instance->ICR = (__FLAG__))) - + /** @brief Enable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None @@ -594,7 +592,7 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions * @{ @@ -667,17 +665,17 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) -#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16) -#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) +#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) +#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) #define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) #define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.c index 682bf4b425b..9304af4491f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: @@ -14,13 +14,12 @@ ##### I2C peripheral Extended features ##### ============================================================================== - [..] Comparing to other previous devices, the I2C interface for STM32F7XX + [..] Comparing to other previous devices, the I2C interface for STM32F7xx devices contains the following additional features (+) Possibility to disable or enable Analog Noise Filter (+) Use of a configured Digital Noise Filter - (+) Disable or enable Fast Mode Plus (available only for STM32F76xxx/STM32F77xxx - devices) + (+) Disable or enable Fast Mode Plus ##### How to use this driver ##### ============================================================================== @@ -29,7 +28,7 @@ (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() (#) Configure the enable or disable of fast mode plus driving capability using the functions : (++) HAL_I2CEx_EnableFastModePlus() - (++) HAL_I2CEx_DisbleFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() @endverbatim ****************************************************************************** * @attention @@ -68,7 +67,7 @@ * @{ */ -/** @defgroup I2CEx I2C Extended HAL module driver +/** @defgroup I2CEx I2CEx * @brief I2C Extended HAL module driver * @{ */ @@ -94,7 +93,7 @@ ##### Extended features functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Configure Noise Filters + (+) Configure Noise Filters (+) Configure Fast Mode Plus @endverbatim @@ -103,9 +102,9 @@ /** * @brief Configure I2C Analog noise filter. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter: New state of the Analog filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) @@ -113,30 +112,30 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - + if(hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY; - + /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); - + /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); - + /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; - + __HAL_I2C_ENABLE(hi2c); - + hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -147,48 +146,48 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t /** * @brief Configure I2C Digital noise filter. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { - uint32_t tmpreg = 0; - + uint32_t tmpreg = 0U; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - + if(hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY; - + /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); - + /* Get the old register value */ tmpreg = hi2c->Instance->CR1; - + /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); - + /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << 8; - + tmpreg |= DigitalFilter << 8U; + /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; - + __HAL_I2C_ENABLE(hi2c); - + hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -197,44 +196,65 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ } } -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(SYSCFG_PMC_I2C1_FMP) /** * @brief Enable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus: Selects the pin. + * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. * @retval None */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) { /* Check the parameter */ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - + /* Enable SYSCFG clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - + /* Enable fast mode plus driving capability for selected pin */ SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); } /** * @brief Disable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus: Selects the pin. + * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. * @retval None */ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) { /* Check the parameter */ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - + /* Enable SYSCFG clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - + /* Disable fast mode plus driving capability for selected pin */ CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); } -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* SYSCFG_PMC_I2C1_FMP */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.h index 1eb4486fd61..c34cfb37443 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.h @@ -2,9 +2,9 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 - * @brief Header file of I2C HAL Extension module. + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of I2C HAL Extended module. ****************************************************************************** * @attention * @@ -57,15 +57,15 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants * @{ */ -/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter * @{ */ -#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) -#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} */ @@ -73,40 +73,71 @@ /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus * @{ */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - -#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP -#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP -#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP -#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP - -#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP -#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP -#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP -#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP - -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#if defined(SYSCFG_PMC_I2C_PB6_FMP) +#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#else +#define I2C_FASTMODEPLUS_PB6 (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported */ +#define I2C_FASTMODEPLUS_PB7 (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C_PB8_FMP) +#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#else +#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */ +#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C1_FMP) +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#else +#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C2_FMP) +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#else +#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C3_FMP) +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#else +#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C4_FMP) +#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#else +#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */ +#endif /** * @} */ - + /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/* Peripheral Control methods ************************************************/ +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(SYSCFG_PMC_I2C1_FMP) void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* SYSCFG_PMC_I2C1_FMP */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Constants I2C Private Constants +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants * @{ */ @@ -115,7 +146,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macro I2C Private Macros +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros * @{ */ #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ @@ -130,7 +161,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) #elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ @@ -138,7 +169,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3)) #elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ @@ -156,16 +187,21 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */ /** * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ */ +/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */ /** * @} */ -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ +/** + * @} */ -/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */ + /** * @} */ @@ -184,5 +220,4 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif /* __STM32F7xx_HAL_I2C_EX_H */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.c index b2c4041e752..c10bae51d61 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2s.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.h index c49460b2fde..4b75336c8b4 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2s.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.c index a3ba2be05ae..14e14b57b19 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_irda.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA (Infrared Data Association) Peripheral @@ -99,6 +99,7 @@ (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt + [..] (@) You can refer to the IRDA HAL driver header file for more useful macros @endverbatim @@ -193,7 +194,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); * @{ */ -/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -405,28 +406,28 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) (++) HAL_IRDA_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_IRDA_Abort() - (+) HAL_IRDA_AbortTransmit() - (+) HAL_IRDA_AbortReceive() - (+) HAL_IRDA_Abort_IT() - (+) HAL_IRDA_AbortTransmit_IT() - (+) HAL_IRDA_AbortReceive_IT() + (++) HAL_IRDA_Abort() + (++) HAL_IRDA_AbortTransmit() + (++) HAL_IRDA_AbortReceive() + (++) HAL_IRDA_Abort_IT() + (++) HAL_IRDA_AbortTransmit_IT() + (++) HAL_IRDA_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_IRDA_AbortCpltCallback() - (+) HAL_IRDA_AbortTransmitCpltCallback() - (+) HAL_IRDA_AbortReceiveCpltCallback() + (++) HAL_IRDA_AbortCpltCallback() + (++) HAL_IRDA_AbortTransmitCpltCallback() + (++) HAL_IRDA_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -1758,16 +1759,6 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) return HAL_TIMEOUT; } } - /* Check if the Receiver is enabled */ - if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } /* Initialize the IRDA state*/ hirda->gState = HAL_IRDA_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.h index b5e23eb7008..a094e5ae5a5 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_irda.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention @@ -599,7 +599,7 @@ typedef struct #include "stm32f7xx_hal_irda_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup IRDA_Exported_Functions IrDA Exported Functions +/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda_ex.h index 04e80d0ab37..82912d8fff0 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of IRDA HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c index 0616729f5f8..262171d7f27 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_iwdg.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.h index 3cb3c5a3de8..e67825e3d13 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_iwdg.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.c index a63678f2f83..828305c1188 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_jpeg.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief JPEG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the JPEG encoder/decoder peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.h index 732600f15f5..42aafe2db43 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_jpeg.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of JPEG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.c index f6dce43e5e4..1355bff1fed 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_lptim.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief LPTIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Low Power Timer (LPTIM) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.h index dc52854521a..b9ebfa1619c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_lptim.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of LPTIM HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.c index 3df29600c1a..03cc1c61b7e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief LTDC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LTDC peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.h index 90ead1ad5af..f10427093d3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of LTDC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.c index 9fa6569b01b..9b7d3f2b3f8 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief LTDC Extension HAL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.h index 932a035ebcb..49e0f1a88e2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of LTDC HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c index 3ffefba7979..b16c323e2f1 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_mdios.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief MDIOS HAL module driver. * This file provides firmware functions to manage the following * functionalities of the MDIOS Peripheral. diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.h index a3e394b7609..d27eb2fc8df 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_mdios.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of MDIOS HAL module. ****************************************************************************** * @attention @@ -43,11 +43,11 @@ extern "C" { #endif -#if defined (MDIOS) - /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" +#if defined (MDIOS) + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mmc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mmc.c new file mode 100644 index 00000000000..437a04c7a76 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mmc.c @@ -0,0 +1,2493 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_mmc.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief MMC card HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (MMC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + MMC card Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_MMC_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with MMC and eMMC cards devices. + It is used as follows: + + (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API: + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + (##) SDMMC pins configuration for MMC card + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA() + and HAL_MMC_WriteBlocks_DMA() APIs). + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); + (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. + (##) NVIC configuration if you need to use interrupt process when using DMA transfer. + (+++) Configure the SDMMC and DMA interrupt priorities using functions + HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority + (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() + and __HAL_MMC_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() + and __HAL_MMC_CLEAR_IT() + (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT() + and HAL_MMC_WriteBlocks_IT() APIs). + (+++) Configure the SDMMC interrupt priorities using function + HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() + and __HAL_MMC_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() + and __HAL_MMC_CLEAR_IT() + (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization + + + *** MMC Card Initialization and configuration *** + ================================================ + [..] + To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes + SDMMC IP (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Initialize the SDMMC peripheral interface with defaullt configuration. + The initialization process is done at 400KHz. You can change or adapt + this frequency by adjusting the "ClockDiv" field. + The MMC Card frequency (SDMMC_CK) is computed as follows: + + SDMMC_CK = SDMMCCLK / (ClockDiv + 2) + + In initialization mode and according to the MMC Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the MMC card. The API used is HAL_MMC_InitCard(). + This phase allows the card initialization and identification + and check the MMC Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with MMC standard. + + This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. + + (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer + frequency is set to 24MHz. You can change or adapt this frequency by adjusting + the "ClockDiv" field. + In transfer mode and according to the MMC Card standard, make sure that the + SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. + To be able to use a frequency higher than 24MHz, you should use the SDMMC + peripheral in bypass mode. Refer to the corresponding reference manual + for more details. + + (#) Select the corresponding MMC Card according to the address read with the step 2. + + (#) Configure the MMC Card in wide bus mode: 4-bits data. + + *** MMC Card Read operation *** + ============================== + [..] + (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Rx interrupt event. + + (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Rx interrupt event. + + *** MMC Card Write operation *** + =============================== + [..] + (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Tx interrupt event. + + (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Tx interrupt event. + + *** MMC card information *** + =========================== + [..] + (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo(). + It returns useful information about the MMC card such as block size, card type, + block number ... + + *** MMC card CSD register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** MMC card CID register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register. + Some of the CID parameters are useful for card initialization and identification. + + *** MMC HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in MMC HAL driver. + + (+) __HAL_MMC_ENABLE : Enable the MMC device + (+) __HAL_MMC_DISABLE : Disable the MMC device + (+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer + (+) __HAL_MMC_DMA_DISABLE: Disable the SDMMC DMA transfer + (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt + (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt + (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not + (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags + + [..] + (@) You can refer to the MMC HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup MMC MMC + * @brief MMC HAL module driver + * @{ + */ + +#ifdef HAL_MMC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup MMC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus); +static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc); +static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc); +static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc); +static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAError(DMA_HandleTypeDef *hdma); +static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma); +static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup MMC_Exported_Functions + * @{ + */ + +/** @addtogroup MMC_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the MMC + card device to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the MMC according to the specified parameters in the + MMC_HandleTypeDef and create the associated handle. + * @param hmmc: Pointer to the MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if(hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance)); + assert_param(IS_SDMMC_CLOCK_EDGE(hmmc->Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_BYPASS(hmmc->Init.ClockBypass)); + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(hmmc->Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv)); + + if(hmmc->State == HAL_MMC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hmmc->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_MMC_MspInit(hmmc); + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize the Card parameters */ + HAL_MMC_InitCard(hmmc); + + /* Initialize the error code */ + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; + + /* Initialize the MMC state */ + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the MMC Card. + * @param hmmc: Pointer to MMC handle + * @note This function initializes the MMC card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + MMC_InitTypeDef Init; + + /* Default SDMMC peripheral configuration for MMC card initialization */ + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDMMC_BUS_WIDE_1B; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDMMC_INIT_CLK_DIV; + + /* Initialize SDMMC peripheral interface with default configuration */ + SDMMC_Init(hmmc->Instance, Init); + + /* Disable SDMMC Clock */ + __HAL_MMC_DISABLE(hmmc); + + /* Set Power State to ON */ + SDMMC_PowerState_ON(hmmc->Instance); + + /* Enable MMC Clock */ + __HAL_MMC_ENABLE(hmmc); + + /* Identify card operating voltage */ + errorstate = MMC_PowerON(hmmc); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Card initialization */ + errorstate = MMC_InitCard(hmmc); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief De-Initializes the MMC card. + * @param hmmc: Pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if(hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance)); + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Set MMC power state to off */ + MMC_PowerOFF(hmmc); + + /* De-Initialize the MSP layer */ + HAL_MMC_MspDeInit(hmmc); + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_RESET; + + return HAL_OK; +} + + +/** + * @brief Initializes the MMC MSP. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize MMC MSP. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group2 + * @brief Data transfer functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data + transfer from/to MMC card. + +@endverbatim + * @{ + */ + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of MMC blocks to read + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); + uint32_t count = 0, *tempbuff = (uint32_t *)pData; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hmmc->Instance, &config); + + /* Read block(s) in polling mode */ + if(NumberOfBlocks > 1) + { + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK; + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + *(tempbuff + count) = SDMMC_ReadFIFO(hmmc->Instance); + } + tempbuff += 8U; + } + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock read */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Empty FIFO if there is still any data */ + while ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXDAVL))) + { + *tempbuff = SDMMC_ReadFIFO(hmmc->Instance); + tempbuff++; + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to write block(s) to a specified address in a card. The Data + * transfer is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of MMC blocks to write + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); + uint32_t count = 0; + uint32_t *tempbuff = (uint32_t *)pData; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK; + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hmmc->Instance, &config); + + /* Write block(s) in polling mode */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE)) + { + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + SDMMC_WriteFIFO(hmmc->Instance, (tempbuff + count)); + } + tempbuff += 8U; + } + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock write */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Rx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pRxBuffPtr = (uint32_t *)pData; + hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks; + + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hmmc->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Read Blocks in IT mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Tx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pTxBuffPtr = (uint32_t *)pData; + hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks; + + /* Enable transfer interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hmmc->Instance, &config); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Rx + * interrupt event. + * @param hmmc: Pointer MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + + /* Set the DMA transfer complete callback */ + hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt; + + /* Set the DMA error callback */ + hmmc->hdmarx->XferErrorCallback = MMC_DMAError; + + /* Set the DMA Abort callback */ + hmmc->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); + + /* Enable MMC DMA transfer */ + __HAL_MMC_DMA_ENABLE(hmmc); + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hmmc->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Tx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + /* Enable MMC Error interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); + + /* Set the DMA transfer complete callback */ + hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt; + + /* Set the DMA error callback */ + hmmc->hdmatx->XferErrorCallback = MMC_DMAError; + + /* Set the DMA Abort callback */ + hmmc->hdmatx->XferAbortCallback = NULL; + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Enable SDMMC DMA transfer */ + __HAL_MMC_DMA_ENABLE(hmmc); + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hmmc->Instance, &config); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Erases the specified memory area of the given MMC card. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if(BlockEndAdd < BlockStartAdd) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(BlockEndAdd > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Check if the card command class supports erase command */ + if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockStartAdd *= 512U; + BlockEndAdd *= 512U; + } + + /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ + errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, BlockStartAdd); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */ + errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, BlockEndAdd); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD38 ERASE */ + errorstate = SDMMC_CmdErase(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles MMC card interrupt request. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + /* Check for SDMMC interrupt flags */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DATAEND) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND); + + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + if((hmmc->Context & MMC_CONTEXT_IT) != RESET) + { + if(((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + HAL_MMC_ErrorCallback(hmmc); + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) + { + HAL_MMC_RxCpltCallback(hmmc); + } + else + { + HAL_MMC_TxCpltCallback(hmmc); + } + } + else if((hmmc->Context & MMC_CONTEXT_DMA) != RESET) + { + if((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + HAL_MMC_ErrorCallback(hmmc); + } + } + if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == RESET)) + { + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the MMC DCTRL register */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + hmmc->State = HAL_MMC_STATE_READY; + + HAL_MMC_TxCpltCallback(hmmc); + } + } + } + + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXFIFOHE) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE); + + MMC_Write_IT(hmmc); + } + + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXFIFOHF) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF); + + MMC_Read_IT(hmmc); + } + + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET) + { + /* Set Error code */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + } + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + + /* Disable all interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + if((hmmc->Context & MMC_CONTEXT_DMA) != RESET) + { + /* Abort the MMC DMA Streams */ + if(hmmc->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) + { + MMC_DMATxAbort(hmmc->hdmatx); + } + } + else if(hmmc->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) + { + MMC_DMARxAbort(hmmc->hdmarx); + } + } + else + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + HAL_MMC_AbortCallback(hmmc); + } + } + else if((hmmc->Context & MMC_CONTEXT_IT) != RESET) + { + /* Set the MMC state to ready to be able to start again the process */ + hmmc->State = HAL_MMC_STATE_READY; + HAL_MMC_ErrorCallback(hmmc); + } + } +} + +/** + * @brief return the MMC state + * @param hmmc: Pointer to mmc handle + * @retval HAL state + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) +{ + return hmmc->State; +} + +/** +* @brief Return the MMC error code +* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. +* @retval MMC Error Code +*/ +uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) +{ + return hmmc->ErrorCode; +} + +/** + * @brief Tx Transfer completed callbacks + * @param hmmc: Pointer to MMC handle + * @retval None + */ + __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief MMC error callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief MMC Abort callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_ErrorCallback can be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group3 + * @brief management functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the MMC card + operations and get the related information + +@endverbatim + * @{ + */ + +/** + * @brief Returns information the information of the card which are stored on + * the CID register. + * @param hmmc: Pointer to MMC handle + * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that + * contains all CID register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +{ + uint32_t tmp = 0; + + /* Byte 0 */ + tmp = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24); + pCID->ManufacturerID = tmp; + + /* Byte 1 */ + tmp = (uint8_t)((hmmc->CID[0] & 0x00FF0000) >> 16); + pCID->OEM_AppliID = tmp << 8; + + /* Byte 2 */ + tmp = (uint8_t)((hmmc->CID[0] & 0x000000FF00) >> 8); + pCID->OEM_AppliID |= tmp; + + /* Byte 3 */ + tmp = (uint8_t)(hmmc->CID[0] & 0x000000FF); + pCID->ProdName1 = tmp << 24; + + /* Byte 4 */ + tmp = (uint8_t)((hmmc->CID[1] & 0xFF000000U) >> 24); + pCID->ProdName1 |= tmp << 16; + + /* Byte 5 */ + tmp = (uint8_t)((hmmc->CID[1] & 0x00FF0000) >> 16); + pCID->ProdName1 |= tmp << 8; + + /* Byte 6 */ + tmp = (uint8_t)((hmmc->CID[1] & 0x0000FF00) >> 8); + pCID->ProdName1 |= tmp; + + /* Byte 7 */ + tmp = (uint8_t)(hmmc->CID[1] & 0x000000FF); + pCID->ProdName2 = tmp; + + /* Byte 8 */ + tmp = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24); + pCID->ProdRev = tmp; + + /* Byte 9 */ + tmp = (uint8_t)((hmmc->CID[2] & 0x00FF0000) >> 16); + pCID->ProdSN = tmp << 24; + + /* Byte 10 */ + tmp = (uint8_t)((hmmc->CID[2] & 0x0000FF00) >> 8); + pCID->ProdSN |= tmp << 16; + + /* Byte 11 */ + tmp = (uint8_t)(hmmc->CID[2] & 0x000000FF); + pCID->ProdSN |= tmp << 8; + + /* Byte 12 */ + tmp = (uint8_t)((hmmc->CID[3] & 0xFF000000U) >> 24); + pCID->ProdSN |= tmp; + + /* Byte 13 */ + tmp = (uint8_t)((hmmc->CID[3] & 0x00FF0000) >> 16); + pCID->Reserved1 |= (tmp & 0xF0) >> 4; + pCID->ManufactDate = (tmp & 0x0F) << 8; + + /* Byte 14 */ + tmp = (uint8_t)((hmmc->CID[3] & 0x0000FF00) >> 8); + pCID->ManufactDate |= tmp; + + /* Byte 15 */ + tmp = (uint8_t)(hmmc->CID[3] & 0x000000FF); + pCID->CID_CRC = (tmp & 0xFE) >> 1; + pCID->Reserved2 = 1; + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the CSD register. + * @param hmmc: Pointer to MMC handle + * @param pCSD: Pointer to a HAL_MMC_CardInfoTypeDef structure that + * contains all CSD register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD) +{ + uint32_t tmp = 0; + + /* Byte 0 */ + tmp = (hmmc->CSD[0] & 0xFF000000U) >> 24; + pCSD->CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); + pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); + pCSD->Reserved1 = tmp & 0x03; + + /* Byte 1 */ + tmp = (hmmc->CSD[0] & 0x00FF0000) >> 16; + pCSD->TAAC = (uint8_t)tmp; + + /* Byte 2 */ + tmp = (hmmc->CSD[0] & 0x0000FF00) >> 8; + pCSD->NSAC = (uint8_t)tmp; + + /* Byte 3 */ + tmp = hmmc->CSD[0] & 0x000000FF; + pCSD->MaxBusClkFrec = (uint8_t)tmp; + + /* Byte 4 */ + tmp = (hmmc->CSD[1] & 0xFF000000U) >> 24; + pCSD->CardComdClasses = (uint16_t)(tmp << 4); + + /* Byte 5 */ + tmp = (hmmc->CSD[1] & 0x00FF0000U) >> 16; + pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); + pCSD->RdBlockLen = (uint8_t)(tmp & 0x0F); + + /* Byte 6 */ + tmp = (hmmc->CSD[1] & 0x0000FF00U) >> 8; + pCSD->PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); + pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); + pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); + pCSD->DSRImpl = (uint8_t)((tmp & 0x10) >> 4); + pCSD->Reserved2 = 0; /*!< Reserved */ + + pCSD->DeviceSize = (tmp & 0x03) << 10; + + /* Byte 7 */ + tmp = (uint8_t)(hmmc->CSD[1] & 0x000000FFU); + pCSD->DeviceSize |= (tmp) << 2; + + /* Byte 8 */ + tmp = (uint8_t)((hmmc->CSD[2] & 0xFF000000U) >> 24); + pCSD->DeviceSize |= (tmp & 0xC0) >> 6; + + pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; + pCSD->MaxRdCurrentVDDMax = (tmp & 0x07); + + /* Byte 9 */ + tmp = (uint8_t)((hmmc->CSD[2] & 0x00FF0000U) >> 16); + pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; + pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; + pCSD->DeviceSizeMul = (tmp & 0x03) << 1; + /* Byte 10 */ + tmp = (uint8_t)((hmmc->CSD[2] & 0x0000FF00U) >> 8); + pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7; + + hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1) ; + hmmc->MmcCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2)); + hmmc->MmcCard.BlockSize = 1 << (pCSD->RdBlockLen); + + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512); + hmmc->MmcCard.LogBlockSize = 512; + + pCSD->EraseGrSize = (tmp & 0x40) >> 6; + pCSD->EraseGrMul = (tmp & 0x3F) << 1; + + /* Byte 11 */ + tmp = (uint8_t)(hmmc->CSD[2] & 0x000000FF); + pCSD->EraseGrMul |= (tmp & 0x80) >> 7; + pCSD->WrProtectGrSize = (tmp & 0x7F); + + /* Byte 12 */ + tmp = (uint8_t)((hmmc->CSD[3] & 0xFF000000U) >> 24); + pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7; + pCSD->ManDeflECC = (tmp & 0x60) >> 5; + pCSD->WrSpeedFact = (tmp & 0x1C) >> 2; + pCSD->MaxWrBlockLen = (tmp & 0x03) << 2; + + /* Byte 13 */ + tmp = (uint8_t)((hmmc->CSD[3] & 0x00FF0000) >> 16); + pCSD->MaxWrBlockLen |= (tmp & 0xC0) >> 6; + pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5; + pCSD->Reserved3 = 0; + pCSD->ContentProtectAppli = (tmp & 0x01); + + /* Byte 14 */ + tmp = (uint8_t)((hmmc->CSD[3] & 0x0000FF00) >> 8); + pCSD->FileFormatGrouop = (tmp & 0x80) >> 7; + pCSD->CopyFlag = (tmp & 0x40) >> 6; + pCSD->PermWrProtect = (tmp & 0x20) >> 5; + pCSD->TempWrProtect = (tmp & 0x10) >> 4; + pCSD->FileFormat = (tmp & 0x0C) >> 2; + pCSD->ECC = (tmp & 0x03); + + /* Byte 15 */ + tmp = (uint8_t)(hmmc->CSD[3] & 0x000000FF); + pCSD->CSD_CRC = (tmp & 0xFE) >> 1; + pCSD->Reserved4 = 1; + + return HAL_OK; +} + +/** + * @brief Gets the MMC card info. + * @param hmmc: Pointer to MMC handle + * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that + * will contain the MMC card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +{ + pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); + pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); + pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd); + pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr); + pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize); + pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr); + pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize); + + return HAL_OK; +} + +/** + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hmmc: Pointer to MMC handle + * @param WideMode: Specifies the MMC card wide bus mode + * This parameter can be one of the following values: + * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer + * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer + * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) +{ + __IO uint32_t count = 0; + SDMMC_InitTypeDef Init; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t response = 0, busy = 0; + + /* Check the parameters */ + assert_param(IS_SDMMC_BUS_WIDE(WideMode)); + + /* Chnage Satte */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Update Clock for Bus mode update */ + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = WideMode; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDMMC_INIT_CLK_DIV; + /* Initialize SDMMC*/ + SDMMC_Init(hmmc->Instance, Init); + + if(WideMode == SDMMC_BUS_WIDE_8B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else if(WideMode == SDMMC_BUS_WIDE_4B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else if(WideMode == SDMMC_BUS_WIDE_1B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else + { + /* WideMode is not a valid argument*/ + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + } + + /* Check for switch error and violation of the trial number of sending CMD 13 */ + while(busy == 0) + { + if(count++ == SDMMC_MAX_TRIAL) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + return HAL_ERROR; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + busy = (((response >> 7) == 1) ? 0 : 1); + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_DATATIMEOUT; + while((response & 0x00000100) == 0) + { + if(count-- == 0) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + return HAL_ERROR; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + } + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Configure the SDMMC peripheral */ + Init.ClockEdge = hmmc->Init.ClockEdge; + Init.ClockBypass = hmmc->Init.ClockBypass; + Init.ClockPowerSave = hmmc->Init.ClockPowerSave; + Init.BusWide = WideMode; + Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; + Init.ClockDiv = hmmc->Init.ClockDiv; + SDMMC_Init(hmmc->Instance, Init); + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief Gets the current mmc card data state. + * @param hmmc: pointer to MMC handle + * @retval Card state + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef cardstate = HAL_MMC_CARD_TRANSFER; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t resp1 = 0; + + errorstate = MMC_SendStatus(hmmc, &resp1); + if(errorstate != HAL_OK) + { + hmmc->ErrorCode |= errorstate; + } + + cardstate = (HAL_MMC_CardStateTypeDef)((resp1 >> 9) & 0x0F); + + return cardstate; +} + +/** + * @brief Abort the current transfer and disable the MMC. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + + if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) + { + /* Disable the MMC DMA request */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Abort the MMC DMA Tx Stream */ + if(hmmc->hdmatx != NULL) + { + HAL_DMA_Abort(hmmc->hdmatx); + } + /* Abort the MMC DMA Rx Stream */ + if(hmmc->hdmarx != NULL) + { + HAL_DMA_Abort(hmmc->hdmarx); + } + } + + hmmc->State = HAL_MMC_STATE_READY; + CardState = HAL_MMC_GetCardState(hmmc); + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + } + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Abort the current transfer and disable the MMC (IT mode). + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + + if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) + { + /* Disable the MMC DMA request */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Abort the MMC DMA Tx Stream */ + if(hmmc->hdmatx != NULL) + { + hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; + if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) + { + hmmc->hdmatx = NULL; + } + } + /* Abort the MMC DMA Rx Stream */ + if(hmmc->hdmarx != NULL) + { + hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; + if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) + { + hmmc->hdmarx = NULL; + } + } + } + + /* No transfer ongoing on both DMA channels*/ + if((hmmc->hdmatx == NULL) && (hmmc->hdmarx == NULL)) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + } + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + HAL_MMC_AbortCallback(hmmc); + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup MMC_Private_Functions + * @{ + */ + +/** + * @brief DMA MMC transmit process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + + /* Enable DATAEND Interrupt */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DATAEND)); +} + +/** + * @brief DMA MMC receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + /* Send stop command in multiblock write */ + if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + HAL_MMC_ErrorCallback(hmmc); + } + } + + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the MMC DCTRL register */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + HAL_MMC_RxCpltCallback(hmmc); +} + +/** + * @brief DMA MMC communication error callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMAError(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if((hmmc->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hmmc->hdmatx->ErrorCode == HAL_DMA_ERROR_TE)) + { + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + + /* Disable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + CardState = HAL_MMC_GetCardState(hmmc); + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + } + + hmmc->State= HAL_MMC_STATE_READY; + } + + HAL_MMC_ErrorCallback(hmmc); +} + +/** + * @brief DMA MMC Tx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if(hmmc->hdmatx != NULL) + { + hmmc->hdmatx = NULL; + } + + /* All DMA channels are aborted */ + if(hmmc->hdmarx == NULL) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + HAL_MMC_AbortCallback(hmmc); + } + else + { + HAL_MMC_ErrorCallback(hmmc); + } + } + } +} + +/** + * @brief DMA MMC Rx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if(hmmc->hdmarx != NULL) + { + hmmc->hdmarx = NULL; + } + + /* All DMA channels are aborted */ + if(hmmc->hdmatx == NULL) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + HAL_MMC_AbortCallback(hmmc); + } + else + { + HAL_MMC_ErrorCallback(hmmc); + } + } + } +} + + +/** + * @brief Initializes the mmc card. + * @param hmmc: Pointer to MMC handle + * @retval MMC Card error state + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardCSDTypeDef CSD; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint16_t mmc_rca = 1; + + /* Check the power State */ + if(SDMMC_GetPowerState(hmmc->Instance) == 0) + { + /* Power off */ + return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + } + + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card identification number data */ + hmmc->CID[0] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + hmmc->CID[1] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); + hmmc->CID[2] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); + hmmc->CID[3] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); + } + + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* MMC Card publishes its RCA. */ + errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get the MMC card RCA */ + hmmc->MmcCard.RelCardAdd = mmc_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card Specific Data */ + hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); + hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); + hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); + } + + /* Get the Card Class */ + hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20); + + /* Get CSD parameters */ + HAL_MMC_GetCardCSD(hmmc, &CSD); + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Configure SDMMC peripheral interface */ + SDMMC_Init(hmmc->Instance, hmmc->Init); + + /* All cards are initialized */ + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores MMC information that will be needed in future + * in the MMC handle. + * @param hmmc: Pointer to MMC handle + * @retval error state + */ +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) +{ + __IO uint32_t count = 0; + uint32_t response = 0, validvoltage = 0; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + while(validvoltage == 0) + { + if(count++ == SDMMC_MAX_VOLT_TRIAL) + { + return HAL_MMC_ERROR_INVALID_VOLTRANGE; + } + + /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */ + errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31) == 1) ? 1 : 0); + } + + /* When power routine is finished and command returns valid voltage */ + if ((response & MMC_HIGH_VOLTAGE_RANGE) == MMC_HIGH_VOLTAGE_RANGE) + { + /* When voltage range of the card is within 2.7V and 3.6V */ + hmmc->MmcCard.CardType = MMC_HIGH_VOLTAGE_CARD; + } + else + { + /* When voltage range of the card is within 1.65V and 1.95V or 2.7V and 3.6V */ + hmmc->MmcCard.CardType = MMC_DUAL_VOLTAGE_CARD; + } + + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Turns the SDMMC output signals off. + * @param hmmc: Pointer to MMC handle + * @retval HAL status + */ +static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc) +{ + /* Set Power State to OFF */ + SDMMC_PowerState_OFF(hmmc->Instance); + + return HAL_OK; +} + +/** + * @brief Returns the current card's status. + * @param hmmc: Pointer to MMC handle + * @param pCardStatus: pointer to the buffer that will contain the MMC card + * status (Card Status register) + * @retval error state + */ +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(pCardStatus == NULL) + { + return HAL_MMC_ERROR_PARAM; + } + + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16)); + if(errorstate != HAL_OK) + { + return errorstate; + } + + /* Get MMC card status */ + *pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Wrap up reading in non-blocking mode. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval HAL status + */ +static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count = 0; + uint32_t* tmp; + + tmp = (uint32_t*)hmmc->pRxBuffPtr; + + /* Read data from SDMMC Rx FIFO */ + for(count = 0; count < 8; count++) + { + *(tmp + count) = SDMMC_ReadFIFO(hmmc->Instance); + } + + hmmc->pRxBuffPtr += 8; + + return HAL_OK; +} + +/** + * @brief Wrap up writing in non-blocking mode. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval HAL status + */ +static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count = 0; + uint32_t* tmp; + + tmp = (uint32_t*)hmmc->pTxBuffPtr; + + /* Write data to SDMMC Tx FIFO */ + for(count = 0; count < 8; count++) + { + SDMMC_WriteFIFO(hmmc->Instance, (tmp + count)); + } + + hmmc->pTxBuffPtr += 8; + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_SD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mmc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mmc.h new file mode 100644 index 00000000000..2ff8586165e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mmc.h @@ -0,0 +1,695 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_mmc.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of MMC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_MMC_H +#define __STM32F7xx_HAL_MMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_sdmmc.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup MMC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_Types MMC Exported Types + * @{ + */ + +/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure + * @{ + */ +typedef enum +{ + HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */ + HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */ + HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */ + HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */ + HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */ + HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */ + HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */ + HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */ +}HAL_MMC_StateTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure + * @{ + */ +typedef enum +{ + HAL_MMC_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */ + HAL_MMC_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */ + HAL_MMC_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */ + HAL_MMC_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */ + HAL_MMC_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */ + HAL_MMC_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */ + HAL_MMC_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */ + HAL_MMC_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */ + HAL_MMC_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */ +}HAL_MMC_CardStateTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition + * @{ + */ +#define MMC_InitTypeDef SDMMC_InitTypeDef +#define MMC_TypeDef SDMMC_TypeDef + +/** + * @brief MMC Card Information Structure definition + */ +typedef struct +{ + uint32_t CardType; /*!< Specifies the card Type */ + + uint32_t Class; /*!< Specifies the class of the card class */ + + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ + + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ + + uint32_t BlockSize; /*!< Specifies one block size in bytes */ + + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ + + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + +}HAL_MMC_CardInfoTypeDef; + +/** + * @brief MMC handle Structure definition + */ +typedef struct +{ + MMC_TypeDef *Instance; /*!< MMC registers base address */ + + MMC_InitTypeDef Init; /*!< MMC required parameters */ + + HAL_LockTypeDef Lock; /*!< MMC locking object */ + + uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< MMC Tx Transfer size */ + + uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< MMC Rx Transfer size */ + + __IO uint32_t Context; /*!< MMC transfer context */ + + __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ + + __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + + DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */ + + DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */ + + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ + + uint32_t CSD[4]; /*!< MMC card specific data table */ + + uint32_t CID[4]; /*!< MMC card identification number table */ + +}MMC_HandleTypeDef; + +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register + * @{ + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access time 1 */ + __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserved */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGrouop; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< Always 1 */ + +}HAL_MMC_CardCSDTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register + * @{ + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2 */ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< Always 1 */ + +}HAL_MMC_CardCIDTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Constants Exported Constants + * @{ + */ + +#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */ +#define CAPACITY ((uint32_t)0x80000000U) /*!< 2 G bytes constant */ + +/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition + * @{ + */ +#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration + * @{ + */ +#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ +#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ +#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ +#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ +#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ +#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ +#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ + +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode + * @{ + */ +/** + * @brief + */ +#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */ +#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */ +#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */ +#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */ +#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards + * @{ + */ +#define MMC_HIGH_VOLTAGE_CARD ((uint32_t)0x00000000U) +#define MMC_DUAL_VOLTAGE_CARD ((uint32_t)0x00000001U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_macros MMC Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/** + * @brief Enable the MMC device. + * @retval None + */ +#define __HAL_MMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the MMC device. + * @retval None + */ +#define __HAL_MMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the MMC device interrupt. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the MMC device interrupt. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified MMC flag is set or not. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_CMDACT: Command transfer in progress + * @arg SDMMC_FLAG_TXACT: Data transmit in progress + * @arg SDMMC_FLAG_RXACT: Data receive in progress + * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full + * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @retval The new state of MMC FLAG (SET or RESET). + */ +#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the MMC's pending flags. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @retval None + */ +#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified MMC interrupt has occurred or not. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval The new state of SD IT (SET or RESET). + */ +#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Clear the MMC's interrupt pending bits. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Functions MMC Exported Functions + * @{ + */ + +/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +/* Non-Blocking mode: IT */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); + +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); + +/* Callback in non blocking modes (DMA) */ +void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions + * @{ + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup MMC_Private_Types MMC Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup MMC_Private_Defines MMC Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Variables MMC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Constants MMC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MMC_Private_Macros MMC Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F7xx_HAL_MMC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.c index 1586d84224b..290d7875a6d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nand.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. @@ -25,9 +25,12 @@ structure declared by the function caller. (+) Access NAND flash memory by read/write operations using the functions - HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea() + HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(), + HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(), + HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(), + HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b() to read/write page(s)/spare area(s). These functions use specific device - information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef + information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef structure. The read/write address information is contained by the Nand_Address_Typedef structure passed as parameter. @@ -363,7 +366,6 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); } - /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -400,8 +402,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) /* Send NAND reset command */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF; - - + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -412,6 +413,27 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) } +/** + * @brief Configure the device: Enter the physical parameters of the device + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +{ + hnand->Config.PageSize = pDeviceConfig->PageSize; + hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; + hnand->Config.BlockSize = pDeviceConfig->BlockSize; + hnand->Config.BlockNbr = pDeviceConfig->BlockNbr; + hnand->Config.PlaneSize = pDeviceConfig->PlaneSize; + hnand->Config.PlaneNbr = pDeviceConfig->BlockNbr; + hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable; + + return HAL_OK; +} + + /** * @brief Read Page(s) from NAND memory block (8-bits addressing) * @param hnand: pointer to a NAND_HandleTypeDef structure that contains @@ -424,6 +446,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) { __IO uint32_t index = 0; + uint32_t tickstart = 0U; uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; /* Process Locked */ @@ -445,48 +468,94 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT nandAddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) read loop */ - while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) - { + while((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead); + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } } - + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); - if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) + + if(hnand->Config.ExtraCommandEnable == ENABLE) { - /* Get Data into Buffer */ - for(; index < size; index++) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); } - else + + /* Get Data into Buffer */ + for(; index < size; index++) { - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress; - } + *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; } /* Increment read pages number */ @@ -496,7 +565,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT NumPageToRead--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); + nandAddress = (uint32_t)(nandAddress + 1); } /* Update the NAND controller state */ @@ -514,13 +583,14 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to destination read buffer + * @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned * @param NumPageToRead : number of pages to read from block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) { __IO uint32_t index = 0; + uint32_t tickstart = 0; uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; /* Process Locked */ @@ -542,33 +612,89 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address nandAddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) read loop */ - while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) + while((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead); + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); /* Send read page command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } } *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); + + if(hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); + } + /* Get Data into Buffer */ for(; index < size; index++) { @@ -582,7 +708,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address NumPageToRead--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); + nandAddress = (uint32_t)(nandAddress + 1); } /* Update the NAND controller state */ @@ -628,10 +754,10 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address nandAddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) write loop */ - while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) + while((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten); + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten); /* Send write page command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; @@ -639,40 +765,64 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); - } - - if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) - { - /* Write data to memory */ - for(; index < size; index++) + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) { - *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); __DSB(); } } - else + else /* (hnand->Config.PageSize) > 512 */ { - /* Write data to memory */ - for(; index < size; index++) + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) { - *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++; + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); __DSB(); } } + + /* Write data to memory */ + for(; index < size; index++) + { + *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; + __DSB(); + } *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); @@ -696,7 +846,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address NumPageToWrite--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); + nandAddress = (uint32_t)(nandAddress + 1); } /* Update the NAND controller state */ @@ -713,7 +863,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write + * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned * @param NumPageToWrite : number of pages to write to block * @retval HAL status */ @@ -742,10 +892,10 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres nandAddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) write loop */ - while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) + while((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten); + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten); /* Send write page command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; @@ -753,20 +903,56 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } } /* Write data to memory */ @@ -798,7 +984,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres NumPageToWrite--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); + nandAddress = (uint32_t)(nandAddress + 1); } /* Update the NAND controller state */ @@ -821,8 +1007,9 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres */ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) { - __IO uint32_t index = 0; - uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0; + __IO uint32_t index = 0; + uint32_t tickstart = 0U; + uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0; /* Process Locked */ __HAL_LOCK(hnand); @@ -840,36 +1027,99 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add hnand->State = HAL_NAND_STATE_BUSY; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = COLUMN_ADDRESS(hnand); /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) + while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead); - - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); + + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512) + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - } + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); + if(hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); + } + /* Get Data into Buffer */ for(; index < size; index++) { @@ -883,7 +1133,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add NumSpareAreaToRead--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize)); + nandAddress = (uint32_t)(nandAddress + 1); } /* Update the NAND controller state */ @@ -900,14 +1150,15 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write + * @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned. * @param NumSpareAreaToRead: Number of spare area to read * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) { __IO uint32_t index = 0; - uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0; + uint32_t tickstart = 0U; + uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0; /* Process Locked */ __HAL_LOCK(hnand); @@ -925,35 +1176,98 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad hnand->State = HAL_NAND_STATE_BUSY; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2); /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) + while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead); + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512) + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - } + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); + + if(hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); + } /* Get Data into Buffer */ for(; index < size; index++) @@ -968,7 +1282,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad NumSpareAreaToRead--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize)); + nandAddress = (uint32_t)(nandAddress + 1); } /* Update the NAND controller state */ @@ -993,7 +1307,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad { __IO uint32_t index = 0; uint32_t tickstart = 0; - uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0; + uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress =0; /* Process Locked */ __HAL_LOCK(hnand); @@ -1010,33 +1324,80 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad /* Update the FMC_NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + /* Page address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = COLUMN_ADDRESS(hnand); /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) + while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten); + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512) + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } } /* Write data to memory */ @@ -1068,7 +1429,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad NumSpareAreaTowrite--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize)); + nandAddress = (uint32_t)(nandAddress + 1); } /* Update the NAND controller state */ @@ -1085,7 +1446,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write + * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned. * @param NumSpareAreaTowrite : number of spare areas to write to block * @retval HAL status */ @@ -1093,7 +1454,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A { __IO uint32_t index = 0; uint32_t tickstart = 0; - uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0; + uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress = 0; /* Process Locked */ __HAL_LOCK(hnand); @@ -1111,32 +1472,79 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A hnand->State = HAL_NAND_STATE_BUSY; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2); /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) + while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten); + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } } /* Write data to memory */ @@ -1168,7 +1576,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A NumSpareAreaTowrite--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize)); + nandAddress = (uint32_t)(nandAddress + 1); } /* Update the NAND controller state */ @@ -1215,13 +1623,6 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy __DSB(); *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - __DSB(); - } *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; __DSB(); @@ -1235,39 +1636,6 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy return HAL_OK; } -/** - * @brief NAND memory read status - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval NAND status - */ -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) -{ - uint32_t data = 0; - uint32_t DeviceAddress = 0; - - /* Identify the device address */ - DeviceAddress = NAND_DEVICE; - - /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS; - - /* Read status register data */ - data = *(__IO uint8_t *)DeviceAddress; - - /* Return the status */ - if((data & NAND_ERROR) == NAND_ERROR) - { - return NAND_ERROR; - } - else if((data & NAND_READY) == NAND_READY) - { - return NAND_READY; - } - - return NAND_BUSY; -} - /** * @brief Increment the NAND memory address * @param hnand: pointer to a NAND_HandleTypeDef structure that contains @@ -1285,17 +1653,17 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA pAddress->Page++; /* Check NAND address is valid */ - if(pAddress->Page == hnand->Info.BlockSize) + if(pAddress->Page == hnand->Config.BlockSize) { pAddress->Page = 0; pAddress->Block++; - if(pAddress->Block == hnand->Info.ZoneSize) + if(pAddress->Block == hnand->Config.PlaneSize) { pAddress->Block = 0; - pAddress->Zone++; + pAddress->Plane++; - if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr)) + if(pAddress->Plane == (hnand->Config.PlaneSize/ hnand->Config.BlockNbr)) { status = NAND_INVALID_ADDRESS; } @@ -1437,6 +1805,39 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) return hnand->State; } +/** + * @brief NAND memory read status + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval NAND status + */ +uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) +{ + uint32_t data = 0; + uint32_t DeviceAddress = 0; + + /* Identify the device address */ + DeviceAddress = NAND_DEVICE; + + /* Send Read status operation command */ + *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS; + + /* Read status register data */ + data = *(__IO uint8_t *)DeviceAddress; + + /* Return the status */ + if((data & NAND_ERROR) == NAND_ERROR) + { + return NAND_ERROR; + } + else if((data & NAND_READY) == NAND_READY) + { + return NAND_READY; + } + + return NAND_BUSY; +} + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.h index 7e36a81c887..9f6dee1e528 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nand.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention @@ -94,7 +94,7 @@ typedef struct { uint16_t Page; /*!< NAND memory Page address */ - uint16_t Zone; /*!< NAND memory Zone address */ + uint16_t Plane; /*!< NAND memory Zone address */ uint16_t Block; /*!< NAND memory Block address */ @@ -105,31 +105,43 @@ typedef struct */ typedef struct { - uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */ + uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes + for 8 bits adressing or words for 16 bits addressing */ - uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */ + uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes + for 8 bits adressing or words for 16 bits addressing */ + + uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ - uint32_t BlockSize; /*!< NAND memory block size number of pages */ + uint32_t BlockNbr; /*!< NAND memory number of total blocks */ + + uint32_t PlaneNbr; /*!< NAND memory number of planes */ - uint32_t BlockNbr; /*!< NAND memory number of blocks */ + uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ - uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */ -}NAND_InfoTypeDef; + FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This + parameter is mandatory for some NAND parts after the read + command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. + Example: Toshiba THTH58BYG3S0HBAI6. + This parameter could be ENABLE or DISABLE + Please check the Read Mode sequnece in the NAND device datasheet */ +}NAND_DeviceConfigTypeDef; /** * @brief NAND handle Structure definition */ typedef struct { - FMC_NAND_TypeDef *Instance; /*!< Register base address */ + FMC_NAND_TypeDef *Instance; /*!< Register base address */ - FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ + FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ + + HAL_LockTypeDef Lock; /*!< NAND locking object */ - HAL_LockTypeDef Lock; /*!< NAND locking object */ + __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ - __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ + NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ - NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */ }NAND_HandleTypeDef; /** * @} @@ -163,6 +175,11 @@ typedef struct /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); + +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); + +HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); + void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); @@ -177,19 +194,21 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); */ /* IO operation functions ****************************************************/ -HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); + HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); + HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); + uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); /** @@ -271,7 +290,9 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize))) + (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + +#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) /** * @brief NAND memory address cycling. @@ -282,6 +303,15 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ + +/** + * @brief NAND memory Columns cycling. + * @param __ADDRESS__: NAND memory address. + * @retval NAND Column address cycling value. + */ +#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ +#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.c index 452dffdc0e0..a41a6d8ccd5 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nor.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.h index 1c44e7cec07..6b2ccdde3e0 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nor.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c index df4ac95b305..b7037e01743 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -206,6 +206,13 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { HAL_PCDEx_ActivateLPM(hpcd); } +#if defined (USB_OTG_GCCFG_BCDEN) + /* Activate Battery charging */ + if (hpcd->Init.battery_charging_enable ==1) + { + HAL_PCDEx_ActivateBCD(hpcd); + } +#endif /* USB_OTG_GCCFG_BCDEN */ USB_DevDisconnect (hpcd->Instance); return HAL_OK; @@ -511,7 +518,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - USB_FlushTxFifo(hpcd->Instance , 0 ); + USB_FlushTxFifo(hpcd->Instance, 0x10); for (i = 0; i < hpcd->Init.dev_endpoints ; i++) { @@ -1008,16 +1015,16 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { USB_OTG_EPTypeDef *ep; - + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - + /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; ep->xfer_count = 0; ep->is_in = 0; ep->num = ep_addr & 0x7F; - + if (hpcd->Init.dma_enable == 1) { ep->dma_addr = (uint32_t)pBuf; @@ -1046,7 +1053,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u */ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; + return hpcd->OUT_ep[ep_addr & 0xF].xfer_count; } /** * @brief Send an amount of data. diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.h index 109a00bd56a..403b05823b6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -94,8 +94,8 @@ typedef struct { PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ - PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ PCD_EPLockDef EPLock[15]; __IO PCD_StateTypeDef State; /*!< PCD communication state */ @@ -104,6 +104,9 @@ typedef struct uint32_t BESL; uint32_t lpm_active; /*!< Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE */ + + uint32_t battery_charging_active; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ void *pData; /*!< Pointer to upper stack Handler */ } PCD_HandleTypeDef; @@ -134,6 +137,7 @@ typedef struct */ #define PCD_PHY_ULPI 1U #define PCD_PHY_EMBEDDED 2U +#define PCD_PHY_UTMI 3U /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.c index 2a7a836b703..0be628fe8f5 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -166,6 +166,125 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) return HAL_OK; } +#if defined (USB_OTG_GCCFG_BCDEN) +/** + * @brief Handle BatteryCharging Process. + * @param hpcd: PCD handle + * @retval HAL status + */ +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t tickstart = HAL_GetTick(); + + /* Start BCD When device is connected */ + if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS) + { + /* Enable DCD : Data Contact Detect */ + USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; + + /* Wait Detect flag or a timeout is happen*/ + while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > 1000) + { + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); + return; + } + } + + /* Right response got */ + HAL_Delay(100); + + /* Check Detect flag*/ + if (USBx->GCCFG & USB_OTG_GCCFG_DCDET) + { + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); + } + + /*Primary detection: checks if connected to Standard Downstream Port + (without charging capability) */ + USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN; + USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + HAL_Delay(100); + + if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET)) + { + /* Case of Standard Downstream Port */ + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); + } + else + { + /* start secondary detection to check connection to Charging Downstream + Port or Dedicated Charging Port */ + USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN; + USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + HAL_Delay(100); + + if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET) + { + /* case Dedicated Charging Port */ + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); + } + else + { + /* case Charging Downstream Port */ + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); + } + } + /* Battery Charging capability discovery finished */ + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + } +} + +/** + * @brief Activate BatteryCharging feature. + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->battery_charging_active = ENABLE; + USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN); + + return HAL_OK; +} + +/** + * @brief Deactivate BatteryCharging feature. + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + hpcd->battery_charging_active = DISABLE; + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + return HAL_OK; +} + + +/** + * @brief Send BatteryCharging message to user layer callback. + * @param hpcd: PCD handle + * @param msg: LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_BCD_Callback could be implemented in the user file + */ +} + +#endif /* USB_OTG_GCCFG_BCDEN */ /** * @brief Send LPM message to user layer callback. * @param hpcd: PCD handle diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.h index f99d50714fa..959f448471f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -60,6 +60,17 @@ typedef enum PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */ }PCD_LPM_MsgTypeDef; +typedef enum +{ + PCD_BCD_ERROR = 0xFF, + PCD_BCD_CONTACT_DETECTION = 0xFE, + PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, + PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, + PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, + PCD_BCD_DISCOVERY_COMPLETED = 0x00, + +}PCD_BCD_MsgTypeDef; + /* Exported constants --------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -73,7 +84,11 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); +void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.c index 66435d3d4b5..c87d2b4d2cd 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -176,7 +176,7 @@ void HAL_PWR_DisableBkUpAccess(void) [..] (+) Wake-up pin is used to wake up the system from Standby mode. This pin is forced in input pull-down configuration and is active on rising edges. - (+) There are to 6 Wake-up pin in the STM32F7 devices family + (+) There are up to 6 Wake-up pin in the STM32F7 devices family *** Low Power modes configuration *** ===================================== diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.h index bd3b48116ee..62749ad3624 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.c index 3303591954a..4e0b6a2d3e1 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.h index 15980ae94b5..d32b7e5c5b3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.c index 99ccf45efd5..82309e038b3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_qspi.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief QSPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the QuadSPI interface (QSPI). diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.h index b5b86b18630..4bd99b83ca4 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_qspi.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of QSPI HAL module. ****************************************************************************** * @attention @@ -119,11 +119,11 @@ typedef struct QUADSPI_TypeDef *Instance; /* QSPI registers base address */ QSPI_InitTypeDef Init; /* QSPI communication parameters */ uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ - __IO uint16_t TxXferSize; /* QSPI Tx Transfer size */ - __IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */ + __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ + __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ - __IO uint16_t RxXferSize; /* QSPI Rx Transfer size */ - __IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */ + __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ + __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ __IO HAL_LockTypeDef Lock; /* Locking object */ __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.c index e02f7a89723..7cb6f6a5f2e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -258,7 +258,8 @@ void HAL_RCC_DeInit(void) */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - uint32_t tickstart = 0; + uint32_t tickstart = 0; + FlagStatus pwrclkchanged = RESET; /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); @@ -426,21 +427,30 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR1 |= PWR_CR1_DBP; - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR1 & PWR_CR1_DBP) == RESET) + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { - return HAL_TIMEOUT; - } + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } } /* Set the new LSE configuration -----------------------------------------*/ @@ -474,6 +484,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.h index 4dc5e72f2db..3c91ad01291 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.c index 440120ffb72..4d864618165 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Extension RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -818,6 +818,582 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0; + uint32_t tmpreg0 = 0; + uint32_t plli2sused = 0; + uint32_t pllsaiused = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + { + pllsaiused = 1; + } + } + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + } + + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + } + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */ + if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + { + /* check for PLLSAIQ Parameter */ + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0); + } + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg = 0; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2; + + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + + /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ)); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ)); + + /* Get the SAI1 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + + /* Get the SAI2 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + + /* Get the I2S clock configuration ------------------------------------------*/ + PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); + + /* Get the I2C1 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Get the I2C2 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + + /* Get the I2C3 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + + /* Get the USART1 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + + /* Get the USART2 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + + /* Get the USART3 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + + /* Get the UART4 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + + /* Get the UART5 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + + /* Get the USART6 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); + + /* Get the UART7 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); + + /* Get the UART8 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); + + /* Get the LPTIM1 clock configuration ------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the CK48 clock configuration -----------------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDMMC1 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); + + /* Get the SDMMC2 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); + + /* Get the RTC Clock configuration -----------------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the TIM Prescaler configuration --------------------------------------------*/ + if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ + /** * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.h index ea10360f89d..028ca0f9ef9 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -226,10 +226,13 @@ typedef struct uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ @@ -275,8 +278,11 @@ typedef struct #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) #define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ @@ -499,7 +505,7 @@ typedef struct /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source * @{ */ -#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) +#define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL @@ -535,7 +541,8 @@ typedef struct * @} */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source * @{ */ @@ -543,12 +550,14 @@ typedef struct #define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL /** * @} - */ + */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source * @{ */ -#define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) +#define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /** * @} @@ -618,15 +627,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ - UNUSED(tmpreg); \ - } while(0) + } while(0) #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -716,6 +717,8 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ @@ -731,11 +734,19 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ UNUSED(tmpreg); \ } while(0) + +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) -#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) @@ -747,8 +758,15 @@ typedef struct #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) +#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** * @brief Enable ETHERNET clock. */ @@ -801,12 +819,15 @@ typedef struct __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ __HAL_RCC_ETHMAC_CLK_DISABLE(); \ } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ @@ -814,6 +835,8 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ UNUSED(tmpreg); \ } while(0) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_CLK_ENABLE() do { \ @@ -842,8 +865,7 @@ typedef struct UNUSED(tmpreg); \ __HAL_RCC_SYSCFG_CLK_ENABLE();\ } while(0) - -#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) + #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) @@ -868,6 +890,18 @@ typedef struct #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) #endif /* STM32F756x || STM32F777xx || STM32F779xx */ +#if defined(STM32F732xx) || defined (STM32F733xx) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) +#endif /* STM32F732xx || STM32F733xx */ + /** @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before @@ -977,7 +1011,9 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) #define __HAL_RCC_RTC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ @@ -985,7 +1021,10 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ UNUSED(tmpreg); \ } while(0) - +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ @@ -1011,14 +1050,6 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ - UNUSED(tmpreg); \ - } while(0) - #define __HAL_RCC_USART2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ @@ -1074,62 +1105,73 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ UNUSED(tmpreg); \ } while(0) - -#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_CEC_CLK_ENABLE() do { \ +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_DAC_CLK_ENABLE() do { \ +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_UART7_CLK_ENABLE() do { \ +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_UART8_CLK_ENABLE() do { \ +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) @@ -1141,13 +1183,17 @@ typedef struct #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) -#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) @@ -1155,13 +1201,17 @@ typedef struct #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) -#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) -#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) -#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) +#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1200,7 +1250,8 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ @@ -1208,7 +1259,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1351,14 +1402,24 @@ typedef struct UNUSED(tmpreg); \ } while(0) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) +#define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F723xx || STM32F733xx */ #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) @@ -1379,9 +1440,12 @@ typedef struct #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) -#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) +#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) +#define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) +#endif /* STM32F723xx || STM32F733xx */ /** * @} @@ -1404,7 +1468,6 @@ typedef struct #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) -#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) @@ -1416,13 +1479,16 @@ typedef struct #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET) -#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET) @@ -1434,8 +1500,15 @@ typedef struct #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** * @brief Enable ETHERNET clock. */ @@ -1457,17 +1530,16 @@ typedef struct #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @brief Get the enable or disable status of the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ -#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) -#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) @@ -1478,6 +1550,17 @@ typedef struct #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) #endif /* STM32F756xx || STM32F777xx || STM32F779xx */ +#if defined(STM32F732xx) || defined (STM32F733xx) +#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) +#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) +#endif /* STM32F732xx || STM32F733xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) #define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) @@ -1510,12 +1593,10 @@ typedef struct #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) -#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) @@ -1523,10 +1604,7 @@ typedef struct #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) -#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) -#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) @@ -1542,12 +1620,10 @@ typedef struct #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) -#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) @@ -1555,13 +1631,30 @@ typedef struct #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) -#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) -#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) + +#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) +#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx */ /** @brief Get the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1591,11 +1684,18 @@ typedef struct #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) #endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) -#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) +#define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) +#endif /* STM32F723xx || STM32F733xx */ + #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) @@ -1619,11 +1719,18 @@ typedef struct #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) #endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) -#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) +#define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) +#endif /* STM32F723xx || STM32F733xx */ + /** * @} */ @@ -1636,8 +1743,6 @@ typedef struct /** @brief Force or release AHB1 peripheral reset. */ #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) -#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) -#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) @@ -1648,12 +1753,8 @@ typedef struct #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) -#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) -#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) -#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) -#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) @@ -1664,18 +1765,27 @@ typedef struct #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) + +#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) - +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** @brief Force or release AHB2 peripheral reset. */ #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) -#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) @@ -1690,6 +1800,17 @@ typedef struct #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) #endif /* STM32F756xx || STM32F777xx || STM32F779xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) +#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) +#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) +#endif /* STM32F732xx || STM32F733xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @brief Force or release AHB3 peripheral reset */ @@ -1718,7 +1839,6 @@ typedef struct #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) @@ -1726,10 +1846,7 @@ typedef struct #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) -#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) @@ -1749,7 +1866,6 @@ typedef struct #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) @@ -1757,14 +1873,24 @@ typedef struct #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) -#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** @brief Force or release APB2 peripheral reset. */ #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) @@ -1785,6 +1911,9 @@ typedef struct #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) +#define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) +#endif /* STM32F723xx || STM32F733xx */ #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) @@ -1804,18 +1933,24 @@ typedef struct #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) +#define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) +#endif /* STM32F723xx || STM32F733xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) #endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) #define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) - -#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) #define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ @@ -1841,11 +1976,6 @@ typedef struct #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN)) #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) -#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) -#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) -#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) -#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) -#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) @@ -1857,8 +1987,6 @@ typedef struct #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) -#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) -#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN)) @@ -1867,11 +1995,6 @@ typedef struct #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN)) #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) -#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) -#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) -#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) -#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) -#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) @@ -1883,8 +2006,25 @@ typedef struct #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) + +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1892,8 +2032,11 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) @@ -1913,6 +2056,11 @@ typedef struct #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) #endif /* STM32F756xx || STM32F777xx || STM32F779xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) +#endif /* STM32F732xx || STM32F733xx */ /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1943,12 +2091,10 @@ typedef struct #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) @@ -1956,10 +2102,7 @@ typedef struct #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) -#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) @@ -1975,12 +2118,10 @@ typedef struct #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) @@ -1988,14 +2129,32 @@ typedef struct #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) -#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) + +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. @@ -2016,7 +2175,6 @@ typedef struct #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) @@ -2037,7 +2195,6 @@ typedef struct #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) @@ -2048,14 +2205,22 @@ typedef struct #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) #define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) - -#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -2082,11 +2247,6 @@ typedef struct #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET) #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) -#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) @@ -2098,8 +2258,6 @@ typedef struct #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET) #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET) #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET) -#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) -#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET) #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET) @@ -2108,11 +2266,6 @@ typedef struct #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET) #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) -#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) @@ -2124,8 +2277,25 @@ typedef struct #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET) #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET) #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) + +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2133,8 +2303,11 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) @@ -2154,6 +2327,11 @@ typedef struct #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) #endif /* STM32F756xx || STM32F777xx || STM32F779xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET) +#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET) +#endif /* STM32F732xx || STM32F733xx */ /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2183,13 +2361,17 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) -#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) @@ -2197,10 +2379,7 @@ typedef struct #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) -#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET) #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET) @@ -2215,13 +2394,17 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) -#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) @@ -2229,14 +2412,24 @@ typedef struct #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) -#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET) #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) + +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. @@ -2257,7 +2450,6 @@ typedef struct #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) -#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) @@ -2266,8 +2458,11 @@ typedef struct #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) #endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ @@ -2286,7 +2481,6 @@ typedef struct #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) -#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) @@ -2295,11 +2489,20 @@ typedef struct #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) #endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -2399,6 +2602,45 @@ typedef struct #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. + * @param __PLLSAIQ__: specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \ + (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\ + ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\ + ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))) + +/** @brief Macro to configure the PLLI2S clock multiplication and division factors. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) + * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SQ__: specifies the division factor for SAI clock. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @param __PLLI2SR__: specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ + ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ + ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))) +#else /** @brief Macro to configure the PLLSAI clock multiplication and division factors. * @note This function must be used only when the PLLSAI is disabled. * @note PLLSAI clock source is common with the main PLL (configured in @@ -2442,6 +2684,7 @@ typedef struct ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\ ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. * @note This function must be called before enabling the PLLI2S. @@ -2459,8 +2702,9 @@ typedef struct */ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. - * * @note This function must be called before enabling the PLLSAI. * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock . * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. @@ -2468,6 +2712,7 @@ typedef struct */ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @brief Macro to configure SAI1 clock source selection. * @note This function must be called before enabling PLLSAI, PLLI2S and @@ -2813,7 +3058,7 @@ typedef struct * * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source. * This parameter can be one of the following values: - * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock @@ -2823,7 +3068,7 @@ typedef struct /** @brief macro to get the LPTIM1 clock source. * @retval The clock source can be one of the following values: - * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock @@ -2881,7 +3126,8 @@ typedef struct */ #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source. * This parameter can be one of the following values: @@ -2897,11 +3143,13 @@ typedef struct * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock */ #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @brief Macro to configure the DFSDM1 clock * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source. * This parameter can be one of the following values: - * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock */ #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ @@ -2909,7 +3157,7 @@ typedef struct /** @brief Macro to get the DFSDM1 clock source. * @retval The clock source can be one of the following values: - * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM1 clock * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock */ #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) @@ -3073,12 +3321,37 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#endif /* STM32F746xx || STM32F756xx */ +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#endif /* STM32F746xx || STM32F756xx */ #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ ((VALUE) == RCC_PLLI2SP_DIV4) ||\ ((VALUE) == RCC_PLLI2SP_DIV6) ||\ - ((VALUE) == RCC_PLLI2SP_DIV8)) + ((VALUE) == RCC_PLLI2SP_DIV8)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) @@ -3170,7 +3443,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)) #define IS_RCC_LPTIM1CLK(SOURCE) \ - (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \ + (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) @@ -3181,14 +3454,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ ((VALUE) == RCC_TIMPRES_ACTIVATED)) -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\ + defined (STM32F746xx) || defined (STM32F756xx) #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) @@ -3203,16 +3477,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) -#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) - -#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || \ +#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) #define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.c index 9fef4983b76..5ff07844d18 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rng.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.h index 5d93ae6577b..2ac29c8b4e8 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rng.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.c index 102b1068243..0836f48790f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h index 46517bda5df..1c3c4ebae62 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -202,8 +202,8 @@ typedef struct /** @defgroup RTC_Hour_Formats RTC Hour Formats * @{ */ -#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U) -#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040U) +#define RTC_HOURFORMAT_24 0x00000000U +#define RTC_HOURFORMAT_12 0x00000040U /** * @} */ @@ -212,8 +212,8 @@ typedef struct /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ -#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U) -#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000U) +#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U +#define RTC_OUTPUT_POLARITY_LOW 0x00100000U /** * @} */ @@ -221,8 +221,8 @@ typedef struct /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U) -#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMTYPE) /* 0x00000008 */ +#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U +#define RTC_OUTPUT_TYPE_PUSHPULL RTC_OR_ALARMTYPE /* 0x00000008 */ /** * @} */ @@ -239,9 +239,9 @@ typedef struct /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions * @{ */ -#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000U) -#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000U) -#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U) +#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U +#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U +#define RTC_DAYLIGHTSAVING_NONE 0x00000000U /** * @} */ @@ -249,8 +249,8 @@ typedef struct /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions * @{ */ -#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U) -#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000U) +#define RTC_STOREOPERATION_RESET 0x00000000U +#define RTC_STOREOPERATION_SET 0x00040000U /** * @} */ @@ -258,8 +258,8 @@ typedef struct /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN ((uint32_t)0x00000000U) -#define RTC_FORMAT_BCD ((uint32_t)0x00000001U) +#define RTC_FORMAT_BIN 0x00000000U +#define RTC_FORMAT_BCD 0x00000001U /** * @} */ @@ -301,8 +301,8 @@ typedef struct /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions * @{ */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000U) +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U /** * @} */ @@ -310,12 +310,12 @@ typedef struct /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions * @{ */ -#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U) +#define RTC_ALARMMASK_NONE 0x00000000U #define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 #define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080U) +#define RTC_ALARMMASK_ALL 0x80808080U /** * @} */ @@ -332,39 +332,39 @@ typedef struct /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000U) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000U) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000U) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000U) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000U) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000U) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000U) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000U) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000U) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000U) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000U) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000U) /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000U) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000U) /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000U) /*!< SS[14:0] are compared and must match - to activate alarm. */ +#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm + comparison.Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match + to activate alarm. */ /** * @} */ @@ -372,14 +372,14 @@ typedef struct /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions * @{ */ -#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) -#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) -#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) -#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) -#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) -#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) -#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE) +#define RTC_IT_TS RTC_CR_TSIE +#define RTC_IT_WUT RTC_CR_WUTIE +#define RTC_IT_ALRA RTC_CR_ALRAIE +#define RTC_IT_ALRB RTC_CR_ALRBIE +#define RTC_IT_TAMP RTC_TAMPCR_TAMPIE /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE +#define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE +#define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE /** * @} */ @@ -387,23 +387,23 @@ typedef struct /** @defgroup RTC_Flags_Definitions RTC Flags Definitions * @{ */ -#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF) -#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F) -#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F) -#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F) -#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF) -#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF) -#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF) -#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF) -#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF) -#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF) -#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF) -#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF) -#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS) -#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF) -#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF) -#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF) -#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF) +#define RTC_FLAG_RECALPF RTC_ISR_RECALPF +#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F +#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F +#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F +#define RTC_FLAG_TSOVF RTC_ISR_TSOVF +#define RTC_FLAG_TSF RTC_ISR_TSF +#define RTC_FLAG_ITSF RTC_ISR_ITSF +#define RTC_FLAG_WUTF RTC_ISR_WUTF +#define RTC_FLAG_ALRBF RTC_ISR_ALRBF +#define RTC_FLAG_ALRAF RTC_ISR_ALRAF +#define RTC_FLAG_INITF RTC_ISR_INITF +#define RTC_FLAG_RSF RTC_ISR_RSF +#define RTC_FLAG_INITS RTC_ISR_INITS +#define RTC_FLAG_SHPF RTC_ISR_SHPF +#define RTC_FLAG_WUTWF RTC_ISR_WUTWF +#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF +#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF /** * @} */ @@ -430,9 +430,9 @@ typedef struct */ #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ do{ \ - (__HANDLE__)->Instance->WPR = 0xCA; \ - (__HANDLE__)->Instance->WPR = 0x53; \ - } while(0) + (__HANDLE__)->Instance->WPR = 0xCAU; \ + (__HANDLE__)->Instance->WPR = 0x53U; \ + } while(0U) /** * @brief Enable the write protection for RTC registers. @@ -441,8 +441,8 @@ typedef struct */ #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ do{ \ - (__HANDLE__)->Instance->WPR = 0xFF; \ - } while(0) + (__HANDLE__)->Instance->WPR = 0xFFU; \ + } while(0U) /** * @brief Enable the RTC ALARMA peripheral. @@ -503,7 +503,7 @@ typedef struct * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) & 0x0000FFFFU) != RESET)? SET : RESET) /** * @brief Get the selected RTC Alarm's flag status. @@ -527,7 +527,7 @@ typedef struct * @arg RTC_FLAG_ALRBF * @retval None */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFFU)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. @@ -697,14 +697,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3FU) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) +#define RTC_TR_RESERVED_MASK 0x007F7F7FU +#define RTC_DR_RESERVED_MASK 0x00FFFF3FU +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK 0xFFFFFF5FU -#define RTC_TIMEOUT_VALUE 1000 +#define RTC_TIMEOUT_VALUE 1000U -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ /** * @} */ @@ -723,12 +723,12 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((__POL__) == RTC_OUTPUT_POLARITY_LOW)) #define IS_RTC_OUTPUT_TYPE(__TYPE__) (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ ((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL)) -#define IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7F) -#define IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7FFF) -#define IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12)) -#define IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= (uint32_t)23) -#define IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= (uint32_t)59) -#define IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= (uint32_t)59) +#define IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= 0x7FU) +#define IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= 0x7FFFU) +#define IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U)) +#define IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) +#define IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) +#define IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) #define IS_RTC_HOURFORMAT12(__PM__) (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM)) #define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \ ((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \ @@ -736,9 +736,9 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \ ((__OPERATION__) == RTC_STOREOPERATION_SET)) #define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD)) -#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= (uint32_t)99) -#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12)) -#define IS_RTC_DATE(__DATE__) (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31)) +#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) +#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) +#define IS_RTC_DATE(__DATE__) (((__DATE__) >= 1U) && ((__DATE__) <= 31U)) #define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \ ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \ ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \ @@ -747,7 +747,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \ ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY)) -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >0U) && ((__DATE__) <= 31U)) #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \ ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \ ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \ @@ -757,9 +757,9 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY)) #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ ((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) -#define IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & 0x7F7F7F7F) == (uint32_t)RESET) +#define IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & 0x7F7F7F7FU) == (uint32_t)RESET) #define IS_RTC_ALARM(__ALARM__) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B)) -#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)0x00007FFF) +#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= 0x00007FFFU) #define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__) (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c index 9fa76b4c346..65e5722c214 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extension peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.h index ab2b6b084ef..fba590f9bbb 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c index 4c8a1ec01fa..53aef1fa3e2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief SAI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Audio Interface (SAI) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.h index 41c6f0b60c5..74171e1cea0 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of SAI HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.c index 0483d03c392..8b61b43e96f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Empty file; This file is no longer used to set synchronization and * to get SAI block frequency. Its content is now moved to common files * (stm32f7xx_hal_sai.c/.h) as there's no device's dependency within F7 diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.h index 53273640ea3..92456e8e6fd 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of SAI Extension HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.c index 0d7fa4d2f72..6cf7661c4a7 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.c @@ -2,15 +2,15 @@ ****************************************************************************** * @file stm32f7xx_hal_sd.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions - * + Peripheral State functions + * + SD card Control functions * @verbatim ============================================================================== @@ -43,35 +43,49 @@ (+++) Configure the SDMMC and DMA interrupt priorities using functions HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() - (+++) SDMMC interrupts are managed using the macros __HAL_SD_SDMMC_ENABLE_IT() - and __HAL_SD_SDMMC_DISABLE_IT() inside the communication process. - (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_SDMMC_GET_IT() - and __HAL_SD_SDMMC_CLEAR_IT() + (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() + and __HAL_SD_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT() + and __HAL_SD_CLEAR_IT() + (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT() + and HAL_SD_WriteBlocks_IT() APIs). + (+++) Configure the SDMMC interrupt priorities using function + HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() + and __HAL_SD_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT() + and __HAL_SD_CLEAR_IT() (#) At this stage, you can perform SD read/write/erase operations after SD card initialization *** SD Card Initialization and configuration *** ================================================ [..] - To initialize the SD Card, use the HAL_SD_Init() function. It Initializes - the SD Card and put it into StandBy State (Ready for data transfer). + To initialize the SD Card, use the HAL_SD_Init() function. It Initializes + SDMMC IP (STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). This function provide the following operations: - - (#) Apply the SD Card initialization process at 400KHz and check the SD Card - type (Standard Capacity or High Capacity). You can change or adapt this - frequency by adjusting the "ClockDiv" field. + + (#) Initialize the SDMMC peripheral interface with defaullt configuration. + The initialization process is done at 400KHz. You can change or adapt + this frequency by adjusting the "ClockDiv" field. The SD Card frequency (SDMMC_CK) is computed as follows: SDMMC_CK = SDMMCCLK / (ClockDiv + 2) In initialization mode and according to the SD Card standard, make sure that the SDMMC_CK frequency doesn't exceed 400KHz. - - (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo - structure. This structure provide also ready computed SD Card capacity - and Block size. - - -@- These information are stored in SD handle structure in case of future use. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the SD card. The API used is HAL_SD_InitCard(). + This phase allows the card initialization and identification + and check the SD Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with SD standard. + + This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. (#) Configure the SD Card Data transfer frequency. By Default, the card transfer frequency is set to 24MHz. You can change or adapt this frequency by adjusting @@ -90,59 +104,94 @@ ============================== [..] (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). + This function allows the read of 512 bytes blocks. You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Rx interrupt event. + + (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT(). + This function allows the read of 512 bytes blocks. You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. - After this, you have to call the function HAL_SD_CheckReadOperation(), to insure - that the read transfer is done correctly in both DMA and SD sides. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Rx interrupt event. *** SD Card Write operation *** =============================== [..] (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). + This function allows the read of 512 bytes blocks. You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). - This function support only 512-bytes block length (the block size should be - chosen as 512 byte). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Tx interrupt event. + + (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT(). + This function allows the read of 512 bytes blocks. You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. - After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure - that the write transfer is done correctly in both DMA and SD sides. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Tx interrupt event. *** SD card status *** ====================== [..] - (+) At any time, you can check the SD Card status and get the SD card state - by using the HAL_SD_GetStatus() function. This function checks first if the - SD card is still connected and then get the internal SD Card transfer state. - (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() - function. + (+) The SD Status contains status bits that are related to the SD Memory + Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus(). + + *** SD card information *** + =========================== + [..] + (+) To get SD card information, you can use the function HAL_SD_GetCardInfo(). + It returns useful information about the SD card such as block size, card type, + block number ... + + *** SD card CSD register *** + ============================ + [..] + (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** SD card CID register *** + ============================ + [..] + (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register. + Some of the CSD parameters are useful for card initialization and identification. *** SD HAL driver macros list *** ================================== [..] Below the list of most used macros in SD HAL driver. - (+) __HAL_SD_SDMMC_ENABLE : Enable the SD device - (+) __HAL_SD_SDMMC_DISABLE : Disable the SD device - (+) __HAL_SD_SDMMC_DMA_ENABLE: Enable the SDMMC DMA transfer - (+) __HAL_SD_SDMMC_DMA_DISABLE: Disable the SDMMC DMA transfer - (+) __HAL_SD_SDMMC_ENABLE_IT: Enable the SD device interrupt - (+) __HAL_SD_SDMMC_DISABLE_IT: Disable the SD device interrupt - (+) __HAL_SD_SDMMC_GET_FLAG:Check whether the specified SD flag is set or not - (+) __HAL_SD_SDMMC_CLEAR_FLAG: Clear the SD's pending flags - + (+) __HAL_SD_ENABLE : Enable the SD device + (+) __HAL_SD_DISABLE : Disable the SD device + (+) __HAL_SD_DMA_ENABLE: Enable the SDMMC DMA transfer + (+) __HAL_SD_DMA_DISABLE: Disable the SDMMC DMA transfer + (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt + (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt + (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not + (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags + + [..] (@) You can refer to the SD HAL driver header file for more useful macros @endverbatim @@ -194,85 +243,7 @@ /** @addtogroup SD_Private_Defines * @{ */ -/** - * @brief SDMMC Data block size - */ -#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4)) -/** - * @brief SDMMC Static flags, Timeout, FIFO Address - */ -#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ - SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ - SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ - SDMMC_FLAG_DBCKEND)) - -#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000U) - -/** - * @brief Mask for errors Card Status R1 (OCR Register) - */ -#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) -#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) -#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) -#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) -#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) -#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) -#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) -#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) -#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) -#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) -#define SD_OCR_CC_ERROR ((uint32_t)0x00100000U) -#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) -#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) -#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) -#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) -#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) -#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) -#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000U) -#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) -#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) - -/** - * @brief Masks for R6 Response - */ -#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) -#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) -#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) - -#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) -#define SD_HIGH_CAPACITY ((uint32_t)0x40000000U) -#define SD_STD_CAPACITY ((uint32_t)0x00000000U) -#define SD_CHECK_PATTERN ((uint32_t)0x000001AAU) - -#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) -#define SD_ALLZERO ((uint32_t)0x00000000U) - -#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) -#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) -#define SD_CARD_LOCKED ((uint32_t)0x02000000U) - -#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) -#define SD_0TO7BITS ((uint32_t)0x000000FFU) -#define SD_8TO15BITS ((uint32_t)0x0000FF00U) -#define SD_16TO23BITS ((uint32_t)0x00FF0000U) -#define SD_24TO31BITS ((uint32_t)0xFF000000U) -#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) - -#define SD_HALFFIFO ((uint32_t)0x00000008U) -#define SD_HALFFIFOBYTES ((uint32_t)0x00000020U) - -/** - * @brief Command Class Supported - */ -#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080U) -#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040U) -#define SD_CCCC_ERASE ((uint32_t)0x00000020U) - -/** - * @brief Following commands are SD Card Specific commands. - * SDMMC_APP_CMD should be sent before sending these commands. - */ -#define SD_SDMMC_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD) + /** * @} */ @@ -284,29 +255,25 @@ /** @defgroup SD_Private_Functions SD Private Functions * @{ */ -static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr); -static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); -static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus); -static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD); -static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA); -static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); -static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma); -static void SD_DMA_RxError(DMA_HandleTypeDef *hdma); -static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma); -static void SD_DMA_TxError(DMA_HandleTypeDef *hdma); +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd); +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd); +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd); +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); +static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd); +static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd); +static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd); +static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SD_DMAError(DMA_HandleTypeDef *hdma); +static void SD_DMATxAbort(DMA_HandleTypeDef *hdma); +static void SD_DMARxAbort(DMA_HandleTypeDef *hdma); /** * @} */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup SD_Exported_Functions * @{ @@ -322,79 +289,129 @@ static void SD_DMA_TxError(DMA_HandleTypeDef *hdma); [..] This section provides functions allowing to initialize/de-initialize the SD card device to be ready for use. - - + @endverbatim * @{ */ /** - * @brief Initializes the SD card according to the specified parameters in the + * @brief Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle. - * @param hsd: SD handle - * @param SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information - * @retval HAL SD error state + * @param hsd: Pointer to the SD handle + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo) -{ - __IO HAL_SD_ErrorTypedef errorstate = SD_OK; - SD_InitTypeDef tmpinit; - - /* Allocate lock resource and initialize it */ - hsd->Lock = HAL_UNLOCKED; +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) +{ + /* Check the SD handle allocation */ + if(hsd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); + assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass)); + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv)); + + if(hsd->State == HAL_SD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsd->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_SD_MspInit(hsd); + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize the Card parameters */ + HAL_SD_InitCard(hsd); + + /* Initialize the error code */ + hsd->ErrorCode = HAL_DMA_ERROR_NONE; - /* Initialize the low level hardware (MSP) */ - HAL_SD_MspInit(hsd); + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; + + /* Initialize the SD state */ + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the SD Card. + * @param hsd: Pointer to SD handle + * @note This function initializes the SD card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; + SD_InitTypeDef Init; /* Default SDMMC peripheral configuration for SD card initialization */ - tmpinit.ClockEdge = SDMMC_CLOCK_EDGE_RISING; - tmpinit.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; - tmpinit.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; - tmpinit.BusWide = SDMMC_BUS_WIDE_1B; - tmpinit.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; - tmpinit.ClockDiv = SDMMC_INIT_CLK_DIV; - + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDMMC_BUS_WIDE_1B; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDMMC_INIT_CLK_DIV; + /* Initialize SDMMC peripheral interface with default configuration */ - SDMMC_Init(hsd->Instance, tmpinit); - - /* Identify card operating voltage */ - errorstate = SD_PowerON(hsd); + SDMMC_Init(hsd->Instance, Init); + + /* Disable SDMMC Clock */ + __HAL_SD_DISABLE(hsd); - if(errorstate != SD_OK) - { - return errorstate; - } + /* Set Power State to ON */ + SDMMC_PowerState_ON(hsd->Instance); - /* Initialize the present SDMMC card(s) and put them in idle state */ - errorstate = SD_Initialize_Cards(hsd); + /* Enable SDMMC Clock */ + __HAL_SD_ENABLE(hsd); - if (errorstate != SD_OK) + /* Identify card operating voltage */ + errorstate = SD_PowerON(hsd); + if(errorstate != HAL_SD_ERROR_NONE) { - return errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; } - - /* Read CSD/CID MSD registers */ - errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo); - - if (errorstate == SD_OK) + + /* Card initialization */ + errorstate = SD_InitCard(hsd); + if(errorstate != HAL_SD_ERROR_NONE) { - /* Select the Card */ - errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16)); + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; } - - /* Configure SDMMC peripheral interface */ - SDMMC_Init(hsd->Instance, hsd->Init); - - return errorstate; + + return HAL_OK; } /** * @brief De-Initializes the SD card. - * @param hsd: SD handle + * @param hsd: Pointer to SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) { + /* Check the SD handle allocation */ + if(hsd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); + + hsd->State = HAL_SD_STATE_BUSY; /* Set SD power state to off */ SD_PowerOFF(hsd); @@ -402,13 +419,16 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) /* De-Initialize the MSP layer */ HAL_SD_MspDeInit(hsd); + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_RESET; + return HAL_OK; } /** * @brief Initializes the SD MSP. - * @param hsd: SD handle + * @param hsd: Pointer to SD handle * @retval None */ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) @@ -423,7 +443,7 @@ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) /** * @brief De-Initialize SD MSP. - * @param hsd: SD handle + * @param hsd: Pointer to SD handle * @retval None */ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) @@ -457,1013 +477,1123 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) /** * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by polling mode. - * @param hsd: SD handle - * @param pReadBuffer: pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data is to be read - * @param BlockSize: SD card Data block size - * @note BlockSize must be 512 bytes. - * @param NumberOfBlocks: Number of SD blocks to read - * @retval SD Card error state + * is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of SD blocks to read + * @param Timeout: Specify timeout value + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); + uint32_t count = 0, *tempbuff = (uint32_t *)pData; - /* Set Block Size for Card */ - sdmmc_cmdinitstructure.Argument = (uint32_t) BlockSize; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = NumberOfBlocks * BlockSize; - sdmmc_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - if(NumberOfBlocks > 1) - { - /* Send CMD18 READ_MULT_BLOCK with argument data address */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; - } - else + if(NULL == pData) { - /* Send CMD17 READ_SINGLE_BLOCK */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - - sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1) + + if(hsd->State == HAL_SD_STATE_READY) { - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); + hsd->ErrorCode = HAL_DMA_ERROR_NONE; - if (errorstate != SD_OK) + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { - return errorstate; + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + /* Read block(s) in polling mode */ + if(NumberOfBlocks > 1) + { + hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + /* Poll on SDMMC flags */ - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0; count < 8; count++) + for(count = 0U; count < 8U; count++) { *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); } - - tempbuff += 8; + tempbuff += 8U; } - } - } - else - { - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); - - if (errorstate != SD_OK) - { - return errorstate; - } + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } - /* In case of single block transfer, no need of stop transfer at all */ - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) - { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + /* Send stop transmission command in case of multiblock read */ + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + if(hsd->SdCard.CardType != CARD_SECURED) { - /* Read data from SDMMC Rx FIFO */ - for (count = 0; count < 8; count++) + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { - *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } - - tempbuff += 8; } - } - } - - /* Send stop transmission command in case of multiblock read */ - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1)) - { - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\ - (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send stop transmission command */ - errorstate = HAL_SD_StopTransfer(hsd); } - } - - /* Get error state */ - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + /* Get error state */ + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } - errorstate = SD_DATA_CRC_FAIL; + /* Empty FIFO if there is still any data */ + while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) + { + *tempbuff = SDMMC_ReadFIFO(hsd->Instance); + tempbuff++; + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + return HAL_ERROR; + } + } - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - errorstate = SD_RX_OVERRUN; + hsd->State = HAL_SD_STATE_READY; - return errorstate; + return HAL_OK; } else { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - - /* Empty FIFO if there is still any data */ - while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0)) - { - *tempbuff = SDMMC_ReadFIFO(hsd->Instance); - tempbuff++; - count--; + hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + return HAL_ERROR; } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - return errorstate; } /** * @brief Allows to write block(s) to a specified address in a card. The Data - * transfer is managed by polling mode. - * @param hsd: SD handle - * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit - * @param WriteAddr: Address from where data is to be written - * @param BlockSize: SD card Data block size - * @note BlockSize must be 512 bytes. - * @param NumberOfBlocks: Number of SD blocks to write - * @retval SD Card error state + * transfer is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of SD blocks to write + * @param Timeout: Specify timeout value + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0; - uint32_t *tempbuff = (uint32_t *)pWriteBuffer; - uint8_t cardstate = 0; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /* Set Block Size for Card */ - sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - if(NumberOfBlocks > 1) - { - /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; - } - else - { - /* Send CMD24 WRITE_SINGLE_BLOCK */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; - } - - sdmmc_cmdinitstructure.Argument = (uint32_t)WriteAddr; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); - } - else - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); - } + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); + uint32_t count = 0; + uint32_t *tempbuff = (uint32_t *)pData; - if (errorstate != SD_OK) + if(NULL == pData) { - return errorstate; + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - - /* Set total number of bytes to write */ - totalnumberofbytes = NumberOfBlocks * BlockSize; - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = NumberOfBlocks * BlockSize; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - /* Write block(s) in polling mode */ - if(NumberOfBlocks > 1) + + if(hsd->State == HAL_SD_STATE_READY) { - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + hsd->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + /* Write block(s) in polling mode */ + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE)) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE)) { - if ((totalnumberofbytes - bytestransferred) < 32) - { - restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); - - /* Write data to SDMMC Tx FIFO */ - for (count = 0; count < restwords; count++) - { - SDMMC_WriteFIFO(hsd->Instance, tempbuff); - tempbuff++; - bytestransferred += 4; - } - } - else + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) { - /* Write data to SDMMC Tx FIFO */ - for (count = 0; count < 8; count++) - { - SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count)); - } - - tempbuff += 8; - bytestransferred += 32; + SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count)); } + tempbuff += 8U; } - } - } - else - { - /* In case of single data block transfer no need of stop command at all */ - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) - { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE)) + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) { - if ((totalnumberofbytes - bytestransferred) < 32) - { - restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); - - /* Write data to SDMMC Tx FIFO */ - for (count = 0; count < restwords; count++) - { - SDMMC_WriteFIFO(hsd->Instance, tempbuff); - tempbuff++; - bytestransferred += 4; - } - } - else + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock write */ + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { - /* Write data to SDMMC Tx FIFO */ - for (count = 0; count < 8; count++) - { - SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count)); - } - - tempbuff += 8; - bytestransferred += 32; + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } } - } - } - - /* Send stop transmission command in case of multiblock write */ - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1)) - { - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send stop transmission command */ - errorstate = HAL_SD_StopTransfer(hsd); } - } - - /* Get error state */ - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - errorstate = SD_DATA_TIMEOUT; + /* Get error state */ + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - errorstate = SD_DATA_CRC_FAIL; + hsd->State = HAL_SD_STATE_READY; - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR); - - errorstate = SD_TX_UNDERRUN; - - return errorstate; + return HAL_OK; } else { - /* No error flag set */ - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* Wait till the card is in programming state */ - errorstate = SD_IsCardProgramming(hsd, &cardstate); - - while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) - { - errorstate = SD_IsCardProgramming(hsd, &cardstate); + hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + return HAL_ERROR; } - - return errorstate; } /** * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by the function HAL_SD_CheckReadOperation() - * to check the completion of the read process - * @param hsd: SD handle - * @param pReadBuffer: Pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data is to be read - * @param BlockSize: SD card Data block size - * @note BlockSize must be 512 bytes. + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the IT transfer process through the SD Rx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Number of blocks to read. - * @retval SD Card error state + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - /* Initialize handle flags */ - hsd->SdTransferCplt = 0; - hsd->DmaTransferCplt = 0; - hsd->SdTransferErr = SD_OK; - - /* Initialize SD Read operation */ - if(NumberOfBlocks > 1) - { - hsd->SdOperation = SD_READ_MULTIPLE_BLOCK; - } - else - { - hsd->SdOperation = SD_READ_SINGLE_BLOCK; - } - - /* Enable transfer interrupts */ - __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\ - SDMMC_IT_DTIMEOUT |\ - SDMMC_IT_DATAEND |\ - SDMMC_IT_RXOVERR)); - - /* Enable SDMMC DMA transfer */ - __HAL_SD_SDMMC_DMA_ENABLE(hsd); - - /* Configure DMA user callbacks */ - hsd->hdmarx->XferCpltCallback = SD_DMA_RxCplt; - hsd->hdmarx->XferErrorCallback = SD_DMA_RxError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4); - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } - - /* Set Block Size for Card */ - sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = BlockSize * NumberOfBlocks; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - /* Check number of blocks command */ - if(NumberOfBlocks > 1) - { - /* Send CMD18 READ_MULT_BLOCK with argument data address */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; - } - else + if(NULL == pData) { - /* Send CMD17 READ_SINGLE_BLOCK */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) + if(hsd->State == HAL_SD_STATE_READY) { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); + hsd->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pRxBuffPtr = (uint32_t *)pData; + hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Read Blocks in IT mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; } else { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); + return HAL_BUSY; } - - /* Update the SD transfer error in SD handle */ - hsd->SdTransferErr = errorstate; - - return errorstate; } - /** * @brief Writes block(s) to a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by the function HAL_SD_CheckWriteOperation() - * to check the completion of the write process (by SD current status polling). - * @param hsd: SD handle - * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit - * @param WriteAddr: Address from where data is to be read - * @param BlockSize: the SD card Data block size - * @note BlockSize must be 512 bytes. + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the IT transfer process through the SD Tx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written * @param NumberOfBlocks: Number of blocks to write - * @retval SD Card error state + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - /* Initialize handle flags */ - hsd->SdTransferCplt = 0; - hsd->DmaTransferCplt = 0; - hsd->SdTransferErr = SD_OK; - - /* Initialize SD Write operation */ - if(NumberOfBlocks > 1) - { - hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK; - } - else - { - hsd->SdOperation = SD_WRITE_SINGLE_BLOCK; - } - - /* Enable transfer interrupts */ - __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\ - SDMMC_IT_DTIMEOUT |\ - SDMMC_IT_DATAEND |\ - SDMMC_IT_TXUNDERR)); - - /* Configure DMA user callbacks */ - hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt; - hsd->hdmatx->XferErrorCallback = SD_DMA_TxError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4); - - /* Enable SDMMC DMA transfer */ - __HAL_SD_SDMMC_DMA_ENABLE(hsd); - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /* Set Block Size for Card */ - sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* Check number of blocks command */ - if(NumberOfBlocks <= 1) - { - /* Send CMD24 WRITE_SINGLE_BLOCK */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; - } - else + if(NULL == pData) { - /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - sdmmc_cmdinitstructure.Argument = (uint32_t)WriteAddr; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) + if(hsd->State == HAL_SD_STATE_READY) { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); + hsd->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pTxBuffPtr = (uint32_t *)pData; + hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; + + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + return HAL_OK; } else { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); - } - - if (errorstate != SD_OK) - { - return errorstate; + return HAL_BUSY; } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = BlockSize * NumberOfBlocks; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - hsd->SdTransferErr = errorstate; - - return errorstate; } /** - * @brief This function waits until the SD DMA data read transfer is finished. - * This API should be called after HAL_SD_ReadBlocks_DMA() function - * to insure that all data sent by the card is already transferred by the - * DMA controller. - * @param hsd: SD handle - * @param Timeout: Timeout duration - * @retval SD Card error state + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the DMA transfer process through the SD Rx + * interrupt event. + * @param hsd: Pointer SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout = Timeout; - uint32_t tmp1, tmp2; - HAL_SD_ErrorTypedef tmp3; - - /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */ - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - - while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0)) - { - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - timeout--; - } - - timeout = Timeout; - - /* Wait until the Rx transfer is no longer active */ - while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) && (timeout > 0)) - { - timeout--; - } + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* Send stop command in multiblock read */ - if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK) + if(NULL == pData) { - errorstate = HAL_SD_StopTransfer(hsd); + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - if ((timeout == 0) && (errorstate == SD_OK)) + if(hsd->State == HAL_SD_STATE_READY) { - errorstate = SD_DATA_TIMEOUT; + hsd->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + + /* Set the DMA transfer complete callback */ + hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt; + + /* Set the DMA error callback */ + hsd->hdmarx->XferErrorCallback = SD_DMAError; + + /* Set the DMA Abort callback */ + hsd->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); + + /* Enable SD DMA transfer */ + __HAL_SD_DMA_ENABLE(hsd); + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* Return error state */ - if (hsd->SdTransferErr != SD_OK) + else { - return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr); + return HAL_BUSY; } - - return errorstate; } /** - * @brief This function waits until the SD DMA data write transfer is finished. - * This API should be called after HAL_SD_WriteBlocks_DMA() function - * to insure that all data sent by the card is already transferred by the - * DMA controller. - * @param hsd: SD handle - * @param Timeout: Timeout duration - * @retval SD Card error state + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the DMA transfer process through the SD Tx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout = Timeout; - uint32_t tmp1, tmp2; - HAL_SD_ErrorTypedef tmp3; - - /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */ - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - - while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0)) - { - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - timeout--; - } + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; - timeout = Timeout; - - /* Wait until the Tx transfer is no longer active */ - while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXACT)) && (timeout > 0)) - { - timeout--; - } - - /* Send stop command in multiblock write */ - if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK) + if(NULL == pData) { - errorstate = HAL_SD_StopTransfer(hsd); + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - if ((timeout == 0) && (errorstate == SD_OK)) + if(hsd->State == HAL_SD_STATE_READY) { - errorstate = SD_DATA_TIMEOUT; + hsd->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + /* Enable SD Error interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); + + /* Set the DMA transfer complete callback */ + hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt; + + /* Set the DMA error callback */ + hsd->hdmatx->XferErrorCallback = SD_DMAError; + + /* Set the DMA Abort callback */ + hsd->hdmatx->XferAbortCallback = NULL; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Enable SDMMC DMA transfer */ + __HAL_SD_DMA_ENABLE(hsd); + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + return HAL_OK; } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* Return error state */ - if (hsd->SdTransferErr != SD_OK) + else { - return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr); + return HAL_BUSY; } - - /* Wait until write is complete */ - while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK) - { - } - - return errorstate; } /** * @brief Erases the specified memory area of the given SD card. - * @param hsd: SD handle - * @param startaddr: Start byte address - * @param endaddr: End byte address - * @retval SD Card error state + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr) +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - - uint32_t delay = 0; - __IO uint32_t maxdelay = 0; - uint8_t cardstate = 0; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* Check if the card command class supports erase command */ - if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0) + if(hsd->State == HAL_SD_STATE_READY) { - errorstate = SD_REQUEST_NOT_APPLICABLE; + hsd->ErrorCode = HAL_DMA_ERROR_NONE; - return errorstate; - } - - /* Get max delay value */ - maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2); - - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; + if(BlockEndAdd < BlockStartAdd) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } - return errorstate; - } - - /* Get start and end block for high capacity cards */ - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - startaddr /= 512; - endaddr /= 512; - } - - /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ - sdmmc_cmdinitstructure.Argument =(uint32_t)startaddr; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); + if(BlockEndAdd > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START); + hsd->State = HAL_SD_STATE_BUSY; - if (errorstate != SD_OK) + /* Check if the card command class supports erase command */ + if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U) { - return errorstate; + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } - /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ - sdmmc_cmdinitstructure.Argument = (uint32_t)endaddr; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END); + if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } - if (errorstate != SD_OK) + /* Get start and end block for high capacity cards */ + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - return errorstate; + BlockStartAdd *= 512U; + BlockEndAdd *= 512U; } + + /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ + errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ + errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + } + + /* Send CMD38 ERASE */ + errorstate = SDMMC_CmdErase(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; } - - /* Send CMD38 ERASE */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_ERASE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE); - - if (errorstate != SD_OK) - { - return errorstate; - } - - for (; delay < maxdelay; delay++) - { - } - - /* Wait until the card is in programming state */ - errorstate = SD_IsCardProgramming(hsd, &cardstate); - - delay = SD_DATATIMEOUT; - - while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) + else { - errorstate = SD_IsCardProgramming(hsd, &cardstate); - delay--; + return HAL_BUSY; } - - return errorstate; } /** * @brief This function handles SD card interrupt request. - * @param hsd: SD handle + * @param hsd: Pointer to SD handle * @retval None */ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) -{ +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; + /* Check for SDMMC interrupt flags */ - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DATAEND)) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET) { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_IT_DATAEND); - - /* SD transfer is complete */ - hsd->SdTransferCplt = 1; - - /* No transfer error */ - hsd->SdTransferErr = SD_OK; - - HAL_SD_XferCpltCallback(hsd); - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - - hsd->SdTransferErr = SD_DATA_CRC_FAIL; + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); - HAL_SD_XferErrorCallback(hsd); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + if((hsd->Context & SD_CONTEXT_IT) != RESET) + { + if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; + HAL_SD_ErrorCallback(hsd); + } + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) + { + HAL_SD_RxCpltCallback(hsd); + } + else + { + HAL_SD_TxCpltCallback(hsd); + } + } + else if((hsd->Context & SD_CONTEXT_DMA) != RESET) + { + if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; + HAL_SD_ErrorCallback(hsd); + } + } + if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET)) + { + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the SD DCTRL register */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + hsd->State = HAL_SD_STATE_READY; + + HAL_SD_TxCpltCallback(hsd); + } + } } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT)) + + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET) { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - hsd->SdTransferErr = SD_DATA_TIMEOUT; + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_TXFIFOHE); - HAL_SD_XferErrorCallback(hsd); + SD_Write_IT(hsd); } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_RXOVERR)) + + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET) { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - - hsd->SdTransferErr = SD_RX_OVERRUN; + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXFIFOHF); - HAL_SD_XferErrorCallback(hsd); + SD_Read_IT(hsd); } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_TXUNDERR)) + + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET) { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR); + /* Set Error code */ + if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + } + if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + } + if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + } + if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + } + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->SdTransferErr = SD_TX_UNDERRUN; + /* Disable all interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - HAL_SD_XferErrorCallback(hsd); + if((hsd->Context & SD_CONTEXT_DMA) != RESET) + { + /* Abort the SD DMA Streams */ + if(hsd->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + { + SD_DMATxAbort(hsd->hdmatx); + } + } + else if(hsd->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + { + SD_DMARxAbort(hsd->hdmarx); + } + } + else + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_READY; + HAL_SD_AbortCallback(hsd); + } + } + else if((hsd->Context & SD_CONTEXT_IT) != RESET) + { + /* Set the SD state to ready to be able to start again the process */ + hsd->State = HAL_SD_STATE_READY; + HAL_SD_ErrorCallback(hsd); + } } - else - { - /* No error flag set */ - } - - /* Disable all SDMMC peripheral interrupt sources */ - __HAL_SD_SDMMC_DISABLE_IT(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_DATAEND |\ - SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF | SDMMC_IT_TXUNDERR |\ - SDMMC_IT_RXOVERR); } - /** - * @brief SD end of transfer callback. - * @param hsd: SD handle - * @retval None + * @brief return the SD state + * @param hsd: Pointer to sd handle + * @retval HAL state */ -__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd) +HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_XferCpltCallback could be implemented in the user file - */ + return hsd->State; } /** - * @brief SD Transfer Error callback. - * @param hsd: SD handle - * @retval None - */ -__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd) +* @brief Return the SD error code +* @param hsd : Pointer to a SD_HandleTypeDef structure that contains + * the configuration information. +* @retval SD Error Code +*/ +uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_XferErrorCallback could be implemented in the user file - */ + return hsd->ErrorCode; } /** - * @brief SD Transfer complete Rx callback in non blocking mode. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Tx Transfer completed callbacks + * @param hsd: Pointer to SD handle * @retval None */ -__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) + __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_RxCpltCallback could be implemented in the user file - */ -} + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_TxCpltCallback can be implemented in the user file + */ +} /** - * @brief SD DMA transfer complete Rx error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Rx Transfer completed callbacks + * @param hsd: Pointer SD handle * @retval None */ -__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) +__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); + UNUSED(hsd); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_RxErrorCallback could be implemented in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_RxCpltCallback can be implemented in the user file + */ } /** - * @brief SD Transfer complete Tx callback in non blocking mode. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief SD error callbacks + * @param hsd: Pointer SD handle * @retval None */ -__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) +__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); + UNUSED(hsd); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_TxCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_ErrorCallback can be implemented in the user file */ -} +} /** - * @brief SD DMA transfer complete error Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief SD Abort callbacks + * @param hsd: Pointer SD handle * @retval None */ -__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) +__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_TxErrorCallback could be implemented in the user file + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_ErrorCallback can be implemented in the user file */ } + /** * @} */ @@ -1477,1916 +1607,1294 @@ __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) ============================================================================== [..] This subsection provides a set of functions allowing to control the SD card - operations. + operations and get the related information @endverbatim * @{ */ /** - * @brief Returns information about specific card. - * @param hsd: SD handle - * @param pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that - * contains all SD cardinformation - * @retval SD Card error state + * @brief Returns information the information of the card which are stored on + * the CID register. + * @param hsd: Pointer to SD handle + * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that + * contains all CID register parameters + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo) +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { - HAL_SD_ErrorTypedef errorstate = SD_OK; uint32_t tmp = 0; - pCardInfo->CardType = (uint8_t)(hsd->CardType); - pCardInfo->RCA = (uint16_t)(hsd->RCA); + /* Byte 0 */ + tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24); + pCID->ManufacturerID = tmp; + + /* Byte 1 */ + tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16); + pCID->OEM_AppliID = tmp << 8; + + /* Byte 2 */ + tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8); + pCID->OEM_AppliID |= tmp; + + /* Byte 3 */ + tmp = (uint8_t)(hsd->CID[0] & 0x000000FF); + pCID->ProdName1 = tmp << 24; + + /* Byte 4 */ + tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24); + pCID->ProdName1 |= tmp << 16; + + /* Byte 5 */ + tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16); + pCID->ProdName1 |= tmp << 8; + + /* Byte 6 */ + tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8); + pCID->ProdName1 |= tmp; + + /* Byte 7 */ + tmp = (uint8_t)(hsd->CID[1] & 0x000000FF); + pCID->ProdName2 = tmp; + + /* Byte 8 */ + tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24); + pCID->ProdRev = tmp; + + /* Byte 9 */ + tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16); + pCID->ProdSN = tmp << 24; + + /* Byte 10 */ + tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8); + pCID->ProdSN |= tmp << 16; + + /* Byte 11 */ + tmp = (uint8_t)(hsd->CID[2] & 0x000000FF); + pCID->ProdSN |= tmp << 8; + + /* Byte 12 */ + tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24); + pCID->ProdSN |= tmp; + + /* Byte 13 */ + tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16); + pCID->Reserved1 |= (tmp & 0xF0) >> 4; + pCID->ManufactDate = (tmp & 0x0F) << 8; + + /* Byte 14 */ + tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8); + pCID->ManufactDate |= tmp; + + /* Byte 15 */ + tmp = (uint8_t)(hsd->CID[3] & 0x000000FF); + pCID->CID_CRC = (tmp & 0xFE) >> 1; + pCID->Reserved2 = 1; + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the CSD register. + * @param hsd: Pointer to SD handle + * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that + * contains all CSD register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) +{ + uint32_t tmp = 0; /* Byte 0 */ tmp = (hsd->CSD[0] & 0xFF000000U) >> 24; - pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); - pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); - pCardInfo->SD_csd.Reserved1 = tmp & 0x03; + pCSD->CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); + pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); + pCSD->Reserved1 = tmp & 0x03; /* Byte 1 */ tmp = (hsd->CSD[0] & 0x00FF0000) >> 16; - pCardInfo->SD_csd.TAAC = (uint8_t)tmp; + pCSD->TAAC = (uint8_t)tmp; /* Byte 2 */ tmp = (hsd->CSD[0] & 0x0000FF00) >> 8; - pCardInfo->SD_csd.NSAC = (uint8_t)tmp; + pCSD->NSAC = (uint8_t)tmp; /* Byte 3 */ tmp = hsd->CSD[0] & 0x000000FF; - pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp; + pCSD->MaxBusClkFrec = (uint8_t)tmp; /* Byte 4 */ tmp = (hsd->CSD[1] & 0xFF000000U) >> 24; - pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4); + pCSD->CardComdClasses = (uint16_t)(tmp << 4); /* Byte 5 */ tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16; - pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); - pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F); + pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); + pCSD->RdBlockLen = (uint8_t)(tmp & 0x0F); /* Byte 6 */ tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8; - pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); - pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); - pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); - pCardInfo->SD_csd.DSRImpl = (uint8_t)((tmp & 0x10) >> 4); - pCardInfo->SD_csd.Reserved2 = 0; /*!< Reserved */ - - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0)) + pCSD->PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); + pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); + pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); + pCSD->DSRImpl = (uint8_t)((tmp & 0x10) >> 4); + pCSD->Reserved2 = 0; /*!< Reserved */ + + if(hsd->SdCard.CardType == CARD_SDSC) { - pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; + pCSD->DeviceSize = (tmp & 0x03) << 10; /* Byte 7 */ tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); - pCardInfo->SD_csd.DeviceSize |= (tmp) << 2; + pCSD->DeviceSize |= (tmp) << 2; /* Byte 8 */ tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); - pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; + pCSD->DeviceSize |= (tmp & 0xC0) >> 6; - pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; - pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); + pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; + pCSD->MaxRdCurrentVDDMax = (tmp & 0x07); /* Byte 9 */ tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); - pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; - pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; - pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; + pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; + pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; + pCSD->DeviceSizeMul = (tmp & 0x03) << 1; /* Byte 10 */ tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); - pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; + pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7; - pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ; - pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2)); - pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen); - pCardInfo->CardCapacity *= pCardInfo->CardBlockSize; + hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1) ; + hsd->SdCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2)); + hsd->SdCard.BlockSize = 1 << (pCSD->RdBlockLen); + + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512); + hsd->SdCard.LogBlockSize = 512; } - else if (hsd->CardType == HIGH_CAPACITY_SD_CARD) + else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) { /* Byte 7 */ tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); - pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; + pCSD->DeviceSize = (tmp & 0x3F) << 16; /* Byte 8 */ tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); - pCardInfo->SD_csd.DeviceSize |= (tmp << 8); + pCSD->DeviceSize |= (tmp << 8); /* Byte 9 */ tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); - pCardInfo->SD_csd.DeviceSize |= (tmp); + pCSD->DeviceSize |= (tmp); /* Byte 10 */ tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); - pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024); - pCardInfo->CardBlockSize = 512; + hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1) * 1024); + hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512; } else { - /* Not supported card type */ - errorstate = SD_ERROR; + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } - - pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; - pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; + + pCSD->EraseGrSize = (tmp & 0x40) >> 6; + pCSD->EraseGrMul = (tmp & 0x3F) << 1; /* Byte 11 */ tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF); - pCardInfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; - pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); + pCSD->EraseGrMul |= (tmp & 0x80) >> 7; + pCSD->WrProtectGrSize = (tmp & 0x7F); /* Byte 12 */ tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24); - pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; - pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; - pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; - pCardInfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; + pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7; + pCSD->ManDeflECC = (tmp & 0x60) >> 5; + pCSD->WrSpeedFact = (tmp & 0x1C) >> 2; + pCSD->MaxWrBlockLen = (tmp & 0x03) << 2; /* Byte 13 */ tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16); - pCardInfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; - pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; - pCardInfo->SD_csd.Reserved3 = 0; - pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01); + pCSD->MaxWrBlockLen |= (tmp & 0xC0) >> 6; + pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5; + pCSD->Reserved3 = 0; + pCSD->ContentProtectAppli = (tmp & 0x01); /* Byte 14 */ tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8); - pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; - pCardInfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6; - pCardInfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5; - pCardInfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4; - pCardInfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2; - pCardInfo->SD_csd.ECC = (tmp & 0x03); + pCSD->FileFormatGrouop = (tmp & 0x80) >> 7; + pCSD->CopyFlag = (tmp & 0x40) >> 6; + pCSD->PermWrProtect = (tmp & 0x20) >> 5; + pCSD->TempWrProtect = (tmp & 0x10) >> 4; + pCSD->FileFormat = (tmp & 0x0C) >> 2; + pCSD->ECC = (tmp & 0x03); /* Byte 15 */ tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF); - pCardInfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1; - pCardInfo->SD_csd.Reserved4 = 1; - - /* Byte 0 */ - tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24); - pCardInfo->SD_cid.ManufacturerID = tmp; - - /* Byte 1 */ - tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.OEM_AppliID = tmp << 8; - - /* Byte 2 */ - tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8); - pCardInfo->SD_cid.OEM_AppliID |= tmp; - - /* Byte 3 */ - tmp = (uint8_t)(hsd->CID[0] & 0x000000FF); - pCardInfo->SD_cid.ProdName1 = tmp << 24; - - /* Byte 4 */ - tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24); - pCardInfo->SD_cid.ProdName1 |= tmp << 16; - - /* Byte 5 */ - tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.ProdName1 |= tmp << 8; - - /* Byte 6 */ - tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ProdName1 |= tmp; - - /* Byte 7 */ - tmp = (uint8_t)(hsd->CID[1] & 0x000000FF); - pCardInfo->SD_cid.ProdName2 = tmp; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24); - pCardInfo->SD_cid.ProdRev = tmp; - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.ProdSN = tmp << 24; - - /* Byte 10 */ - tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ProdSN |= tmp << 16; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CID[2] & 0x000000FF); - pCardInfo->SD_cid.ProdSN |= tmp << 8; - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24); - pCardInfo->SD_cid.ProdSN |= tmp; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; - pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8; + pCSD->CSD_CRC = (tmp & 0xFE) >> 1; + pCSD->Reserved4 = 1; - /* Byte 14 */ - tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ManufactDate |= tmp; - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CID[3] & 0x000000FF); - pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; - pCardInfo->SD_cid.Reserved2 = 1; - - return errorstate; + return HAL_OK; } /** - * @brief Enables wide bus operation for the requested card if supported by - * card. - * @param hsd: SD handle - * @param WideMode: Specifies the SD card wide bus mode - * This parameter can be one of the following values: - * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer (Only for MMC) - * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer - * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer - * @retval SD Card error state + * @brief Gets the SD status info. + * @param hsd: Pointer to SD handle + * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that + * will contain the SD card status information + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode) +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDMMC_InitTypeDef tmpinit; + uint32_t tmp = 0; + uint32_t sd_status[16]; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* MMC Card does not support this feature */ - if (hsd->CardType == MULTIMEDIA_CARD) + errorstate = SD_SendSDStatus(hsd, sd_status); + if(errorstate != HAL_OK) { - errorstate = SD_UNSUPPORTED_FEATURE; - - return errorstate; + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } - else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) + else { - if (WideMode == SDMMC_BUS_WIDE_8B) - { - errorstate = SD_UNSUPPORTED_FEATURE; - } - else if (WideMode == SDMMC_BUS_WIDE_4B) - { - errorstate = SD_WideBus_Enable(hsd); - } - else if (WideMode == SDMMC_BUS_WIDE_1B) - { - errorstate = SD_WideBus_Disable(hsd); - } - else - { - /* WideMode is not a valid argument*/ - errorstate = SD_INVALID_PARAMETER; - } - - if (errorstate == SD_OK) - { - /* Configure the SDMMC peripheral */ - tmpinit.ClockEdge = hsd->Init.ClockEdge; - tmpinit.ClockBypass = hsd->Init.ClockBypass; - tmpinit.ClockPowerSave = hsd->Init.ClockPowerSave; - tmpinit.BusWide = WideMode; - tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl; - tmpinit.ClockDiv = hsd->Init.ClockDiv; - SDMMC_Init(hsd->Instance, tmpinit); - } - } - - return errorstate; -} - -/** - * @brief Aborts an ongoing data transfer. - * @param hsd: SD handle - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Send CMD12 STOP_TRANSMISSION */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_STOP_TRANSMISSION; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION); - - return errorstate; -} - -/** - * @brief Switches the SD card to High Speed mode. - * This API must be used after "Transfer State" - * @note This operation should be followed by the configuration - * of PLL to have SDMMCCK clock between 67 and 75 MHz - * @param hsd: SD handle - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - - uint8_t SD_hs[64] = {0}; - uint32_t SD_scr[2] = {0, 0}; - uint32_t SD_SPEC = 0 ; - uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs; - - /* Initialize the Data control register */ - hsd->Instance->DCTRL = 0; - - /* Get SCR Register */ - errorstate = SD_FindSCR(hsd, SD_scr); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Test the Version supported by the card*/ - SD_SPEC = (SD_scr[1] & 0x01000000) | (SD_scr[1] & 0x02000000); - - if (SD_SPEC != SD_ALLZERO) - { - /* Set Block Size for Card */ - sdmmc_cmdinitstructure.Argument = (uint32_t)64; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); + /* Byte 0 */ + tmp = (sd_status[0] & 0xC0) >> 6; + pStatus->DataBusWidth = (uint8_t)tmp; - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + /* Byte 0 */ + tmp = (sd_status[0] & 0x20) >> 5; + pStatus->SecuredMode = (uint8_t)tmp; - if (errorstate != SD_OK) - { - return errorstate; - } + /* Byte 2 */ + tmp = (sd_status[0] & 0x00FF0000U) >> 16; + pStatus->CardType = (uint16_t)(tmp << 8); - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = 64; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); + /* Byte 3 */ + tmp = (sd_status[0] & 0xFF000000U) >> 24; + pStatus->CardType |= (uint16_t)tmp; - /* Send CMD6 switch mode */ - sdmmc_cmdinitstructure.Argument = 0x80FFFF01U; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); + /* Byte 4 */ + tmp = (sd_status[1] & 0xFF); + pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24); - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH); + /* Byte 5 */ + tmp = (sd_status[1] & 0xFF00) >> 8; + pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16); - if (errorstate != SD_OK) - { - return errorstate; - } - - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) - { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) - { - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); - } - - tempbuff += 8; - } - } + /* Byte 6 */ + tmp = (sd_status[1] & 0xFF0000) >> 16; + pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8); - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; - - return errorstate; - } - else - { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - - while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0)) - { - *tempbuff = SDMMC_ReadFIFO(hsd->Instance); - tempbuff++; - count--; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* Test if the switch mode HS is ok */ - if ((SD_hs[13]& 2) != 2) - { - errorstate = SD_UNSUPPORTED_FEATURE; - } - } - - return errorstate; -} - -/** - * @} - */ - -/** @addtogroup SD_Exported_Functions_Group4 - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in runtime the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the current SD card's status. - * @param hsd: SD handle - * @param pSDstatus: Pointer to the buffer that will contain the SD card status - * SD Status register) - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t count = 0; - - /* Check SD response */ - if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; + /* Byte 7 */ + tmp = (sd_status[1] & 0xFF000000U) >> 24; + pStatus->ProtectedAreaSize |= (uint32_t)tmp; - return errorstate; - } - - /* Set block size for card if it is not equal to current block size for card */ - sdmmc_cmdinitstructure.Argument = 64; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD55 */ - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = 64; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STATUS; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Get status data */ - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) - { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) - { - for (count = 0; count < 8; count++) - { - *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance); - } - - pSDstatus += 8; - } - } - - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); + /* Byte 8 */ + tmp = (sd_status[2] & 0xFF); + pStatus->SpeedClass = (uint8_t)tmp; - errorstate = SD_DATA_TIMEOUT; + /* Byte 9 */ + tmp = (sd_status[2] & 0xFF00) >> 8; + pStatus->PerformanceMove = (uint8_t)tmp; - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + /* Byte 10 */ + tmp = (sd_status[2] & 0xF00000) >> 20; + pStatus->AllocationUnitSize = (uint8_t)tmp; - errorstate = SD_DATA_CRC_FAIL; + /* Byte 11 */ + tmp = (sd_status[2] & 0xFF000000U) >> 24; + pStatus->EraseSize = (uint16_t)(tmp << 8); - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + /* Byte 12 */ + tmp = (sd_status[3] & 0xFF); + pStatus->EraseSize |= (uint16_t)tmp; - errorstate = SD_RX_OVERRUN; + /* Byte 13 */ + tmp = (sd_status[3] & 0xFC00) >> 10; + pStatus->EraseTimeout = (uint8_t)tmp; - return errorstate; - } - else - { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0)) - { - *pSDstatus = SDMMC_ReadFIFO(hsd->Instance); - pSDstatus++; - count--; + /* Byte 13 */ + tmp = (sd_status[3] & 0x0300) >> 8; + pStatus->EraseOffset = (uint8_t)tmp; } - /* Clear all the static status flags*/ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Gets the current sd card data status. - * @param hsd: SD handle - * @retval Data Transfer state - */ -HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd) -{ - HAL_SD_CardStateTypedef cardstate = SD_CARD_TRANSFER; - - /* Get SD card state */ - cardstate = SD_GetState(hsd); - - /* Find SD status according to card state*/ - if (cardstate == SD_CARD_TRANSFER) - { - return SD_TRANSFER_OK; - } - else if(cardstate == SD_CARD_ERROR) - { - return SD_TRANSFER_ERROR; - } - else - { - return SD_TRANSFER_BUSY; - } + return HAL_OK; } /** - * @brief Gets the SD card status. - * @param hsd: SD handle - * @param pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that + * @brief Gets the SD card info. + * @param hsd: Pointer to SD handle + * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that * will contain the SD card status information - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t tmp = 0; - uint32_t sd_status[16]; - - errorstate = HAL_SD_SendSDStatus(hsd, sd_status); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Byte 0 */ - tmp = (sd_status[0] & 0xC0) >> 6; - pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp; - - /* Byte 0 */ - tmp = (sd_status[0] & 0x20) >> 5; - pCardStatus->SECURED_MODE = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (sd_status[0] & 0x00FF0000) >> 16; - pCardStatus->SD_CARD_TYPE = (uint16_t)(tmp << 8); - - /* Byte 3 */ - tmp = (sd_status[0] & 0xFF000000) >> 24; - pCardStatus->SD_CARD_TYPE |= (uint16_t)tmp; - - /* Byte 4 */ - tmp = (sd_status[1] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA = (uint32_t)(tmp << 24); - - /* Byte 5 */ - tmp = (sd_status[1] & 0xFF00) >> 8; - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 16); - - /* Byte 6 */ - tmp = (sd_status[1] & 0xFF0000) >> 16; - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 8); - - /* Byte 7 */ - tmp = (sd_status[1] & 0xFF000000) >> 24; - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)tmp; - - /* Byte 8 */ - tmp = (sd_status[2] & 0xFF); - pCardStatus->SPEED_CLASS = (uint8_t)tmp; - - /* Byte 9 */ - tmp = (sd_status[2] & 0xFF00) >> 8; - pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp; - - /* Byte 10 */ - tmp = (sd_status[2] & 0xF00000) >> 20; - pCardStatus->AU_SIZE = (uint8_t)tmp; - - /* Byte 11 */ - tmp = (sd_status[2] & 0xFF000000) >> 24; - pCardStatus->ERASE_SIZE = (uint16_t)(tmp << 8); - - /* Byte 12 */ - tmp = (sd_status[3] & 0xFF); - pCardStatus->ERASE_SIZE |= (uint16_t)tmp; - - /* Byte 13 */ - tmp = (sd_status[3] & 0xFC00) >> 10; - pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp; - - /* Byte 13 */ - tmp = (sd_status[3] & 0x0300) >> 8; - pCardStatus->ERASE_OFFSET = (uint8_t)tmp; - - return errorstate; -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private function ----------------------------------------------------------*/ -/** @addtogroup SD_Private_Functions - * @{ - */ - -/** - * @brief SD DMA transfer complete Rx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* DMA transfer is complete */ - hsd->DmaTransferCplt = 1; - - /* Wait until SD transfer is complete */ - while(hsd->SdTransferCplt == 0) - { - } - - /* Disable the DMA channel */ - HAL_DMA_Abort(hdma); - - /* Transfer complete user callback */ - HAL_SD_DMA_RxCpltCallback(hsd->hdmarx); -} - -/** - * @brief SD DMA transfer Error Rx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_RxError(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Transfer complete user callback */ - HAL_SD_DMA_RxErrorCallback(hsd->hdmarx); -} - -/** - * @brief SD DMA transfer complete Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* DMA transfer is complete */ - hsd->DmaTransferCplt = 1; - - /* Wait until SD transfer is complete */ - while(hsd->SdTransferCplt == 0) - { - } - - /* Disable the DMA channel */ - HAL_DMA_Abort(hdma); - - /* Transfer complete user callback */ - HAL_SD_DMA_TxCpltCallback(hsd->hdmatx); -} - -/** - * @brief SD DMA transfer Error Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_TxError(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Transfer complete user callback */ - HAL_SD_DMA_TxErrorCallback(hsd->hdmatx); -} - -/** - * @brief Returns the SD current state. - * @param hsd: SD handle - * @retval SD card current state - */ -static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd) -{ - uint32_t resp1 = 0; - - if (SD_SendStatus(hsd, &resp1) != SD_OK) - { - return SD_CARD_ERROR; - } - else - { - return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F); - } -} - -/** - * @brief Initializes all cards or single card as the case may be Card(s) come - * into standby state. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint16_t sd_rca = 1; - - if(SDMMC_GetPowerState(hsd->Instance) == 0) /* Power off */ - { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; - } - - if(hsd->CardType != SECURE_DIGITAL_IO_CARD) - { - /* Send CMD2 ALL_SEND_CID */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_ALL_SEND_CID; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_LONG; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp2Error(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get Card identification number data */ - hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); - hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); - hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); - } - - if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send CMD3 SET_REL_ADDR with argument 0 */ - /* SD Card publishes its RCA. */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_REL_ADDR; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca); - - if(errorstate != SD_OK) - { - return errorstate; - } - } - - if (hsd->CardType != SECURE_DIGITAL_IO_CARD) - { - /* Get the SD card RCA */ - hsd->RCA = sd_rca; - - /* Send CMD9 SEND_CSD with argument as card's RCA */ - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_CSD; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_LONG; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp2Error(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get Card Specific Data */ - hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); - hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); - hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); - } - - /* All cards are initialized */ - return errorstate; -} - -/** - * @brief Selects od Deselects the corresponding card. - * @param hsd: SD handle - * @param addr: Address of the card to be selected - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Send CMD7 SDMMC_SEL_DESEL_CARD */ - sdmmc_cmdinitstructure.Argument = (uint32_t)addr; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEL_DESEL_CARD; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD); - - return errorstate; -} - -/** - * @brief Enquires cards about their operating voltage and configures clock - * controls and stores SD information that will be needed in future - * in the SD handle. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - __IO HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response = 0, count = 0, validvoltage = 0; - uint32_t sdtype = SD_STD_CAPACITY; - - /* Power ON Sequence -------------------------------------------------------*/ - /* Disable SDMMC Clock */ - __HAL_SD_SDMMC_DISABLE(hsd); - - /* Set Power State to ON */ - SDMMC_PowerState_ON(hsd->Instance); - - /* 1ms: required power up waiting time before starting the SD initialization - sequence */ - HAL_Delay(1); - - /* Enable SDMMC Clock */ - __HAL_SD_SDMMC_ENABLE(hsd); - - /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/ - /* No CMD response required */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_GO_IDLE_STATE; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_NO; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdError(hsd); - - if(errorstate != SD_OK) - { - /* CMD Response Timeout (wait for CMDSENT flag) */ - return errorstate; - } - - /* CMD8: SEND_IF_COND ------------------------------------------------------*/ - /* Send CMD8 to verify SD card interface operating condition */ - /* Argument: - [31:12]: Reserved (shall be set to '0') - - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - - [7:0]: Check Pattern (recommended 0xAA) */ - /* CMD Response: R7 */ - sdmmc_cmdinitstructure.Argument = SD_CHECK_PATTERN; - sdmmc_cmdinitstructure.CmdIndex = SD_SDMMC_SEND_IF_COND; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp7Error(hsd); - - if (errorstate == SD_OK) - { - /* SD Card 2.0 */ - hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; - sdtype = SD_HIGH_CAPACITY; - } - - /* Send CMD55 */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - /* If errorstate is Command Timeout, it is a MMC card */ - /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) - or SD card 1.x */ - if(errorstate == SD_OK) - { - /* SD CARD */ - /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)) - { - - /* SEND CMD55 APP_CMD with RCA as 0 */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD41 */ - sdmmc_cmdinitstructure.Argument = SD_VOLTAGE_WINDOW_SD | sdtype; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_OP_COND; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp3Error(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get command response */ - response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); - - count++; - } - - if(count >= SD_MAX_VOLT_TRIAL) - { - errorstate = SD_INVALID_VOLTRANGE; - - return errorstate; - } - - if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ - { - hsd->CardType = HIGH_CAPACITY_SD_CARD; - } - - } /* else MMC Card */ - - return errorstate; -} - -/** - * @brief Turns the SDMMC output signals off. - * @param hsd: SD handle - * @retval SD Card error state + * @retval HAL status */ -static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd) +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Set Power State to OFF */ - SDMMC_PowerState_OFF(hsd->Instance); + pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); + pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); + pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); + pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); + pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); + pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); + pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); + pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); - return errorstate; + return HAL_OK; } /** - * @brief Returns the current card's status. - * @param hsd: SD handle - * @param pCardStatus: pointer to the buffer that will contain the SD card - * status (Card Status register) - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - if(pCardStatus == NULL) - { - errorstate = SD_INVALID_PARAMETER; - - return errorstate; - } + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hsd: Pointer to SD handle + * @param WideMode: Specifies the SD card wide bus mode + * This parameter can be one of the following values: + * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer + * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer + * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) +{ + SDMMC_InitTypeDef Init; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* Send Status command */ - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); + /* Check the parameters */ + assert_param(IS_SDMMC_BUS_WIDE(WideMode)); - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS); + /* Chnage Satte */ + hsd->State = HAL_SD_STATE_BUSY; - if(errorstate != SD_OK) + if(hsd->SdCard.CardType != CARD_SECURED) { - return errorstate; + if(WideMode == SDMMC_BUS_WIDE_8B) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + else if(WideMode == SDMMC_BUS_WIDE_4B) + { + errorstate = SD_WideBus_Enable(hsd); + + hsd->ErrorCode |= errorstate; + } + else if(WideMode == SDMMC_BUS_WIDE_1B) + { + errorstate = SD_WideBus_Disable(hsd); + + hsd->ErrorCode |= errorstate; + } + else + { + /* WideMode is not a valid argument*/ + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + } + } + else + { + /* MMC Card does not support this feature */ + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; } - /* Get SD card status */ - *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else + { + /* Configure the SDMMC peripheral */ + Init.ClockEdge = hsd->Init.ClockEdge; + Init.ClockBypass = hsd->Init.ClockBypass; + Init.ClockPowerSave = hsd->Init.ClockPowerSave; + Init.BusWide = WideMode; + Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + Init.ClockDiv = hsd->Init.ClockDiv; + SDMMC_Init(hsd->Instance, Init); + } + + /* Change State */ + hsd->State = HAL_SD_STATE_READY; - return errorstate; + return HAL_OK; } + /** - * @brief Checks for error conditions for CMD0. - * @param hsd: SD handle - * @retval SD Card error state + * @brief Gets the current sd card data state. + * @param hsd: pointer to SD handle + * @retval Card state */ -static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd) +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout, tmp; - - timeout = SDMMC_CMD0TIMEOUT; - - tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT); - - while((timeout > 0) && (!tmp)) - { - tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT); - timeout--; - } + HAL_SD_CardStateTypeDef cardstate = HAL_SD_CARD_TRANSFER; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t resp1 = 0; - if(timeout == 0) + errorstate = SD_SendStatus(hsd, &resp1); + if(errorstate != HAL_OK) { - errorstate = SD_CMD_RSP_TIMEOUT; - return errorstate; + hsd->ErrorCode |= errorstate; } + + cardstate = (HAL_SD_CardStateTypeDef)((resp1 >> 9) & 0x0F); - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - return errorstate; + return cardstate; } /** - * @brief Checks for error conditions for R7 response. - * @param hsd: SD handle - * @retval SD Card error state + * @brief Abort the current transfer and disable the SD. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information for SD module. + * @retval HAL status */ -static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd) +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorstate = SD_ERROR; - uint32_t timeout = SDMMC_CMD0TIMEOUT, tmp; - - tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT); + HAL_SD_CardStateTypeDef CardState; - while((!tmp) && (timeout > 0)) - { - tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT); - timeout--; - } + /* DIsable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - if((timeout == 0) || tmp) + if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) { - /* Card is not V2.0 compliant or card does not support the set voltage range */ - errorstate = SD_CMD_RSP_TIMEOUT; + /* Disable the SD DMA request */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - - return errorstate; + /* Abort the SD DMA Tx Stream */ + if(hsd->hdmatx != NULL) + { + HAL_DMA_Abort(hsd->hdmatx); + } + /* Abort the SD DMA Rx Stream */ + if(hsd->hdmarx != NULL) + { + HAL_DMA_Abort(hsd->hdmarx); + } } - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDREND)) + hsd->State = HAL_SD_STATE_READY; + CardState = HAL_SD_GetCardState(hsd); + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { - /* Card is SD V2.0 compliant */ - errorstate = SD_OK; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CMDREND); - - return errorstate; + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); } - - return errorstate; + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + return HAL_ERROR; + } + return HAL_OK; } /** - * @brief Checks for error conditions for R1 response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index - * @retval SD Card error state + * @brief Abort the current transfer and disable the SD (IT mode). + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information for SD module. + * @retval HAL status */ -static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD) +HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response_r1; + HAL_SD_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) - { - } + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - - return errorstate; - } - else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL)) + if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL); + /* Disable the SD DMA request */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - return errorstate; + /* Abort the SD DMA Tx Stream */ + if(hsd->hdmatx != NULL) + { + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + { + hsd->hdmatx = NULL; + } + } + /* Abort the SD DMA Rx Stream */ + if(hsd->hdmarx != NULL) + { + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + { + hsd->hdmarx = NULL; + } + } } - /* Check response received is of desired command */ - if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD) + /* No transfer ongoing on both DMA channels*/ + if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + } + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + HAL_SD_AbortCallback(hsd); + } } - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + return HAL_OK; +} + +/** + * @} + */ - /* We have received response, retrieve it for analysis */ - response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); +/** + * @} + */ - if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return errorstate; - } +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief DMA SD transmit process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } + /* Enable DATAEND Interrupt */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DATAEND)); +} + +/** + * @brief DMA SD receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + uint32_t errorstate = HAL_SD_ERROR_NONE; - if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) + /* Send stop command in multiblock write */ + if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA)) { - return(SD_ADDR_MISALIGNED); + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; + HAL_SD_ErrorCallback(hsd); + } } - if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the SD DCTRL register */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } + hsd->State = HAL_SD_STATE_READY; + + HAL_SD_RxCpltCallback(hsd); +} + +/** + * @brief DMA SD communication error callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMAError(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; - if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) + if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE)) { - return(SD_WRITE_PROT_VIOLATION); + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + + /* Disable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + CardState = HAL_SD_GetCardState(hsd); + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + } + + hsd->State= HAL_SD_STATE_READY; } + + HAL_SD_ErrorCallback(hsd); +} + +/** + * @brief DMA SD Tx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; - if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) + if(hsd->hdmatx != NULL) { - return(SD_LOCK_UNLOCK_FAILED); + hsd->hdmatx = NULL; } - if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) + /* All DMA channels are aborted */ + if(hsd->hdmarx == NULL) { - return(SD_COM_CRC_FAILED); + CardState = HAL_SD_GetCardState(hsd); + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_READY; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + HAL_SD_AbortCallback(hsd); + } + else + { + HAL_SD_ErrorCallback(hsd); + } + } } +} + +/** + * @brief DMA SD Rx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; - if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) + if(hsd->hdmarx != NULL) { - return(SD_ILLEGAL_CMD); + hsd->hdmarx = NULL; } - if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) + /* All DMA channels are aborted */ + if(hsd->hdmatx == NULL) { - return(SD_CARD_ECC_FAILED); + CardState = HAL_SD_GetCardState(hsd); + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_READY; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + HAL_SD_AbortCallback(hsd); + } + else + { + HAL_SD_ErrorCallback(hsd); + } + } } +} + + +/** + * @brief Initializes the sd card. + * @param hsd: Pointer to SD handle + * @retval SD Card error state + */ +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardCSDTypeDef CSD; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint16_t sd_rca = 1; - if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) + /* Check the power State */ + if(SDMMC_GetPowerState(hsd->Instance) == 0) { - return(SD_CC_ERROR); + /* Power off */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) + if(hsd->SdCard.CardType != CARD_SECURED) { - return(SD_GENERAL_UNKNOWN_ERROR); + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card identification number data */ + hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + } } - if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) + if(hsd->SdCard.CardType != CARD_SECURED) { - return(SD_STREAM_READ_UNDERRUN); + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* SD Card publishes its RCA. */ + errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } } - - if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) + if(hsd->SdCard.CardType != CARD_SECURED) { - return(SD_STREAM_WRITE_OVERRUN); + /* Get the SD card RCA */ + hsd->SdCard.RelCardAdd = sd_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card Specific Data */ + hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + } } - if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE) - { - return(SD_CID_CSD_OVERWRITE); - } + /* Get the Card Class */ + hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20); - if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) + /* Get CSD parameters */ + HAL_SD_GetCardCSD(hsd, &CSD); + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16)); + if(errorstate != HAL_SD_ERROR_NONE) { - return(SD_WP_ERASE_SKIP); + return errorstate; } + + /* Configure SDMMC peripheral interface */ + SDMMC_Init(hsd->Instance, hsd->Init); + + /* All cards are initialized */ + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores SD information that will be needed in future + * in the SD handle. + * @param hsd: Pointer to SD handle + * @retval error state + */ +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) +{ + __IO uint32_t count = 0; + uint32_t response = 0, validvoltage = 0; + uint32_t errorstate = HAL_SD_ERROR_NONE; - if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { - return(SD_CARD_ECC_DISABLED); + return errorstate; } - if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) + /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ + errorstate = SDMMC_CmdOperCond(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { - return(SD_ERASE_RESET); + hsd->SdCard.CardVersion = CARD_V1_X; + + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while(validvoltage == 0) + { + if(count++ == SDMMC_MAX_VOLT_TRIAL) + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31) == 1) ? 1 : 0); + } + /* Card type is SDSC */ + hsd->SdCard.CardType = CARD_SDSC; } - - if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) + else { - return(SD_AKE_SEQ_ERROR); + hsd->SdCard.CardVersion = CARD_V2_X; + + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while(validvoltage == 0) + { + if(count++ == SDMMC_MAX_VOLT_TRIAL) + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Get command response */ + response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31) == 1) ? 1 : 0); + } + + if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + { + hsd->SdCard.CardType = CARD_SDHC_SDXC; + } + else + { + hsd->SdCard.CardType = CARD_SDSC; + } } - return errorstate; + return HAL_SD_ERROR_NONE; } /** - * @brief Checks for error conditions for R3 (OCR) response. - * @param hsd: SD handle - * @retval SD Card error state + * @brief Turns the SDMMC output signals off. + * @param hsd: Pointer to SD handle + * @retval HAL status */ -static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd) +static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - - while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) - { - } - - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + /* Set Power State to OFF */ + SDMMC_PowerState_OFF(hsd->Instance); - return errorstate; + return HAL_OK; } /** - * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param hsd: SD handle - * @retval SD Card error state + * @brief Send Status info command. + * @param hsd: pointer to SD handle + * @param pSDstatus: Pointer to the buffer that will contain the SD card status + * SD Status register) + * @retval error state */ -static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd) +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { - HAL_SD_ErrorTypedef errorstate = SD_OK; + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); + uint32_t count = 0; - while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) + /* Check SD response */ + if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } - - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT)) + + /* Set block size for card if it is not equal to current block size for card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + if(errorstate != HAL_SD_ERROR_NONE) { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - + hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL)) + + /* Send CMD55 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); + if(errorstate != HAL_SD_ERROR_NONE) { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL); - + hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; } - else - { - /* No error flag set */ - } - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Checks for error conditions for R6 (RCA) response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index - * @param pRCA: Pointer to the variable that will contain the SD card relative - * address RCA - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response_r1; + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 64; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hsd->Instance, &config); - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) + /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ + errorstate = SDMMC_CmdStatusRegister(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { + hsd->ErrorCode |= HAL_SD_ERROR_NONE; + return errorstate; } - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT)) + /* Get status data */ + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + { + for(count = 0; count < 8; count++) + { + *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance); + } + + pSDstatus += 8; + } - return errorstate; + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } } - else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL)) + + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL); - - return errorstate; + return HAL_SD_ERROR_DATA_TIMEOUT; } - else + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) { - /* No error flag set */ - } - - /* Check response received is of desired command */ - if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD) + return HAL_SD_ERROR_DATA_CRC_FAIL; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; + return HAL_SD_ERROR_RX_OVERRUN; } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* We have received response, retrieve it. */ - response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO) + + while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) { - *pRCA = (uint16_t) (response_r1 >> 16); + *pSDstatus = SDMMC_ReadFIFO(hsd->Instance); + pSDstatus++; - return errorstate; + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } } - if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } + /* Clear all the static status flags*/ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Returns the current card's status. + * @param hsd: Pointer to SD handle + * @param pCardStatus: pointer to the buffer that will contain the SD card + * status (Card Status register) + * @retval error state + */ +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; - if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD) + if(pCardStatus == NULL) { - return(SD_ILLEGAL_CMD); + return HAL_SD_ERROR_PARAM; } - if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED) + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); + if(errorstate != HAL_OK) { - return(SD_COM_CRC_FAILED); + return errorstate; } - return errorstate; + /* Get SD card status */ + *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + + return HAL_SD_ERROR_NONE; } /** * @brief Enables the SDMMC wide bus mode. - * @param hsd: SD handle - * @retval SD Card error state + * @param hsd: pointer to SD handle + * @retval error state */ -static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd) +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t scr[2] = {0, 0}; + uint32_t errorstate = HAL_SD_ERROR_NONE; - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) + if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - - if(errorstate != SD_OK) + if(errorstate != HAL_OK) { return errorstate; } /* If requested card supports wide bus operation */ - if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) + if((scr[1] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA.*/ - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); + if(errorstate != HAL_OK) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - sdmmc_cmdinitstructure.Argument = 2; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2); + if(errorstate != HAL_OK) { return errorstate; } - - return errorstate; + + return HAL_SD_ERROR_NONE; } else { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } -} +} /** * @brief Disables the SDMMC wide bus mode. - * @param hsd: SD handle - * @retval SD Card error state + * @param hsd: Pointer to SD handle + * @retval error state */ -static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd) +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) { - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t scr[2] = {0, 0}; + uint32_t errorstate = HAL_SD_ERROR_NONE; - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) + if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - - if(errorstate != SD_OK) + if(errorstate != HAL_OK) { return errorstate; } /* If requested card supports 1 bit mode operation */ - if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) + if((scr[1] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA */ - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); + if(errorstate != HAL_OK) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0); + if(errorstate != HAL_OK) { return errorstate; } - return errorstate; + return HAL_SD_ERROR_NONE; } else { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } } /** * @brief Finds the SD card SCR register value. - * @param hsd: SD handle + * @param hsd: Pointer to SD handle * @param pSCR: pointer to the buffer that will contain the SCR value - * @retval SD Card error state + * @retval error state */ -static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); uint32_t index = 0; uint32_t tempscr[2] = {0, 0}; /* Set Block Size To 8 Bytes */ - /* Send CMD55 APP_CMD with argument as card's RCA */ - sdmmc_cmdinitstructure.Argument = (uint32_t)8; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8); + if(errorstate != HAL_OK) { return errorstate; } - + /* Send CMD55 APP_CMD with argument as card's RCA */ - sdmmc_cmdinitstructure.Argument = (uint32_t)((hsd->RCA) << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16)); + if(errorstate != HAL_OK) { return errorstate; } - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = 8; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); + + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 8; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hsd->Instance, &config); /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdSendSCR(hsd->Instance); + if(errorstate != HAL_OK) { return errorstate; } - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) { - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) { *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance); index++; } + + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } } - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - return errorstate; + return HAL_SD_ERROR_DATA_TIMEOUT; } - else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - return errorstate; + return HAL_SD_ERROR_DATA_CRC_FAIL; } - else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - return errorstate; + return HAL_SD_ERROR_RX_OVERRUN; } else { /* No error flag set */ + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + + *(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24); + + *(pSCR) = ((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24); } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) |\ - ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); - - *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) |\ - ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); - - return errorstate; + + return HAL_SD_ERROR_NONE; } /** - * @brief Checks if the SD card is in programming state. - * @param hsd: SD handle - * @param pStatus: pointer to the variable that will contain the SD card state - * @retval SD Card error state + * @brief Wrap up reading in non-blocking mode. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval HAL status */ -static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus) +static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd) { - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - __IO uint32_t responseR1 = 0; - - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) - { - } - - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - - return errorstate; - } - else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL)) - { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL); - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Check response received is of desired command */ - if((uint32_t)SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS) - { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - - /* We have received response, retrieve it for analysis */ - responseR1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - /* Find out card status */ - *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F); - - if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return errorstate; - } - - if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } - - if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) - { - return(SD_ADDR_MISALIGNED); - } - - if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } - - if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } - - if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } - - if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) - { - return(SD_WRITE_PROT_VIOLATION); - } - - if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) - { - return(SD_LOCK_UNLOCK_FAILED); - } - - if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) - { - return(SD_CARD_ECC_FAILED); - } - - if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) - { - return(SD_CC_ERROR); - } - - if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) - { - return(SD_STREAM_READ_UNDERRUN); - } + uint32_t count = 0; + uint32_t* tmp; + + tmp = (uint32_t*)hsd->pRxBuffPtr; - if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) + /* Read data from SDMMC Rx FIFO */ + for(count = 0; count < 8; count++) { - return(SD_STREAM_WRITE_OVERRUN); + *(tmp + count) = SDMMC_ReadFIFO(hsd->Instance); } - if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE) - { - return(SD_CID_CSD_OVERWRITE); - } + hsd->pRxBuffPtr += 8; - if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) - { - return(SD_WP_ERASE_SKIP); - } + return HAL_OK; +} + +/** + * @brief Wrap up writing in non-blocking mode. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval HAL status + */ +static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd) +{ + uint32_t count = 0; + uint32_t* tmp; - if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) - { - return(SD_CARD_ECC_DISABLED); - } + tmp = (uint32_t*)hsd->pTxBuffPtr; - if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) + /* Write data to SDMMC Tx FIFO */ + for(count = 0; count < 8; count++) { - return(SD_ERASE_RESET); + SDMMC_WriteFIFO(hsd->Instance, (tmp + count)); } - if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) - { - return(SD_AKE_SEQ_ERROR); - } + hsd->pTxBuffPtr += 8; - return errorstate; -} + return HAL_OK; +} /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.h index 17bbc5f961f..fc21d5334f4 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sd.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of SD HAL module. ****************************************************************************** * @attention @@ -60,48 +60,116 @@ * @{ */ -/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition +/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure + * @{ + */ +typedef enum +{ + HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */ + HAL_SD_STATE_READY = ((uint32_t)0x00000001U), /*!< SD initialized and ready for use */ + HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< SD Timeout state */ + HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */ + HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */ + HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receinving State */ + HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */ + HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */ +}HAL_SD_StateTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure + * @{ + */ +typedef enum +{ + HAL_SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */ + HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */ + HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */ + HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */ + HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */ + HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */ + HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */ + HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */ + HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */ +}HAL_SD_CardStateTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition * @{ */ #define SD_InitTypeDef SDMMC_InitTypeDef #define SD_TypeDef SDMMC_TypeDef +/** + * @brief SD Card Information Structure definition + */ typedef struct { - SD_TypeDef *Instance; /*!< SDMMC register base address */ + uint32_t CardType; /*!< Specifies the card Type */ - SD_InitTypeDef Init; /*!< SD required parameters */ + uint32_t CardVersion; /*!< Specifies the card version */ + + uint32_t Class; /*!< Specifies the class of the card class */ + + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ - HAL_LockTypeDef Lock; /*!< SD locking object */ + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ + + uint32_t BlockSize; /*!< Specifies one block size in bytes */ - uint32_t CardType; /*!< SD card type */ + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ + + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + +}HAL_SD_CardInfoTypeDef; + +/** + * @brief SD handle Structure definition + */ +typedef struct +{ + SD_TypeDef *Instance; /*!< SD registers base address */ - uint32_t RCA; /*!< SD relative card address */ + SD_InitTypeDef Init; /*!< SD required parameters */ - uint32_t CSD[4]; /*!< SD card specific data table */ + HAL_LockTypeDef Lock; /*!< SD locking object */ - uint32_t CID[4]; /*!< SD card identification number table */ + uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< SD Tx Transfer size */ + + uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< SD Rx Transfer size */ - __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */ + __IO uint32_t Context; /*!< SD transfer context */ + + __IO HAL_SD_StateTypeDef State; /*!< SD card State */ - __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */ + __IO uint32_t ErrorCode; /*!< SD Card Error codes */ + + DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ - __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */ + DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ - __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */ + HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ - DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ + uint32_t CSD[4]; /*!< SD card specific data table */ - DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ + uint32_t CID[4]; /*!< SD card identification number table */ }SD_HandleTypeDef; + /** * @} */ -/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register +/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register * @{ - */ + */ typedef struct { __IO uint8_t CSDStruct; /*!< CSD structure */ @@ -141,13 +209,13 @@ typedef struct __IO uint8_t ECC; /*!< ECC code */ __IO uint8_t CSD_CRC; /*!< CSD CRC */ __IO uint8_t Reserved4; /*!< Always 1 */ - -}HAL_SD_CSDTypedef; + +}HAL_SD_CardCSDTypeDef; /** * @} */ -/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register +/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register * @{ */ typedef struct @@ -163,266 +231,122 @@ typedef struct __IO uint8_t CID_CRC; /*!< CID CRC */ __IO uint8_t Reserved2; /*!< Always 1 */ -}HAL_SD_CIDTypedef; +}HAL_SD_CardCIDTypeDef; /** * @} */ -/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13 +/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 * @{ */ typedef struct { - __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */ - __IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */ - __IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */ - __IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */ - __IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */ - __IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */ - __IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */ - __IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */ - __IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */ - __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */ - -}HAL_SD_CardStatusTypedef; + __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */ + __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */ + __IO uint16_t CardType; /*!< Carries information about card type */ + __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */ + __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */ + __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */ + __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */ + __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */ + __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */ + __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */ + +}HAL_SD_CardStatusTypeDef; /** * @} */ -/** @defgroup SD_Exported_Types_Group5 SD Card information structure - * @{ - */ -typedef struct -{ - HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */ - HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */ - uint64_t CardCapacity; /*!< Card capacity */ - uint32_t CardBlockSize; /*!< Card block size */ - uint16_t RCA; /*!< SD relative card address */ - uint8_t CardType; /*!< SD card type */ - -}HAL_SD_CardInfoTypedef; /** * @} */ -/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SD_Exported_Constants Exported Constants * @{ */ -typedef enum -{ -/** - * @brief SD specific error defines - */ - SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */ - SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */ - SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */ - SD_DATA_TIMEOUT = (4), /*!< Data timeout */ - SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */ - SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */ - SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */ - SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */ - SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */ - SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ - SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */ - SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */ - SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */ - SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ - SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */ - SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */ - SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */ - SD_CC_ERROR = (18), /*!< Internal card controller error */ - SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */ - SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */ - SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */ - SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */ - SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */ - SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */ - SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ - SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */ - SD_INVALID_VOLTRANGE = (27), - SD_ADDR_OUT_OF_RANGE = (28), - SD_SWITCH_ERROR = (29), - SD_SDMMC_DISABLED = (30), - SD_SDMMC_FUNCTION_BUSY = (31), - SD_SDMMC_FUNCTION_FAILED = (32), - SD_SDMMC_UNKNOWN_FUNCTION = (33), - -/** - * @brief Standard error defines - */ - SD_INTERNAL_ERROR = (34), - SD_NOT_CONFIGURED = (35), - SD_REQUEST_PENDING = (36), - SD_REQUEST_NOT_APPLICABLE = (37), - SD_INVALID_PARAMETER = (38), - SD_UNSUPPORTED_FEATURE = (39), - SD_UNSUPPORTED_HW = (40), - SD_ERROR = (41), - SD_OK = (0) - -}HAL_SD_ErrorTypedef; -/** - * @} - */ -/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure - * @{ - */ -typedef enum -{ - SD_TRANSFER_OK = 0, /*!< Transfer success */ - SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */ - SD_TRANSFER_ERROR = 2 /*!< Transfer failed */ - -}HAL_SD_TransferStateTypedef; -/** - * @} - */ +#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */ -/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure +/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition * @{ - */ -typedef enum -{ - SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */ - SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */ - SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */ - SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */ - SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */ - SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */ - SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */ - SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */ - SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card is in error state */ - -}HAL_SD_CardStateTypedef; + */ +#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + /** * @} */ - -/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure + +/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration * @{ - */ -typedef enum -{ - SD_READ_SINGLE_BLOCK = 0U, /*!< Read single block operation */ - SD_READ_MULTIPLE_BLOCK = 1U, /*!< Read multiple blocks operation */ - SD_WRITE_SINGLE_BLOCK = 2U, /*!< Write single block operation */ - SD_WRITE_MULTIPLE_BLOCK = 3U /*!< Write multiple blocks operation */ + */ +#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ +#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ +#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ +#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ +#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ +#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ +#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ -}HAL_SD_OperationTypedef; /** * @} */ +/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards + * @{ + */ +#define CARD_SDSC ((uint32_t)0x00000000U) +#define CARD_SDHC_SDXC ((uint32_t)0x00000001U) +#define CARD_SECURED ((uint32_t)0x00000003U) + /** * @} */ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SD_Exported_Constants SD Exported Constants +/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version * @{ */ - -/** - * @brief SD Commands Index - */ -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ -#define SD_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SD_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SD_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ -#define SD_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ -#define SD_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its - operating condition register (OCR) content in the response on the CMD line. */ -#define SD_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information - and asks the card whether card supports voltage. */ -#define SD_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SD_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ -#define SD_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ -#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14U) -#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands - (read, write, lock). Default block length is fixed to 512 Bytes. Not effective - for SDHS and SDXC. */ -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by - STOP_TRANSMISSION command. */ -#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ -#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SD_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ -#define SD_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ -#define SD_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ -#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ -#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ -#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SD_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command - system set by switch function command (CMD6). */ -#define SD_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. - Reserved for each command system set by switch function command (CMD6). */ -#define SD_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ -#define SD_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ -#define SD_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ -#define SD_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by - the SET_BLOCK_LEN command. */ -#define SD_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather - than a standard command. */ -#define SD_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card - for general purpose/application specific commands. */ -#define SD_CMD_NO_CMD ((uint8_t)64U) - -/** - * @brief Following commands are SD Card Specific commands. - * SDMMC_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus - widths are given in SCR register. */ -#define SD_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with - 32bit+CRC data block. */ -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to - send its operating condition register (OCR) content in the response on the CMD line. */ -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */ -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ -#define SD_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ -#define SD_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ - -/** - * @brief Following commands are SD Card Specific security commands. - * SD_CMD_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43U) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_MID ((uint8_t)44U) /*!< For SD card only */ -#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) /*!< For SD card only */ -#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) /*!< For SD card only */ -#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) /*!< For SD card only */ - -/** - * @brief Supported SD Memory Cards +#define CARD_V1_X ((uint32_t)0x00000000U) +#define CARD_V2_X ((uint32_t)0x00000001U) +/** + * @} */ -#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000U) -#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001U) -#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002U) -#define MULTIMEDIA_CARD ((uint32_t)0x00000003U) -#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004U) -#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005U) -#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006U) -#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007U) + /** * @} */ @@ -437,25 +361,25 @@ typedef enum * @brief Enable the SD device. * @retval None */ -#define __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance) +#define __HAL_SD_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance) /** * @brief Disable the SD device. * @retval None */ -#define __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance) +#define __HAL_SD_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance) /** * @brief Enable the SDMMC DMA transfer. * @retval None */ -#define __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance) +#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance) /** * @brief Disable the SDMMC DMA transfer. * @retval None */ -#define __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) +#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) /** * @brief Enable the SD device interrupt. @@ -486,7 +410,7 @@ typedef enum * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt * @retval None */ -#define __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) +#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** * @brief Disable the SD device interrupt. @@ -517,7 +441,7 @@ typedef enum * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt * @retval None */ -#define __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) +#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** * @brief Check whether the specified SD flag is set or not. @@ -548,7 +472,7 @@ typedef enum * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received * @retval The new state of SD FLAG (SET or RESET). */ -#define __HAL_SD_SDMMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) +#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) /** * @brief Clear the SD's pending flags. @@ -568,7 +492,7 @@ typedef enum * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received * @retval None */ -#define __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) +#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) /** * @brief Check whether the specified SD interrupt has occurred or not. @@ -599,7 +523,7 @@ typedef enum * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt * @retval The new state of SD IT (SET or RESET). */ -#define __HAL_SD_SDMMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) +#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** * @brief Clear the SD's interrupt pending bits. @@ -618,7 +542,8 @@ typedef enum * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt * @retval None */ -#define __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) +#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + /** * @} */ @@ -631,8 +556,9 @@ typedef enum /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ -HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo); -HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); void HAL_SD_MspInit(SD_HandleTypeDef *hsd); void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); /** @@ -643,26 +569,23 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); * @{ */ /* Blocking mode: Polling */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr); +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +/* Non-Blocking mode: IT */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -/* Non-Blocking mode: Interrupt */ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); /* Callback in non blocking modes (DMA) */ -void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd); -void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd); - -/* Non-Blocking mode: DMA */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); -HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); +void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); +void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); /** * @} */ @@ -670,25 +593,38 @@ HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Ti /** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions * @{ */ -HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo); -HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode); -HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd); -HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode); /** * @} */ - -/* Peripheral State functions ************************************************/ -/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions + +/** @defgroup SD_Exported_Functions_Group4 SD card related functions * @{ */ -HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); -HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus); -HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ - + +/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd); +uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management + * @{ + */ +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} */ @@ -756,6 +692,7 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd); * @} */ + /** * @} */ @@ -764,6 +701,11 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd); * @} */ +/** + * @} + */ + + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.c index 44a6c2e5896..8f182b552bf 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sdram.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief SDRAM HAL module driver. * This file provides a generic firmware to drive SDRAM memories mounted * as external device. diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.h index 2d502c8ea02..42c2265c76c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sdram.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of SDRAM HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.c index e7c76b58a32..99d293adc3e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -396,14 +396,14 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. [..] - Smartcard is a single wire half duplex communication protocol. + (#) Smartcard is a single wire half duplex communication protocol. The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. The USART should be configured as: - (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register - (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. + defined in the ISO 7816-3 standard. + (#) The USART should be configured as: + (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register + (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. - [..] - (+) There are two modes of transfer: + (#) There are two modes of transfer: (++) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. @@ -417,47 +417,47 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected. - (+) Blocking mode APIs are : + (#) Blocking mode APIs are : (++) HAL_SMARTCARD_Transmit() (++) HAL_SMARTCARD_Receive() - (+) Non Blocking mode APIs with Interrupt are : + (#) Non Blocking mode APIs with Interrupt are : (++) HAL_SMARTCARD_Transmit_IT() (++) HAL_SMARTCARD_Receive_IT() (++) HAL_SMARTCARD_IRQHandler() - (+) Non Blocking mode functions with DMA are : + (#) Non Blocking mode functions with DMA are : (++) HAL_SMARTCARD_Transmit_DMA() (++) HAL_SMARTCARD_Receive_DMA() - (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_SMARTCARD_TxCpltCallback() (++) HAL_SMARTCARD_RxCpltCallback() (++) HAL_SMARTCARD_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_SMARTCARD_Abort() - (+) HAL_SMARTCARD_AbortTransmit() - (+) HAL_SMARTCARD_AbortReceive() - (+) HAL_SMARTCARD_Abort_IT() - (+) HAL_SMARTCARD_AbortTransmit_IT() - (+) HAL_SMARTCARD_AbortReceive_IT() + (++) HAL_SMARTCARD_Abort() + (++) HAL_SMARTCARD_AbortTransmit() + (++) HAL_SMARTCARD_AbortReceive() + (++) HAL_SMARTCARD_Abort_IT() + (++) HAL_SMARTCARD_AbortTransmit_IT() + (++) HAL_SMARTCARD_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_SMARTCARD_AbortCpltCallback() - (+) HAL_SMARTCARD_AbortTransmitCpltCallback() - (+) HAL_SMARTCARD_AbortReceiveCpltCallback() + (++) HAL_SMARTCARD_AbortCpltCallback() + (++) HAL_SMARTCARD_AbortTransmitCpltCallback() + (++) HAL_SMARTCARD_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -1843,16 +1843,6 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar return HAL_TIMEOUT; } } - /* Check if the Receiver is enabled */ - if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } /* Initialize the SMARTCARD states */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.h index 24eb03b2b62..802c7911e24 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention @@ -687,9 +687,9 @@ typedef struct * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disables the specified SmartCard interrupt. * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. @@ -704,9 +704,9 @@ typedef struct * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Checks whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__: specifies the SMARTCARD Handle. @@ -724,7 +724,7 @@ typedef struct * @arg SMARTCARD_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U))) /** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled. * @param __HANDLE__: specifies the SMARTCARD Handle. @@ -742,7 +742,7 @@ typedef struct * @arg SMARTCARD_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \ +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \ (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) @@ -815,10 +815,10 @@ typedef struct * @{ */ /* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc); -HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc); -void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc); -void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc); +HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); /** * @} */ @@ -857,8 +857,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard * @{ */ /* Peripheral State functions **************************************************/ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc); -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard); +uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.c index d5194936661..5ac86deb030 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief SMARTCARD HAL module driver. * * This file provides extended firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.h index 719771a8954..f7e4105935e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smbus.c new file mode 100644 index 00000000000..64539de0af9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smbus.c @@ -0,0 +1,2053 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_smbus.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief SMBUS HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the System Management Bus (SMBus) peripheral, + * based on I2C principles of operation : + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SMBUS HAL driver can be used as follows: + + (#) Declare a SMBUS_HandleTypeDef handle structure, for example: + SMBUS_HandleTypeDef hsmbus; + + (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: + (##) Enable the SMBUSx interface clock + (##) SMBUS pins configuration + (+++) Enable the clock for the SMBUS GPIOs + (+++) Configure SMBUS pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SMBUSx interrupt priority + (+++) Enable the NVIC SMBUS IRQ Channel + + (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode, + Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, + Peripheral mode and Packet Error Check mode in the hsmbus Init structure. + + (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: + (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. + + (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() + + (#) For SMBUS IO operations, only one mode of operations is available within this driver + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() + (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() + (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() + (++) The associated previous transfer callback is called at the end of abort process + (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive + (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode + using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). + (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() + (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Alert Error Code using function HAL_SMBUS_GetError() + (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() + (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Error Code using function HAL_SMBUS_GetError() + + *** SMBUS HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SMBUS HAL driver. + + (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral + (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral + (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not + (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag + (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt + (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + + [..] + (@) You can refer to the SMBUS HAL driver header file for more useful macros + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUS SMBUS + * @brief SMBUS HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Define SMBUS Private Constants + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */ +#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define MAX_NBYTE_SIZE 255U +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions + * @{ + */ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); + +static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); +static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus); +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); + +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); + +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions + * @{ + */ + +/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the SMBUSx peripheral: + + (+) User must Implement HAL_SMBUS_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, IT and NVIC ). + + (+) Call the function HAL_SMBUS_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Bus Timeout + (++) Analog Filer mode + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + (++) Packet Error Check mode + (++) Peripheral mode + + + (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration + of the selected SMBUSx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SMBUS according to the specified parameters + * in the SMBUS_InitTypeDef and initialize the associated handle. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the SMBUS handle allocation */ + if(hsmbus == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter)); + assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1)); + assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode)); + assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode)); + assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2)); + assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks)); + assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode)); + assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode)); + assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); + assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); + + if(hsmbus->State == HAL_SMBUS_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsmbus->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_SMBUS_MspInit(hsmbus); + } + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ + /* Configure SMBUSx: Frequency range */ + hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ + /* Configure SMBUSx: Bus Timeout */ + hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN; + hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN; + hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout; + + /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/ + /* Configure SMBUSx: Own Address1 and ack own address1 mode */ + hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + if(hsmbus->Init.OwnAddress1 != 0U) + { + if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) + { + hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); + } + else /* SMBUS_ADDRESSINGMODE_10BIT */ + { + hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1); + } + } + + /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ + /* Configure SMBUSx: Addressing Master mode */ + if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) + { + hsmbus->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ + /* AUTOEND and NACK bit will be manage during Transfer process */ + hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ + /* Configure SMBUSx: Dual mode and Own Address2 */ + hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U)); + + /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ + /* Configure SMBUSx: Generalcall and NoStretch mode */ + hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); + + /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ + if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) + && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) ) + { + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + } + + /* Enable the selected SMBUS peripheral */ + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the SMBUS peripheral. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the SMBUS handle allocation */ + if(hsmbus == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the SMBUS Peripheral Clock */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_SMBUS_MspDeInit(hsmbus); + + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; + hsmbus->State = HAL_SMBUS_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} + +/** + * @brief Initialize the SMBUS MSP. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the SMBUS MSP. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SMBUS data + transfers. + + (#) Blocking mode function to check if device is ready for usage is : + (++) HAL_SMBUS_IsDeviceReady() + + (#) There is only one mode of transfer: + (++) Non-Blocking mode : The communication is performed using Interrupts. + These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated SMBUS IRQ when using Interrupt mode. + + (#) Non-Blocking mode functions with Interrupt are : + (++) HAL_SMBUS_Master_Transmit_IT() + (++) HAL_SMBUS_Master_Receive_IT() + (++) HAL_SMBUS_Slave_Transmit_IT() + (++) HAL_SMBUS_Slave_Receive_IT() + (++) HAL_SMBUS_EnableListen_IT() + (++) HAL_SMBUS_DisableListen_IT() + (++) HAL_SMBUS_EnableAlert_IT() + (++) HAL_SMBUS_DisableAlert_IT() + + (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode: + (++) HAL_SMBUS_MasterTxCpltCallback() + (++) HAL_SMBUS_MasterRxCpltCallback() + (++) HAL_SMBUS_SlaveTxCpltCallback() + (++) HAL_SMBUS_SlaveRxCpltCallback() + (++) HAL_SMBUS_AddrCallback() + (++) HAL_SMBUS_ListenCpltCallback() + (++) HAL_SMBUS_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if(hsmbus->pBuffPtr == NULL) + { + hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; + } + + if(Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + { + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + } + else + { + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + { + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + } + + /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if(hsmbus->pBuffPtr == NULL) + { + hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; + } + + if(Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + { + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + } + else + { + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + { + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master/host SMBUS process communication with Interrupt. + * @note This abort can be called only if state is ready + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) +{ + if(hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + /* Keep the same state as previous */ + /* to perform as well the call of the corresponding end of transfer callback */ + if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; + } + else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); + } + else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX); + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set SBC bit to manage Acknowledge at each bit */ + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + + /* Enable Address Acknowledge */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + if(Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + { + SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + } + else + { + /* Set NBYTE to transmit */ + SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX); + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set SBC bit to manage Acknowledge at each bit */ + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + + /* Enable Address Acknowledge */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferSize = Size; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Set NBYTE to receive */ + /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ + /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ + /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ + /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ + if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + { + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + } + else + { + SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) +{ + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + + /* Enable the Address Match interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR); + + return HAL_OK; +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Disable Address listen mode only if a transfer is not ongoing */ + if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + { + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Disable the Address Match interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the SMBUS alert mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Enable SMBus alert */ + hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + + /* Enable Alert Interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT); + + return HAL_OK; +} +/** + * @brief Disable the SMBUS alert mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Enable SMBus alert */ + hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; + + /* Disable Alert Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT); + + return HAL_OK; +} + +/** + * @brief Check if target device is ready for communication. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + __IO uint32_t SMBUS_Trials = 0U; + + if(hsmbus->State == HAL_SMBUS_STATE_READY) + { + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + do + { + /* Generate Start */ + hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + return HAL_TIMEOUT; + } + } + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (SMBUS_Trials++ == Trials) + { + /* Generate Stop */ + hsmbus->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + } + }while(SMBUS_Trials < Trials); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_TIMEOUT; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief Handle SMBUS event interrupt request. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) +{ + uint32_t tmpisrvalue = 0U; + + /* Use a local variable to store the current ISR flags */ + /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ + tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); + + /* SMBUS in mode Transmitter ---------------------------------------------------*/ + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) + { + /* Slave mode selected */ + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + { + SMBUS_Slave_ISR(hsmbus); + } + /* Master mode selected */ + else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + SMBUS_Master_ISR(hsmbus); + } + } + + /* SMBUS in mode Receiver ----------------------------------------------------*/ + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) + { + /* Slave mode selected */ + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + { + SMBUS_Slave_ISR(hsmbus); + } + /* Master mode selected */ + else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Master_ISR(hsmbus); + } + } + + /* SMBUS in mode Listener Only --------------------------------------------------*/ + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) + && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) + { + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + { + SMBUS_Slave_ISR(hsmbus); + } + } +} + +/** + * @brief Handle SMBUS error interrupt request. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) +{ + /* SMBUS Bus error interrupt occurred ------------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); + } + + /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); + } + + /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); + } + + /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; + + /* Clear TIMEOUT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); + } + + /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + } + + /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; + + /* Clear PEC error flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); + } + + /* Call the Error Callback in case of Error detected */ + if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) + { + /* Do not Reset the HAL state in case of ALERT error */ + if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + { + if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) + { + /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ + /* keep HAL_SMBUS_STATE_LISTEN if set */ + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + } + } + + /* Call the Error callback to prevent upper layer */ + HAL_SMBUS_ErrorCallback(hsmbus); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param TransferDirection: Master request Transfer Direction (Write/Read) + * @param AddrMatchCode: Address Match Code + * @retval None + */ +__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief SMBUS error callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_ErrorCallback() could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the SMBUS handle state. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL state + */ +uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) +{ + /* Return SMBUS handle state */ + return hsmbus->State; +} + +/** +* @brief Return the SMBUS error code. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. +* @retval SMBUS Error Code +*/ +uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) +{ + return hsmbus->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions + * @brief Data transfers Private functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) +{ + uint16_t DevAddress; + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Error callback to prevent upper layer */ + HAL_SMBUS_ErrorCallback(hsmbus); + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + SMBUS_RESET_CR2(hsmbus); + + /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* REenable the selected SMBUS peripheral */ + __HAL_SMBUS_ENABLE(hsmbus); + + HAL_SMBUS_MasterTxCpltCallback(hsmbus); + } + else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + /* Store Last receive data if any */ + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + + if((hsmbus->XferSize > 0U)) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + SMBUS_RESET_CR2(hsmbus); + + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + HAL_SMBUS_MasterRxCpltCallback(hsmbus); + } + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + { + /* Write data to TXDR */ + hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) + { + if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + { + DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); + + if(hsmbus->XferCount > MAX_NBYTE_SIZE) + { + SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = hsmbus->XferCount; + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + } + else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U)) + { + /* Call TxCpltCallback() if no stop mode is set */ + if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + HAL_SMBUS_MasterTxCpltCallback(hsmbus); + } + else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + HAL_SMBUS_MasterRxCpltCallback(hsmbus); + } + } + } + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) + { + if(hsmbus->XferCount == 0U) + { + /* Specific use case for Quick command */ + if(hsmbus->pBuffPtr == NULL) + { + /* Generate a Stop command */ + hsmbus->Instance->CR2 |= I2C_CR2_STOP; + } + /* Call TxCpltCallback() if no stop mode is set */ + else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + { + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + HAL_SMBUS_MasterTxCpltCallback(hsmbus); + } + else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + HAL_SMBUS_MasterRxCpltCallback(hsmbus); + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) +{ + uint8_t TransferDirection = 0U; + uint16_t SlaveAddrCode = 0U; + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + { + /* Check that SMBUS transfer finished */ + /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if(hsmbus->XferCount == 0U) + { + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + } + else + { + /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/ + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Set HAL State to "Idle" State, mean to LISTEN state */ + /* So reset Slave Busy state */ + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); + + /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Error callback to prevent upper layer */ + HAL_SMBUS_ErrorCallback(hsmbus); + } + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) + { + TransferDirection = SMBUS_GET_DIR(hsmbus); + SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus); + + /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ + /* Other ADDRInterrupt will be treat in next Listen usecase */ + __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call Slave Addr callback */ + HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); + } + else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) + { + if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + { + /* Read data from RXDR */ + (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + hsmbus->XferSize--; + hsmbus->XferCount--; + + if(hsmbus->XferCount == 1U) + { + /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ + /* or only the last Byte of Transfer */ + /* So reset the RELOAD bit mode */ + hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; + SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + } + else if(hsmbus->XferCount == 0U) + { + /* Last Byte is received, disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Rx complete callback to inform upper layer of the end of receive process */ + HAL_SMBUS_SlaveRxCpltCallback(hsmbus); + } + else + { + /* Set Reload for next Bytes */ + SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + + /* Ack last Byte Read */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + } + } + else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + { + if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + { + if(hsmbus->XferCount > MAX_NBYTE_SIZE) + { + SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = hsmbus->XferCount; + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + } + } + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if(hsmbus->XferCount > 0U) + { + /* Write data to TXDR */ + hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); + hsmbus->XferCount--; + hsmbus->XferSize--; + } + + if(hsmbus->XferCount == 0U) + { + /* Last Byte is Transmitted */ + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Tx complete callback to inform upper layer of the end of transmit process */ + HAL_SMBUS_SlaveTxCpltCallback(hsmbus); + } + } + + /* Check if STOPF is set */ + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + { + if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + { + /* Store Last receive data if any */ + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + + if((hsmbus->XferSize > 0U)) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Disable RX and TX Interrupts */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); + + /* Disable ADDR Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); + + /* Disable Address Acknowledge */ + hsmbus->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + SMBUS_RESET_CR2(hsmbus); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear ADDR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + + hsmbus->XferOptions = 0U; + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */ + HAL_SMBUS_ListenCpltCallback(hsmbus); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} +/** + * @brief Manage the enabling of Interrupts. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) + { + /* Enable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + { + /* Enable ADDR, STOP interrupt */ + tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; + } + + if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + { + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; + } + + if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + { + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of SMBUS interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); + + return HAL_OK; +} +/** + * @brief Manage the disabling of Interrupts. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) ) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + { + /* Disable TC, STOP, NACK, TXI interrupt */ + tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; + + if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + { + /* Disable STOPI, NACKI */ + tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; + } + } + + if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + { + /* Disable TC, STOP, NACK, RXI interrupt */ + tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; + + if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + { + /* Disable STOPI, NACKI */ + tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; + } + } + + if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + { + /* Enable ADDR, STOP interrupt */ + tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; + + if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); + + return HAL_OK; +} +/** + * @brief Handle SMBUS Communication Timeout. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param Flag Specifies the SMBUS flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hsmbus->PreviousState = hsmbus->State; + hsmbus->State= HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hsmbus->PreviousState = hsmbus->State; + hsmbus->State= HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hsmbus SMBUS handle. + * @param DevAddress specifies the slave address to be programmed. + * @param Size specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the SMBUS START condition generation. + * This parameter can be one or a combination of the following values: + * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode. + * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode. + * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode. + * @param Request New state of the SMBUS START condition generation. + * This parameter can be one of the following values: + * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request. + * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +{ + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); + assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); + + /* Get the CR2 register value */ + tmpreg = hsmbus->Instance->CR2; + + /* clear tmpreg specific bits */ + tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); + + /* update tmpreg */ + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request); + + /* update CR2 register */ + hsmbus->Instance->CR2 = tmpreg; +} + +/** + * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) +{ + /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME */ + if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME; + } + /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */ + else if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */ + else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */ + else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; + } +} +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smbus.h new file mode 100644 index 00000000000..58ebbd6d33d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smbus.h @@ -0,0 +1,697 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_smbus.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of SMBUS HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_SMBUS_H +#define __STM32F7xx_HAL_SMBUS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SMBUS_Exported_Types SMBUS Exported Types + * @{ + */ + +/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition + * @brief SMBUS Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. + This parameter calculated by referring to SMBUS initialization + section in Reference manual */ + uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. + This parameter can be a value of @ref SMBUS_Analog_Filter */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. + This parameter can be a value of @ref SMBUS_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref SMBUS_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref SMBUS_own_address2_masks. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref SMBUS_nostretch_mode */ + + uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. + This parameter can be a value of @ref SMBUS_packet_error_check_mode */ + + uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. + This parameter can be a value of @ref SMBUS_peripheral_mode */ + + uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization + section in Reference manual */ +} SMBUS_InitTypeDef; +/** + * @} + */ + +/** @defgroup HAL_state_definition HAL state definition + * @brief HAL State definition + * @{ + */ +#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ +#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ +#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ +#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ +#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ +/** + * @} + */ + +/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition + * @brief SMBUS Error Code definition + * @{ + */ +#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ +#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ +#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ +#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ +#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ +/** + * @} + */ + +/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition + * @brief SMBUS handle Structure definition + * @{ + */ +typedef struct +{ + I2C_TypeDef *Instance; /*!< SMBUS registers base address */ + + SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ + + uint16_t XferSize; /*!< SMBUS transfer size */ + + __IO uint16_t XferCount; /*!< SMBUS transfer counter */ + + __IO uint32_t XferOptions; /*!< SMBUS transfer options */ + + __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ + + HAL_LockTypeDef Lock; /*!< SMBUS locking object */ + + __IO uint32_t State; /*!< SMBUS communication state */ + + __IO uint32_t ErrorCode; /*!< SMBUS Error code */ + +}SMBUS_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants + * @{ + */ + +/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter + * @{ + */ +#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) +#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup SMBUS_addressing_mode SMBUS addressing mode + * @{ + */ +#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) +#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode + * @{ + */ + +#define SMBUS_DUALADDRESS_DISABLE (0x00000000U) +#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks + * @{ + */ + +#define SMBUS_OA2_NOMASK ((uint8_t)0x00U) +#define SMBUS_OA2_MASK01 ((uint8_t)0x01U) +#define SMBUS_OA2_MASK02 ((uint8_t)0x02U) +#define SMBUS_OA2_MASK03 ((uint8_t)0x03U) +#define SMBUS_OA2_MASK04 ((uint8_t)0x04U) +#define SMBUS_OA2_MASK05 ((uint8_t)0x05U) +#define SMBUS_OA2_MASK06 ((uint8_t)0x06U) +#define SMBUS_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + + +/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode + * @{ + */ +#define SMBUS_GENERALCALL_DISABLE (0x00000000U) +#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode + * @{ + */ +#define SMBUS_NOSTRETCH_DISABLE (0x00000000U) +#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode + * @{ + */ +#define SMBUS_PEC_DISABLE (0x00000000U) +#define SMBUS_PEC_ENABLE I2C_CR1_PECEN +/** + * @} + */ + +/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode + * @{ + */ +#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN +#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) +#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN +/** + * @} + */ + +/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition + * @{ + */ + +#define SMBUS_SOFTEND_MODE (0x00000000U) +#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD +#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND +#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE +/** + * @} + */ + +/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition + * @{ + */ + +#define SMBUS_NO_STARTSTOP (0x00000000U) +#define SMBUS_GENERATE_STOP I2C_CR2_STOP +#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) +#define SMBUS_GENERATE_START_WRITE I2C_CR2_START +/** + * @} + */ + +/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition + * @{ + */ + +/* List of XferOptions in usage of : + * 1- Restart condition when direction change + * 2- No Restart condition in other use cases + */ +#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE +#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) +#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) +#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) +#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) +#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) +#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) +/** + * @} + */ + +/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition + * @brief SMBUS Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define SMBUS_IT_ERRI I2C_CR1_ERRIE +#define SMBUS_IT_TCI I2C_CR1_TCIE +#define SMBUS_IT_STOPI I2C_CR1_STOPIE +#define SMBUS_IT_NACKI I2C_CR1_NACKIE +#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE +#define SMBUS_IT_RXI I2C_CR1_RXIE +#define SMBUS_IT_TXI I2C_CR1_TXIE +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) +#define SMBUS_IT_ALERT (SMBUS_IT_ERRI) +#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) +/** + * @} + */ + +/** @defgroup SMBUS_Flag_definition SMBUS Flag definition + * @brief Flag definition + * Elements values convention: 0xXXXXYYYY + * - XXXXXXXX : Flag mask + * @{ + */ + +#define SMBUS_FLAG_TXE I2C_ISR_TXE +#define SMBUS_FLAG_TXIS I2C_ISR_TXIS +#define SMBUS_FLAG_RXNE I2C_ISR_RXNE +#define SMBUS_FLAG_ADDR I2C_ISR_ADDR +#define SMBUS_FLAG_AF I2C_ISR_NACKF +#define SMBUS_FLAG_STOPF I2C_ISR_STOPF +#define SMBUS_FLAG_TC I2C_ISR_TC +#define SMBUS_FLAG_TCR I2C_ISR_TCR +#define SMBUS_FLAG_BERR I2C_ISR_BERR +#define SMBUS_FLAG_ARLO I2C_ISR_ARLO +#define SMBUS_FLAG_OVR I2C_ISR_OVR +#define SMBUS_FLAG_PECERR I2C_ISR_PECERR +#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define SMBUS_FLAG_ALERT I2C_ISR_ALERT +#define SMBUS_FLAG_BUSY I2C_ISR_BUSY +#define SMBUS_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros + * @{ + */ + +/** @brief Reset SMBUS handle state. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) + +/** @brief Enable the specified SMBUS interrupts. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref SMBUS_IT_ERRI Errors interrupt enable + * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref SMBUS_IT_RXI RX interrupt enable + * @arg @ref SMBUS_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified SMBUS interrupts. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref SMBUS_IT_ERRI Errors interrupt enable + * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref SMBUS_IT_RXI RX interrupt enable + * @arg @ref SMBUS_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified SMBUS interrupt source is enabled or not. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref SMBUS_IT_ERRI Errors interrupt enable + * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref SMBUS_IT_RXI RX interrupt enable + * @arg @ref SMBUS_IT_TXI TX interrupt enable + * + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SMBUS flag is set or not. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty + * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status + * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty + * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) + * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_STOPF STOP detection flag + * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) + * @arg @ref SMBUS_FLAG_TCR Transfer complete reload + * @arg @ref SMBUS_FLAG_BERR Bus error + * @arg @ref SMBUS_FLAG_ARLO Arbitration lost + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_PECERR PEC error in reception + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_ALERT SMBus alert + * @arg @ref SMBUS_FLAG_BUSY Bus busy + * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define SMBUS_FLAG_MASK (0x0001FFFFU) +#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) + +/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) + * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_STOPF STOP detection flag + * @arg @ref SMBUS_FLAG_BERR Bus error + * @arg @ref SMBUS_FLAG_ARLO Arbitration lost + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_PECERR PEC error in reception + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Enable the specified SMBUS peripheral. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified SMBUS peripheral. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Macro SMBUS Private Macros + * @{ + */ + +#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ + ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) + +#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ + ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) + +#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) + +#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ + ((MASK) == SMBUS_OA2_MASK01) || \ + ((MASK) == SMBUS_OA2_MASK02) || \ + ((MASK) == SMBUS_OA2_MASK03) || \ + ((MASK) == SMBUS_OA2_MASK04) || \ + ((MASK) == SMBUS_OA2_MASK05) || \ + ((MASK) == SMBUS_OA2_MASK06) || \ + ((MASK) == SMBUS_OA2_MASK07)) + +#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ + ((CALL) == SMBUS_GENERALCALL_ENABLE)) + +#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ + ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) + +#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ + ((PEC) == SMBUS_PEC_ENABLE)) + +#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) + +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) + + +#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_NO_STARTSTOP)) + + +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ + ((REQUEST) == SMBUS_NEXT_FRAME) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \ + IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) + +#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) +#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) + +#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + +#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) +#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) +#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) +#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) + +#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR) +#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) + +#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions + * @{ + */ + +/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); + +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup Blocking_mode_Polling Blocking mode Polling + * @{ + */ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +/** + * @} + */ + +/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt + * @{ + */ +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); + +HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + +/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ +void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); + +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); + +/** + * @} + */ + +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Functions SMBUS Private Functions + * @{ + */ +/* Private functions are defined in stm32f7xx_hal_smbus.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F7xx_HAL_SMBUS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.c index 7bb0d9cc53e..0aa95e3431d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_spdifrx.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief This file provides firmware functions to manage the following * functionalities of the SPDIFRX audio interface: * + Initialization and Configuration diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.h index 687166d88ee..1fedfe77231 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_spdifrx.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of SPDIFRX HAL module. ****************************************************************************** * @attention @@ -43,10 +43,10 @@ extern "C" { #endif -#if defined (SPDIFRX) - /* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" +#include "stm32f7xx_hal_def.h" + +#if defined (SPDIFRX) /** @addtogroup STM32F7xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.c index 664a6b4edd0..eb1b753c21b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_spi.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: @@ -52,7 +52,17 @@ (#) The CRC feature is not managed when the DMA circular mode is enabled (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + [..] + (@) The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + (@) + (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + + @endverbatim + Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, the following table resume the max SPI frequency reached with data size 8bits/16bits, according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : @@ -106,14 +116,7 @@ | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | +----------------------------------------------------------------------------------------------+ - @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), - SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). - @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() - (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() - (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() - @endverbatim ****************************************************************************** * @attention * @@ -1853,21 +1856,31 @@ error : HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; + uint32_t tickstart = 0U; /* Initialized local variable */ errorcode = HAL_OK; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) { hspi->TxISR = SPI_AbortTx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT); } if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) { hspi->RxISR = SPI_AbortRx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT); + } + + while (hspi->State != HAL_SPI_STATE_ABORT) + { + if ((HAL_GetTick() - tickstart) >= HAL_MAX_DELAY) + { + return HAL_TIMEOUT; + } } /* Clear ERRIE interrupts in case of DMA Mode */ @@ -1982,23 +1995,33 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; + uint32_t tickstart = 0U; uint32_t abortcplt ; /* Initialized local variable */ errorcode = HAL_OK; abortcplt = 1U; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) { hspi->TxISR = SPI_AbortTx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT); } if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) { hspi->RxISR = SPI_AbortRx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT); + } + + while (hspi->State != HAL_SPI_STATE_ABORT) + { + if ((HAL_GetTick() - tickstart) >= HAL_MAX_DELAY) + { + return HAL_TIMEOUT; + } } /* Clear ERRIE interrupts in case of DMA Mode */ @@ -3624,13 +3647,24 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) */ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) { + uint32_t tickstart = 0U; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + if ((HAL_GetTick() - tickstart) >= HAL_MAX_DELAY) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) @@ -3655,10 +3689,21 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) */ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) { + uint32_t tickstart = 0U; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + if ((HAL_GetTick() - tickstart) >= HAL_MAX_DELAY) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) { diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.h index 7696bf7963c..c8b33bf6a8e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_spi.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.c index 39c61de7995..a8ade6bc293 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sram.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.h index 349e182e1fd..644c3409984 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sram.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.c index e65e9e0c9e4..1af358829ef 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -210,9 +210,12 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); } @@ -493,7 +496,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + if(htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -1008,6 +1012,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -1526,6 +1531,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -2011,7 +2017,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + if(htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -2291,6 +2298,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); @@ -4737,6 +4747,9 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) tmpcr1 |= (uint32_t)Structure->ClockDivision; } + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + TIMx->CR1 = tmpcr1; /* Set the Auto-reload value */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.h index 00abc539f85..161ea1a57a6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -85,6 +85,10 @@ typedef struct - the number of half PWM period in center-aligned mode This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ + } TIM_Base_InitTypeDef; /** @@ -363,6 +367,16 @@ typedef struct #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U) #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ + /** * @} */ @@ -1285,6 +1299,9 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ ((__STATE__) == TIM_OCFAST_ENABLE)) diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.c index 7e53246d8fd..04b7b883d53 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer extension peripheral: @@ -176,6 +176,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -1625,252 +1626,399 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, __HAL_UNLOCK(htim); return HAL_OK; -} +} /** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM Output Compare handle - * @param sConfig: TIM Output Compare configuration structure - * @param Channel : TIM Channels to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @brief Configures the TIM in master mode. + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) -{ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ - __HAL_LOCK(htim); + __HAL_LOCK(htim); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } - htim->State = HAL_TIM_STATE_BUSY; + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; - switch (Channel) + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + + /* Check input state */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT)); + + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 5 in Output Compare */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - } - break; + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 6 in Output Compare */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - } - break; - - default: - break; + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); } - htim->State = HAL_TIM_STATE_READY; + - __HAL_UNLOCK(htim); + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); return HAL_OK; } - +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) /** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM PWM handle - * @param sConfig: TIM PWM configuration structure - * @param Channel : TIM Channels to be configured + * @brief Configures the break input source. + * @param htim: TIM handle. + * @param BreakInput: Break input to configure * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig: Break input source configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, - uint32_t Channel) +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + { + uint32_t tmporx = 0; + uint32_t bkin_enable_mask = 0; + uint32_t bkin_enable_bitpos = 0; + /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + /* Check input state */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) + switch(sBreakInputConfig->Source) { - case TIM_CHANNEL_1: + case TIM_BREAKINPUTSOURCE_BKIN: { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = 0; } break; - - case TIM_CHANNEL_2: + + case TIM_BREAKINPUTSOURCE_DFSDM1: { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; - } - break; - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; - } - break; - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the Channel 5 in PWM mode */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel5*/ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode; + bkin_enable_mask = TIM1_AF1_BKDF1BKE; + bkin_enable_bitpos = 8; } + break; + + default: break; - - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the Channel 5 in PWM mode */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel6 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; - } + } + + switch(BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + } + break; + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + } + break; + default: break; - - default: - break; } - htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Remap: specifies the TIM input remapping source. + * This parameter can be one of the following values: + * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) + * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. + * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. + * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. + * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock. + * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock. + * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. + * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous + * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock + * (HSE divided by a programmable prescaler) + * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + __HAL_LOCK(htim); + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + /* Set the Timer remapping configuration */ + htim->Instance->OR = Remap; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim: TIM handle. + * @param OCRef: specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(OCRef)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= OCRef; + + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); return HAL_OK; } +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extension Callbacks functions ##### + ============================================================================== + [..] + This section provides Extension TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non blocking mode + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_CommutationCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non blocking mode + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extension Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface state + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIMEx_CommutationCallback(htim); +} +/** + * @} + */ /** * @brief Configures the OCRef clear feature @@ -1907,9 +2055,6 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; - /* Clear the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); @@ -1917,14 +2062,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, htim->Instance->SMCR = tmpsmcr; } break; - - case TIM_CLEARINPUTSOURCE_OCREFCLR: - { - /* Clear the OCREF clear selection bit */ - htim->Instance->SMCR &= ~TIM_SMCR_OCCS; - } - break; - + case TIM_CLEARINPUTSOURCE_ETR: { /* Check the parameters */ @@ -1936,9 +2074,6 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, sClearInputConfig->ClearInputPrescaler, sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; } break; default: @@ -2026,405 +2161,265 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } else { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; - } - } - break; - default: - break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in master mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) -{ - uint32_t tmpcr2; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ - if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); - - /* Clear the MMS2 bits */ - tmpcr2 &= ~TIM_CR2_MMS2; - /* Select the TRGO2 source*/ - tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - } + /* Disable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; + } + } + break; + default: + break; + } - /* Reset the MMS Bits */ - tmpcr2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - tmpcr2 |= sMasterConfig->MasterOutputTrigger; + __HAL_UNLOCK(htim); - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - - /* Update TIMx CR2 */ - htim->Instance->CR2 = tmpcr2; - - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; + return HAL_OK; +} - __HAL_UNLOCK(htim); - - return HAL_OK; -} - /** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim: TIM Output Compare handle + * @param sConfig: TIM Output Compare configuration structure + * @param Channel : TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) -{ - uint32_t tmpbdtr = 0; - + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) +{ /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); - assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); - assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); - assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); - assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); - assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); - assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Check input state */ - __HAL_LOCK(htim); + __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + } + break; - /* Clear the BDTR bits */ - tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI | - TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP | - TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF | - TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P); - - /* Set the BDTR bits */ - tmpbdtr |= sBreakDeadTimeConfig->DeadTime; - tmpbdtr |= sBreakDeadTimeConfig->LockLevel; - tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode; - tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode; - tmpbdtr |= sBreakDeadTimeConfig->BreakState; - tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity; - tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput; - tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT); - tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT); - tmpbdtr |= sBreakDeadTimeConfig->Break2State; - tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity; + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + } + break; + + default: + break; + } - /* Set TIMx_BDTR */ - htim->Instance->BDTR = tmpbdtr; + htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); + __HAL_UNLOCK(htim); return HAL_OK; } -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) + /** - * @brief Configures the break input source. - * @param htim: TIM handle. - * @param BreakInput: Break input to configure + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim: TIM PWM handle + * @param sConfig: TIM PWM configuration structure + * @param Channel : TIM Channels to be configured * This parameter can be one of the following values: - * @arg TIM_BREAKINPUT_BRK: Timer break input - * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @param sBreakInputConfig: Break input source configuration + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, - uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef* sConfig, + uint32_t Channel) { - uint32_t tmporx = 0; - uint32_t bkin_enable_mask = 0; - uint32_t bkin_enable_bitpos = 0; - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_BREAKINPUT(BreakInput)); - assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); - assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); - + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + /* Check input state */ __HAL_LOCK(htim); - switch(sBreakInputConfig->Source) + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) { - case TIM_BREAKINPUTSOURCE_BKIN: + case TIM_CHANNEL_1: { - bkin_enable_mask = TIM1_AF1_BKINE; - bkin_enable_bitpos = 0; + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + } + break; + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; + } + break; + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + } + break; + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; } break; - - case TIM_BREAKINPUTSOURCE_DFSDM1: + + case TIM_CHANNEL_5: { - bkin_enable_mask = TIM1_AF1_BKDF1BKE; - bkin_enable_bitpos = 8; + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; } - break; - - default: break; - } - - switch(BreakInput) - { - case TIM_BREAKINPUT_BRK: - { - /* Get the TIMx_AF1 register value */ - tmporx = htim->Instance->AF1; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set TIMx_AF1 */ - htim->Instance->AF1 = tmporx; - } - break; - case TIM_BREAKINPUT_BRK2: - { - /* Get the TIMx_AF2 register value */ - tmporx = htim->Instance->AF2; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set TIMx_AF2 */ - htim->Instance->AF2 = tmporx; - } - break; - default: + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; + } break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Remap: specifies the TIM input remapping source. - * This parameter can be one of the following values: - * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) - * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. - * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. - * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. - * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock. - * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock. - * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. - * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous - * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock - * (HSE divided by a programmable prescaler) - * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - __HAL_LOCK(htim); - /* Check parameters */ - assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); - assert_param(IS_TIM_REMAP(Remap)); - - /* Set the Timer remapping configuration */ - htim->Instance->OR = Remap; + default: + break; + } htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Group channel 5 and channel 1, 2 or 3 - * @param htim: TIM handle. - * @param OCRef: specifies the reference signal(s) the OC5REF is combined with. - * This parameter can be any combination of the following values: - * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC - * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF - * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF - * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef) -{ - /* Check parameters */ - assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_GROUPCH5(OCRef)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Clear GC5Cx bit fields */ - htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1); - - /* Set GC5Cx bit fields */ - htim->Instance->CCR5 |= OCRef; - - htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); return HAL_OK; } -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * -@verbatim - ============================================================================== - ##### Extension Callbacks functions ##### - ============================================================================== - [..] - This section provides Extension TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - -/** - * @brief Hall commutation changed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_CommutationCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Break detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_BreakCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extension Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Hall Sensor interface state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @brief TIM DMA Commutation callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIMEx_CommutationCallback(htim); -} - /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral @@ -2557,11 +2552,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Write to TIMx CCER */ TIMx->CCER = tmpccer; -} - -/** - * @} - */ +} #endif /* HAL_TIM_MODULE_ENABLED */ /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.h index aa9a61defa9..fa4d11c7958 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention @@ -151,7 +151,7 @@ typedef struct { #define TIM_CHANNEL_5 ((uint32_t)0x0010U) #define TIM_CHANNEL_6 ((uint32_t)0x0014U) #define TIM_CHANNEL_ALL ((uint32_t)0x003CU) - + /** * @} */ @@ -201,7 +201,6 @@ typedef struct { * @{ */ #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U) -#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002U) #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U) /** * @} @@ -356,6 +355,48 @@ typedef struct { ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ ((__HANDLE__)->Instance->CCR6)) +/** + * @brief Sets the TIM Output compare preload. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Resets the TIM Output compare preload. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) + /** * @} */ @@ -536,7 +577,6 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim); #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF) #define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF) #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ ((MODE) == TIM_CLEARINPUTSOURCE_NONE)) #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \ ((STATE) == TIM_BREAK2_DISABLE)) diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.c index 481ee8dfd56..b54ce5dc466 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_uart.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: @@ -2030,16 +2030,6 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) return HAL_TIMEOUT; } } - /* Check if the Receiver is enabled */ - if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout Occurred */ - return HAL_TIMEOUT; - } - } /* Initialize the UART State */ huart->gState= HAL_UART_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.h index 66eb4f38c23..b4628277327 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_uart.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of UART HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart_ex.h index ba1e1172f4b..b864b1d28ad 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of UART HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.c index cafd2412777..64c6f2707d5 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_usart.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter @@ -1960,16 +1960,6 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) return HAL_TIMEOUT; } } - /* Check if the Receiver is enabled */ - if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) - { - husart->State= HAL_USART_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } /* Initialize the USART state*/ husart->State= HAL_USART_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.h index fb23f132fac..2e97df3e7cf 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_usart.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of USART HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart_ex.h index 4a80f8893be..3b5b057336e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of USART HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.c index 25bc8e451a9..36c292c93fb 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_wwdg.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.h index e4628b8f397..3a546a062c8 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_wwdg.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.c new file mode 100644 index 00000000000..4b8d53ffa83 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.c @@ -0,0 +1,920 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_adc.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief ADC LL module driver + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_adc.h" +#include "stm32f7xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (ADC1) || defined (ADC2) || defined (ADC3) + +/** @addtogroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup ADC_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* common to several ADC instances. */ +#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ + ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC instance. */ +#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ + ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ + ) + +#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ + ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ + || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ + ) + +#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ + ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ + || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ + ) + +#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ + ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ + || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC group regular */ +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + ) + +#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ + ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ + || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ + ) + +#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ + ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ + ) + +#define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ + ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ + || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ + ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ + ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC group injected */ +#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ + ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ + ) +#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ + ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ + || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ + || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ + ) + +#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ + ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ + || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ + ) + +#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ + ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ + ) + +#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ + ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ + || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* multimode. */ +#if defined(ADC3) +#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ + ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \ + ) +#else +#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ + ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ + ) +#endif + +#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ + ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \ + ) + +#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ + ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \ + ) + +#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ + ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ + || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ + || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ + ) + +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize registers of all ADC instances belonging to + * the same ADC common instance to their default reset values. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + + + /* Force reset of ADC clock (core clock) */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); + + /* Release reset of ADC clock (core clock) */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC); + + return SUCCESS; +} + +/** + * @brief Initialize some features of ADC common parameters + * (all ADC instances belonging to the same ADC common instance) + * and multimode (for devices with several ADC instances available). + * @note The setting of ADC common parameters is conditioned to + * ADC instances state: + * All ADC instances belonging to the same ADC common instance + * must be disabled. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are initialized + * - ERROR: ADC common registers are not initialized + */ +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); + + assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); + if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + { + assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); + assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); + } + + /* Note: Hardware constraint (refer to description of functions */ + /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ + /* On this STM32 serie, setting of these features is conditioned to */ + /* ADC state: */ + /* All ADC instances of the ADC common group must be disabled. */ + if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) + { + /* Configuration of ADC hierarchical scope: */ + /* - common to several ADC */ + /* (all ADC instances belonging to the same ADC common instance) */ + /* - Set ADC clock (conversion clock) */ + /* - multimode (if several ADC instances available on the */ + /* selected device) */ + /* - Set ADC multimode configuration */ + /* - Set ADC multimode DMA transfer */ + /* - Set ADC multimode: delay between 2 sampling phases */ + if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + { + MODIFY_REG(ADCxy_COMMON->CCR, + ADC_CCR_ADCPRE + | ADC_CCR_MULTI + | ADC_CCR_DMA + | ADC_CCR_DDS + | ADC_CCR_DELAY + , + ADC_CommonInitStruct->CommonClock + | ADC_CommonInitStruct->Multimode + | ADC_CommonInitStruct->MultiDMATransfer + | ADC_CommonInitStruct->MultiTwoSamplingDelay + ); + } + else + { + MODIFY_REG(ADCxy_COMMON->CCR, + ADC_CCR_ADCPRE + | ADC_CCR_MULTI + | ADC_CCR_DMA + | ADC_CCR_DDS + | ADC_CCR_DELAY + , + ADC_CommonInitStruct->CommonClock + | LL_ADC_MULTI_INDEPENDENT + ); + } + } + else + { + /* Initialization error: One or several ADC instances belonging to */ + /* the same ADC common instance are not disabled. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. + * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +{ + /* Set ADC_CommonInitStruct fields to default values */ + /* Set fields of ADC common */ + /* (all ADC instances belonging to the same ADC common instance) */ + ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; + + /* Set fields of ADC multimode */ + ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; + ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; + ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES; +} + +/** + * @brief De-initialize registers of the selected ADC instance + * to their default reset values. + * @note To reset all ADC instances quickly (perform a hard reset), + * use function @ref LL_ADC_CommonDeInit(). + * @param ADCx ADC instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are de-initialized + * - ERROR: ADC registers are not de-initialized + */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + /* Disable ADC instance if not already disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 1U) + { + /* Set ADC group regular trigger source to SW start to ensure to not */ + /* have an external trigger event occurring during the conversion stop */ + /* ADC disable process. */ + LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); + + /* Set ADC group injected trigger source to SW start to ensure to not */ + /* have an external trigger event occurring during the conversion stop */ + /* ADC disable process. */ + LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); + + /* Disable the ADC instance */ + LL_ADC_Disable(ADCx); + } + + /* Check whether ADC state is compliant with expected state */ + /* (hardware requirements of bits state to reset registers below) */ + if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) + { + /* ========== Reset ADC registers ========== */ + /* Reset register SR */ + CLEAR_BIT(ADCx->SR, + ( LL_ADC_FLAG_STRT + | LL_ADC_FLAG_JSTRT + | LL_ADC_FLAG_EOCS + | LL_ADC_FLAG_OVR + | LL_ADC_FLAG_JEOS + | LL_ADC_FLAG_AWD1 ) + ); + + /* Reset register CR1 */ + CLEAR_BIT(ADCx->CR1, + ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN + | ADC_CR1_JAWDEN + | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN + | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN + | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE + | ADC_CR1_AWDCH ) + ); + + /* Reset register CR2 */ + CLEAR_BIT(ADCx->CR2, + ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL + | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL + | ADC_CR2_ALIGN | ADC_CR2_EOCS + | ADC_CR2_DDS | ADC_CR2_DMA + | ADC_CR2_CONT | ADC_CR2_ADON ) + ); + + /* Reset register SMPR1 */ + CLEAR_BIT(ADCx->SMPR1, + ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 + | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 + | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) + ); + + /* Reset register SMPR2 */ + CLEAR_BIT(ADCx->SMPR2, + ( ADC_SMPR2_SMP9 + | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 + | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 + | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) + ); + + /* Reset register JOFR1 */ + CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); + /* Reset register JOFR2 */ + CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); + /* Reset register JOFR3 */ + CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); + /* Reset register JOFR4 */ + CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); + + /* Reset register HTR */ + SET_BIT(ADCx->HTR, ADC_HTR_HT); + /* Reset register LTR */ + CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); + + /* Reset register SQR1 */ + CLEAR_BIT(ADCx->SQR1, + ( ADC_SQR1_L + | ADC_SQR1_SQ16 + | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) + ); + + /* Reset register SQR2 */ + CLEAR_BIT(ADCx->SQR2, + ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 + | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) + ); + + + /* Reset register JSQR */ + CLEAR_BIT(ADCx->JSQR, + ( ADC_JSQR_JL + | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 + | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) + ); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable */ + + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ + /* bits in access mode read only, no direct reset applicable */ + + /* Reset register CCR */ + CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); + } + + return status; +} + +/** + * @brief Initialize some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Affects both group regular and group injected (availability + * of ADC group injected depends on STM32 families). + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, some other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular or group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); + assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); + assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 0U) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC instance */ + /* - Set ADC data resolution */ + /* - Set ADC conversion data alignment */ + MODIFY_REG(ADCx->CR1, + ADC_CR1_RES + | ADC_CR1_SCAN + , + ADC_InitStruct->Resolution + | ADC_InitStruct->SequencersScanMode + ); + + MODIFY_REG(ADCx->CR2, + ADC_CR2_ALIGN + , + ADC_InitStruct->DataAlignment + ); + + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_InitTypeDef field to default value. + * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) +{ + /* Set ADC_InitStruct fields to default values */ + /* Set fields of ADC instance */ + ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; + ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + + /* Enable scan mode to have a generic behavior with ADC of other */ + /* STM32 families, without this setting available: */ + /* ADC group regular sequencer and ADC group injected sequencer depend */ + /* only of their own configuration. */ + ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; + +} + +/** + * @brief Initialize some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular or group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); + if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + } + assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); + assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 0U) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC group regular */ + /* - Set ADC group regular trigger source */ + /* - Set ADC group regular sequencer length */ + /* - Set ADC group regular sequencer discontinuous mode */ + /* - Set ADC group regular continuous mode */ + /* - Set ADC group regular conversion data transfer: no transfer or */ + /* transfer by DMA, and DMA requests mode */ + /* Note: On this STM32 serie, ADC trigger edge is set when starting */ + /* ADC conversion. */ + /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ + if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_DISCEN + | ADC_CR1_DISCNUM + , + ADC_REG_InitStruct->SequencerLength + | ADC_REG_InitStruct->SequencerDiscont + ); + } + else + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_DISCEN + | ADC_CR1_DISCNUM + , + ADC_REG_InitStruct->SequencerLength + | LL_ADC_REG_SEQ_DISCONT_DISABLE + ); + } + + MODIFY_REG(ADCx->CR2, + ADC_CR2_EXTSEL + | ADC_CR2_EXTEN + | ADC_CR2_CONT + | ADC_CR2_DMA + | ADC_CR2_DDS + , + (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) + | ADC_REG_InitStruct->ContinuousMode + | ADC_REG_InitStruct->DMATransfer + ); + + /* Set ADC group regular sequencer length and scan direction */ + /* Note: Hardware constraint (refer to description of this function): */ + /* Note: If ADC instance feature scan mode is disabled */ + /* (refer to ADC instance initialization structure */ + /* parameter @ref SequencersScanMode */ + /* or function @ref LL_ADC_SetSequencersScanMode() ), */ + /* this parameter is discarded. */ + LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. + * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +{ + /* Set ADC_REG_InitStruct fields to default values */ + /* Set fields of ADC group regular */ + /* Note: On this STM32 serie, ADC trigger edge is set when starting */ + /* ADC conversion. */ + /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ + ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; + ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; + ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; +} + +/** + * @brief Initialize some features of ADC group injected. + * @note These parameters have an impact on ADC scope: ADC group injected. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "INJ"). + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); + if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + { + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); + } + assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 0U) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC group injected */ + /* - Set ADC group injected trigger source */ + /* - Set ADC group injected sequencer length */ + /* - Set ADC group injected sequencer discontinuous mode */ + /* - Set ADC group injected conversion trigger: independent or */ + /* from ADC group regular */ + /* Note: On this STM32 serie, ADC trigger edge is set when starting */ + /* ADC conversion. */ + /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ + if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_JDISCEN + | ADC_CR1_JAUTO + , + ADC_INJ_InitStruct->SequencerDiscont + | ADC_INJ_InitStruct->TrigAuto + ); + } + else + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_JDISCEN + | ADC_CR1_JAUTO + , + LL_ADC_REG_SEQ_DISCONT_DISABLE + | ADC_INJ_InitStruct->TrigAuto + ); + } + + MODIFY_REG(ADCx->CR2, + ADC_CR2_JEXTSEL + | ADC_CR2_JEXTEN + , + (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) + ); + + /* Note: Hardware constraint (refer to description of this function): */ + /* Note: If ADC instance feature scan mode is disabled */ + /* (refer to ADC instance initialization structure */ + /* parameter @ref SequencersScanMode */ + /* or function @ref LL_ADC_SetSequencersScanMode() ), */ + /* this parameter is discarded. */ + LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. + * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) +{ + /* Set ADC_INJ_InitStruct fields to default values */ + /* Set fields of ADC group injected */ + ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; + ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; + ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; + ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 || ADC2 || ADC3 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.h new file mode 100644 index 00000000000..433115e4a5f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.h @@ -0,0 +1,4767 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_adc.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of ADC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_ADC_H +#define __STM32F7xx_LL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (ADC1) || defined (ADC2) || defined (ADC3) + +/** @defgroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @{ + */ + +/* Internal mask for ADC group regular sequencer: */ +/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ +/* - sequencer register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group regular sequencer configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SQR1_REGOFFSET (0x00000000U) +#define ADC_SQR2_REGOFFSET (0x00000100U) +#define ADC_SQR3_REGOFFSET (0x00000200U) +#define ADC_SQR4_REGOFFSET (0x00000300U) + +#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) +#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Definition of ADC group regular sequencer bits information to be inserted */ +/* into ADC group regular sequencer ranks literals definition. */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ +#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ +#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ +#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ +#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ +#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ +#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ +#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ +#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ + + + +/* Internal mask for ADC group injected sequencer: */ +/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ +/* - data register offset */ +/* - offset register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group injected data register */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_JDR1_REGOFFSET (0x00000000U) +#define ADC_JDR2_REGOFFSET (0x00000100U) +#define ADC_JDR3_REGOFFSET (0x00000200U) +#define ADC_JDR4_REGOFFSET (0x00000300U) + +/* Internal register offset for ADC group injected offset configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_JOFR1_REGOFFSET (0x00000000U) +#define ADC_JOFR2_REGOFFSET (0x00001000U) +#define ADC_JOFR3_REGOFFSET (0x00002000U) +#define ADC_JOFR4_REGOFFSET (0x00003000U) + +#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) +#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) +#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Definition of ADC group injected sequencer bits information to be inserted */ +/* into ADC group injected sequencer ranks literals definition. */ +#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */ +#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */ +#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */ +#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */ + + + +/* Internal mask for ADC group regular trigger: */ +/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ +/* - regular trigger source */ +/* - regular trigger edge */ +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \ + ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \ + ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \ + ((ADC_CR2_EXTSEL) >> (4U * 3U)) ) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)) ) + +/* Definition of ADC group regular trigger bits information. */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */ + + + +/* Internal mask for ADC group injected trigger: */ +/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ +/* - injected trigger source */ +/* - injected trigger edge */ +#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \ + ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \ + ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \ + ((ADC_CR2_JEXTSEL) >> (4U * 3U)) ) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)) ) + +/* Definition of ADC group injected trigger bits information. */ +#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */ +#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */ + + + + + + +/* Internal mask for ADC channel: */ +/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ +/* - channel identifier defined by number */ +/* - channel differentiation between external channels (connected to */ +/* GPIO pins) and internal channels (connected to internal paths) */ +/* - channel sampling time defined by SMPRx register offset */ +/* and SMPx bits positions into SMPRx register */ +#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) +/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ + +/* Channel differentiation between external and internal channels */ +#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x40000000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ +#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT (0x10000000U) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ +#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) + +/* Internal register offset for ADC channel sampling time configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SMPR1_REGOFFSET (0x00000000U) +#define ADC_SMPR2_REGOFFSET (0x02000000U) +#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) + +#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000U) +#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ + +/* Definition of channels ID number information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_NUMBER (0x00000000U) +#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) +#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) +#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) +#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) +#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 ) + +/* Definition of channels sampling time information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ +#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ +#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ +#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ +#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ +#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ +#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ +#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ +#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ +#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ +#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ +#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ +#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ +#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ +#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ +#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ +#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ +#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ +#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */ + + +/* Internal mask for ADC analog watchdog: */ +/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ +/* (concatenation of multiple bits used in different analog watchdogs, */ +/* (feature of several watchdogs not available on all STM32 families)). */ +/* - analog watchdog 1: monitored channel defined by number, */ +/* selection of ADC group (ADC groups regular and-or injected). */ + +/* Internal register offset for ADC analog watchdog channel configuration */ +#define ADC_AWD_CR1_REGOFFSET (0x00000000U) + +#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) + +#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) +#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) + +/* Internal register offset for ADC analog watchdog threshold configuration */ +#define ADC_AWD_TR1_HIGH_REGOFFSET (0x00000000U) +#define ADC_AWD_TR1_LOW_REGOFFSET (0x00000001U) +#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) + + +/* ADC registers bits positions */ +#define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */ +#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ + + +/* ADC internal channels related definitions */ +/* Internal voltage reference VrefInt */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF07A4A)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +/* Temperature sensor */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF07A4C)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF07A4E)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Macros ADC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: isolate bits with the + * selected mask and shift them to the register LSB + * (shift mask on register position bit 0). + * @param __BITS__ Bits in register 32 bits + * @param __MASK__ Mask in register 32 bits + * @retval Bits in register 32 bits + */ +#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ + (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address + */ +#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of ADC common parameters + * and multimode + * (all ADC instances belonging to the same ADC common instance). + * @note The setting of these parameters by function @ref LL_ADC_CommonInit() + * is conditioned to ADC instances state (all ADC instances + * sharing the same ADC common instance): + * All ADC instances sharing the same ADC common instance must be + * disabled. + */ +typedef struct +{ + uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ + + uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). + This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ + + uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. + This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ + + uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. + This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ + +} LL_ADC_CommonInitTypeDef; + +/** + * @brief Structure definition of some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Affects both group regular and group injected (availability + * of ADC group injected depends on STM32 families). + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t Resolution; /*!< Set ADC resolution. + This parameter can be a value of @ref ADC_LL_EC_RESOLUTION + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ + + uint32_t DataAlignment; /*!< Set ADC conversion data alignment. + This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ + + uint32_t SequencersScanMode; /*!< Set ADC scan selection. + This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ + +} LL_ADC_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_REG_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE + @note On this STM32 serie, setting of external trigger edge is performed + using function @ref LL_ADC_REG_StartConversionExtTrig(). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH + @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE + @note This parameter has an effect only if group regular sequencer is enabled + (scan length of 2 ranks or more). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). + This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE + Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ + + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. + This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ + +} LL_ADC_REG_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group injected. + * @note These parameters have an impact on ADC scope: ADC group injected. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "INJ"). + * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE + @note On this STM32 serie, setting of external trigger edge is performed + using function @ref LL_ADC_INJ_StartConversionExtTrig(). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH + @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE + @note This parameter has an effect only if group injected sequencer is enabled + (scan length of 2 ranks or more). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ + + uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO + Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ + +} LL_ADC_INJ_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_LL_EC_FLAG ADC flags + * @brief Flags defines which can be used with LL_ADC_ReadReg function + * @{ + */ +#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ +#define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */ +#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ +#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ +#define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */ +#define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */ +#define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */ +#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ +#define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */ +#define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + * @{ + */ +#define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */ +#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @{ + */ +/* List of ADC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @{ + */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (0x00000000U) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels may be available */ +/* (connections to other peripherals). */ +/* If they are not listed below, they do not require any specific */ +/* path enable. In this case, Access to measurement path is done */ +/* only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ +#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define LL_ADC_RESOLUTION_12B (0x00000000U) /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */ +#define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */ +#define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + * @{ + */ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection + * @{ + */ +#define LL_ADC_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ +#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define LL_ADC_GROUP_REGULAR (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_INJECTED (0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/ +#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003U) /*!< ADC both groups regular and injected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ +#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F7, ADC channel available only on ADC instance: ADC1. */ +#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F7, ADC channel available only on ADC instance: ADC1. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F7, ADC channel available only on ADC instance: ADC1. */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @{ + */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 ((uint32_t)ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM5_TRGO (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CR2_EXTSEL_3 |ADC_CR2_EXTSEL_2| ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @{ + */ +#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ +#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ +#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode +* @{ +*/ +#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + * @{ + */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions) + * @{ + */ +#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV (0x00000000U) /*!< ADC flag EOC (end of unitary conversion) selected */ +#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ +#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ +#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ +#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ +#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ +#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ +#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ +#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ +#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ +#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source + * @{ + */ +#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000U) /*!< ADC group injected conversion trigger internal: SW start. */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge + * @{ + */ +#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ +#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ +#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode +* @{ +*/ +#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ +#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ +/** + * @} + */ + + +/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length + * @{ + */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */ +#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks + * @{ + */ +#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */ +#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */ +#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */ +#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define LL_ADC_SAMPLINGTIME_3CYCLES (0x00000000U) /*!< Sampling time 3 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + * @{ + */ +#define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ +#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ +#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ +#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ +#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ +#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ +#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @{ + */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode + * @{ + */ +#define LL_ADC_MULTI_INDEPENDENT (0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */ +#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ +#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ +#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ +#if defined(ADC3) +#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */ +#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */ +#define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */ +#define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */ +#define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */ +#define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer + * @{ + */ +#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases + * @{ + */ +#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (0x00000000U) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/ +#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave + * @{ + */ +#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ +#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ +#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ +/** + * @} + */ + + + +/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @note Only ADC IP HW delays are defined in ADC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ +/* not timeout values. */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Indications for estimation of ADC timeout delays, for this */ +/* STM32 serie: */ +/* - ADC enable time: maximum delay is 2us */ +/* (refer to device datasheet, parameter "tSTAB") */ +/* - ADC conversion time: duration depending on ADC clock and ADC */ +/* configuration. */ +/* (refer to device reference manual, section "Timing") */ + +/* Delay for internal voltage reference stabilization time. */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ + +/* Delay for temperature sensor stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals LL_ADC_CHANNEL_x. + * @note Example: + * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + +/** + * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "LL_ADC_CHANNEL_4". + * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) <= 9U) \ + ? ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + : \ + ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + ) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + */ +#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1. + * (2) On devices STM32F7x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + ( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ + ) +/** + * @brief Helper macro to define ADC analog watchdog parameter: + * define a single channel to monitor with analog watchdog + * from sequencer channel and groups definition. + * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). + * Example: + * LL_ADC_SetAnalogWDMonitChannels( + * ADC1, LL_ADC_AWD1, + * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @param __GROUP__ This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @arg @ref LL_ADC_GROUP_INJECTED + * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + */ +#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ + (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ + : \ + ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ + : \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ + ) + +/** + * @brief Helper macro to set the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetAnalogWDThresholds + * (< ADCx param >, + * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to get the value of + * analog watchdog threshold high (on 8 bits): + * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION + * (LL_ADC_RESOLUTION_8B, + * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ + ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the ADC multimode conversion data of ADC master + * or ADC slave from raw value with both ADC conversion data concatenated. + * @note This macro is intended to be used when multimode transfer by DMA + * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). + * In this case the transferred data need to processed with this macro + * to separate the conversion data of ADC master and ADC slave. + * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ + (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#if defined(ADC1) && defined(ADC2) && defined(ADC3) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC123_COMMON) +#elif defined(ADC1) && defined(ADC2) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC12_COMMON) +#else +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC1_COMMON) +#endif + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#if defined(ADC1) && defined(ADC2) && defined(ADC3) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) | \ + LL_ADC_IsEnabled(ADC3) ) +#elif defined(ADC1) && defined(ADC2) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) ) +#else +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1)) +#endif + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \ + (((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \ + ) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ + ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + ) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 serie, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + ) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this STM32 serie, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ + ) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * On STM32F7, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32F4, refer to device datasheet parameter "V25". + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + ((( ( \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000) \ + - \ + (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000) \ + ) \ + ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (__TEMPSENSOR_CALX_TEMP__) \ + ) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @{ + */ +/* Note: LL ADC functions to set DMA transfer are located into sections of */ +/* configuration of ADC instance, groups and multimode (if available): */ +/* @ref LL_ADC_REG_SetDMATransfer(), ... */ + +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n + * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n + * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr + * @param ADCx ADC instance + * @param Register This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) + * + * (1) Available on devices with several ADC instances. + * @retval ADC register address + */ +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +{ + register uint32_t data_reg_addr = 0U; + + if (Register == LL_ADC_DMA_REG_REGULAR_DATA) + { + /* Retrieve address of register DR */ + data_reg_addr = (uint32_t)&(ADCx->DR); + } + else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ + { + /* Retrieve address of register CDR */ + data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances + * @{ + */ + +/** + * @brief Set parameter common to several ADC: Clock source and prescaler. + * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param CommonClock This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock); +} + +/** + * @brief Get parameter common to several ADC: Clock source and prescaler. + * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE)); +} + +/** + * @brief Set parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n + * CCR VBATE LL_ADC_SetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal); +} + +/** + * @brief Get parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n + * CCR VBATE LL_ADC_GetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Set ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR1 RES LL_ADC_SetResolution + * @param ADCx ADC instance + * @param Resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution); +} + +/** + * @brief Get ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR1 RES LL_ADC_GetResolution + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + */ +__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES)); +} + +/** + * @brief Set ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); +} + +/** + * @brief Get ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + */ +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); +} + +/** + * @brief Set ADC sequencers scan mode, for all ADC groups + * (group regular, group injected). + * @note According to sequencers scan mode : + * - If disabled: ADC conversion is performed in unitary conversion + * mode (one channel converted, that defined in rank 1). + * Configuration of sequencers of all ADC groups + * (sequencer scan length, ...) is discarded: equivalent to + * scan length of 1 rank. + * - If enabled: ADC conversions are performed in sequence conversions + * mode, according to configuration of sequencers of + * each ADC group (sequencer scan length, ...). + * Refer to function @ref LL_ADC_REG_SetSequencerLength() + * and to function @ref LL_ADC_INJ_SetSequencerLength(). + * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode + * @param ADCx ADC instance + * @param ScanMode This parameter can be one of the following values: + * @arg @ref LL_ADC_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_SEQ_SCAN_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); +} + +/** + * @brief Get ADC sequencers scan mode, for all ADC groups + * (group regular, group injected). + * @note According to sequencers scan mode : + * - If disabled: ADC conversion is performed in unitary conversion + * mode (one channel converted, that defined in rank 1). + * Configuration of sequencers of all ADC groups + * (sequencer scan length, ...) is discarded: equivalent to + * scan length of 1 rank. + * - If enabled: ADC conversions are performed in sequence conversions + * mode, according to configuration of sequencers of + * each ADC group (sequencer scan length, ...). + * Refer to function @ref LL_ADC_REG_SetSequencerLength() + * and to function @ref LL_ADC_INJ_SetSequencerLength(). + * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_SEQ_SCAN_ENABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Set ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note On this STM32 serie, setting of external trigger edge is performed + * using function @ref LL_ADC_REG_StartConversionExtTrig(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n + * CR2 EXTEN LL_ADC_REG_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ +/* Note: On this STM32 serie, ADC group regular external trigger edge */ +/* is used to perform a ADC conversion start. */ +/* This function does not set external trigger edge. */ +/* This feature is set using function */ +/* @ref LL_ADC_REG_StartConversionExtTrig(). */ + MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); +} + +/** + * @brief Get ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note To determine whether group regular trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") + * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n + * CR2 EXTEN LL_ADC_REG_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +{ + register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */ + register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); + + /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */ + /* to match with triggers literals definition. */ + return ((TriggerSource + & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN) + ); +} + +/** + * @brief Get ADC group regular conversion trigger source internal (SW start) + or external. + * @note In case of group regular trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_REG_GetTriggerSource(). + * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN)); +} + +/** + * @brief Get ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @note On this STM32 serie, setting of external trigger edge is performed + * using function @ref LL_ADC_REG_StartConversionExtTrig(). + * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN)); +} + + +/** + * @brief Set ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note On this STM32 serie, group regular sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); +} + +/** + * @brief Get ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note On this STM32 serie, group regular sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); +} + +/** + * @brief Set ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note It is not possible to enable both ADC auto-injected mode + * and ADC group regular sequencer discontinuous mode. + * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n + * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); +} + +/** + * @brief Get ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n + * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); +} + +/** + * @brief Set ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note This function performs configuration of: + * - Channels ordering into each rank of scan sequence: + * whatever channel can be placed into whatever rank. + * @note On this STM32 serie, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register and register position depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), + (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note On this STM32 serie, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + + return (uint32_t) (READ_BIT(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ); +} + +/** + * @brief Set ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode + * @param ADCx ADC instance + * @param Continuous This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); +} + +/** + * @brief Get ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); +} + +/** + * @brief Set ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note For devices with several ADC instances: ADC multimode DMA + * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n + * CR2 DDS LL_ADC_REG_SetDMATransfer + * @param ADCx ADC instance + * @param DMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer); +} + +/** + * @brief Get ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note For devices with several ADC instances: ADC multimode DMA + * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n + * CR2 DDS LL_ADC_REG_GetDMATransfer + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS)); +} + +/** + * @brief Specify which ADC flag between EOC (end of unitary conversion) + * or EOS (end of sequence conversions) is used to indicate + * the end of conversion. + * @note This feature is aimed to be set when using ADC with + * programming model by polling or interruption + * (programming model by DMA usually uses DMA interruptions + * to indicate end of conversion and data transfer). + * @note For ADC group injected, end of conversion (flag&IT) is raised + * only at the end of the sequence. + * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion + * @param ADCx ADC instance + * @param EocSelection This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV + * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection); +} + +/** + * @brief Get which ADC flag between EOC (end of unitary conversion) + * or EOS (end of sequence conversions) is used to indicate + * the end of conversion. + * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV + * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Set ADC group injected conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note On this STM32 serie, setting of external trigger edge is performed + * using function @ref LL_ADC_INJ_StartConversionExtTrig(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n + * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ +/* Note: On this STM32 serie, ADC group injected external trigger edge */ +/* is used to perform a ADC conversion start. */ +/* This function does not set external trigger edge. */ +/* This feature is set using function */ +/* @ref LL_ADC_INJ_StartConversionExtTrig(). */ + MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); +} + +/** + * @brief Get ADC group injected conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note To determine whether group injected trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") + * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n + * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) +{ + register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */ + register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); + + /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */ + /* to match with triggers literals definition. */ + return ((TriggerSource + & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL) + | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN) + ); +} + +/** + * @brief Get ADC group injected conversion trigger source internal (SW start) + or external + * @note In case of group injected trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_INJ_GetTriggerSource. + * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN)); +} + +/** + * @brief Get ADC group injected conversion trigger polarity. + * Applicable only for trigger source set to external trigger. + * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING + * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN)); +} + +/** + * @brief Set ADC group injected sequencer length and scan direction. + * @note This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note On this STM32 serie, group injected sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); +} + +/** + * @brief Get ADC group injected sequencer length and scan direction. + * @note This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note On this STM32 serie, group injected sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); +} + +/** + * @brief Set ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); +} + +/** + * @brief Get ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); +} + +/** + * @brief Set ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + MODIFY_REG(ADCx->JSQR, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), + (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); +} + +/** + * @brief Get ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +{ + return (uint32_t)(READ_BIT(ADCx->JSQR, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK) + ); +} + +/** + * @brief Set ADC group injected conversion trigger: + * independent or from ADC group regular. + * @note This mode can be used to extend number of data registers + * updated after one ADC conversion trigger and with data + * permanently kept (not erased by successive conversions of scan of + * ADC sequencer ranks), up to 5 data registers: + * 1 data register on ADC group regular, 4 data registers + * on ADC group injected. + * @note If ADC group injected injected trigger source is set to an + * external trigger, this feature must be must be set to + * independent trigger. + * ADC group injected automatic trigger is compliant only with + * group injected trigger source set to SW start, without any + * further action on ADC group injected conversion start or stop: + * in this case, ADC group injected is controlled only + * from ADC group regular. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto + * @param ADCx ADC instance + * @param TrigAuto This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); +} + +/** + * @brief Get ADC group injected conversion trigger: + * independent or from ADC group regular. + * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); +} + +/** + * @brief Set ADC group injected offset. + * @note It sets: + * - ADC group injected rank to which the offset programmed + * will be applied + * - Offset level (offset to be subtracted from the raw + * converted data). + * Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @note Offset cannot be enabled or disabled. + * To emulate offset disabled, set an offset value equal to 0. + * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n + * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n + * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n + * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_JOFR1_JOFFSET1, + OffsetLevel); +} + +/** + * @brief Get ADC group injected offset. + * @note It gives offset level (offset to be subtracted from the raw converted data). + * Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n + * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n + * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n + * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_JOFR1_JOFFSET1) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels + * @{ + */ + +/** + * @brief Set sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 serie. + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) +{ + /* Set bits with content of parameter "SamplingTime" with bits position */ + /* in register and register position depending on parameter "Channel". */ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), + SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); +} + +/** + * @brief Get sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 serie. + * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) + >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @{ + */ + +/** + * @brief Set ADC analog watchdog monitored channels: + * a single channel or all channels, + * on ADC groups regular and-or injected. + * @note Once monitored channels are selected, analog watchdog + * is enabled. + * @note In case of need to define a single channel to monitor + * with analog watchdog from sequencer channel definition, + * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). + * @note On this STM32 serie, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n + * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n + * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDChannelGroup This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) +{ + MODIFY_REG(ADCx->CR1, + (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), + AWDChannelGroup); +} + +/** + * @brief Get ADC analog watchdog monitored channel. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Applicable only when the analog watchdog is set to monitor + * one channel. + * @note On this STM32 serie, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n + * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n + * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); +} + +/** + * @brief Set ADC analog watchdog threshold value of threshold + * high or low. + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note On this STM32 serie, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n + * LTR LT LL_ADC_SetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + + MODIFY_REG(*preg, + ADC_HTR_HT, + AWDThresholdValue); +} + +/** + * @brief Get ADC analog watchdog threshold value of threshold high or + * threshold low. + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). + * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n + * LTR LT LL_ADC_GetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF +*/ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + + return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode + * @{ + */ + +/** + * @brief Set ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CCR MULTI LL_ADC_SetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param Multimode This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode); +} + +/** + * @brief Get ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CCR MULTI LL_ADC_GetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI)); +} + +/** + * @brief Set ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n + * CCR DDS LL_ADC_SetMultiDMATransfer + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param MultiDMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer); +} + +/** + * @brief Get ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n + * CCR DDS LL_ADC_GetMultiDMATransfer + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS)); +} + +/** + * @brief Set ADC multimode delay between 2 sampling phases. + * @note The sampling delay range depends on ADC resolution: + * - ADC resolution 12 bits can have maximum delay of 12 cycles. + * - ADC resolution 10 bits can have maximum delay of 10 cycles. + * - ADC resolution 8 bits can have maximum delay of 8 cycles. + * - ADC resolution 6 bits can have maximum delay of 6 cycles. + * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param MultiTwoSamplingDelay This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); +} + +/** + * @brief Get ADC multimode delay between 2 sampling phases. + * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); +} + +/** + * @} + */ +/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Enable the selected ADC instance. + * @note On this STM32 serie, after ADC enable, a delay for + * ADC internal analog stabilization is required before performing a + * ADC conversion start. + * Refer to device datasheet, parameter tSTAB. + * @rmtoll CR2 ADON LL_ADC_Enable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_ADON); +} + +/** + * @brief Disable the selected ADC instance. + * @rmtoll CR2 ADON LL_ADC_Disable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); +} + +/** + * @brief Get the selected ADC instance enable state. + * @rmtoll CR2 ADON LL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Start ADC group regular conversion. + * @note On this STM32 serie, this function is relevant only for + * internal trigger (SW start), not for external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * start must be performed using function + * @ref LL_ADC_REG_StartConversionExtTrig(). + * (if external trigger edge would have been set during ADC other + * settings, ADC conversion would start at trigger event + * as soon as ADC is enabled). + * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_SWSTART); +} + +/** + * @brief Start ADC group regular conversion from external trigger. + * @note ADC conversion will start at next trigger event (on the selected + * trigger edge) following the ADC start conversion command. + * @note On this STM32 serie, this function is relevant for + * ADC conversion start from external trigger. + * If internal trigger (SW start) is needed, perform ADC conversion + * start using function @ref LL_ADC_REG_StartConversionSWStart(). + * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + SET_BIT(ADCx->CR2, ExternalTriggerEdge); +} + +/** + * @brief Stop ADC group regular conversion from external trigger. + * @note No more ADC conversion will start at next trigger event + * following the ADC stop conversion command. + * If a conversion is on-going, it will be completed. + * @note On this STM32 serie, there is no specific command + * to stop a conversion on-going or to stop ADC converting + * in continuous mode. These actions can be performed + * using function @ref LL_ADC_Disable(). + * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC multimode conversion data of ADC master, ADC slave + * or raw data with ADC master and slave concatenated. + * @note If raw data with ADC master and slave concatenated is retrieved, + * a macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * (however this macro is mainly intended for multimode + * transfer by DMA, because this function can do the same + * by getting multimode conversion data of ADC master or ADC slave + * separately). + * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n + * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param ConversionData This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @arg @ref LL_ADC_MULTI_MASTER_SLAVE + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, + ADC_DR_ADC2DATA) + >> POSITION_VAL(ConversionData) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Start ADC group injected conversion. + * @note On this STM32 serie, this function is relevant only for + * internal trigger (SW start), not for external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * start must be performed using function + * @ref LL_ADC_INJ_StartConversionExtTrig(). + * (if external trigger edge would have been set during ADC other + * settings, ADC conversion would start at trigger event + * as soon as ADC is enabled). + * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART); +} + +/** + * @brief Start ADC group injected conversion from external trigger. + * @note ADC conversion will start at next trigger event (on the selected + * trigger edge) following the ADC start conversion command. + * @note On this STM32 serie, this function is relevant for + * ADC conversion start from external trigger. + * If internal trigger (SW start) is needed, perform ADC conversion + * start using function @ref LL_ADC_INJ_StartConversionSWStart(). + * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING + * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + SET_BIT(ADCx->CR2, ExternalTriggerEdge); +} + +/** + * @brief Stop ADC group injected conversion from external trigger. + * @note No more ADC conversion will start at next trigger event + * following the ADC stop conversion command. + * If a conversion is on-going, it will be completed. + * @note On this STM32 serie, there is no specific command + * to stop a conversion on-going or to stop ADC converting + * in continuous mode. These actions can be performed + * using function @ref LL_ADC_Disable(). + * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint16_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint16_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint8_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint8_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @{ + */ + +/** + * @brief Get flag ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); +} + +/** + * @brief Get flag ADC group regular overrun. + * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); +} + + +/** + * @brief Get flag ADC group injected end of sequence conversions. + * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); +} + +/** + * @brief Get flag ADC analog watchdog 1 flag + * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); +} + +/** + * @brief Clear flag ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS); +} + +/** + * @brief Clear flag ADC group regular overrun. + * @rmtoll SR OVR LL_ADC_ClearFlag_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR); +} + + +/** + * @brief Clear flag ADC group injected end of sequence conversions. + * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); +} + +/** + * @brief Clear flag ADC analog watchdog 1. + * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration, of the ADC master. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration, of the ADC slave 1. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1)); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration, of the ADC slave 2. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2)); +} +/** + * @brief Get flag multimode ADC group regular overrun of the ADC master. + * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); +} + +/** + * @brief Get flag multimode ADC group regular overrun of the ADC slave 1. + * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1)); +} + +/** + * @brief Get flag multimode ADC group regular overrun of the ADC slave 2. + * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2)); +} + + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. + * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1)); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1. + * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2)); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2. + * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3)); +} + +/** + * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. + * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); +} + +/** + * @brief Get flag multimode analog watchdog 1 of the ADC slave 1. + * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1)); +} + +/** + * @brief Get flag multimode analog watchdog 1 of the ADC slave 2. + * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); +} + + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @{ + */ + +/** + * @brief Enable interruption ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS); +} + +/** + * @brief Enable ADC group regular interruption overrun. + * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR1, LL_ADC_IT_OVR); +} + + +/** + * @brief Enable interruption ADC group injected end of sequence conversions. + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); +} + +/** + * @brief Enable interruption ADC analog watchdog 1. + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); +} + +/** + * @brief Disable interruption ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS); +} + +/** + * @brief Disable interruption ADC group regular overrun. + * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR); +} + + +/** + * @brief Disable interruption ADC group injected end of sequence conversions. + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); +} + +/** + * @brief Disable interruption ADC analog watchdog 1. + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); +} + +/** + * @brief Get state of interruption ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * (0: interrupt disabled, 1: interrupt enabled) + * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS)); +} + +/** + * @brief Get state of interruption ADC group regular overrun + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); +} + + +/** + * @brief Get state of interruption ADC group injected end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); +} + +/** + * @brief Get state of interruption ADC analog watchdog 1 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/* Initialization of some features of ADC common parameters and multimode */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); + +/* De-initialization of ADC instance, ADC group regular and ADC group injected */ +/* (availability of ADC group injected depends on STM32 families) */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); + +/* Initialization of some features of ADC instance */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); + +/* Initialization of some features of ADC instance and ADC group regular */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); + +/* Initialization of some features of ADC instance and ADC group injected */ +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 || ADC2 || ADC3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_ADC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_bus.h new file mode 100644 index 00000000000..d31658cc174 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_bus.h @@ -0,0 +1,1994 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_bus.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_BUS_H +#define __STM32F7xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN +#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN +#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN +#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN +#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN +#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN +#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN +#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN +#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN +#if defined(GPIOJ) +#define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN +#endif /* GPIOJ */ +#if defined(GPIOK) +#define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN +#endif /* GPIOK */ +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN +#define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#if defined(DMA2D) +#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN +#endif /* DMA2D */ +#if defined(ETH) +#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN +#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN +#endif /* ETH */ +#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN +#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN +#define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN +#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN +#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN +#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(DCMI) +#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN +#endif /* DCMI */ +#if defined(JPEG) +#define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN +#endif /* JPEG */ +#if defined(CRYP) +#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN +#endif /* CRYP */ +#if defined(AES) +#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN +#endif /* AES */ +#if defined(HASH) +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#endif /* HASH */ +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN +#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN +#if defined(SPDIFRX) +#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN +#endif /* SPDIFRX */ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN +#if defined(I2C4) +#define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN +#endif /* I2C4 */ +#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN +#if defined(CAN2) +#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN +#endif /* CAN2 */ +#if defined(CAN3) +#define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN +#endif /* CAN3 */ +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN +#endif /* CEC */ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN +#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN +#if defined(RCC_APB1ENR_RTCEN) +#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN +#endif /* RCC_APB1ENR_RTCEN */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN +#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN +#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN +#define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN +#if defined(SDMMC2) +#define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN +#endif /* SDMMC2 */ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN +#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN +#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN +#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN +#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN +#if defined(SPI6) +#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN +#endif /* SPI6 */ +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#if defined(LTDC) +#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN +#endif /* LTDC */ +#if defined(DSI) +#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN +#endif /* DSI */ +#if defined(DFSDM1_Channel0) +#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN +#endif /* DFSDM1_Channel0 */ +#if defined(MDIOS) +#define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN +#endif /* MDIOS */ +#if defined(USB_HS_PHYC) +#define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN +#endif /* USB_HS_PHYC */ +#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripheral clocks in low-power mode + * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripheral clocks in low-power mode + * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripheral clocks in low-power mode + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB2 peripheral clocks in low-power mode + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripheral clocks in low-power mode + * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB3 peripheral clocks in low-power mode + * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n + * APB1ENR RTCEN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n + * APB1ENR RTCEN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in low-power mode + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripheral clocks in low-power mode + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n + * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDMMC2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR MDIOEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR OTGPHYCEN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDMMC2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR MDIOEN LL_APB2_GRP1_DisableClock\n + * APB2ENR OTGPHYCEN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDMMC2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR MDIORST LL_APB2_GRP1_ForceReset\n + * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDMMC2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR MDIORST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripheral clocks in low-power mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR MDIOLPEN LL_APB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripheral clocks in low-power mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR MDIOLPEN LL_APB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_BUS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_cortex.h new file mode 100644 index 00000000000..dc9b7808607 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_cortex.h @@ -0,0 +1,657 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_cortex.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_CORTEX_H +#define __STM32F7xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M7 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC27 for Cortex-M7 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_CORTEX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_crc.c new file mode 100644 index 00000000000..845bcb10513 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_crc.c @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_crc.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief CRC LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_crc.h" +#include "stm32f7xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (CRC) + +/** @addtogroup CRC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup CRC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize CRC registers (Registers restored to their default values). + * @param CRCx CRC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: CRC registers are de-initialized + * - ERROR: CRC registers are not de-initialized + */ +ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(CRCx)); + + if (CRCx == CRC) + { + /* Force CRC reset */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC); + + /* Release CRC reset */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (CRC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_crc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_crc.h new file mode 100644 index 00000000000..7dd61af2e5f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_crc.h @@ -0,0 +1,479 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_crc.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of CRC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_CRC_H +#define __STM32F7xx_LL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(CRC) + +/** @defgroup CRC_LL CRC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants + * @{ + */ + +/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length + * @{ + */ +#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse + * @{ + */ +#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */ +#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */ +#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */ +#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse + * @{ + */ +#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */ +#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value + * @brief Normal representation of this polynomial value is + * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . + * @{ + */ +#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions + * @{ + */ + +/** + * @brief Reset the CRC calculation unit. + * @note If Programmable Initial CRC value feature + * is available, also set the Data Register to the value stored in the + * CRC_INIT register, otherwise, reset Data Register to its default value. + * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit + * @param CRCx CRC Instance + * @retval None + */ +__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_RESET); +} + +/** + * @brief Configure size of the polynomial. + * @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize + * @param CRCx CRC Instance + * @param PolySize This parameter can be one of the following values: + * @arg @ref LL_CRC_POLYLENGTH_32B + * @arg @ref LL_CRC_POLYLENGTH_16B + * @arg @ref LL_CRC_POLYLENGTH_8B + * @arg @ref LL_CRC_POLYLENGTH_7B + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize) +{ + MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize); +} + +/** + * @brief Return size of the polynomial. + * @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_POLYLENGTH_32B + * @arg @ref LL_CRC_POLYLENGTH_16B + * @arg @ref LL_CRC_POLYLENGTH_8B + * @arg @ref LL_CRC_POLYLENGTH_7B + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); +} + +/** + * @brief Configure the reversal of the bit order of the input data + * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode); +} + +/** + * @brief Return type of reversal for input data bit order + * @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + */ +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN)); +} + +/** + * @brief Configure the reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode); +} + +/** + * @brief Configure the reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + */ +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); +} + +/** + * @brief Initialize the Programmable initial CRC value. + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to write the correct value + * @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter. + * @rmtoll INIT INIT LL_CRC_SetInitialData + * @param CRCx CRC Instance + * @param InitCrc Value to be programmed in Programmable initial CRC value register + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc) +{ + WRITE_REG(CRCx->INIT, InitCrc); +} + +/** + * @brief Return current Initial CRC value. + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to read the correct value + * @rmtoll INIT INIT LL_CRC_GetInitialData + * @param CRCx CRC Instance + * @retval Value programmed in Programmable initial CRC value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->INIT)); +} + +/** + * @brief Initialize the Programmable polynomial value + * (coefficients of the polynomial to be used for CRC calculation). + * @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter. + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll POL POL LL_CRC_SetPolynomialCoef + * @param CRCx CRC Instance + * @param PolynomCoef Value to be programmed in Programmable Polynomial value register + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef) +{ + WRITE_REG(CRCx->POL, PolynomCoef); +} + +/** + * @brief Return current Programmable polynomial value + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll POL POL LL_CRC_GetPolynomialCoef + * @param CRCx CRC Instance + * @retval Value programmed in Programmable Polynomial value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->POL)); +} + +/** + * @} + */ + +/** @defgroup CRC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write given 32-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData32 + * @param CRCx CRC Instance + * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) +{ + WRITE_REG(CRCx->DR, InData); +} + +/** + * @brief Write given 16-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData16 + * @param CRCx CRC Instance + * @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) +{ + *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData; +} + +/** + * @brief Write given 8-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData8 + * @param CRCx CRC Instance + * @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData) +{ + *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData; +} + +/** + * @brief Return current CRC calculation result. 32 bits value is returned. + * @rmtoll DR DR LL_CRC_ReadData32 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). + */ +__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->DR)); +} + +/** + * @brief Return current CRC calculation result. 16 bits value is returned. + * @note This function is expected to be used in a 16 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData16 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). + */ +__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx) +{ + return (uint16_t)READ_REG(CRCx->DR); +} + +/** + * @brief Return current CRC calculation result. 8 bits value is returned. + * @note This function is expected to be used in a 8 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData8 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx) +{ + return (uint8_t)READ_REG(CRCx->DR); +} + +/** + * @brief Return current CRC calculation result. 7 bits value is returned. + * @note This function is expected to be used in a 7 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData7 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) +{ + return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU); +} + +/** + * @brief Return data stored in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one byte. + * @rmtoll IDR IDR LL_CRC_Read_IDR + * @param CRCx CRC Instance + * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). + */ +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->IDR)); +} + +/** + * @brief Store data in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one byte. + * @rmtoll IDR IDR LL_CRC_Write_IDR + * @param CRCx CRC Instance + * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) +{ + *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_CRC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dac.c new file mode 100644 index 00000000000..efe349f676f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dac.c @@ -0,0 +1,273 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_dac.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief DAC LL module driver + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_dac.h" +#include "stm32f7xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(DAC) + +/** @addtogroup DAC_LL DAC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup DAC_LL_Private_Macros + * @{ + */ + +#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ + ( \ + ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ + || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ + ) + +#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ + ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ + ) + +#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ + ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + ) + +#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \ + ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \ + ) + +#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ + ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ + || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + ) + +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DAC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize registers of the selected DAC instance + * to their default reset values. + * @param DACx DAC instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DAC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) +{ + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(DACx)); + + /* Force reset of DAC1 clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1); + + /* Release reset of DAC1 clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1); + return SUCCESS; +} + +/** + * @brief Initialize some features of DAC instance. + * @note The setting of these parameters by function @ref LL_DAC_Init() + * is conditioned to DAC state: + * DAC instance must be disabled. + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DAC registers are initialized + * - ERROR: DAC registers are not initialized + */ +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(DACx)); + assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel)); + assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource)); + assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer)); + assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration)); + if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) + { + assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig)); + } + + /* Note: Hardware constraint (refer to description of this function) */ + /* DAC instance must be disabled. */ + if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U) + { + /* Configuration of DAC channel: */ + /* - TriggerSource */ + /* - WaveAutoGeneration */ + /* - OutputBuffer */ + if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) + { + MODIFY_REG(DACx->CR, + ( DAC_CR_TSEL1 + | DAC_CR_WAVE1 + | DAC_CR_MAMP1 + | DAC_CR_BOFF1 + ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + , + ( DAC_InitStruct->TriggerSource + | DAC_InitStruct->WaveAutoGeneration + | DAC_InitStruct->WaveAutoGenerationConfig + | DAC_InitStruct->OutputBuffer + ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); + } + else + { + MODIFY_REG(DACx->CR, + ( DAC_CR_TSEL1 + | DAC_CR_WAVE1 + | DAC_CR_BOFF1 + ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + , + ( DAC_InitStruct->TriggerSource + | LL_DAC_WAVE_AUTO_GENERATION_NONE + | DAC_InitStruct->OutputBuffer + ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); + } + } + else + { + /* Initialization error: DAC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_DAC_InitTypeDef field to default value. + * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) +{ + /* Set DAC_InitStruct fields to default values */ + DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE; + DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE; + /* Note: Parameter discarded if wave auto generation is disabled, */ + /* set anyway to its default value. */ + DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0; + DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dac.h new file mode 100644 index 00000000000..e68bef3b05d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dac.h @@ -0,0 +1,1316 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_dac.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of DAC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_DAC_H +#define __STM32F7xx_LL_DAC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(DAC) + +/** @defgroup DAC_LL DAC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DAC_LL_Private_Constants DAC Private Constants + * @{ + */ + +/* Internal masks for DAC channels definition */ +/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ +/* - channel bits position into register CR */ +/* - channel bits position into register SWTRIG */ +/* - channel register offset of data holding register DHRx */ +/* - channel register offset of data output register DORx */ +#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ +#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ +#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) + +#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ +#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ +#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) + +#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ +#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U +#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U +#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U +#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) + +#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ +#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ +#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) + +/* DAC registers bits positions */ +#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ +#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ +#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ + +/* Miscellaneous data */ +#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DAC_LL_Private_Macros DAC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: isolate bits with the + * selected mask and shift them to the register LSB + * (shift mask on register position bit 0). + * @param __BITS__ Bits in register 32 bits + * @param __MASK__ Mask in register 32 bits + * @retval Bits in register 32 bits +*/ +#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \ + (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address +*/ +#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of DAC instance. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ + + uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. + This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ + + uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. + If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS + If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE + @note If waveform automatic generation mode is disabled, this parameter is discarded. + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ + + uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. + This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ + +} LL_DAC_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants + * @{ + */ + +/** @defgroup DAC_LL_EC_GET_FLAG DAC flags + * @brief Flags defines which can be used with LL_DAC_ReadReg function + * @{ + */ +/* DAC channel 1 flags */ +#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ + +/* DAC channel 2 flags */ +#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_IT DAC interruptions + * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions + * @{ + */ +#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ +#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_CHANNEL DAC channels + * @{ + */ +#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ +#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source + * @{ + */ +#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ +#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ +#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode + * @{ + */ +#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ +#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits + * @{ + */ +#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude + * @{ + */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer + * @{ + */ +#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ +#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ +/** + * @} + */ + + +/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution + * @{ + */ +#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ +#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose + * @{ + */ +/* List of DAC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ +#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */ +#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays + * @note Only DAC IP HW delays are defined in DAC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Delay for DAC channel voltage settling time from DAC channel startup */ +/* (transition from disable to enable). */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm (min), 50pF (max) */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tWAKEUP"). */ +/* Unit: us */ +#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ + +/* Delay for DAC channel voltage settling time. */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm min, 50pF max */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSETTLING"). */ +/* Unit: us */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros + * @{ + */ + +/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros + * @{ + */ + +/** + * @brief Write a value in DAC register + * @param __INSTANCE__ DAC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DAC register + * @param __INSTANCE__ DAC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +/** + * @} + */ + +/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro + * @{ + */ + +/** + * @brief Helper macro to get DAC channel number in decimal format + * from literals LL_DAC_CHANNEL_x. + * Example: + * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) + * will return decimal number "1". + * @note The input can be a value from functions where a channel + * number is returned. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval 1...2 + */ +#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + ((__CHANNEL__) & DAC_SWTR_CHX_MASK) + +/** + * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x + * from number in decimal format. + * Example: + * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) + * will return a data equivalent to "LL_DAC_CHANNEL_1". + * @note If the input parameter does not correspond to a DAC channel, + * this macro returns value '0'. + * @param __DECIMAL_NB__ 1...2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + */ +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) == 1U) \ + ? ( \ + LL_DAC_CHANNEL_1 \ + ) \ + : \ + (((__DECIMAL_NB__) == 2U) \ + ? ( \ + LL_DAC_CHANNEL_2 \ + ) \ + : \ + ( \ + 0 \ + ) \ + ) \ + ) + +/** + * @brief Helper macro to define the DAC conversion data full-scale digital + * value corresponding to the selected DAC resolution. + * @note DAC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __DAC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_DAC_RESOLUTION_12B + * @arg @ref LL_DAC_RESOLUTION_8B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) + +/** + * @brief Helper macro to calculate the DAC conversion data (unit: digital + * value) corresponding to a voltage (unit: mVolt). + * @note This helper macro is intended to provide input data in voltage + * rather than digital value, + * to be used with LL DAC functions such as + * @ref LL_DAC_ConvertData12RightAligned(). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel + * (unit: mVolt). + * @param __DAC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_DAC_RESOLUTION_12B + * @arg @ref LL_DAC_RESOLUTION_8B + * @retval DAC conversion data (unit: digital value) + */ +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ + __DAC_VOLTAGE__,\ + __DAC_RESOLUTION__) \ + ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ + ) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions + * @{ + */ +/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels + * @{ + */ + +/** + * @brief Set the conversion trigger source for the selected DAC channel. + * @note For conversion trigger source to be effective, DAC trigger + * must be enabled using function @ref LL_DAC_EnableTrigger(). + * @note To set conversion trigger source, DAC channel must be disabled. + * Otherwise, the setting is discarded. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n + * CR TSEL2 LL_DAC_SetTriggerSource + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) +{ + MODIFY_REG(DACx->CR, + DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the conversion trigger source for the selected DAC channel. + * @note For conversion trigger source to be effective, DAC trigger + * must be enabled using function @ref LL_DAC_EnableTrigger(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n + * CR TSEL2 LL_DAC_GetTriggerSource + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + */ +__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the waveform automatic generation mode + * for the selected DAC channel. + * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n + * CR WAVE2 LL_DAC_SetWaveAutoGeneration + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param WaveAutoGeneration This parameter can be one of the following values: + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) +{ + MODIFY_REG(DACx->CR, + DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the waveform automatic generation mode + * for the selected DAC channel. + * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n + * CR WAVE2 LL_DAC_GetWaveAutoGeneration + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the noise waveform generation for the selected DAC channel: + * Noise mode and parameters LFSR (linear feedback shift register). + * @note For wave generation to be effective, DAC channel + * wave generation mode must be enabled using + * function @ref LL_DAC_SetWaveAutoGeneration(). + * @note This setting can be set when the selected DAC channel is disabled + * (otherwise, the setting operation is ignored). + * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n + * CR MAMP2 LL_DAC_SetWaveNoiseLFSR + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param NoiseLFSRMask This parameter can be one of the following values: + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) +{ + MODIFY_REG(DACx->CR, + DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Set the noise waveform generation for the selected DAC channel: + * Noise mode and parameters LFSR (linear feedback shift register). + * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n + * CR MAMP2 LL_DAC_GetWaveNoiseLFSR + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the triangle waveform generation for the selected DAC channel: + * triangle mode and amplitude. + * @note For wave generation to be effective, DAC channel + * wave generation mode must be enabled using + * function @ref LL_DAC_SetWaveAutoGeneration(). + * @note This setting can be set when the selected DAC channel is disabled + * (otherwise, the setting operation is ignored). + * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n + * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param TriangleAmplitude This parameter can be one of the following values: + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) +{ + MODIFY_REG(DACx->CR, + DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Set the triangle waveform generation for the selected DAC channel: + * triangle mode and amplitude. + * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n + * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the output buffer for the selected DAC channel. + * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n + * CR BOFF2 LL_DAC_SetOutputBuffer + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param OutputBuffer This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) +{ + MODIFY_REG(DACx->CR, + DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the output buffer state for the selected DAC channel. + * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n + * CR BOFF2 LL_DAC_GetOutputBuffer + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + */ +__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DAC DMA transfer request of the selected channel. + * @note To configure DMA source address (peripheral address), + * use function @ref LL_DAC_DMA_GetRegAddr(). + * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n + * CR DMAEN2 LL_DAC_EnableDMAReq + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC DMA transfer request of the selected channel. + * @note To configure DMA source address (peripheral address), + * use function @ref LL_DAC_DMA_GetRegAddr(). + * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n + * CR DMAEN2 LL_DAC_DisableDMAReq + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC DMA transfer request state of the selected channel. + * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) + * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n + * CR DMAEN2 LL_DAC_IsDMAReqEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (READ_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); +} + +/** + * @brief Function to help to configure DMA transfer to DAC: retrieve the + * DAC register address from DAC instance and a list of DAC registers + * intended to be used (most commonly) with DMA transfer. + * @note These DAC registers are data holding registers: + * when DAC conversion is requested, DAC generates a DMA transfer + * request to have data available in DAC data holding registers. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * (uint32_t)&< array or variable >, + * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), + * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); + * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n + * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n + * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param Register This parameter can be one of the following values: + * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED + * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED + * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED + * @retval DAC register address + */ +__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) +{ + /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ + /* DAC channel selected. */ + return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register)))); +} +/** + * @} + */ + +/** @defgroup DAC_LL_EF_Operation Operation on DAC channels + * @{ + */ + +/** + * @brief Enable DAC selected channel. + * @rmtoll CR EN1 LL_DAC_Enable\n + * CR EN2 LL_DAC_Enable + * @note After enable from off state, DAC channel requires a delay + * for output voltage to reach accuracy +/- 1 LSB. + * Refer to device datasheet, parameter "tWAKEUP". + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC selected channel. + * @rmtoll CR EN1 LL_DAC_Disable\n + * CR EN2 LL_DAC_Disable + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC enable state of the selected channel. + * (0: DAC channel is disabled, 1: DAC channel is enabled) + * @rmtoll CR EN1 LL_DAC_IsEnabled\n + * CR EN2 LL_DAC_IsEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (READ_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); +} + +/** + * @brief Enable DAC trigger of the selected channel. + * @note - If DAC trigger is disabled, DAC conversion is performed + * automatically once the data holding register is updated, + * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": + * @ref LL_DAC_ConvertData12RightAligned(), ... + * - If DAC trigger is enabled, DAC conversion is performed + * only when a hardware of software trigger event is occurring. + * Select trigger source using + * function @ref LL_DAC_SetTriggerSource(). + * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n + * CR TEN2 LL_DAC_EnableTrigger + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC trigger of the selected channel. + * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n + * CR TEN2 LL_DAC_DisableTrigger + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC trigger state of the selected channel. + * (0: DAC trigger is disabled, 1: DAC trigger is enabled) + * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n + * CR TEN2 LL_DAC_IsTriggerEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (READ_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); +} + +/** + * @brief Trig DAC conversion by software for the selected DAC channel. + * @note Preliminarily, DAC trigger must be set to software trigger + * using function @ref LL_DAC_SetTriggerSource() + * with parameter "LL_DAC_TRIGGER_SOFTWARE". + * and DAC trigger must be enabled using + * function @ref LL_DAC_EnableTrigger(). + * @note For devices featuring DAC with 2 channels: this function + * can perform a SW start of both DAC channels simultaneously. + * Two channels can be selected as parameter. + * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) + * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n + * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion + * @param DACx DAC instance + * @param DAC_Channel This parameter can a combination of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->SWTRIGR, + (DAC_Channel & DAC_SWTR_CHX_MASK)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (LSB aligned on bit 0), + * for the selected DAC channel. + * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n + * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + DAC_DHR12R1_DACC1DHR, + Data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (MSB aligned on bit 15), + * for the selected DAC channel. + * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n + * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + DAC_DHR12L1_DACC1DHR, + Data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 8 bits left alignment (LSB aligned on bit 0), + * for the selected DAC channel. + * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n + * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + DAC_DHR8R1_DACC1DHR, + Data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (LSB aligned on bit 0), + * for both DAC channels. + * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n + * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF + * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +{ + MODIFY_REG(DACx->DHR12RD, + (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), + ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (MSB aligned on bit 15), + * for both DAC channels. + * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n + * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF + * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +{ + /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ + /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ + /* the 4 LSB must be taken into account for the shift value. */ + MODIFY_REG(DACx->DHR12LD, + (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), + ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 8 bits left alignment (LSB aligned on bit 0), + * for both DAC channels. + * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n + * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF + * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +{ + MODIFY_REG(DACx->DHR8RD, + (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), + ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); +} + +/** + * @brief Retrieve output data currently generated for the selected DAC channel. + * @note Whatever alignment and resolution settings + * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": + * @ref LL_DAC_ConvertData12RightAligned(), ...), + * output data format is 12 bits right aligned (LSB aligned on bit 0). + * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n + * DOR2 DACC2DOR LL_DAC_RetrieveOutputData + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); + + return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); +} + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management + * @{ + */ +/** + * @brief Get DAC underrun flag for DAC channel 1 + * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); +} + +/** + * @brief Get DAC underrun flag for DAC channel 2 + * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); +} + +/** + * @brief Clear DAC underrun flag for DAC channel 1 + * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) +{ + WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); +} + +/** + * @brief Clear DAC underrun flag for DAC channel 2 + * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) +{ + WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); +} + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_IT_Management IT management + * @{ + */ + +/** + * @brief Enable DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); +} + +/** + * @brief Enable DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); +} + +/** + * @brief Disable DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); +} + +/** + * @brief Disable DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); +} + +/** + * @brief Get DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); +} + +/** + * @brief Get DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx); +ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct); +void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_DAC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma.c new file mode 100644 index 00000000000..d5231caf382 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma.c @@ -0,0 +1,464 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_dma.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief DMA LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_dma.h" +#include "stm32f7xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DMA_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) + +#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ + ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \ + ((__VALUE__) == LL_DMA_MODE_PFCTRL)) + +#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ + ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) + +#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ + ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) + +#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) + +#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) + +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + +#if defined(DMA_CHANNEL_SELECTION_8_15) +#define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \ + ((__VALUE__) == LL_DMA_CHANNEL_1) || \ + ((__VALUE__) == LL_DMA_CHANNEL_2) || \ + ((__VALUE__) == LL_DMA_CHANNEL_3) || \ + ((__VALUE__) == LL_DMA_CHANNEL_4) || \ + ((__VALUE__) == LL_DMA_CHANNEL_5) || \ + ((__VALUE__) == LL_DMA_CHANNEL_6) || \ + ((__VALUE__) == LL_DMA_CHANNEL_7) || \ + ((__VALUE__) == LL_DMA_CHANNEL_8) || \ + ((__VALUE__) == LL_DMA_CHANNEL_9) || \ + ((__VALUE__) == LL_DMA_CHANNEL_10) || \ + ((__VALUE__) == LL_DMA_CHANNEL_11) || \ + ((__VALUE__) == LL_DMA_CHANNEL_12) || \ + ((__VALUE__) == LL_DMA_CHANNEL_13) || \ + ((__VALUE__) == LL_DMA_CHANNEL_14) || \ + ((__VALUE__) == LL_DMA_CHANNEL_15)) + +#else +#define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \ + ((__VALUE__) == LL_DMA_CHANNEL_1) || \ + ((__VALUE__) == LL_DMA_CHANNEL_2) || \ + ((__VALUE__) == LL_DMA_CHANNEL_3) || \ + ((__VALUE__) == LL_DMA_CHANNEL_4) || \ + ((__VALUE__) == LL_DMA_CHANNEL_5) || \ + ((__VALUE__) == LL_DMA_CHANNEL_6) || \ + ((__VALUE__) == LL_DMA_CHANNEL_7)) + +#endif /* DMA_CHANNEL_SELECTION_8_15 */ + +#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ + ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ + ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ + ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) + +#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \ + (((STREAM) == LL_DMA_STREAM_0) || \ + ((STREAM) == LL_DMA_STREAM_1) || \ + ((STREAM) == LL_DMA_STREAM_2) || \ + ((STREAM) == LL_DMA_STREAM_3) || \ + ((STREAM) == LL_DMA_STREAM_4) || \ + ((STREAM) == LL_DMA_STREAM_5) || \ + ((STREAM) == LL_DMA_STREAM_6) || \ + ((STREAM) == LL_DMA_STREAM_7) || \ + ((STREAM) == LL_DMA_STREAM_ALL))) ||\ + (((INSTANCE) == DMA2) && \ + (((STREAM) == LL_DMA_STREAM_0) || \ + ((STREAM) == LL_DMA_STREAM_1) || \ + ((STREAM) == LL_DMA_STREAM_2) || \ + ((STREAM) == LL_DMA_STREAM_3) || \ + ((STREAM) == LL_DMA_STREAM_4) || \ + ((STREAM) == LL_DMA_STREAM_5) || \ + ((STREAM) == LL_DMA_STREAM_6) || \ + ((STREAM) == LL_DMA_STREAM_7) || \ + ((STREAM) == LL_DMA_STREAM_ALL)))) + +#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \ + ((STATE) == LL_DMA_FIFOMODE_ENABLE)) + +#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \ + ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \ + ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \ + ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL)) + +#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \ + ((BURST) == LL_DMA_MBURST_INC4) || \ + ((BURST) == LL_DMA_MBURST_INC8) || \ + ((BURST) == LL_DMA_MBURST_INC16)) + +#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \ + ((BURST) == LL_DMA_PBURST_INC4) || \ + ((BURST) == LL_DMA_PBURST_INC8) || \ + ((BURST) == LL_DMA_PBURST_INC16)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the DMA registers to their default reset values. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @arg @ref LL_DMA_STREAM_ALL + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are de-initialized + * - ERROR: DMA registers are not de-initialized + */ +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream) +{ + DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0; + ErrorStatus status = SUCCESS; + + /* Check the DMA Instance DMAx and Stream parameters*/ + assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); + + if (Stream == LL_DMA_STREAM_ALL) + { + if (DMAx == DMA1) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); + } + else if (DMAx == DMA2) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); + } + else + { + status = ERROR; + } + } + else + { + /* Disable the selected Stream */ + LL_DMA_DisableStream(DMAx,Stream); + + /* Get the DMA Stream Instance */ + tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream)); + + /* Reset DMAx_Streamy configuration register */ + LL_DMA_WriteReg(tmp, CR, 0U); + + /* Reset DMAx_Streamy remaining bytes register */ + LL_DMA_WriteReg(tmp, NDTR, 0U); + + /* Reset DMAx_Streamy peripheral address register */ + LL_DMA_WriteReg(tmp, PAR, 0U); + + /* Reset DMAx_Streamy memory address register */ + LL_DMA_WriteReg(tmp, M0AR, 0U); + + /* Reset DMAx_Streamy memory address register */ + LL_DMA_WriteReg(tmp, M1AR, 0U); + + /* Reset DMAx_Streamy FIFO control register */ + LL_DMA_WriteReg(tmp, FCR, 0x00000021U); + + /* Reset Channel register field for DMAx Stream*/ + LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0); + + if(Stream == LL_DMA_STREAM_0) + { + /* Reset the Stream0 pending flags */ + DMAx->LIFCR = 0x0000003FU; + } + else if(Stream == LL_DMA_STREAM_1) + { + /* Reset the Stream1 pending flags */ + DMAx->LIFCR = 0x00000F40U; + } + else if(Stream == LL_DMA_STREAM_2) + { + /* Reset the Stream2 pending flags */ + DMAx->LIFCR = 0x003F0000U; + } + else if(Stream == LL_DMA_STREAM_3) + { + /* Reset the Stream3 pending flags */ + DMAx->LIFCR = 0x0F400000U; + } + else if(Stream == LL_DMA_STREAM_4) + { + /* Reset the Stream4 pending flags */ + DMAx->HIFCR = 0x0000003FU; + } + else if(Stream == LL_DMA_STREAM_5) + { + /* Reset the Stream5 pending flags */ + DMAx->HIFCR = 0x00000F40U; + } + else if(Stream == LL_DMA_STREAM_6) + { + /* Reset the Stream6 pending flags */ + DMAx->HIFCR = 0x003F0000U; + } + else if(Stream == LL_DMA_STREAM_7) + { + /* Reset the Stream7 pending flags */ + DMAx->HIFCR = 0x0F400000U; + } + else + { + status = ERROR; + } + } + + return status; +} + +/** + * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. + * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros : + * @arg @ref __LL_DMA_GET_INSTANCE + * @arg @ref __LL_DMA_GET_STREAM + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are initialized + * - ERROR: Not applicable + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Check the DMA Instance DMAx and Stream parameters*/ + assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); + + /* Check the DMA parameters from DMA_InitStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); + assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); + assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); + assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); + assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); + assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel)); + assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode)); + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) + { + assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold)); + assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst)); + assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst)); + } + + /*---------------------------- DMAx SxCR Configuration ------------------------ + * Configure DMAx_Streamy: data transfer direction, data transfer mode, + * peripheral and memory increment mode, + * data size alignment and priority level with parameters : + * - Direction: DMA_SxCR_DIR[1:0] bits + * - Mode: DMA_SxCR_CIRC bit + * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit + * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit + * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits + * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits + * - Priority: DMA_SxCR_PL[1:0] bits + */ + LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \ + DMA_InitStruct->Mode | \ + DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + DMA_InitStruct->MemoryOrM2MDstIncMode | \ + DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + DMA_InitStruct->MemoryOrM2MDstDataSize | \ + DMA_InitStruct->Priority + ); + + if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) + { + /*---------------------------- DMAx SxFCR Configuration ------------------------ + * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters : + * - FIFOMode: DMA_SxFCR_DMDIS bit + * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits + */ + LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold); + + /*---------------------------- DMAx SxCR Configuration -------------------------- + * Configure DMAx_Streamy: memory burst transfer with parameters : + * - MemBurst: DMA_SxCR_MBURST[1:0] bits + */ + LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst); + + /*---------------------------- DMAx SxCR Configuration -------------------------- + * Configure DMAx_Streamy: peripheral burst transfer with parameters : + * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits + */ + LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst); + } + + /*-------------------------- DMAx SxM0AR Configuration -------------------------- + * Configure the memory or destination base address with parameter : + * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits + */ + LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress); + + /*-------------------------- DMAx SxPAR Configuration --------------------------- + * Configure the peripheral or source base address with parameter : + * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits + */ + LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress); + + /*--------------------------- DMAx SxNDTR Configuration ------------------------- + * Configure the peripheral base address with parameter : + * - NbData: DMA_SxNDT[15:0] bits + */ + LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData); + + /*--------------------------- DMA SxCR_CHSEL Configuration ---------------------- + * Configure the peripheral base address with parameter : + * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits + */ + LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval None + */ +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Set DMA_InitStruct fields to default values */ + DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; + DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; + DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + DMA_InitStruct->NbData = 0x00000000U; + DMA_InitStruct->Channel = LL_DMA_CHANNEL_0; + DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; + DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE; + DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4; + DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE; + DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma.h new file mode 100644 index 00000000000..48b5945b699 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma.h @@ -0,0 +1,2911 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_dma.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_DMA_H +#define __STM32F7xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ +static const uint8_t STREAM_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) +}; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Constants DMA Private Constants + * @{ + */ +#if defined(DMA_SxCR_CHSEL_3) +#define DMA_CHANNEL_SELECTION_8_15 +#endif /* DMA_SxCR_CHSEL_3 */ +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Stream + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t Channel; /*!< Specifies the peripheral channel. + This parameter can be a value of @ref DMA_LL_EC_CHANNEL + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_LL_FIFOMODE + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream + + This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_MBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_PBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_STREAM STREAM + * @{ + */ +#define LL_DMA_STREAM_0 0x00000000U +#define LL_DMA_STREAM_1 0x00000001U +#define LL_DMA_STREAM_2 0x00000002U +#define LL_DMA_STREAM_3 0x00000003U +#define LL_DMA_STREAM_4 0x00000004U +#define LL_DMA_STREAM_5 0x00000005U +#define LL_DMA_STREAM_6 0x00000006U +#define LL_DMA_STREAM_7 0x00000007U +#define LL_DMA_STREAM_ALL 0xFFFF0000U +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION DIRECTION + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE MODE + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ +#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE MODE + * @{ + */ +#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ +#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH PERIPH + * @{ + */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY MEMORY + * @{ + */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE + * @{ + */ +#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ +#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY PRIORITY + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */ +#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */ +#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */ +#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */ +#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */ +#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */ +#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */ +#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */ +#if defined(DMA_CHANNEL_SELECTION_8_15) +#define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */ +#define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */ +#define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */ +#define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */ +#define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */ +#define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */ +#define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */ +#define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL /* Select Channel15 of DMA Instance */ +#endif /* DMA_CHANNEL_SELECTION_8_15 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MBURST MBURST + * @{ + */ +#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ +#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ +#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ +#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PBURST PBURST + * @{ + */ +#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ +#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ +#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ +#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE + * @{ + */ +#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ +#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 + * @{ + */ +#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ +#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ +#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ +#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ +#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ +#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD + * @{ + */ +#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ +#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ +#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM + * @{ + */ +#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ +#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy + * @{ + */ +/** + * @brief Convert DMAx_Streamy into DMAx + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval DMAx + */ +#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) + +/** + * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval LL_DMA_CHANNEL_y + */ +#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ + LL_DMA_STREAM_7) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy + * @param __DMA_INSTANCE__ DMAx + * @param __STREAM__ LL_DMA_STREAM_y + * @retval DMAx_Streamy + */ +#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ + DMA2_Stream7) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA stream. + * @rmtoll CR EN LL_DMA_EnableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); +} + +/** + * @brief Disable DMA stream. + * @rmtoll CR EN LL_DMA_DisableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); +} + +/** + * @brief Check if DMA stream is enabled or disabled. + * @rmtoll CR EN LL_DMA_IsEnabledStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); +} + +/** + * @brief Configure all parameters linked to DMA transfer. + * @rmtoll CR DIR LL_DMA_ConfigTransfer\n + * CR CIRC LL_DMA_ConfigTransfer\n + * CR PINC LL_DMA_ConfigTransfer\n + * CR MINC LL_DMA_ConfigTransfer\n + * CR PSIZE LL_DMA_ConfigTransfer\n + * CR MSIZE LL_DMA_ConfigTransfer\n + * CR PL LL_DMA_ConfigTransfer\n + * CR PFCTRL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + *@retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, + DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR)); +} + +/** + * @brief Set DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_SetMode\n + * CR PFCTRL LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); +} + +/** + * @brief Get DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_GetMode\n + * CR PFCTRL LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size); +} + +/** + * @brief Get Memory size. + * @rmtoll CR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE)); +} + +/** + * @brief Set Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param OffsetSize This parameter can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize); +} + +/** + * @brief Get Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + */ +__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS)); +} + +/** + * @brief Set Stream priority level. + * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority); +} + +/** + * @brief Get Stream priority level. + * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_SetDataLength + * @note This action has no effect if + * stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param NbData Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_GetDataLength + * @note Once the stream is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT)); +} + +/** + * @brief Select Channel number associated to the Stream. + * @rmtoll CR CHSEL LL_DMA_SetChannelSelection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @arg @ref LL_DMA_CHANNEL_12 (*) + * @arg @ref LL_DMA_CHANNEL_13 (*) + * @arg @ref LL_DMA_CHANNEL_14 (*) + * @arg @ref LL_DMA_CHANNEL_15 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel); +} + +/** + * @brief Get the Channel number associated to the Stream. + * @rmtoll CR CHSEL LL_DMA_GetChannelSelection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @arg @ref LL_DMA_CHANNEL_12 (*) + * @arg @ref LL_DMA_CHANNEL_13 (*) + * @arg @ref LL_DMA_CHANNEL_14 (*) + * @arg @ref LL_DMA_CHANNEL_15 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL)); +} + +/** + * @brief Set Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mburst This parameter can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst); +} + +/** + * @brief Get Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST)); +} + +/** + * @brief Set Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Pburst This parameter can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst); +} + +/** + * @brief Get Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST)); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_SetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param CurrentMemory This parameter can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_GetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT)); +} + +/** + * @brief Enable the double buffer mode. + * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Disable the double buffer mode. + * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Get FIFO status. + * @rmtoll FCR FS LL_DMA_GetFIFOStatus + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOSTATUS_0_25 + * @arg @ref LL_DMA_FIFOSTATUS_25_50 + * @arg @ref LL_DMA_FIFOSTATUS_50_75 + * @arg @ref LL_DMA_FIFOSTATUS_75_100 + * @arg @ref LL_DMA_FIFOSTATUS_EMPTY + * @arg @ref LL_DMA_FIFOSTATUS_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); +} + +/** + * @brief Disable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Enable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Select FIFO threshold. + * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold); +} + +/** + * @brief Get FIFO threshold. + * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); +} + +/** + * @brief Configure the FIFO . + * @rmtoll FCR FTH LL_DMA_ConfigFifo\n + * FCR DMDIS LL_DMA_ConfigFifo + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param FifoMode This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOMODE_ENABLE + * @arg @ref LL_DMA_FIFOMODE_DISABLE + * @param FifoThreshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA stream is enabled. + * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n + * PAR PA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DstAddress Between 0 to 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @rmtoll PAR PA LL_DMA_SetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param PeriphAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress); +} + +/** + * @brief Get the Memory address. + * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); +} + +/** + * @brief Get the Peripheral address. + * @rmtoll PAR PA LL_DMA_GetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); + } + +/** + * @brief Get the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) + { + return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); + } + +/** + * @brief Get the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); +} + +/** + * @brief Set Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_SetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Address Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address); +} + +/** + * @brief Get Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_GetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Stream 0 half transfer flag. + * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); +} + +/** + * @brief Get Stream 1 half transfer flag. + * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); +} + +/** + * @brief Get Stream 2 half transfer flag. + * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); +} + +/** + * @brief Get Stream 3 half transfer flag. + * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); +} + +/** + * @brief Get Stream 4 half transfer flag. + * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); +} + +/** + * @brief Get Stream 5 half transfer flag. + * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); +} + +/** + * @brief Get Stream 6 half transfer flag. + * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); +} + +/** + * @brief Get Stream 7 half transfer flag. + * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); +} + +/** + * @brief Get Stream 0 transfer complete flag. + * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); +} + +/** + * @brief Get Stream 1 transfer complete flag. + * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); +} + +/** + * @brief Get Stream 2 transfer complete flag. + * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); +} + +/** + * @brief Get Stream 3 transfer complete flag. + * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); +} + +/** + * @brief Get Stream 4 transfer complete flag. + * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); +} + +/** + * @brief Get Stream 5 transfer complete flag. + * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); +} + +/** + * @brief Get Stream 6 transfer complete flag. + * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); +} + +/** + * @brief Get Stream 7 transfer complete flag. + * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); +} + +/** + * @brief Get Stream 0 transfer error flag. + * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); +} + +/** + * @brief Get Stream 1 transfer error flag. + * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); +} + +/** + * @brief Get Stream 2 transfer error flag. + * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); +} + +/** + * @brief Get Stream 3 transfer error flag. + * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); +} + +/** + * @brief Get Stream 4 transfer error flag. + * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); +} + +/** + * @brief Get Stream 5 transfer error flag. + * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); +} + +/** + * @brief Get Stream 6 transfer error flag. + * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); +} + +/** + * @brief Get Stream 7 transfer error flag. + * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); +} + +/** + * @brief Get Stream 0 direct mode error flag. + * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); +} + +/** + * @brief Get Stream 1 direct mode error flag. + * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); +} + +/** + * @brief Get Stream 2 direct mode error flag. + * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); +} + +/** + * @brief Get Stream 3 direct mode error flag. + * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); +} + +/** + * @brief Get Stream 4 direct mode error flag. + * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); +} + +/** + * @brief Get Stream 5 direct mode error flag. + * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); +} + +/** + * @brief Get Stream 6 direct mode error flag. + * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); +} + +/** + * @brief Get Stream 7 direct mode error flag. + * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); +} + +/** + * @brief Get Stream 0 FIFO error flag. + * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); +} + +/** + * @brief Get Stream 1 FIFO error flag. + * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); +} + +/** + * @brief Get Stream 2 FIFO error flag. + * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); +} + +/** + * @brief Get Stream 3 FIFO error flag. + * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); +} + +/** + * @brief Get Stream 4 FIFO error flag. + * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); +} + +/** + * @brief Get Stream 5 FIFO error flag. + * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); +} + +/** + * @brief Get Stream 6 FIFO error flag. + * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); +} + +/** + * @brief Get Stream 7 FIFO error flag. + * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); +} + +/** + * @brief Clear Stream 0 half transfer flag. + * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF0); +} + +/** + * @brief Clear Stream 1 half transfer flag. + * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF1); +} + +/** + * @brief Clear Stream 2 half transfer flag. + * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF2); +} + +/** + * @brief Clear Stream 3 half transfer flag. + * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF3); +} + +/** + * @brief Clear Stream 4 half transfer flag. + * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF4); +} + +/** + * @brief Clear Stream 5 half transfer flag. + * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF5); +} + +/** + * @brief Clear Stream 6 half transfer flag. + * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF6); +} + +/** + * @brief Clear Stream 7 half transfer flag. + * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF7); +} + +/** + * @brief Clear Stream 0 transfer complete flag. + * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF0); +} + +/** + * @brief Clear Stream 1 transfer complete flag. + * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF1); +} + +/** + * @brief Clear Stream 2 transfer complete flag. + * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF2); +} + +/** + * @brief Clear Stream 3 transfer complete flag. + * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF3); +} + +/** + * @brief Clear Stream 4 transfer complete flag. + * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF4); +} + +/** + * @brief Clear Stream 5 transfer complete flag. + * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF5); +} + +/** + * @brief Clear Stream 6 transfer complete flag. + * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF6); +} + +/** + * @brief Clear Stream 7 transfer complete flag. + * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF7); +} + +/** + * @brief Clear Stream 0 transfer error flag. + * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF0); +} + +/** + * @brief Clear Stream 1 transfer error flag. + * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF1); +} + +/** + * @brief Clear Stream 2 transfer error flag. + * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF2); +} + +/** + * @brief Clear Stream 3 transfer error flag. + * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF3); +} + +/** + * @brief Clear Stream 4 transfer error flag. + * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF4); +} + +/** + * @brief Clear Stream 5 transfer error flag. + * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF5); +} + +/** + * @brief Clear Stream 6 transfer error flag. + * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF6); +} + +/** + * @brief Clear Stream 7 transfer error flag. + * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF7); +} + +/** + * @brief Clear Stream 0 direct mode error flag. + * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); +} + +/** + * @brief Clear Stream 1 direct mode error flag. + * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); +} + +/** + * @brief Clear Stream 2 direct mode error flag. + * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); +} + +/** + * @brief Clear Stream 3 direct mode error flag. + * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); +} + +/** + * @brief Clear Stream 4 direct mode error flag. + * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); +} + +/** + * @brief Clear Stream 5 direct mode error flag. + * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); +} + +/** + * @brief Clear Stream 6 direct mode error flag. + * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); +} + +/** + * @brief Clear Stream 7 direct mode error flag. + * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); +} + +/** + * @brief Clear Stream 0 FIFO error flag. + * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF0); +} + +/** + * @brief Clear Stream 1 FIFO error flag. + * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF1); +} + +/** + * @brief Clear Stream 2 FIFO error flag. + * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF2); +} + +/** + * @brief Clear Stream 3 FIFO error flag. + * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF3); +} + +/** + * @brief Clear Stream 4 FIFO error flag. + * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF4); +} + +/** + * @brief Clear Stream 5 FIFO error flag. + * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF5); +} + +/** + * @brief Clear Stream 6 FIFO error flag. + * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF6); +} + +/** + * @brief Clear Stream 7 FIFO error flag. + * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Enable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_EnableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Enable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_EnableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Disable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_DisableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Disable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_DisableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Check if Half transfer interrup is enabled. + * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); +} + +/** + * @brief Check if Transfer error nterrup is enabled. + * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE); +} + +/** + * @brief Check if Transfer complete interrup is enabled. + * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); +} + +/** + * @brief Check if Direct mode error interrupt is enabled. + * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE); +} + +/** + * @brief Check if FIFO error interrup is enabled. + * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma2d.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma2d.c new file mode 100644 index 00000000000..b0da89c939d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma2d.c @@ -0,0 +1,653 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_dma2d.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief DMA2D LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_dma2d.h" +#include "stm32f7xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (DMA2D) + +/** @addtogroup DMA2D_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA2D_LL_Private_Constants DMA2D Private Constants + * @{ + */ +#define LL_DMA2D_COLOR 0xFFU /*!< Maximum output color setting */ +#define LL_DMA2D_NUMBEROFLINES DMA2D_NLR_NL /*!< Maximum number of lines */ +#define LL_DMA2D_NUMBEROFPIXELS (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos) /*!< Maximum number of pixels per lines */ +#define LL_DMA2D_OFFSET_MAX 0x3FFFU /*!< Maximum output line offset expressed in pixels */ +#define LL_DMA2D_CLUTSIZE_MAX 0xFFU /*!< Maximum CLUT size */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DMA2D_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \ + ((MODE) == LL_DMA2D_MODE_M2M_PFC) || \ + ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \ + ((MODE) == LL_DMA2D_MODE_R2M)) + +#define IS_LL_DMA2D_OCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \ + ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888) || \ + ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB565) || \ + ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB1555) || \ + ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB4444)) + +#define IS_LL_DMA2D_GREEN(GREEN) ((GREEN) <= LL_DMA2D_COLOR) +#define IS_LL_DMA2D_RED(RED) ((RED) <= LL_DMA2D_COLOR) +#define IS_LL_DMA2D_BLUE(BLUE) ((BLUE) <= LL_DMA2D_COLOR) +#define IS_LL_DMA2D_ALPHA(ALPHA) ((ALPHA) <= LL_DMA2D_COLOR) + +#define IS_LL_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= LL_DMA2D_OFFSET_MAX) + +#define IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES) +#define IS_LL_DMA2D_PIXEL(PIXELS) ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS) + +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) +#define IS_LL_DMA2D_ALPHAINV(ALPHA) (((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \ + ((ALPHA) == LL_DMA2D_ALPHA_INVERTED)) + +#define IS_LL_DMA2D_RBSWAP(RBSWAP) (((RBSWAP) == LL_DMA2D_RB_MODE_REGULAR) || \ + ((RBSWAP) == LL_DMA2D_RB_MODE_SWAP)) + +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ +#define IS_LL_DMA2D_LCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB1555) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB4444) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L8) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL44) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL88) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L4) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A8) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A4)) + +#define IS_LL_DMA2D_CLUTCMODE(CLUTCMODE) (((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_ARGB8888) || \ + ((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_RGB888)) + +#define IS_LL_DMA2D_CLUTSIZE(SIZE) ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX) + +#define IS_LL_DMA2D_ALPHAMODE(MODE) (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \ + ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE) || \ + ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA2D_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions + * @{ + */ + +/** + * @brief De-initialize DMA2D registers (registers restored to their default values). + * @param DMA2Dx DMA2D Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA2D registers are de-initialized + * - ERROR: DMA2D registers are not de-initialized + */ +ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + + if (DMA2Dx == DMA2D) + { + /* Force reset of DMA2D clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2D); + + /* Release reset of DMA2D clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2D); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct. + * @note DMA2D transfers must be disabled to set initialization bits in configuration registers, + * otherwise ERROR result is returned. + * @param DMA2Dx DMA2D Instance + * @param DMA2D_InitStruct: pointer to a LL_DMA2D_InitTypeDef structure + * that contains the configuration information for the specified DMA2D peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content + * - ERROR: Issue occurred during DMA2D registers initialization + */ +ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct) +{ + ErrorStatus status = ERROR; + LL_DMA2D_ColorTypeDef DMA2D_ColorStruct; + uint32_t tmp = 0U, tmp1 = 0U, tmp2 = 0U; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_MODE(DMA2D_InitStruct->Mode)); + assert_param(IS_LL_DMA2D_OCMODE(DMA2D_InitStruct->ColorMode)); + assert_param(IS_LL_DMA2D_GREEN(DMA2D_InitStruct->OutputGreen)); + assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed)); + assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue)); + assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha)); + assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset)); + assert_param(IS_LL_DMA2D_LINE(DMA2D_InitStruct->NbrOfLines)); + assert_param(IS_LL_DMA2D_PIXEL(DMA2D_InitStruct->NbrOfPixelsPerLines)); +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_InitStruct->AlphaInversionMode)); + assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_InitStruct->RBSwapMode)); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + /* DMA2D transfers must be disabled to configure bits in initialization registers */ + tmp = LL_DMA2D_IsTransferOngoing(DMA2Dx); + tmp1 = LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2Dx); + tmp2 = LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2Dx); + if ((tmp == 0U) && (tmp1 == 0U) && (tmp2 == 0U)) + { + /* DMA2D CR register configuration -------------------------------------------*/ + LL_DMA2D_SetMode(DMA2Dx, DMA2D_InitStruct->Mode); + + /* DMA2D OPFCCR register configuration ---------------------------------------*/ +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI), \ + (DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode)); +#else + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, DMA2D_InitStruct->ColorMode); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + /* DMA2D OOR register configuration ------------------------------------------*/ + LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset); + + /* DMA2D NLR register configuration ------------------------------------------*/ + LL_DMA2D_ConfigSize(DMA2Dx, DMA2D_InitStruct->NbrOfLines, DMA2D_InitStruct->NbrOfPixelsPerLines); + + /* DMA2D OMAR register configuration ------------------------------------------*/ + LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress); + + /* DMA2D OCOLR register configuration ------------------------------------------*/ + DMA2D_ColorStruct.ColorMode = DMA2D_InitStruct->ColorMode; + DMA2D_ColorStruct.OutputBlue = DMA2D_InitStruct->OutputBlue; + DMA2D_ColorStruct.OutputGreen = DMA2D_InitStruct->OutputGreen; + DMA2D_ColorStruct.OutputRed = DMA2D_InitStruct->OutputRed; + DMA2D_ColorStruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha; + LL_DMA2D_ConfigOutputColor(DMA2Dx, &DMA2D_ColorStruct); + + status = SUCCESS; + } + /* If DMA2D transfers are not disabled, return ERROR */ + + return (status); +} + +/** + * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value. + * @param DMA2D_InitStruct: pointer to a @ref LL_DMA2D_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct) +{ + /* Set DMA2D_InitStruct fields to default values */ + DMA2D_InitStruct->Mode = LL_DMA2D_MODE_M2M; + DMA2D_InitStruct->ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB8888; + DMA2D_InitStruct->LineOffset = 0x0U; + DMA2D_InitStruct->OutputBlue = 0x0U; + DMA2D_InitStruct->OutputGreen = 0x0U; + DMA2D_InitStruct->OutputRed = 0x0U; + DMA2D_InitStruct->OutputAlpha = 0x0U; + DMA2D_InitStruct->OutputMemoryAddress = 0x0U; + DMA2D_InitStruct->NbrOfLines = 0x0U; + DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U; +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + DMA2D_InitStruct->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR; + DMA2D_InitStruct->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR; +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ +} + +/** + * @brief Configure the foreground or background according to the specified parameters + * in the LL_DMA2D_LayerCfgTypeDef structure. + * @param DMA2Dx DMA2D Instance + * @param DMA2D_LayerCfg: pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains + * the configuration information for the specified layer. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval None + */ +void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LL_DMA2D_OFFSET(DMA2D_LayerCfg->LineOffset)); + assert_param(IS_LL_DMA2D_LCMODE(DMA2D_LayerCfg->ColorMode)); + assert_param(IS_LL_DMA2D_CLUTCMODE(DMA2D_LayerCfg->CLUTColorMode)); + assert_param(IS_LL_DMA2D_CLUTSIZE(DMA2D_LayerCfg->CLUTSize)); + assert_param(IS_LL_DMA2D_ALPHAMODE(DMA2D_LayerCfg->AlphaMode)); + assert_param(IS_LL_DMA2D_GREEN(DMA2D_LayerCfg->Green)); + assert_param(IS_LL_DMA2D_RED(DMA2D_LayerCfg->Red)); + assert_param(IS_LL_DMA2D_BLUE(DMA2D_LayerCfg->Blue)); + assert_param(IS_LL_DMA2D_ALPHA(DMA2D_LayerCfg->Alpha)); +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_LayerCfg->AlphaInversionMode)); + assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode)); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + if (LayerIdx == 0U) + { + /* Configure the background memory address */ + LL_DMA2D_BGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress); + + /* Configure the background line offset */ + LL_DMA2D_BGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset); + +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + /* Configure the background Alpha value, Alpha mode, RB swap, Alpha inversion + CLUT size, CLUT Color mode and Color mode */ + MODIFY_REG(DMA2Dx->BGPFCCR, \ + (DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_RBS | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_AM | \ + DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \ + ((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \ + DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \ + (DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \ + DMA2D_LayerCfg->ColorMode)); +#else + /* Configure the background Alpha value, Alpha mode, CLUT size, CLUT Color mode and Color mode */ + MODIFY_REG(DMA2Dx->BGPFCCR, \ + (DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \ + ((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->AlphaMode | \ + (DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \ + DMA2D_LayerCfg->ColorMode)); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + /* Configure the background color */ + LL_DMA2D_BGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue); + + /* Configure the background CLUT memory address */ + LL_DMA2D_BGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress); + } + else + { + /* Configure the foreground memory address */ + LL_DMA2D_FGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress); + + /* Configure the foreground line offset */ + LL_DMA2D_FGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset); + +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + /* Configure the foreground Alpha value, Alpha mode, RB swap, Alpha inversion + CLUT size, CLUT Color mode and Color mode */ + MODIFY_REG(DMA2Dx->FGPFCCR, \ + (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_RBS | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_AM | \ + DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \ + ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \ + DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \ + (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \ + DMA2D_LayerCfg->ColorMode)); +#else + /* Configure the foreground Alpha value, Alpha mode, CLUT size, CLUT Color mode and Color mode */ + MODIFY_REG(DMA2Dx->FGPFCCR, \ + (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \ + ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->AlphaMode | \ + (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \ + DMA2D_LayerCfg->ColorMode)); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + /* Configure the foreground color */ + LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue); + + /* Configure the foreground CLUT memory address */ + LL_DMA2D_FGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress); + } +} + +/** + * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value. + * @param DMA2D_LayerCfg: pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg) +{ + /* Set DMA2D_LayerCfg fields to default values */ + DMA2D_LayerCfg->MemoryAddress = 0x0U; + DMA2D_LayerCfg->ColorMode = LL_DMA2D_INPUT_MODE_ARGB8888; + DMA2D_LayerCfg->LineOffset = 0x0U; + DMA2D_LayerCfg->CLUTColorMode = LL_DMA2D_CLUT_COLOR_MODE_ARGB8888; + DMA2D_LayerCfg->CLUTSize = 0x0U; + DMA2D_LayerCfg->AlphaMode = LL_DMA2D_ALPHA_MODE_NO_MODIF; + DMA2D_LayerCfg->Alpha = 0x0U; + DMA2D_LayerCfg->Blue = 0x0U; + DMA2D_LayerCfg->Green = 0x0U; + DMA2D_LayerCfg->Red = 0x0U; + DMA2D_LayerCfg->CLUTMemoryAddress = 0x0U; +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + DMA2D_LayerCfg->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR; + DMA2D_LayerCfg->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR; +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ +} + +/** + * @brief Initialize DMA2D output color register according to the specified parameters + * in DMA2D_ColorStruct. + * @param DMA2Dx DMA2D Instance + * @param DMA2D_ColorStruct: pointer to a LL_DMA2D_ColorTypeDef structure that contains + * the color configuration information for the specified DMA2D peripheral. + * @retval None + */ +void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct) +{ + uint32_t outgreen = 0U; + uint32_t outred = 0U; + uint32_t outalpha = 0U; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_OCMODE(DMA2D_ColorStruct->ColorMode)); + assert_param(IS_LL_DMA2D_GREEN(DMA2D_ColorStruct->OutputGreen)); + assert_param(IS_LL_DMA2D_RED(DMA2D_ColorStruct->OutputRed)); + assert_param(IS_LL_DMA2D_BLUE(DMA2D_ColorStruct->OutputBlue)); + assert_param(IS_LL_DMA2D_ALPHA(DMA2D_ColorStruct->OutputAlpha)); + + /* DMA2D OCOLR register configuration ------------------------------------------*/ + if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) + { + outgreen = DMA2D_ColorStruct->OutputGreen << 8U; + outred = DMA2D_ColorStruct->OutputRed << 16U; + outalpha = DMA2D_ColorStruct->OutputAlpha << 24U; + } + else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) + { + outgreen = DMA2D_ColorStruct->OutputGreen << 8U; + outred = DMA2D_ColorStruct->OutputRed << 16U; + outalpha = 0x00000000U; + } + else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) + { + outgreen = DMA2D_ColorStruct->OutputGreen << 5U; + outred = DMA2D_ColorStruct->OutputRed << 11U; + outalpha = 0x00000000U; + } + else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) + { + outgreen = DMA2D_ColorStruct->OutputGreen << 5U; + outred = DMA2D_ColorStruct->OutputRed << 10U; + outalpha = DMA2D_ColorStruct->OutputAlpha << 15U; + } + else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ + { + outgreen = DMA2D_ColorStruct->OutputGreen << 4U; + outred = DMA2D_ColorStruct->OutputRed << 8U; + outalpha = DMA2D_ColorStruct->OutputAlpha << 12U; + } + LL_DMA2D_SetOutputColor(DMA2Dx, (outgreen | outred | DMA2D_ColorStruct->OutputBlue | outalpha)); +} + +/** + * @brief Return DMA2D output Blue color. + * @param DMA2Dx DMA2D Instance. + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF + */ +uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + uint32_t color = 0U; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); + + /* DMA2D OCOLR register reading ------------------------------------------*/ + if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU)); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU)); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU)); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU)); + } + else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFU)); + } + + return color; +} + +/** + * @brief Return DMA2D output Green color. + * @param DMA2Dx DMA2D Instance. + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF + */ +uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + uint32_t color = 0U; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); + + /* DMA2D OCOLR register reading ------------------------------------------*/ + if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7E0U) >> 5U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x3E0U) >> 5U); + } + else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF0U) >> 4U); + } + + return color; +} + +/** + * @brief Return DMA2D output Red color. + * @param DMA2Dx DMA2D Instance. + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF + */ +uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + uint32_t color = 0U; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); + + /* DMA2D OCOLR register reading ------------------------------------------*/ + if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF800U) >> 11U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7C00U) >> 10U); + } + else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF00U) >> 8U); + } + + return color; +} + +/** + * @brief Return DMA2D output Alpha color. + * @param DMA2Dx DMA2D Instance. + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF + */ +uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + uint32_t color = 0U; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); + + /* DMA2D OCOLR register reading ------------------------------------------*/ + if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF000000U) >> 24U); + } + else if ((ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) || (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)) + { + color = 0x0U; + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x8000U) >> 15U); + } + else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF000U) >> 12U); + } + + return color; +} + +/** + * @brief Configure DMA2D transfer size. + * @param DMA2Dx DMA2D Instance + * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF + * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF + * @retval None + */ +void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines) +{ + MODIFY_REG(DMA2Dx->NLR, (DMA2D_NLR_PL | DMA2D_NLR_NL), \ + ((NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos) | NbrOfLines)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (DMA2D) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma2d.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma2d.h new file mode 100644 index 00000000000..6d387f479d9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma2d.h @@ -0,0 +1,2070 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_dma2d.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of DMA2D LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_DMA2D_H +#define __STM32F7xx_LL_DMA2D_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (DMA2D) + +/** @defgroup DMA2D_LL DMA2D + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures + * @{ + */ + +/** + * @brief LL DMA2D Init Structure Definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the DMA2D transfer mode. + - This parameter can be one value of @ref DMA2D_LL_EC_MODE. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/ + + uint32_t ColorMode; /*!< Specifies the color format of the output image. + - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */ + + uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputGreen; /*!< Specifies the Green value of the output image. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputRed; /*!< Specifies the Red value of the output image. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter is not considered if RGB888 or RGB565 color mode is selected. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputMemoryAddress; /*!< Specifies the memory address. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ + + uint32_t LineOffset; /*!< Specifies the output line offset value. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */ + + uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */ + + uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */ + +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode. + - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */ + + uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode. + - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */ +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + +} LL_DMA2D_InitTypeDef; + +/** + * @brief LL DMA2D Layer Configuration Structure Definition + */ +typedef struct +{ + uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer, + - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */ + + uint32_t LineOffset; /*!< Specifies the foreground or background line offset value. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer, + - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */ + + uint32_t ColorMode; /*!< Specifies the foreground or background color mode. + - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */ + + uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode. + - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */ + + uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer, + - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */ + + uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode. + - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */ + + uint32_t Alpha; /*!< Specifies the foreground or background Alpha value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer, + - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */ + + uint32_t Blue; /*!< Specifies the foreground or background Blue color value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer, + - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */ + + uint32_t Green; /*!< Specifies the foreground or background Green color value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer, + - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */ + + uint32_t Red; /*!< Specifies the foreground or background Red color value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer, + - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */ + + uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer, + - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */ + +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode. + - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */ + + uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode. + This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP . + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */ +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + +} LL_DMA2D_LayerCfgTypeDef; + +/** + * @brief LL DMA2D Output Color Structure Definition + */ +typedef struct +{ + uint32_t ColorMode; /*!< Specifies the color format of the output image. + - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */ + + uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputGreen; /*!< Specifies the Green value of the output image. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputRed; /*!< Specifies the Red value of the output image. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter is not considered if RGB888 or RGB565 color mode is selected. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + +} LL_DMA2D_ColorTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants + * @{ + */ + +/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA2D_ReadReg function + * @{ + */ +#define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ +#define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ +#define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ +#define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ +#define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ +#define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions + * @{ + */ +#define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ +#define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ +#define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ +#define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ +#define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ +#define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_MODE Mode + * @{ + */ +#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ +#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ +#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ +#define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode + * @{ + */ +#define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ +#define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */ +#define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */ +#define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */ +#define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode + * @{ + */ +#define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ +#define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */ +#define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */ +#define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */ +#define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */ +#define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */ +#define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */ +#define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */ +#define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */ +#define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */ +#define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode + * @{ + */ +#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */ +#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */ +#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value + with original alpha channel value */ +/** + * @} + */ + +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) +/** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap + * @{ + */ +#define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */ +#define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion + * @{ + */ +#define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */ +#define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */ +/** + * @} + */ + +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ +/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode + * @{ + */ +#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ +#define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros + * @{ + */ + +/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in DMA2D register. + * @param __INSTANCE__ DMA2D Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA2D register. + * @param __INSTANCE__ DMA2D Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions + * @{ + */ + +/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions + * @{ + */ + +/** + * @brief Start a DMA2D transfer. + * @rmtoll CR START LL_DMA2D_Start + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_START); +} + +/** + * @brief Indicate if a DMA2D transfer is ongoing. + * @rmtoll CR START LL_DMA2D_IsTransferOngoing + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)); +} + +/** + * @brief Suspend DMA2D transfer. + * @note This API can be used to suspend automatic foreground or background CLUT loading. + * @rmtoll CR SUSP LL_DMA2D_Suspend + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); +} + +/** + * @brief Resume DMA2D transfer. + * @note This API can be used to resume automatic foreground or background CLUT loading. + * @rmtoll CR SUSP LL_DMA2D_Resume + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START); +} + +/** + * @brief Indicate if DMA2D transfer is suspended. + * @note This API can be used to indicate whether or not automatic foreground or + * background CLUT loading is suspended. + * @rmtoll CR SUSP LL_DMA2D_IsSuspended + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)); +} + +/** + * @brief Abort DMA2D transfer. + * @note This API can be used to abort automatic foreground or background CLUT loading. + * @rmtoll CR ABORT LL_DMA2D_Abort + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); +} + +/** + * @brief Indicate if DMA2D transfer is aborted. + * @note This API can be used to indicate whether or not automatic foreground or + * background CLUT loading is aborted. + * @rmtoll CR ABORT LL_DMA2D_IsAborted + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)); +} + +/** + * @brief Set DMA2D mode. + * @rmtoll CR MODE LL_DMA2D_SetMode + * @param DMA2Dx DMA2D Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_MODE_M2M + * @arg @ref LL_DMA2D_MODE_M2M_PFC + * @arg @ref LL_DMA2D_MODE_M2M_BLEND + * @arg @ref LL_DMA2D_MODE_R2M + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode); +} + +/** + * @brief Return DMA2D mode + * @rmtoll CR MODE LL_DMA2D_GetMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_MODE_M2M + * @arg @ref LL_DMA2D_MODE_M2M_PFC + * @arg @ref LL_DMA2D_MODE_M2M_BLEND + * @arg @ref LL_DMA2D_MODE_R2M + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); +} + +/** + * @brief Set DMA2D output color mode. + * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode + * @param DMA2Dx DMA2D Instance + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode); +} + +/** + * @brief Return DMA2D output color mode. + * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); +} + +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) +/** + * @brief Set DMA2D output Red Blue swap mode. + * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode + * @param DMA2Dx DMA2D Instance + * @param RBSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode); +} + +/** + * @brief Return DMA2D output Red Blue swap mode. + * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); +} + +/** + * @brief Set DMA2D output alpha inversion mode. + * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @param AlphaInversionMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode); +} + +/** + * @brief Return DMA2D output alpha inversion mode. + * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); +} + +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + +/** + * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll OOR LO LL_DMA2D_SetLineOffset + * @param DMA2Dx DMA2D Instance + * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) +{ + MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset); +} + +/** + * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll OOR LO LL_DMA2D_GetLineOffset + * @param DMA2Dx DMA2D Instance + * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); +} + +/** + * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits). + * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines + * @param DMA2Dx DMA2D Instance + * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines) +{ + MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos)); +} + +/** + * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits) + * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines + * @param DMA2Dx DMA2D Instance + * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); +} + +/** + * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits). + * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines + * @param DMA2Dx DMA2D Instance + * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines) +{ + MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines); +} + +/** + * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits). + * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines + * @param DMA2Dx DMA2D Instance + * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); +} + +/** + * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr + * @param DMA2Dx DMA2D Instance + * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress); +} + +/** + * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); +} + +/** + * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits). + * @note Output color format depends on output color mode, ARGB8888, RGB888, + * RGB565, ARGB1555 or ARGB4444. + * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting + * with respect to color mode is not done by the user code. + * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n + * OCOLR GREEN LL_DMA2D_SetOutputColor\n + * OCOLR RED LL_DMA2D_SetOutputColor\n + * OCOLR ALPHA LL_DMA2D_SetOutputColor + * @param DMA2Dx DMA2D Instance + * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) +{ + MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ + OutputColor); +} + +/** + * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits). + * @note Alpha channel and red, green, blue color values must be retrieved from the returned + * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444) + * as set by @ref LL_DMA2D_SetOutputColorMode. + * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n + * OCOLR GREEN LL_DMA2D_GetOutputColor\n + * OCOLR RED LL_DMA2D_GetOutputColor\n + * OCOLR ALPHA LL_DMA2D_GetOutputColor + * @param DMA2Dx DMA2D Instance + * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ + (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); +} + +/** + * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits). + * @rmtoll LWR LW LL_DMA2D_SetLineWatermark + * @param DMA2Dx DMA2D Instance + * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark) +{ + MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark); +} + +/** + * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits). + * @rmtoll LWR LW LL_DMA2D_GetLineWatermark + * @param DMA2Dx DMA2D Instance + * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); +} + +/** + * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits). + * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime + * @param DMA2Dx DMA2D Instance + * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime) +{ + MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos)); +} + +/** + * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits). + * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime + * @param DMA2Dx DMA2D Instance + * @retval Dead time value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); +} + +/** + * @brief Enable DMA2D dead time functionality. + * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); +} + +/** + * @brief Disable DMA2D dead time functionality. + * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); +} + +/** + * @brief Indicate if DMA2D dead time functionality is enabled. + * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)); +} + +/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions + * @{ + */ + +/** + * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr + * @param DMA2Dx DMA2D Instance + * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress); +} + +/** + * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); +} + +/** + * @brief Enable DMA2D foreground CLUT loading. + * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START); +} + +/** + * @brief Indicate if DMA2D foreground CLUT loading is enabled. + * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)); +} + +/** + * @brief Set DMA2D foreground color mode. + * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode + * @param DMA2Dx DMA2D Instance + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode); +} + +/** + * @brief Return DMA2D foreground color mode. + * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); +} + +/** + * @brief Set DMA2D foreground alpha mode. + * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode + * @param DMA2Dx DMA2D Instance + * @param AphaMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode); +} + +/** + * @brief Return DMA2D foreground alpha mode. + * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); +} + +/** + * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha + * @param DMA2Dx DMA2D Instance + * @param Alpha Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos)); +} + +/** + * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha + * @param DMA2Dx DMA2D Instance + * @retval Alpha value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); +} + +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) +/** + * @brief Set DMA2D foreground Red Blue swap mode. + * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @param RBSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode); +} + +/** + * @brief Return DMA2D foreground Red Blue swap mode. + * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); +} + +/** + * @brief Set DMA2D foreground alpha inversion mode. + * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @param AlphaInversionMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode); +} + +/** + * @brief Return DMA2D foreground alpha inversion mode. + * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); +} + +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + +/** + * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset + * @param DMA2Dx DMA2D Instance + * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) +{ + MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset); +} + +/** + * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset + * @param DMA2Dx DMA2D Instance + * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); +} + +/** + * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits). + * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor + * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor + * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \ + ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue)); +} + +/** + * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) +{ + MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos)); +} + +/** + * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor + * @param DMA2Dx DMA2D Instance + * @retval Red color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); +} + +/** + * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor + * @param DMA2Dx DMA2D Instance + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) +{ + MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos)); +} + +/** + * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor + * @param DMA2Dx DMA2D Instance + * @retval Green color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); +} + +/** + * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor + * @param DMA2Dx DMA2D Instance + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue); +} + +/** + * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor + * @param DMA2Dx DMA2D Instance + * @retval Blue color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); +} + +/** + * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress); +} + +/** + * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); +} + +/** + * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize + * @param DMA2Dx DMA2D Instance + * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos)); +} + +/** + * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize + * @param DMA2Dx DMA2D Instance + * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); +} + +/** + * @brief Set DMA2D foreground CLUT color mode. + * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @param CLUTColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode); +} + +/** + * @brief Return DMA2D foreground CLUT color mode. + * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); +} + +/** + * @} + */ + +/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions + * @{ + */ + +/** + * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr + * @param DMA2Dx DMA2D Instance + * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress); +} + +/** + * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); +} + +/** + * @brief Enable DMA2D background CLUT loading. + * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START); +} + +/** + * @brief Indicate if DMA2D background CLUT loading is enabled. + * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)); +} + +/** + * @brief Set DMA2D background color mode. + * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode + * @param DMA2Dx DMA2D Instance + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode); +} + +/** + * @brief Return DMA2D background color mode. + * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); +} + +/** + * @brief Set DMA2D background alpha mode. + * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode + * @param DMA2Dx DMA2D Instance + * @param AphaMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode); +} + +/** + * @brief Return DMA2D background alpha mode. + * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); +} + +/** + * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha + * @param DMA2Dx DMA2D Instance + * @param Alpha Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos)); +} + +/** + * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha + * @param DMA2Dx DMA2D Instance + * @retval Alpha value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); +} + +#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) +/** + * @brief Set DMA2D background Red Blue swap mode. + * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @param RBSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode); +} + +/** + * @brief Return DMA2D background Red Blue swap mode. + * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); +} + +/** + * @brief Set DMA2D background alpha inversion mode. + * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @param AlphaInversionMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode); +} + +/** + * @brief Return DMA2D background alpha inversion mode. + * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); +} + +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + +/** + * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset + * @param DMA2Dx DMA2D Instance + * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) +{ + MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset); +} + +/** + * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset + * @param DMA2Dx DMA2D Instance + * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); +} + +/** + * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits). + * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor + * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor + * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \ + ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue)); +} + +/** + * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) +{ + MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos)); +} + +/** + * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor + * @param DMA2Dx DMA2D Instance + * @retval Red color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); +} + +/** + * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor + * @param DMA2Dx DMA2D Instance + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) +{ + MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos)); +} + +/** + * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor + * @param DMA2Dx DMA2D Instance + * @retval Green color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); +} + +/** + * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor + * @param DMA2Dx DMA2D Instance + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue); +} + +/** + * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor + * @param DMA2Dx DMA2D Instance + * @retval Blue color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); +} + +/** + * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress); +} + +/** + * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); +} + +/** + * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize + * @param DMA2Dx DMA2D Instance + * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos)); +} + +/** + * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize + * @param DMA2Dx DMA2D Instance + * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); +} + +/** + * @brief Set DMA2D background CLUT color mode. + * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @param CLUTColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode); +} + +/** + * @brief Return DMA2D background CLUT color mode. + * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management + * @{ + */ + +/** + * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not + * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)); +} + +/** + * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not + * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)); +} + +/** + * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not + * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)); +} + +/** + * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not + * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)); +} + +/** + * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not + * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)); +} + +/** + * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not + * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)); +} + +/** + * @brief Clear DMA2D Configuration Error Interrupt Flag + * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF); +} + +/** + * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag + * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF); +} + +/** + * @brief Clear DMA2D CLUT Access Error Interrupt Flag + * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF); +} + +/** + * @brief Clear DMA2D Transfer Watermark Interrupt Flag + * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF); +} + +/** + * @brief Clear DMA2D Transfer Complete Interrupt Flag + * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF); +} + +/** + * @brief Clear DMA2D Transfer Error Interrupt Flag + * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF); +} + +/** + * @} + */ + +/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management + * @{ + */ + +/** + * @brief Enable Configuration Error Interrupt + * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); +} + +/** + * @brief Enable CLUT Transfer Complete Interrupt + * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); +} + +/** + * @brief Enable CLUT Access Error Interrupt + * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); +} + +/** + * @brief Enable Transfer Watermark Interrupt + * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); +} + +/** + * @brief Enable Transfer Complete Interrupt + * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); +} + +/** + * @brief Enable Transfer Error Interrupt + * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); +} + +/** + * @brief Disable Configuration Error Interrupt + * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); +} + +/** + * @brief Disable CLUT Transfer Complete Interrupt + * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); +} + +/** + * @brief Disable CLUT Access Error Interrupt + * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); +} + +/** + * @brief Disable Transfer Watermark Interrupt + * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); +} + +/** + * @brief Disable Transfer Complete Interrupt + * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); +} + +/** + * @brief Disable Transfer Error Interrupt + * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); +} + +/** + * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled. + * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)); +} + +/** + * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled. + * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)); +} + +/** + * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled. + * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)); +} + +/** + * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled. + * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)); +} + +/** + * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled. + * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)); +} + +/** + * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled. + * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) +{ + return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)); +} + + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions + * @{ + */ + +ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); +ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); +void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); +void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); +void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); +void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); +uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (DMA2D) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_DMA2D_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_exti.c new file mode 100644 index 00000000000..541de36e24c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_exti.c @@ -0,0 +1,232 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_exti.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief EXTI LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_exti.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Private_Macros + * @{ + */ + +#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) + +#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + + +#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the EXTI registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are de-initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_DeInit(void) +{ + /* Interrupt mask register set to default reset values */ + LL_EXTI_WriteReg(IMR, 0x00000000U); + /* Event mask register set to default reset values */ + LL_EXTI_WriteReg(EMR, 0x00000000U); + /* Rising Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(RTSR, 0x00000000U); + /* Falling Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(FTSR, 0x00000000U); + /* Software interrupt event register set to default reset values */ + LL_EXTI_WriteReg(SWIER, 0x00000000U); + /* Pending register set to default reset values */ + LL_EXTI_WriteReg(PR, 0x01FFFFFFU); + + return SUCCESS; +} + +/** + * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + ErrorStatus status = SUCCESS; + /* Check the parameters */ + assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + + /* ENABLE LineCommand */ + if (EXTI_InitStruct->LineCommand != DISABLE) + { + assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + + /* Configure EXTI Lines in range from 0 to 31 */ + if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT & Event on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + } + } + } + /* DISABLE LineCommand */ + else + { + /* De-configure EXTI Lines in range from 0 to 31 */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + } + return status; +} + +/** + * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval None + */ +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->LineCommand = DISABLE; + EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EXTI) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_exti.h new file mode 100644 index 00000000000..715e1bf2137 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_exti.h @@ -0,0 +1,968 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_exti.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_EXTI_H +#define __STM32F7xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.c index 553408fcc81..446e58121af 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_fmc.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief FMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.h index cf64d2aa9b7..ab781fc7a4e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_fmc.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of FMC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_gpio.c new file mode 100644 index 00000000000..6a433d40a30 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_gpio.c @@ -0,0 +1,325 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_gpio.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief GPIO LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_gpio.h" +#include "stm32f7xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + +/** @addtogroup GPIO_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Private_Macros + * @{ + */ +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) + +#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + +#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + ((__VALUE__) == LL_GPIO_PULL_DOWN)) + +#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + ((__VALUE__) == LL_GPIO_AF_7 ) ||\ + ((__VALUE__) == LL_GPIO_AF_8 ) ||\ + ((__VALUE__) == LL_GPIO_AF_9 ) ||\ + ((__VALUE__) == LL_GPIO_AF_10 ) ||\ + ((__VALUE__) == LL_GPIO_AF_11 ) ||\ + ((__VALUE__) == LL_GPIO_AF_12 ) ||\ + ((__VALUE__) == LL_GPIO_AF_13 ) ||\ + ((__VALUE__) == LL_GPIO_AF_14 ) ||\ + ((__VALUE__) == LL_GPIO_AF_15 )) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize GPIO registers (Registers restored to their default values). + * @param GPIOx GPIO Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: Wrong GPIO Port + */ +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force and Release reset on clock of GPIOx Port */ + if (GPIOx == GPIOA) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA); + } + else if (GPIOx == GPIOB) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB); + } + else if (GPIOx == GPIOC) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC); + } +#if defined(GPIOD) + else if (GPIOx == GPIOD) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD); + } +#endif /* GPIOD */ +#if defined(GPIOE) + else if (GPIOx == GPIOE) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE); + } +#endif /* GPIOE */ +#if defined(GPIOF) + else if (GPIOx == GPIOF) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF); + } +#endif /* GPIOF */ +#if defined(GPIOG) + else if (GPIOx == GPIOG) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG); + } +#endif /* GPIOG */ +#if defined(GPIOH) + else if (GPIOx == GPIOH) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH); + } +#endif /* GPIOH */ +#if defined(GPIOI) + else if (GPIOx == GPIOI) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOI); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI); + } +#endif /* GPIOI */ +#if defined(GPIOJ) + else if (GPIOx == GPIOJ) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOJ); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ); + } +#endif /* GPIOJ */ +#if defined(GPIOK) + else if (GPIOx == GPIOK) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOK); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK); + } +#endif /* GPIOK */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * that contains the configuration information for the specified GPIO peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t pinpos = 0x00000000U; + uint32_t currentpin = 0x00000000U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + pinpos = POSITION_VAL(GPIO_InitStruct->Pin); + + /* Configure the port pins */ + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + { + /* Get current io position */ + currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); + + if (currentpin) + { + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Speed mode parameters */ + assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + + /* Speed mode configuration */ + LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + } + + /* Pull-up Pull down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + { + /* Check Alternate parameter */ + assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + + /* Speed mode configuration */ + if (POSITION_VAL(currentpin) < 0x00000008U) + { + LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + else + { + LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + } + } + pinpos++; + } + + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + + } + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct->Alternate = LL_GPIO_AF_0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_gpio.h new file mode 100644 index 00000000000..e26c9b87d00 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_gpio.h @@ -0,0 +1,1000 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_gpio.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_GPIO_H +#define __STM32F7xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + GPIO_BSRR_BS_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, + (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), + (Speed << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, + (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, + (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)), + (Alternate << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)), + (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, (PinMask << 16)); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_i2c.c new file mode 100644 index 00000000000..2f163d1c01c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_i2c.c @@ -0,0 +1,258 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_i2c.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief I2C LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_i2c.h" +#include "stm32f7xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_LL_Private_Macros + * @{ + */ + +#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP)) + +#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \ + ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE)) + +#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU) + +#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) + +#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \ + ((__VALUE__) == LL_I2C_NACK)) + +#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \ + ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the I2C registers to their default reset values. + * @param I2Cx I2C Instance. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are de-initialized + * - ERROR: I2C registers are not de-initialized + */ +uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx) +{ + ErrorStatus status = SUCCESS; + + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + if (I2Cx == I2C1) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); + } + else if (I2Cx == I2C2) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2); + + } + else if (I2Cx == I2C3) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3); + } +#if defined(I2C4) + else if (I2Cx == I2C4) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C4); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C4); + } +#endif + else + { + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. + * @param I2Cx I2C Instance. + * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are initialized + * - ERROR: Not applicable + */ +uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) +{ + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + /* Check the I2C parameters from I2C_InitStruct */ + assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode)); + assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter)); + assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter)); + assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1)); + assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge)); + assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize)); + + /* Disable the selected I2Cx Peripheral */ + LL_I2C_Disable(I2Cx); + + /*---------------------------- I2Cx CR1 Configuration ------------------------ + * Configure the analog and digital noise filters with parameters : + * - AnalogFilter: I2C_CR1_ANFOFF bit + * - DigitalFilter: I2C_CR1_DNF[3:0] bits + */ + LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter); + + /*---------------------------- I2Cx TIMINGR Configuration -------------------- + * Configure the SDA setup, hold time and the SCL high, low period with parameter : + * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0], + * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits + */ + LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing); + + /* Enable the selected I2Cx Peripheral */ + LL_I2C_Enable(I2Cx); + + /*---------------------------- I2Cx OAR1 Configuration ----------------------- + * Disable, Configure and Enable I2Cx device own address 1 with parameters : + * - OwnAddress1: I2C_OAR1_OA1[9:0] bits + * - OwnAddrSize: I2C_OAR1_OA1MODE bit + */ + LL_I2C_DisableOwnAddress1(I2Cx); + LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize); + LL_I2C_EnableOwnAddress1(I2Cx); + + /*---------------------------- I2Cx MODE Configuration ----------------------- + * Configure I2Cx peripheral mode with parameter : + * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits + */ + LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode); + + /*---------------------------- I2Cx CR2 Configuration ------------------------ + * Configure the ACKnowledge or Non ACKnowledge condition + * after the address receive match code or next received byte with parameter : + * - TypeAcknowledge: I2C_CR2_NACK bit + */ + LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_I2C_InitTypeDef field to default value. + * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval None + */ +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) +{ + /* Set I2C_InitStruct fields to default values */ + I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C; + I2C_InitStruct->Timing = 0U; + I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE; + I2C_InitStruct->DigitalFilter = 0U; + I2C_InitStruct->OwnAddress1 = 0U; + I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK; + I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 || I2C4 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_i2c.h new file mode 100644 index 00000000000..43206d71e5a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_i2c.h @@ -0,0 +1,2207 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_i2c.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_I2C_H +#define __STM32F7xx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_Private_Macros I2C Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ + + uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. + This parameter must be set by referring to the STM32CubeMX Tool and + the helper macro @ref __LL_I2C_CONVERT_TIMINGS() + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */ + + uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION + + This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + + uint32_t DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ + + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE + + This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_I2C_WriteReg function + * @{ + */ +#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ +#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ +#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ +#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ +#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ +#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ +#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ +#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ +#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ +#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ +#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ +#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ +#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ +#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ +#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ +#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ +#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ +#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ +#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ +#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ +#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ +#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ +#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ +#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ +#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ +#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode + * @{ + */ +#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ +#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks + * @{ + */ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length + * @{ + */ +#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ +#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction + * @{ + */ +#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ +#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_MODE Transfer End Mode + * @{ + */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation + * @{ + */ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings + * @{ + */ +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc) + * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc) + * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc) + * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc) + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); +} + +/** + * @brief Configure Noise Filters (Analog and Digital). + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n + * CR1 DNF LL_I2C_ConfigFilters + * @param I2Cx I2C Instance. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); +} + +/** + * @brief Configure Digital Noise Filter. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter + * @param I2Cx I2C Instance. + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); +} + +/** + * @brief Enable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)); +} + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n + * RXDR RXDATA LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) +{ + register uint32_t data_reg_addr = 0U; + + if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) + { + /* return address of TXDR register */ + data_reg_addr = (uint32_t) & (I2Cx->TXDR); + } + else + { + /* return address of RXDR register */ + data_reg_addr = (uint32_t) & (I2Cx->RXDR); + } + + return data_reg_addr; +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); +} + +/** + * @brief Enable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Disable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Check if hardware byte control in slave mode is enabled or disabled. + * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)); +} + + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)); +} + +/** + * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. + * @note Changing this bit is not allowed, when the START bit is set. + * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode + * @param I2Cx I2C Instance. + * @param AddressingMode This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); +} + +/** + * @brief Get the Master addressing mode. + * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + */ +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n + * OAR1 OA1MODE LL_I2C_SetOwnAddress1 + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Enable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Disable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n + * OAR2 OA2MSK LL_I2C_SetOwnAddress2 + * @param I2Cx I2C Instance. + * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. + * @param OwnAddrMask This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS2_NOMASK + * @arg @ref LL_I2C_OWNADDRESS2_MASK01 + * @arg @ref LL_I2C_OWNADDRESS2_MASK02 + * @arg @ref LL_I2C_OWNADDRESS2_MASK03 + * @arg @ref LL_I2C_OWNADDRESS2_MASK04 + * @arg @ref LL_I2C_OWNADDRESS2_MASK05 + * @arg @ref LL_I2C_OWNADDRESS2_MASK06 + * @arg @ref LL_I2C_OWNADDRESS2_MASK07 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) +{ + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)); +} + +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming + * @param I2Cx I2C Instance. + * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @note This parameter is computed with the STM32CubeMX Tool. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) +{ + WRITE_REG(I2Cx->TIMINGR, Timing); +} + +/** + * @brief Get the Timing Prescaler setting. + * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); +} + +/** + * @brief Get the SCL low period setting. + * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); +} + +/** + * @brief Get the SCL high period setting. + * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); +} + +/** + * @brief Get the SDA hold time. + * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); +} + +/** + * @brief Get the SDA setup time. + * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); +} + +/** + * @brief Configure peripheral mode. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n + * CR1 SMBDEN LL_I2C_SetMode + * @param I2Cx I2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n + * CR1 SMBDEN LL_I2C_GetMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)); +} + +/** + * @brief Configure the SMBus Clock Timeout. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @param TimeoutB + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, + uint32_t TimeoutB) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, + TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); +} + +/** + * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); +} + +/** + * @brief Get the SMBus Clock TimeoutA setting. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); +} + +/** + * @brief Set the SMBus Clock TimeoutA mode. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); +} + +/** + * @brief Get the SMBus Clock TimeoutA mode. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); +} + +/** + * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutB is disabled. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Enable the SMBus Clock Timeout. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Disable the SMBus Clock Timeout. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Check if the SMBus Clock Timeout is enabled or disabled. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Disable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Check if the TXIS Interrupt is enabled or disabled. + * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)); +} + +/** + * @brief Enable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Disable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Check if Address match interrupt is enabled or disabled. + * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)); +} + +/** + * @brief Enable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Disable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Check if Not acknowledge received interrupt is enabled or disabled. + * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)); +} + +/** + * @brief Enable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Disable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Check if STOP detection interrupt is enabled or disabled. + * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)); +} + +/** + * @brief Enable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Disable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Check if Transfer Complete interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)); +} + +/** + * @brief Enable Error interrupts. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Disable Error interrupts. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)); +} + +/** + * @brief Indicate the status of Transmit interrupt flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)); +} + +/** + * @brief Indicate the status of Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the received slave address matched with one of the enabled slave address. + * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)); +} + +/** + * @brief Indicate the status of Not Acknowledge received flag. + * @note RESET: Clear default value. + * SET: When a NACK is received after a byte transmission. + * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)); +} + +/** + * @brief Indicate the status of Stop detection flag. + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. + * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=1 and NBYTES date have been transferred. + * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag (slave mode). + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When the received PEC does not match with the PEC register content. + * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When a timeout or extended clock timeout occurs. + * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When SMBus host configuration, SMBus alert enabled and + * a falling edge event occurs on SMBA pin. + * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)); +} + +/** + * @brief Clear Address Matched flag. + * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); +} + +/** + * @brief Clear Not Acknowledge flag. + * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); +} + +/** + * @brief Clear Stop detection flag. + * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); +} + +/** + * @brief Clear Transmit data register empty flag (TXE). + * @note This bit can be clear by software in order to flush the transmit data register (TXDR). + * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) +{ + WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); +} + +/** + * @brief Clear SMBus PEC error flag. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); +} + +/** + * @brief Clear SMBus Alert flag. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable automatic STOP condition generation (master mode). + * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. + * This bit has no effect in slave mode or when RELOAD bit is set. + * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Disable automatic STOP condition generation (master mode). + * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. + * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Check if automatic STOP condition is enabled or disabled. + * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)); +} + +/** + * @brief Enable reload mode (master mode). + * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. + * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Disable reload mode (master mode). + * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). + * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Check if reload mode is enabled or disabled. + * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)); +} + +/** + * @brief Configure the number of bytes for transfer. + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize + * @param I2Cx I2C Instance. + * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Get the number of bytes configured for transfer. + * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @note Usage in Slave mode only. + * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR2 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_STOP); +} + +/** + * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master sends the complete 10bit slave address read sequence : + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master only sends the first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. + * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)); +} + +/** + * @brief Configure the transfer direction (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest + * @param I2Cx I2C Instance. + * @param TransferRequest This parameter can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); +} + +/** + * @brief Get the transfer direction requested (master mode). + * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); +} + +/** + * @brief Configure the slave address for transfer (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr + * @param I2Cx I2C Instance. + * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); +} + +/** + * @brief Get the slave address programmed for transfer. + * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n + * CR2 ADD10 LL_I2C_HandleTransfer\n + * CR2 RD_WRN LL_I2C_HandleTransfer\n + * CR2 START LL_I2C_HandleTransfer\n + * CR2 STOP LL_I2C_HandleTransfer\n + * CR2 RELOAD LL_I2C_HandleTransfer\n + * CR2 NBYTES LL_I2C_HandleTransfer\n + * CR2 AUTOEND LL_I2C_HandleTransfer\n + * CR2 HEAD10R LL_I2C_HandleTransfer + * @param I2Cx I2C Instance. + * @param SlaveAddr Specifies the slave address to be programmed. + * @param SlaveAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRSLAVE_7BIT + * @arg @ref LL_I2C_ADDRSLAVE_10BIT + * @param TransferSize Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=255. + * @param EndMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_RELOAD + * @arg @ref LL_I2C_MODE_AUTOEND + * @arg @ref LL_I2C_MODE_SOFTEND + * @arg @ref LL_I2C_MODE_SMBUS_RELOAD + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC + * @param Request This parameter can be one of the following values: + * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP + * @arg @ref LL_I2C_GENERATE_STOP + * @arg @ref LL_I2C_GENERATE_START_READ + * @arg @ref LL_I2C_GENERATE_START_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE + * @retval None + */ +__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, + SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request); +} + +/** + * @brief Indicate the value of transfer direction (slave mode). + * @note RESET: Write transfer, Slave enters in receiver mode. + * SET: Read transfer, Slave enters in transmitter mode. + * @rmtoll ISR DIR LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); +} + +/** + * @brief Return the slave matched address. + * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); +} + +/** + * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. + * This bit has no effect when RELOAD bit is set. + * This bit has no effect in device mode when SBC bit is not set. + * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); +} + +/** + * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll PECR PEC LL_I2C_GetSMBusPEC + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF +*/ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); +} + +/** + * @brief Read Receive Data register. + * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + WRITE_REG(I2Cx->TXDR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); +uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 || I2C4 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_iwdg.h new file mode 100644 index 00000000000..b00eadd84c5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_iwdg.h @@ -0,0 +1,363 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_iwdg.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of IWDG LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_IWDG_H +#define __STM32F7xx_LL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(IWDG) + +/** @defgroup IWDG_LL IWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants + * @{ + */ + +#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ +#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ +#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ +#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_IWDG_ReadReg function + * @{ + */ +#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ +#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ +#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */ + +/** + * @} + */ + +/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider + * @{ + */ +#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ +#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ +#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ +#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ +#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ +#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ +#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions + * @{ + */ +/** @defgroup IWDG_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Start the Independent Watchdog + * @note Except if the hardware watchdog option is selected + * @rmtoll KR KEY LL_IWDG_Enable + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE); +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * @rmtoll KR KEY LL_IWDG_ReloadCounter + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD); +} + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_EnableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); +} + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_DisableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); +} + +/** + * @brief Select the prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_SetPrescaler + * @param IWDGx IWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) +{ + WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); +} + +/** + * @brief Get the selected prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_GetPrescaler + * @param IWDGx IWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + */ +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +{ + return (uint32_t)(READ_REG(IWDGx->PR)); +} + +/** + * @brief Specify the IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_SetReloadCounter + * @param IWDGx IWDG Instance + * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) +{ + WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); +} + +/** + * @brief Get the specified IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_GetReloadCounter + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +{ + return (uint32_t)(READ_REG(IWDGx->RLR)); +} + +/** + * @brief Specify high limit of the window value to be compared to the down-counter. + * @rmtoll WINR WIN LL_IWDG_SetWindow + * @param IWDGx IWDG Instance + * @param Window Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) +{ + WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window); +} + +/** + * @brief Get the high limit of the window value specified. + * @rmtoll WINR WIN LL_IWDG_GetWindow + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) +{ + return (uint32_t)(READ_REG(IWDGx->WINR)); +} + +/** + * @} + */ + +/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if flag Prescaler Value Update is set or not + * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)); +} + +/** + * @brief Check if flag Reload Value Update is set or not + * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)); +} + +/** + * @brief Check if flag Window Value Update is set or not + * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)); +} + +/** + * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not + * @rmtoll SR PVU LL_IWDG_IsReady\n + * SR WVU LL_IWDG_IsReady\n + * SR RVU LL_IWDG_IsReady + * @param IWDGx IWDG Instance + * @retval State of bits (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* IWDG) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_IWDG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.c new file mode 100644 index 00000000000..143af126a35 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.c @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_lptim.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief LPTIM LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_lptim.h" +#include "stm32f7xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (LPTIM1) || defined (LPTIM2) + +/** @addtogroup LPTIM_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPTIM_LL_Private_Macros + * @{ + */ +#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + +#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + +#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + +#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LPTIM_LL_Exported_Functions + * @{ + */ + +/** @addtogroup LPTIM_LL_EF_Init + * @{ + */ + +/** + * @brief Set LPTIMx registers to their reset values. + * @param LPTIMx LP Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx registers are de-initialized + * - ERROR: invalid LPTIMx instance + */ +ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx) +{ + ErrorStatus result = SUCCESS; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + + if (LPTIMx == LPTIM1) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1); + } +#if defined(LPTIM2) + else if (LPTIMx == LPTIM2) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2); + } +#endif + else + { + result = ERROR; + } + + return result; +} + +/** + * @brief Set each fields of the LPTIM_InitStruct structure to its default + * value. + * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure + * @retval None + */ +void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct) +{ + /* Set the default configuration */ + LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL; + LPTIM_InitStruct->Prescaler = LL_LPTIM_PRESCALER_DIV1; + LPTIM_InitStruct->Waveform = LL_LPTIM_OUTPUT_WAVEFORM_PWM; + LPTIM_InitStruct->Polarity = LL_LPTIM_OUTPUT_POLARITY_REGULAR; +} + +/** + * @brief Configure the LPTIMx peripheral according to the specified parameters. + * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled. + * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable(). + * @param LPTIMx LP Timer Instance + * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx instance has been initialized + * - ERROR: LPTIMx instance hasn't been initialized + */ +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct) +{ + ErrorStatus result = SUCCESS; + + /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled + (ENABLE bit is reset to 0). + */ + if (LL_LPTIM_IsEnabled(LPTIMx)) + { + result = ERROR; + } + else + { + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); + + /* Set CKSEL bitfield according to ClockSource value */ + /* Set PRESC bitfield according to Prescaler value */ + /* Set WAVE bitfield according to Waveform value */ + /* Set WAVEPOL bitfield according to Polarity value */ + MODIFY_REG(LPTIMx->CFGR, + (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL), + LPTIM_InitStruct->ClockSource | \ + LPTIM_InitStruct->Prescaler | \ + LPTIM_InitStruct->Waveform | \ + LPTIM_InitStruct->Polarity); + } + + return result; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (LPTIM1) || defined (LPTIM2) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h new file mode 100644 index 00000000000..6800983f55e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h @@ -0,0 +1,1382 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_lptim.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of LPTIM LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_LPTIM_H +#define __STM32F7xx_LL_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ +#if defined (LPTIM1) + +/** @defgroup LPTIM_LL LPTIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure + * @{ + */ + +/** + * @brief LPTIM Init structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. + This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE. + + This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/ + + uint32_t Prescaler; /*!< Specifies the prescaler division ratio. + This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER. + + This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/ + + uint32_t Waveform; /*!< Specifies the waveform shape. + This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM. + + This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ + + uint32_t Polarity; /*!< Specifies waveform polarity. + This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ +} LL_LPTIM_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants + * @{ + */ + +/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_LPTIM_ReadReg function + * @{ + */ +#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */ +#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ +#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ +#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ +#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ +#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ +#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions + * @{ + */ +#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */ +#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */ +#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */ +#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */ +#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */ +#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */ +#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode + * @{ + */ +#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in LPTIM register + * @param __INSTANCE__ LPTIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration + * @{ + */ + +/** + * @brief Enable the LPTIM instance + * @note After setting the ENABLE bit, a delay of two counter clock is needed + * before the LPTIM instance is actually enabled. + * @rmtoll CR ENABLE LL_LPTIM_Enable + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); +} + +/** + * @brief Disable the LPTIM instance + * @rmtoll CR ENABLE LL_LPTIM_Disable + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); +} + +/** + * @brief Indicates whether the LPTIM instance is enabled. + * @rmtoll CR ENABLE LL_LPTIM_IsEnabled + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE)); +} + +/** + * @brief Starts the LPTIM counter in the desired mode. + * @note LPTIM instance must be enabled before starting the counter. + * @note It is possible to change on the fly from One Shot mode to + * Continuous mode. + * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n + * CR SNGSTRT LL_LPTIM_StartCounter + * @param LPTIMx Low-Power Timer instance + * @param OperatingMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS + * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode) +{ + MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode); +} + + +/** + * @brief Set the LPTIM registers update mode (enable/disable register preload) + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @param UpdateMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode); +} + +/** + * @brief Get the LPTIM registers update mode + * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); +} + +/** + * @brief Set the auto reload value + * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled + * @note After a write to the LPTIMx_ARR register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the ARROK flag be set, will + * lead to unpredictable results. + * @note autoreload value be strictly greater than the compare value. + * @rmtoll ARR ARR LL_LPTIM_SetAutoReload + * @param LPTIMx Low-Power Timer instance + * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload) +{ + MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload); +} + +/** + * @brief Get actual auto reload value + * @rmtoll ARR ARR LL_LPTIM_GetAutoReload + * @param LPTIMx Low-Power Timer instance + * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); +} + +/** + * @brief Set the compare value + * @note After a write to the LPTIMx_CMP register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the CMPOK flag be set, will + * lead to unpredictable results. + * @rmtoll CMP CMP LL_LPTIM_SetCompare + * @param LPTIMx Low-Power Timer instance + * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue) +{ + MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue); +} + +/** + * @brief Get actual compare value + * @rmtoll CMP CMP LL_LPTIM_GetCompare + * @param LPTIMx Low-Power Timer instance + * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP)); +} + +/** + * @brief Get actual counter value + * @note When the LPTIM instance is running with an asynchronous clock, reading + * the LPTIMx_CNT register may return unreliable values. So in this case + * it is necessary to perform two consecutive read accesses and verify + * that the two returned values are identical. + * @rmtoll CNT CNT LL_LPTIM_GetCounter + * @param LPTIMx Low-Power Timer instance + * @retval Counter value + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); +} + +/** + * @brief Set the counter mode (selection of the LPTIM counter clock source). + * @note The counter mode can be set only when the LPTIM instance is disabled. + * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode + * @param LPTIMx Low-Power Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode); +} + +/** + * @brief Get the counter mode + * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); +} + +/** + * @brief Configure the LPTIM instance output (LPTIMx_OUT) + * @note This function must be called when the LPTIM instance is disabled. + * @note Regarding the LPTIM output polarity the change takes effect + * immediately, so the output default value will change immediately after + * the polarity is re-configured, even before the timer is enabled. + * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n + * CFGR WAVPOL LL_LPTIM_ConfigOutput + * @param LPTIMx Low-Power Timer instance + * @param Waveform This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity); +} + +/** + * @brief Set waveform shape + * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform + * @param LPTIMx Low-Power Timer instance + * @param Waveform This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform); +} + +/** + * @brief Get actual waveform shape + * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); +} + +/** + * @brief Set output polarity + * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity + * @param LPTIMx Low-Power Timer instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity); +} + +/** + * @brief Get actual output polarity + * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL)); +} + +/** + * @brief Set actual prescaler division ratio. + * @note This function must be called when the LPTIM instance is disabled. + * @note When the LPTIM is configured to be clocked by an internal clock source + * and the LPTIM counter is configured to be updated by active edges + * detected on the LPTIM external Input1, the internal clock provided to + * the LPTIM must be not be prescaled. + * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler + * @param LPTIMx Low-Power Timer instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_LPTIM_PRESCALER_DIV1 + * @arg @ref LL_LPTIM_PRESCALER_DIV2 + * @arg @ref LL_LPTIM_PRESCALER_DIV4 + * @arg @ref LL_LPTIM_PRESCALER_DIV8 + * @arg @ref LL_LPTIM_PRESCALER_DIV16 + * @arg @ref LL_LPTIM_PRESCALER_DIV32 + * @arg @ref LL_LPTIM_PRESCALER_DIV64 + * @arg @ref LL_LPTIM_PRESCALER_DIV128 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler); +} + +/** + * @brief Get actual prescaler division ratio. + * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_PRESCALER_DIV1 + * @arg @ref LL_LPTIM_PRESCALER_DIV2 + * @arg @ref LL_LPTIM_PRESCALER_DIV4 + * @arg @ref LL_LPTIM_PRESCALER_DIV8 + * @arg @ref LL_LPTIM_PRESCALER_DIV16 + * @arg @ref LL_LPTIM_PRESCALER_DIV32 + * @arg @ref LL_LPTIM_PRESCALER_DIV64 + * @arg @ref LL_LPTIM_PRESCALER_DIV128 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); +} + + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration + * @{ + */ + +/** + * @brief Enable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note The first trigger event will start the timer, any successive trigger + * event will reset the counter and the timer will restart. + * @note The timeout value corresponds to the compare value; if no trigger + * occurs within the expected time frame, the MCU is waked-up by the + * compare match event. + * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT); +} + +/** + * @brief Disable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note A trigger event arriving when the timer is already started will be + * ignored. + * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT); +} + +/** + * @brief Indicate whether the timeout function is enabled. + * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT)); +} + +/** + * @brief Start the LPTIM counter + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN); +} + +/** + * @brief Configure the external trigger used as a trigger event for the LPTIM. + * @note This function must be called when the LPTIM instance is disabled. + * @note An internal clock source must be present when a digital filter is + * required for the trigger. + * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n + * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n + * CFGR TRIGEN LL_LPTIM_ConfigTrigger + * @param LPTIMx Low-Power Timer instance + * @param Source This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 + * @param Filter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_FILTER_NONE + * @arg @ref LL_LPTIM_TRIG_FILTER_2 + * @arg @ref LL_LPTIM_TRIG_FILTER_4 + * @arg @ref LL_LPTIM_TRIG_FILTER_8 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING + * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity); +} + +/** + * @brief Get actual external trigger source. + * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); +} + +/** + * @brief Get actual external trigger filter. + * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_FILTER_NONE + * @arg @ref LL_LPTIM_TRIG_FILTER_2 + * @arg @ref LL_LPTIM_TRIG_FILTER_4 + * @arg @ref LL_LPTIM_TRIG_FILTER_8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); +} + +/** + * @brief Get actual external trigger polarity. + * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING + * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration + * @{ + */ + +/** + * @brief Set the source of the clock used by the LPTIM instance. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource + * @param LPTIMx Low-Power Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource); +} + +/** + * @brief Get actual LPTIM instance clock source. + * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); +} + +/** + * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source. + * @note This function must be called when the LPTIM instance is disabled. + * @note When both external clock signal edges are considered active ones, + * the LPTIM must also be clocked by an internal clock source with a + * frequency equal to at least four times the external clock frequency. + * @note An internal clock source must be present when a digital filter is + * required for external clock. + * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n + * CFGR CKPOL LL_LPTIM_ConfigClock + * @param LPTIMx Low-Power Timer instance + * @param ClockFilter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_FILTER_NONE + * @arg @ref LL_LPTIM_CLK_FILTER_2 + * @arg @ref LL_LPTIM_CLK_FILTER_4 + * @arg @ref LL_LPTIM_CLK_FILTER_8 + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING + * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity); +} + +/** + * @brief Get actual clock polarity + * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING + * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); +} + +/** + * @brief Get actual clock digital filter + * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_FILTER_NONE + * @arg @ref LL_LPTIM_CLK_FILTER_2 + * @arg @ref LL_LPTIM_CLK_FILTER_4 + * @arg @ref LL_LPTIM_CLK_FILTER_8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode + * @{ + */ + +/** + * @brief Configure the encoder mode. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING + * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode); +} + +/** + * @brief Get actual encoder mode. + * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING + * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); +} + +/** + * @brief Enable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @note In this mode the LPTIM instance must be clocked by an internal clock + * source. Also, the prescaler division ratio must be equal to 1. + * @note LPTIM instance must be configured in continuous mode prior enabling + * the encoder mode. + * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC); +} + +/** + * @brief Disable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC); +} + +/** + * @brief Indicates whether the LPTIM operates in encoder mode. + * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear the compare match flag (CMPMCF) + * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF); +} + +/** + * @brief Inform application whether a compare match interrupt has occurred. + * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM)); +} + +/** + * @brief Clear the autoreload match flag (ARRMCF) + * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); +} + +/** + * @brief Inform application whether a autoreload match interrupt has occured. + * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM)); +} + +/** + * @brief Clear the external trigger valid edge flag(EXTTRIGCF). + * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF); +} + +/** + * @brief Inform application whether a valid edge on the selected external trigger input has occurred. + * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG)); +} + +/** + * @brief Clear the compare register update interrupt flag (CMPOKCF). + * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated. + * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK)); +} + +/** + * @brief Clear the autoreload register update interrupt flag (ARROKCF). + * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated. + * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK)); +} + +/** + * @brief Clear the counter direction change to up interrupt flag (UPCF). + * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode). + * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP)); +} + +/** + * @brief Clear the counter direction change to down interrupt flag (DOWNCF). + * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode). + * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable compare match interrupt (CMPMIE). + * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE); +} + +/** + * @brief Disable compare match interrupt (CMPMIE). + * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE); +} + +/** + * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled. + * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE)); +} + +/** + * @brief Enable autoreload match interrupt (ARRMIE). + * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE); +} + +/** + * @brief Disable autoreload match interrupt (ARRMIE). + * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE); +} + +/** + * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled. + * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE)); +} + +/** + * @brief Enable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE); +} + +/** + * @brief Disable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE); +} + +/** + * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled. + * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE)); +} + +/** + * @brief Enable compare register write completed interrupt (CMPOKIE). + * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE); +} + +/** + * @brief Disable compare register write completed interrupt (CMPOKIE). + * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE); +} + +/** + * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled. + * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE)); +} + +/** + * @brief Enable autoreload register write completed interrupt (ARROKIE). + * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE); +} + +/** + * @brief Disable autoreload register write completed interrupt (ARROKIE). + * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE); +} + +/** + * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. + * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE)); +} + +/** + * @brief Enable direction change to up interrupt (UPIE). + * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE); +} + +/** + * @brief Disable direction change to up interrupt (UPIE). + * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE); +} + +/** + * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. + * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE)); +} + +/** + * @brief Enable direction change to down interrupt (DOWNIE). + * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE); +} + +/** + * @brief Disable direction change to down interrupt (DOWNIE). + * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE); +} + +/** + * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. + * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); +void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPTIM1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_LPTIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_pwr.c new file mode 100644 index 00000000000..c53503e8563 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_pwr.c @@ -0,0 +1,105 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_pwr.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief PWR LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_pwr.h" +#include "stm32f7xx_ll_bus.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_LL_Exported_Functions + * @{ + */ + +/** @addtogroup PWR_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the PWR registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PWR registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_PWR_DeInit(void) +{ + /* Force reset of PWR clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR); + + /* Release reset of PWR clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR); + + WRITE_REG(PWR->CR2, (PWR_CR2_CWUPF1 | PWR_CR2_CWUPF2 | PWR_CR2_CWUPF3 | PWR_CR2_CWUPF4 | PWR_CR2_CWUPF5 | PWR_CR2_CWUPF6)); + + return SUCCESS; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined(PWR) */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_pwr.h new file mode 100644 index 00000000000..f84281e9608 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_pwr.h @@ -0,0 +1,1036 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_pwr.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_PWR_H +#define __STM32F7xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR1_CSBF PWR_CR1_CSBF /*!< Clear standby flag */ + +#define LL_PWR_CR2_CWUF6 PWR_CR2_CWUF6 /*!< Clear WKUP pin 6 */ +#define LL_PWR_CR2_CWUF5 PWR_CR2_CWUF5 /*!< Clear WKUP pin 5 */ +#define LL_PWR_CR2_CWUF4 PWR_CR2_CWUF4 /*!< Clear WKUP pin 4 */ +#define LL_PWR_CR2_CWUF3 PWR_CR2_CWUF3 /*!< Clear WKUP pin 3 */ +#define LL_PWR_CR2_CWUF2 PWR_CR2_CWUF2 /*!< Clear WKUP pin 2 */ +#define LL_PWR_CR2_CWUF1 PWR_CR2_CWUF1 /*!< Clear WKUP pin 1 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR1_WUIF PWR_CSR1_WUIF /*!< Wakeup flag */ +#define LL_PWR_CSR1_SBF PWR_CSR1_SBF /*!< Standby flag */ +#define LL_PWR_CSR1_PVDO PWR_CSR1_PVDO /*!< Power voltage detector output flag */ +#define LL_PWR_CSR1_BRR PWR_CSR1_BRR /*!< Backup Regulator ready flag */ +#define LL_PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY /*!< Voltage scaling select flag */ +#define LL_PWR_CSR1_ODRDY PWR_CSR1_ODRDY /*!< Over-drive mode ready */ +#define LL_PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY /*!< Over-drive mode switching ready */ +#define LL_PWR_CSR1_UDRDY PWR_CSR1_UDRDY /*!< Under-drive ready flag */ + +#define LL_PWR_CSR2_EWUP1 PWR_CSR2_EWUP1 /*!< Enable WKUP pin 1 */ +#define LL_PWR_CSR2_EWUP2 PWR_CSR2_EWUP2 /*!< Enable WKUP pin 2 */ +#define LL_PWR_CSR2_EWUP3 PWR_CSR2_EWUP3 /*!< Enable WKUP pin 3 */ +#define LL_PWR_CSR2_EWUP4 PWR_CSR2_EWUP4 /*!< Enable WKUP pin 4 */ +#define LL_PWR_CSR2_EWUP5 PWR_CSR2_EWUP5 /*!< Enable WKUP pin 5 */ +#define LL_PWR_CSR2_EWUP6 PWR_CSR2_EWUP6 /*!< Enable WKUP pin 6 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode (with main Regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR1_MRUDS | PWR_CR1_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU PWR_CR1_LPDS /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY PWR_CR1_PDDS /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_CR1_VOS_0 +#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_CR1_VOS_1 +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0 | PWR_CR1_VOS_1) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 2.0 V */ +#define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */ +#define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.3 V */ +#define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.5 V */ +#define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.6 V */ +#define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.8 V */ +#define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< Voltage threshold detected by PVD 2.9 V */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1 /*!< WKUP pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2 /*!< WKUP pin 2 : PA2 */ +#define LL_PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3 /*!< WKUP pin 3 : PC1 */ +#define LL_PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4 /*!< WKUP pin 4 : PC13 */ +#define LL_PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5 /*!< WKUP pin 5 : PI8 */ +#define LL_PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6 /*!< WKUP pin 6 : PI11 */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Under Drive Mode + * @rmtoll CR1 UDEN LL_PWR_EnableUnderDriveMode + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main Regulator or the low power Regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage Regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_UDEN); +} + +/** + * @brief Disable Under Drive Mode + * @rmtoll CR1 UDEN LL_PWR_DisableUnderDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_UDEN); +} + +/** + * @brief Check if Under Drive Mode is enabled + * @rmtoll CR1 UDEN LL_PWR_IsEnabledUnderDriveMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_UDEN) == (PWR_CR1_UDEN)); +} + +/** + * @brief Enable Over drive switching + * @rmtoll CR1 ODSWEN LL_PWR_EnableOverDriveSwitching + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_ODSWEN); +} + +/** + * @brief Disable Over drive switching + * @rmtoll CR1 ODSWEN LL_PWR_DisableOverDriveSwitching + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_ODSWEN); +} + +/** + * @brief Check if Over drive switching is enabled + * @rmtoll CR1 ODSWEN LL_PWR_IsEnabledOverDriveSwitching + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_ODSWEN) == (PWR_CR1_ODSWEN)); +} + +/** + * @brief Enable Over drive Mode + * @rmtoll CR1 ODEN LL_PWR_EnableOverDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_ODEN); +} + +/** + * @brief Disable Over drive Mode + * @rmtoll CR1 ODEN LL_PWR_DisableOverDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_ODEN); +} + +/** + * @brief Check if Over drive switching is enabled + * @rmtoll CR1 ODEN LL_PWR_IsEnabledOverDriveMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_ODEN) == (PWR_CR1_ODEN)); +} + +/** + * @brief Set the main internal Regulator output voltage + * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); +} + +/** + * @brief Get the main internal Regulator output voltage + * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); +} + +/** + * @brief Enable Main Regulator in deepsleep under-drive Mode + * @rmtoll CR1 MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_MRUDS); +} + +/** + * @brief Disable Main Regulator in deepsleep under-drive Mode + * @rmtoll CR1 MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_MRUDS); +} + +/** + * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled + * @rmtoll CR1 MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_MRUDS) == (PWR_CR1_MRUDS)); +} + +/** + * @brief Enable Low Power Regulator in deepsleep under-drive Mode + * @rmtoll CR1 LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_LPUDS); +} + +/** + * @brief Disable Low Power Regulator in deepsleep under-drive Mode + * @rmtoll CR1 LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPUDS); +} + +/** + * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled + * @rmtoll CR1 LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_LPUDS) == (PWR_CR1_LPUDS)); +} + +/** + * @brief Enable the Flash Power Down in Stop Mode + * @rmtoll CR1 FPDS LL_PWR_EnableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_FPDS); +} + +/** + * @brief Disable the Flash Power Down in Stop Mode + * @rmtoll CR1 FPDS LL_PWR_DisableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_FPDS); +} + +/** + * @brief Check if the Flash Power Down in Stop Mode is enabled + * @rmtoll CR1 FPDS LL_PWR_IsEnabledFlashPowerDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_FPDS) == (PWR_CR1_FPDS)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)); +} + +/** + * @brief Enable Backup Regulator + * @rmtoll CSR1 BRE LL_PWR_EnableBkUpRegulator + * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and + * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup + * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, + * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that + * the data written into the RAM will be maintained in the Standby and VBAT modes. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) +{ + SET_BIT(PWR->CSR1, PWR_CSR1_BRE); +} + +/** + * @brief Disable Backup Regulator + * @rmtoll CSR1 BRE LL_PWR_DisableBkUpRegulator + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) +{ + CLEAR_BIT(PWR->CSR1, PWR_CSR1_BRE); +} + +/** + * @brief Check if the backup Regulator is enabled + * @rmtoll CSR1 BRE LL_PWR_IsEnabledBkUpRegulator + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_BRE) == (PWR_CSR1_BRE)); +} + +/** + * @brief Set voltage Regulator mode during deep sleep mode + * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode); +} + +/** + * @brief Get voltage Regulator mode during deep sleep mode + * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS)); +} + +/** + * @brief Set Power Down mode when CPU enters deepsleep + * @rmtoll CR1 PDDS LL_PWR_SetPowerMode\n + * CR1 LPDS LL_PWR_SetPowerMode\n + * CR1 FPDS LL_PWR_SetPowerMode\n + * CR1 LPUDS LL_PWR_SetPowerMode\n + * CR1 MRUDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE + * @arg @ref LL_PWR_MODE_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS), PDMode); +} + +/** + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR1 PDDS LL_PWR_GetPowerMode\n + * CR1 LPDS LL_PWR_GetPowerMode\n + * CR1 FPDS LL_PWR_GetPowerMode\n + * CR1 LPUDS LL_PWR_GetPowerMode\n + * CR1 MRUDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS))); +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR1 PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR1 PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR1 PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR1 PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR1 PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_PVDE) == (PWR_CR1_PVDE)); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR2 EWUP1 LL_PWR_EnableWakeUpPin\n + * CSR2 EWUP2 LL_PWR_EnableWakeUpPin\n + * CSR2 EWUP3 LL_PWR_EnableWakeUpPin\n + * CSR2 EWUP4 LL_PWR_EnableWakeUpPin\n + * CSR2 EWUP5 LL_PWR_EnableWakeUpPin\n + * CSR2 EWUP6 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR2, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR2 EWUP1 LL_PWR_DisableWakeUpPin\n + * CSR2 EWUP2 LL_PWR_DisableWakeUpPin\n + * CSR2 EWUP3 LL_PWR_DisableWakeUpPin\n + * CSR2 EWUP4 LL_PWR_DisableWakeUpPin\n + * CSR2 EWUP5 LL_PWR_DisableWakeUpPin\n + * CSR2 EWUP6 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR2, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR2 EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * CSR2 EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * CSR2 EWUP3 LL_PWR_IsEnabledWakeUpPin\n + * CSR2 EWUP4 LL_PWR_IsEnabledWakeUpPin\n + * CSR2 EWUP5 LL_PWR_IsEnabledWakeUpPin\n + * CSR2 EWUP6 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CSR2, WakeUpPin) == (WakeUpPin)); +} + +/** + * @brief Set the Wake-Up pin polarity low for the event detection + * @rmtoll CR2 WUPP1 LL_PWR_SetWakeUpPinPolarityLow\n + * CR2 WUPP2 LL_PWR_SetWakeUpPinPolarityLow\n + * CR2 WUPP3 LL_PWR_SetWakeUpPinPolarityLow\n + * CR2 WUPP4 LL_PWR_SetWakeUpPinPolarityLow\n + * CR2 WUPP5 LL_PWR_SetWakeUpPinPolarityLow\n + * CR2 WUPP6 LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CR2, WakeUpPin); +} + +/** + * @brief Set the Wake-Up pin polarity high for the event detection + * @rmtoll CR2 WUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR2 WUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR2 WUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR2 WUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR2 WUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR2 WUPP6 LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CR2, WakeUpPin); +} + +/** + * @brief Get the Wake-Up pin polarity for the event detection + * @rmtoll CR2 WUPP1 LL_PWR_IsWakeUpPinPolarityLow\n + * CR2 WUPP2 LL_PWR_IsWakeUpPinPolarityLow\n + * CR2 WUPP3 LL_PWR_IsWakeUpPinPolarityLow\n + * CR2 WUPP4 LL_PWR_IsWakeUpPinPolarityLow\n + * CR2 WUPP5 LL_PWR_IsWakeUpPinPolarityLow\n + * CR2 WUPP6 LL_PWR_IsWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CR2, WakeUpPin) == (WakeUpPin)); +} + +/** + * @brief Enable Internal WakeUp + * @rmtoll CSR1 EIWUP LL_PWR_EnableInternalWakeUp + * @note This API must be used when RTC events (Alarm A or Alarm B, RTC Tamper, RTC TimeStamp + * or RTC Wakeup time) are used to wake up the system from Standby mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableInternalWakeUp(void) +{ + SET_BIT(PWR->CSR1, PWR_CSR1_EIWUP); +} + +/** + * @brief Disable Internal WakeUp + * @rmtoll CSR1 EIWUP LL_PWR_DisableInternalWakeUp + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableInternalWakeUp(void) +{ + CLEAR_BIT(PWR->CSR1, PWR_CSR1_EIWUP); +} + +/** + * @brief Check if the Internal WakeUp functionality is enabled + * @rmtoll CSR1 EIWUP LL_PWR_IsEnabledInternalWakeUp + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternalWakeUp(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_EIWUP) == (PWR_CSR1_EIWUP)); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag 6 + * @rmtoll CSR2 WUPF6 LL_PWR_IsActiveFlag_WU6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF6) == (PWR_CSR2_WUPF6)); +} + +/** + * @brief Get Wake-up Flag 5 + * @rmtoll CSR2 WUPF5 LL_PWR_IsActiveFlag_WU5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF5) == (PWR_CSR2_WUPF5)); +} + +/** + * @brief Get Wake-up Flag 4 + * @rmtoll CSR2 WUPF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF4) == (PWR_CSR2_WUPF4)); +} + +/** + * @brief Get Wake-up Flag 3 + * @rmtoll CSR2 WUPF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF3) == (PWR_CSR2_WUPF3)); +} + +/** + * @brief Get Wake-up Flag 2 + * @rmtoll CSR2 WUPF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF2) == (PWR_CSR2_WUPF2)); +} + +/** + * @brief Get Wake-up Flag 1 + * @rmtoll CSR2 WUPF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF1) == (PWR_CSR2_WUPF1)); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR1 SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_SBF) == (PWR_CSR1_SBF)); +} + +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)); +} + +/** + * @brief Get Backup Regulator ready Flag + * @rmtoll CSR1 BRR LL_PWR_IsActiveFlag_BRR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_BRR) == (PWR_CSR1_BRR)); +} + +/** + * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level + * @rmtoll CSR1 VOSRDY LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_VOSRDY) == (PWR_CSR1_VOSRDY)); +} + +/** + * @brief Indicate whether the Over-Drive mode is ready or not + * @rmtoll CSR1 ODRDY LL_PWR_IsActiveFlag_OD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_ODRDY) == (PWR_CSR1_ODRDY)); +} + +/** + * @brief Indicate whether the Over-Drive mode switching is ready or not + * @rmtoll CSR1 ODSWRDY LL_PWR_IsActiveFlag_ODSW + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_ODSWRDY) == (PWR_CSR1_ODSWRDY)); +} + +/** + * @brief Indicate whether the Under-Drive mode is ready or not + * @rmtoll CSR1 UDRDY LL_PWR_IsActiveFlag_UD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_UDRDY) == (PWR_CSR1_UDRDY)); +} + +/** + * @brief Clear Standby Flag + * @rmtoll CR1 CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_CSBF); +} + +/** + * @brief Clear Wake-up Flag 6 + * @rmtoll CR2 CWUF6 LL_PWR_ClearFlag_WU6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF6); +} + +/** + * @brief Clear Wake-up Flag 5 + * @rmtoll CR2 CWUF5 LL_PWR_ClearFlag_WU5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF5); +} + +/** + * @brief Clear Wake-up Flag 4 + * @rmtoll CR2 CWUF4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF4); +} + +/** + * @brief Clear Wake-up Flag 3 + * @rmtoll CR2 CWUF3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF3); +} + +/** + * @brief Clear Wake-up Flag 2 + * @rmtoll CR2 CWUF2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF2); +} + +/** + * @brief Clear Wake-up Flag 1 + * @rmtoll CR2 CWUF1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF1); +} + +/** + * @brief Clear Under-Drive ready Flag + * @rmtoll CSR1 UDRDY LL_PWR_ClearFlag_UD + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_UD(void) +{ + WRITE_REG(PWR->CSR1, PWR_CSR1_UDRDY); +} + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.c new file mode 100644 index 00000000000..8003e81dad0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.c @@ -0,0 +1,1581 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_rcc.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief RCC LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @addtogroup RCC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE)) + +#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE)) + +#if defined(I2C4) +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) +#else +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) +#endif /* I2C4 */ + +#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)) + +#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE)) + +#if defined(SDMMC2) +#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE)) +#else +#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE)) +#endif /* SDMMC2 */ + +#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) + +#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) + +#if defined(DFSDM1_Channel0) +#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE)) + +#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)) +#endif /* DFSDM1_Channel0 */ + +#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE)) + +#if defined(CEC) +#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) +#endif /* CEC */ + +#if defined(DSI) +#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE)) +#endif /* DSI */ + +#if defined(LTDC) +#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE)) +#endif /* LTDC */ + +#if defined(SPDIFRX) +#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE)) +#endif /* SPDIFRX */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +uint32_t RCC_GetSystemClockFreq(void); +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_PLL_GetFreqDomain_SYS(void); +uint32_t RCC_PLL_GetFreqDomain_SAI(void); +uint32_t RCC_PLL_GetFreqDomain_48M(void); +#if defined(DSI) +uint32_t RCC_PLL_GetFreqDomain_DSI(void); +#endif /* DSI */ +uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void); +uint32_t RCC_PLLSAI_GetFreqDomain_48M(void); +#if defined(LTDC) +uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void); +#endif /* LTDC */ +uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void); +uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void); +#if defined(SPDIFRX) +uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void); +#endif /* SPDIFRX */ +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RCC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RCC_DeInit(void) +{ + uint32_t vl_mask = 0U; + + /* Set HSION bit */ + LL_RCC_HSI_Enable(); + + /* Reset CFGR register */ + LL_RCC_WriteReg(CFGR, 0x00000000U); + + vl_mask = 0xFFFFFFFFU; + + /* Reset HSEON, PLLSYSON bits */ + CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON)); + + /* Reset PLLSAION bit */ + CLEAR_BIT(vl_mask, RCC_CR_PLLSAION); + + /* Reset PLLI2SON bit */ + CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON); + + /* Write new mask in CR register */ + LL_RCC_WriteReg(CR, vl_mask); + + /* Set HSITRIM bits to the reset value*/ + LL_RCC_HSI_SetCalibTrimming(0x10U); + + /* Reset PLLCFGR register */ + LL_RCC_WriteReg(PLLCFGR, 0x24003010U); + + /* Reset PLLI2SCFGR register */ + LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U); + + /* Reset PLLSAICFGR register */ + LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U); + + /* Reset HSEBYP bit */ + LL_RCC_HSE_DisableBypass(); + + /* Disable all interrupts */ + LL_RCC_WriteReg(CIR, 0x00000000U); + + return SUCCESS; +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks + * and different peripheral clocks available on the device. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) + * or HSI_VALUE(**) multiplied/divided by the PLL factors. + * @note (**) HSI_VALUE is a constant defined in this file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in this file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks + * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); + + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +/** + * @brief Return USARTx clock frequency + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE + * @arg @ref LL_RCC_USART6_CLKSOURCE + * @retval USART clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) +{ + uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); + + if (USARTxSource == LL_RCC_USART1_CLKSOURCE) + { + /* USART1CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ + default: + usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + else if (USARTxSource == LL_RCC_USART2_CLKSOURCE) + { + /* USART2CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + else if (USARTxSource == LL_RCC_USART6_CLKSOURCE) + { + /* USART6CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART6_CLKSOURCE_PCLK2: /* USART6 Clock is PCLK2 */ + default: + usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + else + { + if (USARTxSource == LL_RCC_USART3_CLKSOURCE) + { + /* USART3CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + } + return usart_frequency; +} + +/** + * @brief Return UARTx clock frequency + * @param UARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE + * @arg @ref LL_RCC_UART5_CLKSOURCE + * @arg @ref LL_RCC_UART7_CLKSOURCE + * @arg @ref LL_RCC_UART8_CLKSOURCE + * @retval UART clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) +{ + uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource)); + + if (UARTxSource == LL_RCC_UART4_CLKSOURCE) + { + /* UART4CLK clock frequency */ + switch (LL_RCC_GetUARTClockSource(UARTxSource)) + { + case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */ + uart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + uart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + uart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */ + default: + uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + else if (UARTxSource == LL_RCC_UART5_CLKSOURCE) + { + /* UART5CLK clock frequency */ + switch (LL_RCC_GetUARTClockSource(UARTxSource)) + { + case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */ + uart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + uart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + uart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */ + default: + uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + else if (UARTxSource == LL_RCC_UART7_CLKSOURCE) + { + /* UART7CLK clock frequency */ + switch (LL_RCC_GetUARTClockSource(UARTxSource)) + { + case LL_RCC_UART7_CLKSOURCE_SYSCLK: /* UART7 Clock is System Clock */ + uart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + uart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_UART7_CLKSOURCE_LSE: /* UART7 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + uart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_UART7_CLKSOURCE_PCLK1: /* UART7 Clock is PCLK1 */ + default: + uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + else + { + if (UARTxSource == LL_RCC_UART8_CLKSOURCE) + { + /* UART8CLK clock frequency */ + switch (LL_RCC_GetUARTClockSource(UARTxSource)) + { + case LL_RCC_UART8_CLKSOURCE_SYSCLK: /* UART8 Clock is System Clock */ + uart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + uart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_UART8_CLKSOURCE_LSE: /* UART8 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + uart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_UART8_CLKSOURCE_PCLK1: /* UART8 Clock is PCLK1 */ + default: + uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + } + return uart_frequency; +} + +/** + * @brief Return I2Cx clock frequency + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval I2C clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready + */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) +{ + uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + + if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) + { + /* I2C1 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ + default: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE) + { + /* I2C2 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */ + default: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE) + { + /* I2C3 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */ + default: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#if defined(I2C4) + else + { + if (I2CxSource == LL_RCC_I2C4_CLKSOURCE) + { + /* I2C4 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */ + default: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + } +#endif /* I2C4 */ + + return i2c_frequency; +} + +/** + * @brief Return I2Sx clock frequency + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @retval I2S clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLLI2S oscillator is not ready + */ +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) +{ + uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); + + if (I2SxSource == LL_RCC_I2S1_CLKSOURCE) + { + /* I2S1 CLK clock frequency */ + switch (LL_RCC_GetI2SClockSource(I2SxSource)) + { + case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */ + if (LL_RCC_PLLI2S_IsReady()) + { + i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S(); + } + break; + + case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */ + default: + i2s_frequency = EXTERNAL_CLOCK_VALUE; + break; + } + } + + return i2s_frequency; +} + +/** + * @brief Return LPTIMx clock frequency + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @retval LPTIM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready + */ +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) +{ + uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); + + if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) + { + /* LPTIM1CLK clock frequency */ + switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + { + case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ + if (LL_RCC_LSI_IsReady()) + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + lptim_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + lptim_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ + default: + lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + + return lptim_frequency; +} + +/** + * @brief Return SAIx clock frequency + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE + * @retval SAI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used + */ +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) +{ + uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource)); + + if (SAIxSource == LL_RCC_SAI1_CLKSOURCE) + { + /* SAI1CLK clock frequency */ + switch (LL_RCC_GetSAIClockSource(SAIxSource)) + { + case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */ + if (LL_RCC_PLLSAI_IsReady()) + { + sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI(); + } + break; + + case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */ + if (LL_RCC_PLLI2S_IsReady()) + { + sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI(); + } + break; + +#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT) + case LL_RCC_SAI1_CLKSOURCE_PLLSRC: + switch (LL_RCC_PLL_GetMainSource()) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 clock source */ + if (LL_RCC_HSE_IsReady()) + { + sai_frequency = HSE_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 clock source */ + default: + if (LL_RCC_HSI_IsReady()) + { + sai_frequency = HSI_VALUE; + } + break; + } + break; +#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */ + case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */ + default: + sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + } + else + { + if (SAIxSource == LL_RCC_SAI2_CLKSOURCE) + { + /* SAI2CLK clock frequency */ + switch (LL_RCC_GetSAIClockSource(SAIxSource)) + { + case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */ + if (LL_RCC_PLLSAI_IsReady()) + { + sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI(); + } + break; + + case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */ + if (LL_RCC_PLLI2S_IsReady()) + { + sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI(); + } + break; + +#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT) + case LL_RCC_SAI2_CLKSOURCE_PLLSRC: + switch (LL_RCC_PLL_GetMainSource()) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */ + if (LL_RCC_HSE_IsReady()) + { + sai_frequency = HSE_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */ + default: + if (LL_RCC_HSI_IsReady()) + { + sai_frequency = HSI_VALUE; + } + break; + } + break; +#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */ + case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */ + default: + sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + } + } + + return sai_frequency; +} + +/** + * @brief Return SDMMCx clock frequency + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval SDMMC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLL is not ready + */ +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) +{ + uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource)); + + if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE) + { + /* SDMMC1CLK clock frequency */ + switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) + { + case LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC1 clock source */ + switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE)) + { + case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */ + if (LL_RCC_PLL_IsReady()) + { + sdmmc_frequency = RCC_PLL_GetFreqDomain_48M(); + } + break; + + case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */ + default: + if (LL_RCC_PLLSAI_IsReady()) + { + sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M(); + } + break; + } + break; + + case LL_RCC_SDMMC1_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC1 clock source */ + default: + sdmmc_frequency = RCC_GetSystemClockFreq(); + break; + } + } +#if defined(SDMMC2) + else + { + /* SDMMC2CLK clock frequency */ + switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) + { + case LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC2 clock source */ + switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE)) + { + case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */ + if (LL_RCC_PLL_IsReady()) + { + sdmmc_frequency = RCC_PLL_GetFreqDomain_48M(); + } + break; + + case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */ + default: + if (LL_RCC_PLLSAI_IsReady()) + { + sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M(); + } + break; + } + break; + + case LL_RCC_SDMMC2_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC2 clock source */ + default: + sdmmc_frequency = RCC_GetSystemClockFreq(); + break; + } + } +#endif /* SDMMC2 */ + + return sdmmc_frequency; +} + +/** + * @brief Return RNGx clock frequency + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval RNG clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) +{ + uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource)); + + /* RNGCLK clock frequency */ + switch (LL_RCC_GetRNGClockSource(RNGxSource)) + { + case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */ + if (LL_RCC_PLL_IsReady()) + { + rng_frequency = RCC_PLL_GetFreqDomain_48M(); + } + break; + + case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */ + default: + if (LL_RCC_PLLSAI_IsReady()) + { + rng_frequency = RCC_PLLSAI_GetFreqDomain_48M(); + } + break; + } + + return rng_frequency; +} + +#if defined(CEC) +/** + * @brief Return CEC clock frequency + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval CEC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) +{ + uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); + + /* CECCLK clock frequency */ + switch (LL_RCC_GetCECClockSource(CECxSource)) + { + case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + cec_frequency = LSE_VALUE; + } + break; + + case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */ + default: + if (LL_RCC_HSI_IsReady()) + { + cec_frequency = HSI_VALUE/488U; + } + break; + } + + return cec_frequency; +} +#endif /* CEC */ + +/** + * @brief Return USBx clock frequency + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval USB clock frequency (in Hz) + */ +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) +{ + uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); + + /* USBCLK clock frequency */ + switch (LL_RCC_GetUSBClockSource(USBxSource)) + { + case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + if (LL_RCC_PLL_IsReady()) + { + usb_frequency = RCC_PLL_GetFreqDomain_48M(); + } + break; + + case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */ + default: + if (LL_RCC_PLLSAI_IsReady()) + { + usb_frequency = RCC_PLLSAI_GetFreqDomain_48M(); + } + break; + } + + return usb_frequency; +} + +#if defined(DFSDM1_Channel0) +/** + * @brief Return DFSDMx clock frequency + * @param DFSDMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE + * @retval DFSDM clock frequency (in Hz) + */ +uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource) +{ + uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource)); + + /* DFSDM1CLK clock frequency */ + switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource)) + { + case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */ + dfsdm_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */ + default: + dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + + return dfsdm_frequency; +} + +/** + * @brief Return DFSDMx Audio clock frequency + * @param DFSDMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE + * @retval DFSDM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource) +{ + uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource)); + + /* DFSDM1CLK clock frequency */ + switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource)) + { + case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */ + dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE); + break; + + case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2: /* SAI2 clock used as DFSDM1 audio clock */ + default: + dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE); + break; + } + + return dfsdm_frequency; +} +#endif /* DFSDM1_Channel0 */ + +#if defined(DSI) +/** + * @brief Return DSI clock frequency + * @param DSIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval DSI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used + */ +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource) +{ + uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource)); + + /* DSICLK clock frequency */ + switch (LL_RCC_GetDSIClockSource(DSIxSource)) + { + case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */ + if (LL_RCC_PLL_IsReady()) + { + dsi_frequency = RCC_PLL_GetFreqDomain_DSI(); + } + break; + + case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */ + default: + dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + + return dsi_frequency; +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Return LTDC clock frequency + * @param LTDCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE + * @retval LTDC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready + */ +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource) +{ + uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource)); + + if (LL_RCC_PLLSAI_IsReady()) + { + ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC(); + } + + return ltdc_frequency; +} +#endif /* LTDC */ + +#if defined(SPDIFRX) +/** + * @brief Return SPDIFRX clock frequency + * @param SPDIFRXxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE + * @retval SPDIFRX clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource) +{ + uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource)); + + if (LL_RCC_PLLI2S_IsReady()) + { + spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX(); + } + + return spdifrx_frequency; +} +#endif /* SPDIFRX */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + frequency = HSI_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ + frequency = RCC_PLL_GetFreqDomain_SYS(); + break; + + default: + frequency = HSI_VALUE; + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} + +/** + * @brief Return PCLK2 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK2 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK2 clock frequency */ + return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); +} + +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_SYS(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); +} + +/** + * @brief Return PLL clock frequency used for 48 MHz domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_48M(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN + 48M Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} + +#if defined(DSI) +/** + * @brief Return PLL clock frequency used for DSI clock + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_DSI(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + DSICLK = PLL_VCO / PLLR + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); +} +#endif /* DSI */ + +/** + * @brief Return PLLSAI clock frequency used for SAI1 and SAI2 domains + * @retval PLLSAI clock frequency (in Hz) + */ +uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN + SAI1 and SAI2 domains clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ()); +} + +/** + * @brief Return PLLSAI clock frequency used for 48Mhz domain + * @retval PLLSAI clock frequency (in Hz) + */ +uint32_t RCC_PLLSAI_GetFreqDomain_48M(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN + 48M Domain clock = PLLSAI_VCO / PLLSAIP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP()); +} + +#if defined(LTDC) +/** + * @brief Return PLLSAI clock frequency used for LTDC domain + * @retval PLLSAI clock frequency (in Hz) + */ +uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN + LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR()); +} +#endif /* LTDC */ + +/** + * @brief Return PLLI2S clock frequency used for SAI1 and SAI2 domains + * @retval PLLI2S clock frequency (in Hz) + */ +uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN + SAI1 and SAI2 domains clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ()); +} + +#if defined(SPDIFRX) +/** + * @brief Return PLLI2S clock frequency used for SPDIFRX domain + * @retval PLLI2S clock frequency (in Hz) + */ +uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN + SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = HSI_VALUE; + break; + } + + return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP()); +} +#endif /* SPDIFRX */ + +/** + * @brief Return PLLI2S clock frequency used for I2S domain + * @retval PLLI2S clock frequency (in Hz) + */ +uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN + I2S Domain clock = PLLI2S_VCO / PLLI2SR + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLI2S_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR()); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.h new file mode 100644 index 00000000000..840ca5c5fb7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.h @@ -0,0 +1,5170 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_rcc.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_RCC_H +#define __STM32F7xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ + +#if defined(RCC_DCKCFGR1_PLLSAIDIVR) +static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16}; +#endif /* RCC_DCKCFGR1_PLLSAIDIVR */ + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */ +#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ +#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */ +#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */ +#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */ +#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */ +#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */ +#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */ +#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */ +#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */ +#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */ +#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */ +#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock + * @{ + */ +#define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ +#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ +#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */ +#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ +#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */ +#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */ +#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */ +#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ +#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */ +#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */ +#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */ +#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */ +#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */ +#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */ +#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */ +#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ +#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */ +#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */ +#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */ +#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */ +#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */ +#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */ +#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */ +#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */ +#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */ +#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */ +#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */ +#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */ +#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */ +#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */ +#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL) /*!< LSE clock used as USART1 clock source */ +#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL) /*!< LSE clock used as USART2 clock source */ +#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL) /*!< LSE clock used as USART3 clock source */ +#define LL_RCC_USART6_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_0) /*!< SYSCLK clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_1) /*!< HSI clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL) /*!< LSE clock used as USART6 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_1) /*!< HSI clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL) /*!< LSE clock used as UART4 clock source */ +#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_1) /*!< HSI clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL) /*!< LSE clock used as UART5 clock source */ +#define LL_RCC_UART7_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_0) /*!< SYSCLK clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_1) /*!< HSI clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL) /*!< LSE clock used as UART7 clock source */ +#define LL_RCC_UART8_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART8 clock source */ +#define LL_RCC_UART8_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_0) /*!< SYSCLK clock used as UART8 clock source */ +#define LL_RCC_UART8_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_1) /*!< HSI clock used as UART8 clock source */ +#define LL_RCC_UART8_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL) /*!< LSE clock used as UART8 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C1SEL|0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_1 >> 16U)) /*!< HSI clock used as I2C1 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C2SEL|0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_1 >> 16U)) /*!< HSI clock used as I2C2 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C3SEL|0x00000000U) /*!< PCLK1 clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_1 >> 16U)) /*!< HSI clock used as I2C3 clock source */ +#if defined(I2C4) +#define LL_RCC_I2C4_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C4SEL|0x00000000U) /*!< PCLK1 clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_1 >> 16U)) /*!< HSI clock used as I2C4 clock source */ +#endif /* I2C4 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI1SEL | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_1 >> 16U)) /*!< External pin clock used as SAI1 clock source */ +#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT) +#define LL_RCC_SAI1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL >> 16U)) /*!< Main source clock used as SAI1 clock source */ +#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */ +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI2SEL | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_1 >> 16U)) /*!< External pin clock used as SAI2 clock source */ +#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT) +#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL >> 16U)) /*!< Main source clock used as SAI2 clock source */ +#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection + * @{ + */ +#define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC1 clock */ +#define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | (RCC_DCKCFGR2_SDMMC1SEL >> 16U)) /*!< System clock clock used as SDMMC1 clock */ +#if defined(SDMMC2) +#define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC2 clock */ +#define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | (RCC_DCKCFGR2_SDMMC2SEL >> 16U)) /*!< System clock clock used as SDMMC2 clock */ +#endif /* SDMMC2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI clock used as RNG clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#define LL_RCC_USB_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI1 clock used as USB clock source */ +/** + * @} + */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ +#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /*!< LSE oscillator clock used as CEC clock */ +#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 RCC_DCKCFGR2_CECSEL /*!< HSI oscillator clock divided by 488 used as CEC clock */ +/** + * @} + */ +#endif /* CEC */ + +/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */ +#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection + * @{ + */ +#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ +#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ +/** + * @} + */ + +#if defined(DFSDM1_Channel0) +/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL /*!< SAI2 clock used as DFSDM1 Audio clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection + * @{ + */ +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */ +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /*!< System clock used as DFSDM1 clock */ +/** + * @} + */ +#endif /* DFSDM1_Channel0 */ + +/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_DCKCFGR2_USART1SEL /*!< USART1 Clock source selection */ +#define LL_RCC_USART2_CLKSOURCE RCC_DCKCFGR2_USART2SEL /*!< USART2 Clock source selection */ +#define LL_RCC_USART3_CLKSOURCE RCC_DCKCFGR2_USART3SEL /*!< USART3 Clock source selection */ +#define LL_RCC_USART6_CLKSOURCE RCC_DCKCFGR2_USART6SEL /*!< USART6 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE RCC_DCKCFGR2_UART4SEL /*!< UART4 Clock source selection */ +#define LL_RCC_UART5_CLKSOURCE RCC_DCKCFGR2_UART5SEL /*!< UART5 Clock source selection */ +#define LL_RCC_UART7_CLKSOURCE RCC_DCKCFGR2_UART7SEL /*!< UART7 Clock source selection */ +#define LL_RCC_UART8_CLKSOURCE RCC_DCKCFGR2_UART8SEL /*!< UART8 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE RCC_DCKCFGR2_I2C1SEL /*!< I2C1 Clock source selection */ +#define LL_RCC_I2C2_CLKSOURCE RCC_DCKCFGR2_I2C2SEL /*!< I2C2 Clock source selection */ +#define LL_RCC_I2C3_CLKSOURCE RCC_DCKCFGR2_I2C3SEL /*!< I2C3 Clock source selection */ +#if defined(I2C4) +#define LL_RCC_I2C4_CLKSOURCE RCC_DCKCFGR2_I2C4SEL /*!< I2C4 Clock source selection */ +#endif /* I2C4 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR1_SAI1SEL /*!< SAI1 Clock source selection */ +#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR1_SAI2SEL /*!< SAI2 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMCx Peripheral SDMMC get clock source + * @{ + */ +#define LL_RCC_SDMMC1_CLKSOURCE RCC_DCKCFGR2_SDMMC1SEL /*!< SDMMC1 Clock source selection */ +#if defined(SDMMC2) +#define LL_RCC_SDMMC2_CLKSOURCE RCC_DCKCFGR2_SDMMC2SEL /*!< SDMMC2 Clock source selection */ +#endif /* SDMMC2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source + * @{ + */ +#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< RNG Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< USB Clock source selection */ +/** + * @} + */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */ +/** + * @} + */ +#endif /* CEC */ + +/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source + * @{ + */ +#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */ +/** + * @} + */ +#if defined(DFSDM1_Channel0) +/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR1_ADFSDM1SEL /*!< DFSDM Audio Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source + * @{ + */ +#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR1_DFSDM1SEL /*!< DFSDM Clock source selection */ +/** + * @} + */ +#endif /* DFSDM1_Channel0 */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR2_DSISEL /*!< DSI Clock source selection */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR1_PLLSAIDIVR /*!< LTDC Clock source selection */ +/** + * @} + */ +#endif /* LTDC */ + +#if defined(SPDIFRX) +/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source + * @{ + */ +#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_PLLI2SCFGR_PLLI2SP /*!< SPDIFRX Clock source selection */ +/** + * @} + */ +#endif /* SPDIFRX */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + * @{ + */ +#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */ +#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR1_TIMPRE /*!< Timers clock to four time PCLK */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor + * @{ + */ +#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */ +#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */ +#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */ +#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */ +#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */ +#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */ +#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */ +#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */ +#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */ +#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */ +#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */ +#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */ +#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */ +#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */ +#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */ +#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */ +#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */ +#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */ +#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */ +#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */ +#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */ +#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */ +#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */ +#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */ +#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */ +#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */ +#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */ +#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */ +#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */ +#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */ +#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */ +#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */ +#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */ +#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */ +#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */ +#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */ +#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */ +#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */ +#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */ +#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */ +#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */ +#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */ +#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */ +#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */ +#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */ +#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */ +#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */ +#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */ +#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */ +#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */ +#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */ +#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */ +#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */ +#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */ +#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */ +#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */ +#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */ +#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */ +#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */ +#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */ +#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */ +#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */ +/** + * @} + */ + +#if defined(RCC_PLLCFGR_PLLR) +/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) + * @{ + */ +#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ +#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ +#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ +#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ +#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ +#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ +/** + * @} + */ +#endif /* RCC_PLLCFGR_PLLR */ + +/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) + * @{ + */ +#define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */ +#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */ +#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) + * @{ + */ +#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */ +#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */ +#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */ +#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */ +#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ +#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */ +#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */ +#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */ +#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */ +#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */ +#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */ +#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */ +#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */ +#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection + * @{ + */ +#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */ +#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ) + * @{ + */ +#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */ +#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */ +#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */ +#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */ +#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */ +#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */ +#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */ +#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */ +#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */ +#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */ +#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */ +#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */ +#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */ +#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ) + * @{ + */ +#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */ +#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR1_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */ +#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR1_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */ +#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */ +#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR1_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */ +#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */ +#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */ +#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */ +#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR1_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */ +#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */ +#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */ +#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */ +#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */ +#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */ +#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */ +#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */ +#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR1_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */ +#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */ +#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */ +#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */ +#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */ +#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */ +#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */ +#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */ +#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */ +#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */ +#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */ +#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */ +#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */ +#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */ +#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */ +#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) + * @{ + */ +#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */ +#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */ +#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */ +#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */ +#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */ +#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */ +/** + * @} + */ + +#if defined(RCC_PLLI2SCFGR_PLLI2SP) +/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP) + * @{ + */ +#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */ +#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */ +#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */ +#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ + +/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ) + * @{ + */ +#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */ +#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */ +#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */ +#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */ +#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */ +#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */ +#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */ +#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */ +#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */ +#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */ +#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */ +#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */ +#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */ +#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ) + * @{ + */ +#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */ +#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR1_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */ +#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR1_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */ +#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */ +#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR1_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */ +#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */ +#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */ +#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */ +#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR1_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */ +#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */ +#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */ +#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */ +#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */ +#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */ +#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */ +#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */ +#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR1_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */ +#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */ +#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */ +#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */ +#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */ +#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */ +#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */ +#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */ +#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */ +#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */ +#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */ +#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */ +#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */ +#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */ +#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */ +#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */ +/** + * @} + */ + +#if defined(RCC_PLLSAICFGR_PLLSAIR) +/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR) + * @{ + */ +#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */ +#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */ +#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */ +#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */ +#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */ +#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */ +/** + * @} + */ +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + +#if defined(RCC_DCKCFGR1_PLLSAIDIVR) +/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR) + * @{ + */ +#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */ +#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR1_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */ +#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR1_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */ +#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVR_1 | RCC_DCKCFGR1_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR1_PLLSAIDIVR */ + +/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP) + * @{ + */ +#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */ +#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */ +#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */ +#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) + +/** + * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) + +#if defined(DSI) +/** + * @brief Helper macro to calculate the PLLCLK frequency used on DSI + * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +#endif /* DSI */ + +/** + * @brief Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains + * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLSAIN__ Between 50 and 432 + * @param __PLLSAIQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + * @param __PLLSAIDIVQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos) + 1U))) + +/** + * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLSAIN__ Between 50 and 432 + * @param __PLLSAIP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U)) + +#if defined(LTDC) +/** + * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLSAIN__ Between 50 and 432 + * @param __PLLSAIR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + * @param __PLLSAIDIVR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos]))) +#endif /* LTDC */ + +/** + * @brief Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains + * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLI2SN__ Between 50 and 432 + * @param __PLLI2SQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + * @param __PLLI2SDIVQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + (((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos) + 1U))) + +#if defined(SPDIFRX) +/** + * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLI2SN__ Between 50 and 432 + * @param __PLLI2SP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U)) +#endif /* SPDIFRX */ + +/** + * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLI2SN__ Between 50 and 432 + * @param __PLLI2SR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 31 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n + * CFGR MCO1PRE LL_RCC_ConfigMCO\n + * CFGR MCO2 LL_RCC_ConfigMCO\n + * CFGR MCO2PRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_3 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_5 + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_3 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_5 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll DCKCFGR2 USART1SEL LL_RCC_SetUSARTClockSource\n + * DCKCFGR2 USART2SEL LL_RCC_SetUSARTClockSource\n + * DCKCFGR2 USART3SEL LL_RCC_SetUSARTClockSource\n + * DCKCFGR2 USART6SEL LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); +} + +/** + * @brief Configure UARTx clock source + * @rmtoll DCKCFGR2 UART4SEL LL_RCC_SetUARTClockSource\n + * DCKCFGR2 UART5SEL LL_RCC_SetUARTClockSource\n + * DCKCFGR2 UART7SEL LL_RCC_SetUARTClockSource\n + * DCKCFGR2 UART8SEL LL_RCC_SetUARTClockSource + * @param UARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU)); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_SetI2CClockSource\n + * DCKCFGR2 I2C2SEL LL_RCC_SetI2CClockSource\n + * DCKCFGR2 I2C3SEL LL_RCC_SetI2CClockSource\n + * DCKCFGR2 I2C4SEL LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U), (I2CxSource << 16U)); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); +} + +/** + * @brief Configure SAIx clock source + * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_SetSAIClockSource\n + * DCKCFGR1 SAI2SEL LL_RCC_SetSAIClockSource + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) +{ + MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); +} + +/** + * @brief Configure SDMMC clock source + * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n + * DCKCFGR2 SDMMC2SEL LL_RCC_SetSDMMCClockSource + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*) + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U)); +} + +/** + * @brief Configure 48Mhz domain clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource + * @param CK48MxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); +} + +/** + * @brief Configure RNG clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); +} + +/** + * @brief Configure USB clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); +} + +#if defined(CEC) +/** + * @brief Configure CEC clock source + * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); +} +#endif /* CEC */ + +/** + * @brief Configure I2S clock source + * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); +} + +#if defined(DSI) +/** + * @brief Configure DSI clock source + * @rmtoll DCKCFGR2 DSISEL LL_RCC_SetDSIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source); +} +#endif /* DSI */ + +#if defined(DFSDM1_Channel0) +/** + * @brief Configure DFSDM Audio clock source + * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source); +} + +/** + * @brief Configure DFSDM Kernel clock source + * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_SetDFSDMClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source); +} +#endif /* DFSDM1_Channel0 */ + +/** + * @brief Get USARTx clock source + * @rmtoll DCKCFGR2 USART1SEL LL_RCC_GetUSARTClockSource\n + * DCKCFGR2 USART2SEL LL_RCC_GetUSARTClockSource\n + * DCKCFGR2 USART3SEL LL_RCC_GetUSARTClockSource\n + * DCKCFGR2 USART6SEL LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE + * @arg @ref LL_RCC_USART6_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U)); +} + +/** + * @brief Get UARTx clock source + * @rmtoll DCKCFGR2 UART4SEL LL_RCC_GetUARTClockSource\n + * DCKCFGR2 UART5SEL LL_RCC_GetUARTClockSource\n + * DCKCFGR2 UART7SEL LL_RCC_GetUARTClockSource\n + * DCKCFGR2 UART8SEL LL_RCC_GetUARTClockSource + * @param UARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE + * @arg @ref LL_RCC_UART5_CLKSOURCE + * @arg @ref LL_RCC_UART7_CLKSOURCE + * @arg @ref LL_RCC_UART8_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_GetI2CClockSource\n + * DCKCFGR2 I2C2SEL LL_RCC_GetI2CClockSource\n + * DCKCFGR2 I2C3SEL LL_RCC_GetI2CClockSource\n + * DCKCFGR2 I2C4SEL LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx); +} + +/** + * @brief Get LPTIMx clock source + * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); +} + +/** + * @brief Get SAIx clock source + * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_GetSAIClockSource\n + * DCKCFGR1 SAI2SEL LL_RCC_GetSAIClockSource + * @param SAIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U | SAIx); +} + +/** + * @brief Get SDMMCx clock source + * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n + * DCKCFGR2 SDMMC2SEL LL_RCC_GetSDMMCClockSource + * @param SDMMCx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*) + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx); +} + +/** + * @brief Get 48Mhz domain clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource + * @param CK48Mx This parameter can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI + */ +__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); +} + +/** + * @brief Get RNGx clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); +} + +/** + * @brief Get USBx clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); +} + +#if defined(CEC) +/** + * @brief Get CEC Clock Source + * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource + * @param CECx This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); +} +#endif /* CEC */ + +/** + * @brief Get I2S Clock Source + * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); +} + +#if defined(DFSDM1_Channel0) +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx)); +} + +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_GetDFSDMClockSource + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx)); +} +#endif /* DFSDM1_Channel0 */ + +#if defined(DSI) +/** + * @brief Get DSI Clock Source + * @rmtoll DCKCFGR2 DSISEL LL_RCC_GetDSIClockSource + * @param DSIx This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx)); +} +#endif /* DSI */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Set HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); +} + +/** + * @brief Get HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM + * @{ + */ + +/** + * @brief Set Timers Clock Prescalers + * @rmtoll DCKCFGR1 TIMPRE LL_RCC_SetTIMPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler); +} + +/** + * @brief Get Timers Clock Prescalers + * @rmtoll DCKCFGR1 TIMPRE LL_RCC_GetTIMPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLP can be written only when PLL is disabled + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); +} + +/** + * @brief Configure PLL used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note This can be selected for USB, RNG, SDMMC1 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); +} + +#if defined(DSI) +/** + * @brief Configure PLL used for DSI clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @note This can be selected for DSI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +} +#endif /* DSI */ + +/** + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 50 and 432 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); +} + +/** + * @brief Get Main PLL division factor for PLLP + * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); +} + +/** + * @brief Get Main PLL division factor for PLLQ + * @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock) + * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); +} + +#if defined(RCC_PLLCFGR_PLLR) +/** + * @brief Get Main PLL division factor for PLLR + * @note used for PLLCLK (system clock) + * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); +} +#endif /* RCC_PLLCFGR_PLLR */ + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +} + +/** + * @brief Configure Spread Spectrum used for PLL + * @note These bits must be written before enabling PLL + * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n + * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n + * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum + * @param Mod Between Min_Data=0 and Max_Data=8191 + * @param Inc Between Min_Data=0 and Max_Data=32767 + * @param Sel This parameter can be one of the following values: + * @arg @ref LL_RCC_SPREAD_SELECT_CENTER + * @arg @ref LL_RCC_SPREAD_SELECT_DOWN + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) +{ + MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel); +} + +/** + * @brief Get Spread Spectrum Modulation Period for PLL + * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation + * @retval Between Min_Data=0 and Max_Data=8191 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); +} + +/** + * @brief Get Spread Spectrum Incrementation Step for PLL + * @note Must be written before enabling PLL + * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation + * @retval Between Min_Data=0 and Max_Data=32767 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); +} + +/** + * @brief Get Spread Spectrum Selection for PLL + * @note Must be written before enabling PLL + * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPREAD_SELECT_CENTER + * @arg @ref LL_RCC_SPREAD_SELECT_DOWN + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); +} + +/** + * @brief Enable Spread Spectrum for PLL. + * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) +{ + SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +} + +/** + * @brief Disable Spread Spectrum for PLL. + * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) +{ + CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLLI2S PLLI2S + * @{ + */ + +/** + * @brief Enable PLLI2S + * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLI2SON); +} + +/** + * @brief Disable PLLI2S + * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); +} + +/** + * @brief Check if PLLI2S Ready + * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); +} + +/** + * @brief Configure PLLI2S used for SAI1 and SAI2 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLQ can be written only when PLLI2S is disabled + * @note This can be selected for SAI1 and SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n + * DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + * @param PLLDIVQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ); + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ); +} + +#if defined(SPDIFRX) +/** + * @brief Configure PLLI2S used for SPDIFRX domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLP can be written only when PLLI2S is disabled + * @note This can be selected for SPDIFRX + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP); +} +#endif /* SPDIFRX */ + +/** + * @brief Configure PLLI2S used for I2S1 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLLI2S is disabled + * @note This can be selected for I2S + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR); +} + +/** + * @brief Get I2SPLL multiplication factor for VCO + * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN + * @retval Between 50 and 432 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); +} + +/** + * @brief Get I2SPLL division factor for PLLI2SQ + * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ)); +} + +/** + * @brief Get I2SPLL division factor for PLLI2SR + * @note used for PLLI2SCLK (I2S clock) + * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); +} + +#if defined(RCC_PLLI2SCFGR_PLLI2SP) +/** + * @brief Get I2SPLL division factor for PLLI2SP + * @note used for PLLSPDIFRXCLK (SPDIFRX clock) + * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP)); +} +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ + +/** + * @brief Get I2SPLL division factor for PLLI2SDIVQ + * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock) + * @rmtoll DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLLSAI PLLSAI + * @{ + */ + +/** + * @brief Enable PLLSAI + * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLSAION); +} + +/** + * @brief Disable PLLSAI + * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); +} + +/** + * @brief Check if PLLSAI Ready + * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY)); +} + +/** + * @brief Configure PLLSAI used for SAI1 and SAI2 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLQ can be written only when PLLSAI is disabled + * @note This can be selected for SAI1 and SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n + * DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + * @param PLLDIVQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ); + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, PLLDIVQ); +} + +/** + * @brief Configure PLLSAI used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLP can be written only when PLLSAI is disabled + * @note This can be selected for USB, RNG, SDMMC1 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP); +} + +#if defined(LTDC) +/** + * @brief Configure PLLSAI used for LTDC domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLLSAI is disabled + * @note This can be selected for LTDC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + * @param PLLDIVR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR); + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, PLLDIVR); +} +#endif /* LTDC */ + +/** + * @brief Get SAIPLL multiplication factor for VCO + * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN + * @retval Between 50 and 432 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); +} + +/** + * @brief Get SAIPLL division factor for PLLSAIQ + * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ)); +} + +#if defined(RCC_PLLSAICFGR_PLLSAIR) +/** + * @brief Get SAIPLL division factor for PLLSAIR + * @note used for PLLSAICLK (SAI clock) + * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR)); +} +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + +/** + * @brief Get SAIPLL division factor for PLLSAIP + * @note used for PLL48MCLK (48M domain clock) + * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP)); +} + +/** + * @brief Get SAIPLL division factor for PLLSAIDIVQ + * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock) + * @rmtoll DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ)); +} + +#if defined(RCC_DCKCFGR1_PLLSAIDIVR) +/** + * @brief Get SAIPLL division factor for PLLSAIDIVR + * @note used for LTDC domain clock + * @rmtoll DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR)); +} +#endif /* RCC_DCKCFGR1_PLLSAIDIVR */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +} + +/** + * @brief Clear PLLI2S ready interrupt flag + * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +} + +/** + * @brief Clear PLLSAI ready interrupt flag + * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +} + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_CSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); +} + +/** + * @brief Check if PLLI2S ready interrupt occurred or not + * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF)); +} + +/** + * @brief Check if PLLSAI ready interrupt occurred or not + * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF)); +} + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Enable PLLI2S ready interrupt + * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +} + +/** + * @brief Enable PLLSAI ready interrupt + * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Disable PLLI2S ready interrupt + * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +} + +/** + * @brief Disable PLLSAI ready interrupt + * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +} + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); +} + +/** + * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE)); +} + +/** + * @brief Checks if PLLSAI ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#if defined(DFSDM1_Channel0) +uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); +uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); +#endif /* DFSDM1_Channel0 */ +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +#if defined(CEC) +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +#endif /* CEC */ +#if defined(LTDC) +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +#endif /* LTDC */ +#if defined(SPDIFRX) +uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource); +#endif /* SPDIFRX */ +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rng.c new file mode 100644 index 00000000000..e87137e17ad --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rng.c @@ -0,0 +1,116 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_rng.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief RNG LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_rng.h" +#include "stm32f7xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (RNG) + +/** @addtogroup RNG_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RNG_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RNG_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize RNG registers (Registers restored to their default values). + * @param RNGx RNG Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RNG registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) +{ + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(RNGx)); + + /* Enable RNG reset state */ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); + + /* Release RNG from reset state */ + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); + + return (SUCCESS); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (RNG) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rng.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rng.h new file mode 100644 index 00000000000..d619443c16c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rng.h @@ -0,0 +1,355 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_rng.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of RNG LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_RNG_H +#define __STM32F7xx_LL_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(RNG) + +/** @defgroup RNG_LL RNG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants + * @{ + */ + +/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RNG_ReadReg function + * @{ + */ +#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */ +#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */ +#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */ +#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */ +#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */ +/** + * @} + */ + +/** @defgroup RNG_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros + * @{ + */ +#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros + * @{ + */ + +/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RNG register + * @param __INSTANCE__ RNG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RNG register + * @param __INSTANCE__ RNG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions + * @{ + */ +/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions + * @{ + */ + +/** + * @brief Enable Random Number Generation + * @rmtoll CR RNGEN LL_RNG_Enable + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_RNGEN); +} + +/** + * @brief Disable Random Number Generation + * @rmtoll CR RNGEN LL_RNG_Disable + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN); +} + +/** + * @brief Check if Random Number Generator is enabled + * @rmtoll CR RNGEN LL_RNG_IsEnabled + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) +{ + return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)); +} + +/** + * @} + */ + +/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Indicate if the RNG Data ready Flag is set or not + * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) +{ + return (READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)); +} + +/** + * @brief Indicate if the Clock Error Current Status Flag is set or not + * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) +{ + return (READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)); +} + +/** + * @brief Indicate if the Seed Error Current Status Flag is set or not + * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) +{ + return (READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)); +} + +/** + * @brief Indicate if the Clock Error Interrupt Status Flag is set or not + * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) +{ + return (READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)); +} + +/** + * @brief Indicate if the Seed Error Interrupt Status Flag is set or not + * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx) +{ + return (READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)); +} + +/** + * @brief Clear Clock Error interrupt Status (CEIS) Flag + * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx) +{ + WRITE_REG(RNGx->SR, ~RNG_SR_CEIS); +} + +/** + * @brief Clear Seed Error interrupt Status (SEIS) Flag + * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx) +{ + WRITE_REG(RNGx->SR, ~RNG_SR_SEIS); +} + +/** + * @} + */ + +/** @defgroup RNG_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable Random Number Generator Interrupt + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_EnableIT + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_IE); +} + +/** + * @brief Disable Random Number Generator Interrupt + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_DisableIT + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_IE); +} + +/** + * @brief Check if Random Number Generator Interrupt is enabled + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_IsEnabledIT + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) +{ + return (READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)); +} + +/** + * @} + */ + +/** @defgroup RNG_LL_EF_Data_Management Data Management + * @{ + */ + +/** + * @brief Return32-bit Random Number value + * @rmtoll DR RNDATA LL_RNG_ReadRandData32 + * @param RNGx RNG Instance + * @retval Generated 32-bit random value + */ +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_REG(RNGx->DR)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RNG) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_RNG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rtc.c new file mode 100644 index 00000000000..c4ba56d008e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rtc.c @@ -0,0 +1,897 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_rtc.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief RTC LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_rtc.h" +#include "stm32f7xx_ll_cortex.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @addtogroup RTC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Constants + * @{ + */ +/* Default values used for prescaler */ +#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU +#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU + +/* Values used for timeout */ +#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */ +#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Macros + * @{ + */ + +#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \ + || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM)) + +#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU) + +#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU) + +#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ + || ((__VALUE__) == LL_RTC_FORMAT_BCD)) + +#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \ + || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM)) + +#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U)) +#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) +#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) +#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) + +#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY)) + +#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) + +#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \ + || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \ + || ((__VALUE__) == LL_RTC_MONTH_MARCH) \ + || ((__VALUE__) == LL_RTC_MONTH_APRIL) \ + || ((__VALUE__) == LL_RTC_MONTH_MAY) \ + || ((__VALUE__) == LL_RTC_MONTH_JUNE) \ + || ((__VALUE__) == LL_RTC_MONTH_JULY) \ + || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \ + || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \ + || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \ + || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \ + || ((__VALUE__) == LL_RTC_MONTH_DECEMBER)) + +#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) + +#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL)) + +#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL)) + + +#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY)) + +#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY)) + + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_LL_EF_Init + * @{ + */ + +/** + * @brief De-Initializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are de-initialized + * - ERROR: RTC registers are not de-initialized + */ +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) +{ + ErrorStatus status = ERROR; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Reset TR, DR and CR registers */ + LL_RTC_WriteReg(RTCx, TR, 0x00000000U); +#if defined(RTC_WAKEUP_SUPPORT) + LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT); +#endif /* RTC_WAKEUP_SUPPORT */ + LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + /* Reset All CR bits except CR[2:0] */ +#if defined(RTC_WAKEUP_SUPPORT) + LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL)); +#else + LL_RTC_WriteReg(RTCx, CR, 0x00000000U); +#endif /* RTC_WAKEUP_SUPPORT */ + LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); + LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U); + LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U); + LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U); + LL_RTC_WriteReg(RTCx, CALR, 0x00000000U); + LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U); + LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U); + + /* Reset ISR register and exit initialization mode */ + LL_RTC_WriteReg(RTCx, ISR, 0x00000000U); + + /* Reset Tamper and alternate functions configuration register */ + LL_RTC_WriteReg(RTCx, TAMPCR, 0x00000000U); + + /* Reset Option register */ + LL_RTC_WriteReg(RTCx, OR, 0x00000000U); + + /* Wait till the RTC RSF flag is set */ + status = LL_RTC_WaitForSynchro(RTCx); + } + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTCx RTC Instance + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat)); + assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler)); + assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Set Hour Format */ + LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat); + + /* Configure Synchronous and Asynchronous prescaler factor */ + LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler); + LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler); + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_InitTypeDef field to default value. + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct) +{ + /* Set RTC_InitStruct fields to default values */ + RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR; + RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT; + RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT; +} + +/** + * @brief Set the RTC current time. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + } + else + { + RTC_TimeStruct->TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds)); + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + } + else + { + RTC_TimeStruct->TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + } + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))); + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours, + RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds); + } + else + { + LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds)); + } + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTC); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + { + status = LL_RTC_WaitForSynchro(RTCx); + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec). + * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24; + RTC_TimeStruct->Hours = 0U; + RTC_TimeStruct->Minutes = 0U; + RTC_TimeStruct->Seconds = 0U; +} + +/** + * @brief Set the RTC current date. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * the date configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Day register is configured + * - ERROR: RTC Day register is not configured + */ +ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U)) + { + RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU; + } + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year)); + assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month)); + assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day)); + } + else + { + assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year))); + assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month))); + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day))); + } + assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year); + } + else + { + LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day), + __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year)); + } + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTC); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + { + status = LL_RTC_WaitForSynchro(RTCx); + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00) + * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY; + RTC_DateStruct->Day = 1U; + RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY; + RTC_DateStruct->Year = 0U; +} + +/** + * @brief Set the RTC Alarm A. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use @ref LL_RTC_ALMA_Disable function). + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARMA registers are configured + * - ERROR: ALARMA registers are not configured + */ +ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Select weekday selection */ + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + /* Set the date for ALARM */ + LL_RTC_ALMA_DisableWeekday(RTCx); + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + else + { + LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + /* Set the week day for ALARM */ + LL_RTC_ALMA_EnableWeekday(RTCx); + LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + + /* Configure the Alarm register */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, + RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + } + else + { + LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + } + /* Set ALARM mask */ + LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return SUCCESS; +} + +/** + * @brief Set the RTC Alarm B. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (@ref LL_RTC_ALMB_Disable function). + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARMB registers are configured + * - ERROR: ALARMB registers are not configured + */ +ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Select weekday selection */ + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + /* Set the date for ALARM */ + LL_RTC_ALMB_DisableWeekday(RTCx); + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + else + { + LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + /* Set the week day for ALARM */ + LL_RTC_ALMB_EnableWeekday(RTCx); + LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + + /* Configure the Alarm register */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, + RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + } + else + { + LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + } + /* Set ALARM mask */ + LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM; + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; + + /* Alarm Day Settings : Day = 1st day of the month */ + RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE; + RTC_AlarmStruct->AlarmDateWeekDay = 1U; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM; + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; + + /* Alarm Day Settings : Day = 1st day of the month */ + RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE; + RTC_AlarmStruct->AlarmDateWeekDay = 1U; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE; +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp = 0U; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Check if the Initialization mode is set */ + if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U) + { + /* Set the Initialization mode */ + LL_RTC_EnableInitMode(RTCx); + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout --; + } + tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + } + return status; +} + +/** + * @brief Exit the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC exited from in Init mode + * - ERROR: Not applicable + */ +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) +{ + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + return SUCCESS; +} + +/** + * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp = 0U; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Clear RSF flag */ + LL_RTC_ClearFlag_RS(RTCx); + + /* Wait the registers to be synchronised */ + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + while ((timeout != 0U) && (tmp != 0U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout--; + } + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + + if (status != ERROR) + { + timeout = RTC_SYNCHRO_TIMEOUT; + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout--; + } + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rtc.h new file mode 100644 index 00000000000..dba714dd3a3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rtc.h @@ -0,0 +1,3867 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_rtc.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of RTC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_RTC_H +#define __STM32F7xx_LL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @defgroup RTC_LL RTC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_LL_Private_Constants RTC Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK 0xFFFFFF5FU + +/* Write protection defines */ +#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) +#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU) +#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U) + +/* Defines used to combine date & time */ +#define RTC_OFFSET_WEEKDAY 24U +#define RTC_OFFSET_DAY 16U +#define RTC_OFFSET_MONTH 8U +#define RTC_OFFSET_HOUR 16U +#define RTC_OFFSET_MINUTE 8U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_Private_Macros RTC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hours Format. + This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetHourFormat(). */ + + uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetAsynchPrescaler(). */ + + uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetSynchPrescaler(). */ +} LL_RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */ + + uint8_t Hours; /*!< Specifies the RTC Time Hours. + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected. + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */ +} LL_RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_LL_EC_WEEKDAY + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */ + + uint8_t Month; /*!< Specifies the RTC Date Month. + This parameter can be a value of @ref RTC_LL_EC_MONTH + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */ + + uint8_t Day; /*!< Specifies the RTC Date Day. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */ +} LL_RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A + or @ref LL_RTC_ALMB_SetMask() for ALARM B + */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay. + This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday() + for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B + */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay. + If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay() + for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B. + + If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay() + for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B. + */ +} LL_RTC_AlarmTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants + * @{ + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EC_FORMAT FORMAT + * @{ + */ +#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay + * @{ + */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay + * @{ + */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RTC_ReadReg function + * @{ + */ +#define LL_RTC_ISR_ITSF RTC_ISR_ITSF +#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF +#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F +#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F +#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F +#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF +#define LL_RTC_ISR_TSF RTC_ISR_TSF +#define LL_RTC_ISR_WUTF RTC_ISR_WUTF +#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF +#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF +#define LL_RTC_ISR_INITF RTC_ISR_INITF +#define LL_RTC_ISR_RSF RTC_ISR_RSF +#define LL_RTC_ISR_INITS RTC_ISR_INITS +#define LL_RTC_ISR_SHPF RTC_ISR_SHPF +#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF +#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF +#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF +/** + * @} + */ + +/** @defgroup RTC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions + * @{ + */ +#define LL_RTC_CR_TSIE RTC_CR_TSIE +#define LL_RTC_CR_WUTIE RTC_CR_WUTIE +#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE +#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE +#define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE +#define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE +#define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE +#define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY + * @{ + */ +#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) /*!< Monday */ +#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ +#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) /*!< Wednesday */ +#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) /*!< Thrusday */ +#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) /*!< Friday */ +#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ +#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_MONTH MONTH + * @{ + */ +#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U) /*!< January */ +#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U) /*!< February */ +#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U) /*!< March */ +#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U) /*!< April */ +#define LL_RTC_MONTH_MAY ((uint8_t)0x05U) /*!< May */ +#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U) /*!< June */ +#define LL_RTC_MONTH_JULY ((uint8_t)0x07U) /*!< July */ +#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U) /*!< August */ +#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) /*!< September */ +#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U) /*!< October */ +#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U) /*!< November */ +#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U) /*!< December */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT + * @{ + */ +#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */ +#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT + * @{ + */ +#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */ +#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */ +#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */ +#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE + * @{ + */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN + * @{ + */ +#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/ +#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT + * @{ + */ +#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND + * @{ + */ +#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */ +#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK + * @{ + */ +#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/ +#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT + * @{ + */ +#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK + * @{ + */ +#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/ +#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT + * @{ + */ +#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE + * @{ + */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT + * @{ + */ +#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER TAMPER + * @{ + */ +#define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */ +#define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */ +#define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + * @{ + */ +#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @{ + */ +#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */ +/** + * @} + */ + +#if defined(RTC_TAMPCR_TAMPPRCH) +/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION + * @{ + */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ +#endif /* RTC_TAMPCR_TAMPPRCH */ + +#if defined(RTC_TAMPCR_TAMPFLT) +/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER + * @{ + */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ +/** + * @} + */ +#endif /* RTC_TAMPCR_TAMPFLT */ + +#if defined(RTC_TAMPCR_TAMPFREQ) +/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER + * @{ + */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ +#endif /* RTC_TAMPCR_TAMPFREQ */ + +/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL + * @{ + */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV + * @{ + */ +#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2) /*!< ck_spre (usually 1 Hz) clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BKP BACKUP + * @{ + */ +#define LL_RTC_BKP_DR0 0x00000000U +#define LL_RTC_BKP_DR1 0x00000001U +#define LL_RTC_BKP_DR2 0x00000002U +#define LL_RTC_BKP_DR3 0x00000003U +#define LL_RTC_BKP_DR4 0x00000004U +#if RTC_BKP_NUMBER > 5 +#define LL_RTC_BKP_DR5 0x00000005U +#define LL_RTC_BKP_DR6 0x00000006U +#define LL_RTC_BKP_DR7 0x00000007U +#define LL_RTC_BKP_DR8 0x00000008U +#define LL_RTC_BKP_DR9 0x00000009U +#define LL_RTC_BKP_DR10 0x0000000AU +#define LL_RTC_BKP_DR11 0x0000000BU +#define LL_RTC_BKP_DR12 0x0000000CU +#define LL_RTC_BKP_DR13 0x0000000DU +#define LL_RTC_BKP_DR14 0x0000000EU +#define LL_RTC_BKP_DR15 0x0000000FU +#endif /* RTC_BKP_NUMBER > 5 */ + +#if RTC_BKP_NUMBER > 16 +#define LL_RTC_BKP_DR16 0x00000010U +#define LL_RTC_BKP_DR17 0x00000011U +#define LL_RTC_BKP_DR18 0x00000012U +#define LL_RTC_BKP_DR19 0x00000013U +#endif /* RTC_BKP_NUMBER > 16 */ + +#if RTC_BKP_NUMBER > 20 +#define LL_RTC_BKP_DR20 0x00000014U +#define LL_RTC_BKP_DR21 0x00000015U +#define LL_RTC_BKP_DR22 0x00000016U +#define LL_RTC_BKP_DR23 0x00000017U +#define LL_RTC_BKP_DR24 0x00000018U +#define LL_RTC_BKP_DR25 0x00000019U +#define LL_RTC_BKP_DR26 0x0000001AU +#define LL_RTC_BKP_DR27 0x0000001BU +#define LL_RTC_BKP_DR28 0x0000001CU +#define LL_RTC_BKP_DR29 0x0000001DU +#define LL_RTC_BKP_DR30 0x0000001EU +#define LL_RTC_BKP_DR31 0x0000001FU +#endif /* RTC_BKP_NUMBER > 20 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output + * @{ + */ +#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 1 Hz */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion + * @{ + */ +#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */ +#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period + * @{ + */ +#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Convert Convert helper Macros + * @{ + */ + +/** + * @brief Helper macro to convert a value from 2 digit decimal format to BCD format + * @param __VALUE__ Byte to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U)) + +/** + * @brief Helper macro to convert a value from BCD format to 2 digit decimal format + * @param __VALUE__ BCD value to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU)) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Date Date helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve weekday. + * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Year in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Year in BCD format (0x00 . . . 0x99) + */ +#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Month in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Day in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Day in BCD format (0x01 . . . 0x31) + */ +#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Time Time helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve hour in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23) + */ +#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve minute in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Minutes in BCD format (0x00. . .0x59) + */ +#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve second in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Seconds in format (0x00. . .0x59) + */ +#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set Hours format (24 hour/day or AM/PM hour format) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll CR FMT LL_RTC_SetHourFormat + * @param RTCx RTC Instance + * @param HourFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat) +{ + MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); +} + +/** + * @brief Get Hours format (24 hour/day or AM/PM hour format) + * @rmtoll CR FMT LL_RTC_GetHourFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + */ +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); +} + +/** + * @brief Select the flag to be routed to RTC_ALARM output + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR OSEL LL_RTC_SetAlarmOutEvent + * @param RTCx RTC Instance + * @param AlarmOutput This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput) +{ + MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput); +} + +/** + * @brief Get the flag to be routed to RTC_ALARM output + * @rmtoll CR OSEL LL_RTC_GetAlarmOutEvent + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); +} + +/** + * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @note Used only when RTC_ALARM is mapped on PC13 + * @rmtoll OR ALARMOUTTYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output) +{ + MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output); +} + +/** + * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @note used only when RTC_ALARM is mapped on PC13 + * @rmtoll OR ALARMOUTTYPE LL_RTC_GetAlarmOutputType + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE)); +} + +/** + * @brief Enable initialization mode + * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + * and prescaler register (RTC_PRER). + * Counters are stopped and start counting from the new value when INIT is reset. + * @rmtoll ISR INIT LL_RTC_EnableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) +{ + /* Set the Initialization mode */ + WRITE_REG(RTCx->ISR, RTC_INIT_MASK); +} + +/** + * @brief Disable initialization mode (Free running mode) + * @rmtoll ISR INIT LL_RTC_DisableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) +{ + /* Exit Initialization mode */ + WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT); +} + +/** + * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR POL LL_RTC_SetOutputPolarity + * @param RTCx RTC Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity) +{ + MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); +} + +/** + * @brief Get Output polarity + * @rmtoll CR POL LL_RTC_GetOutputPolarity + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + */ +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); +} + +/** + * @brief Enable Bypass the shadow registers + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR BYPSHAD LL_RTC_EnableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Disable Bypass the shadow registers + * @rmtoll CR BYPSHAD LL_RTC_DisableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Check if Shadow registers bypass is enabled or not. + * @rmtoll CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)); +} + +/** + * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll CR REFCKON LL_RTC_EnableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_REFCKON); +} + +/** + * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll CR REFCKON LL_RTC_DisableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON); +} + +/** + * @brief Set Asynchronous prescaler factor + * @rmtoll PRER PREDIV_A LL_RTC_SetAsynchPrescaler + * @param RTCx RTC Instance + * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Set Synchronous prescaler factor + * @rmtoll PRER PREDIV_S LL_RTC_SetSynchPrescaler + * @param RTCx RTC Instance + * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); +} + +/** + * @brief Get Asynchronous prescaler factor + * @rmtoll PRER PREDIV_A LL_RTC_GetAsynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7F + */ +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Get Synchronous prescaler factor + * @rmtoll PRER PREDIV_S LL_RTC_GetSynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); +} + +/** + * @brief Enable the write protection for RTC registers. + * @rmtoll WPR KEY LL_RTC_EnableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); +} + +/** + * @brief Disable the write protection for RTC registers. + * @rmtoll WPR KEY LL_RTC_DisableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Time Time + * @{ + */ + +/** + * @brief Set time format (AM/24-hour or PM notation) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll TR PM LL_RTC_TIME_SetFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); +} + +/** + * @brief Get time format (AM or PM notation) + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @rmtoll TR PM LL_RTC_TIME_GetFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); +} + +/** + * @brief Set Hours in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format + * @rmtoll TR HT LL_RTC_TIME_SetHour\n + * TR HU LL_RTC_TIME_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))); +} + +/** + * @brief Get Hours in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to + * Binary format + * @rmtoll TR HT LL_RTC_TIME_GetHour\n + * TR HU LL_RTC_TIME_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU)); + return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)); +} + +/** + * @brief Set Minutes in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll TR MNT LL_RTC_TIME_SetMinute\n + * TR MNU LL_RTC_TIME_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos))); +} + +/** + * @brief Get Minutes in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD + * to Binary format + * @rmtoll TR MNT LL_RTC_TIME_GetMinute\n + * TR MNU LL_RTC_TIME_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)); + return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)); +} + +/** + * @brief Set Seconds in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll TR ST LL_RTC_TIME_SetSecond\n + * TR SU LL_RTC_TIME_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos))); +} + +/** + * @brief Get Seconds in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD + * to Binary format + * @rmtoll TR ST LL_RTC_TIME_GetSecond\n + * TR SU LL_RTC_TIME_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)); + return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)); +} + +/** + * @brief Set time (hour, minute and second) in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note TimeFormat and Hours should follow the same format + * @rmtoll TR PM LL_RTC_TIME_Config\n + * TR HT LL_RTC_TIME_Config\n + * TR HU LL_RTC_TIME_Config\n + * TR MNT LL_RTC_TIME_Config\n + * TR MNU LL_RTC_TIME_Config\n + * TR ST LL_RTC_TIME_Config\n + * TR SU LL_RTC_TIME_Config + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +{ + register uint32_t temp = 0U; + + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); + MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp); +} + +/** + * @brief Get time (hour, minute and second) in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll TR HT LL_RTC_TIME_Get\n + * TR HU LL_RTC_TIME_Get\n + * TR MNT LL_RTC_TIME_Get\n + * TR MNU LL_RTC_TIME_Get\n + * TR ST LL_RTC_TIME_Get\n + * TR SU LL_RTC_TIME_Get + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_TIME_GetSecond(RTCx)); +} + +/** + * @brief Memorize whether the daylight saving time change has been performed + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR BKP LL_RTC_TIME_EnableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Disable memorization whether the daylight saving time change has been performed. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR BKP LL_RTC_TIME_DisableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Check if RTC Day Light Saving stored operation has been enabled or not + * @rmtoll CR BKP LL_RTC_TIME_IsDayLightStoreEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)); +} + +/** + * @brief Subtract 1 hour (winter time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR SUB1H LL_RTC_TIME_DecHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_SUB1H); +} + +/** + * @brief Add 1 hour (summer time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR ADD1H LL_RTC_TIME_IncHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ADD1H); +} + +/** + * @brief Get Sub second value in the synchronous prescaler counter. + * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through + * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar + * SubSeconds value in second fraction ratio with time unit following + * generic formula: + * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending + * (ie. SHFP=0) when PREDIV_S >= SS. + * @rmtoll SSR SS LL_RTC_TIME_GetSubSecond + * @param RTCx RTC Instance + * @retval Sub second value (number between 0 and 65535) + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); +} + +/** + * @brief Synchronize to a remote clock with a high degree of precision. + * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @rmtoll SHIFTR ADD1S LL_RTC_TIME_Synchronize\n + * SHIFTR SUBFS LL_RTC_TIME_Synchronize + * @param RTCx RTC Instance + * @param ShiftSecond This parameter can be one of the following values: + * @arg @ref LL_RTC_SHIFT_SECOND_DELAY + * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE + * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF) + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction) +{ + WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Date Date + * @{ + */ + +/** + * @brief Set Year in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format + * @rmtoll DR YT LL_RTC_DATE_SetYear\n + * DR YU LL_RTC_DATE_SetYear + * @param RTCx RTC Instance + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))); +} + +/** + * @brief Get Year in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format + * @rmtoll DR YT LL_RTC_DATE_GetYear\n + * DR YU LL_RTC_DATE_GetYear + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x99 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU)); + return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)); +} + +/** + * @brief Set Week day + * @rmtoll DR WDU LL_RTC_DATE_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos); +} + +/** + * @brief Get Week day + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); +} + +/** + * @brief Set Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format + * @rmtoll DR MT LL_RTC_DATE_SetMonth\n + * DR MU LL_RTC_DATE_SetMonth + * @param RTCx RTC Instance + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos))); +} + +/** + * @brief Get Month in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll DR MT LL_RTC_DATE_GetMonth\n + * DR MU LL_RTC_DATE_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)); + return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)); +} + +/** + * @brief Set Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll DR DT LL_RTC_DATE_SetDay\n + * DR DU LL_RTC_DATE_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos))); +} + +/** + * @brief Get Day in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll DR DT LL_RTC_DATE_GetDay\n + * DR DU LL_RTC_DATE_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU)); + return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)); +} + +/** + * @brief Set date (WeekDay, Day, Month and Year) in BCD format + * @rmtoll DR WDU LL_RTC_DATE_Config\n + * DR MT LL_RTC_DATE_Config\n + * DR MU LL_RTC_DATE_Config\n + * DR DT LL_RTC_DATE_Config\n + * DR DU LL_RTC_DATE_Config\n + * DR YT LL_RTC_DATE_Config\n + * DR YU LL_RTC_DATE_Config + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) +{ + register uint32_t temp = 0U; + + temp = (WeekDay << RTC_DR_WDU_Pos) | \ + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); + + MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp); +} + +/** + * @brief Get date (WeekDay, Day, Month and Year) in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll DR WDU LL_RTC_DATE_Get\n + * DR MT LL_RTC_DATE_Get\n + * DR MU LL_RTC_DATE_Get\n + * DR DT LL_RTC_DATE_Get\n + * DR DU LL_RTC_DATE_Get\n + * DR YT LL_RTC_DATE_Get\n + * DR YU LL_RTC_DATE_Get + * @param RTCx RTC Instance + * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx) << RTC_OFFSET_DAY) | (LL_RTC_DATE_GetMonth(RTCx) << RTC_OFFSET_MONTH) | LL_RTC_DATE_GetYear(RTCx)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMA ALARMA + * @{ + */ + +/** + * @brief Enable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR ALRAE LL_RTC_ALMA_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Disable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR ALRAE LL_RTC_ALMA_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Specify the Alarm A masks. + * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_SetMask\n + * ALRMAR MSK3 LL_RTC_ALMA_SetMask\n + * ALRMAR MSK2 LL_RTC_ALMA_SetMask\n + * ALRMAR MSK1 LL_RTC_ALMA_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask); +} + +/** + * @brief Get the Alarm A masks. + * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_GetMask\n + * ALRMAR MSK3 LL_RTC_ALMA_GetMask\n + * ALRMAR MSK2 LL_RTC_ALMA_GetMask\n + * ALRMAR MSK1 LL_RTC_ALMA_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); +} + +/** + * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Disable AlarmA Week day selection (DU[3:0] represents the date ) + * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Set ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll ALRMAR DT LL_RTC_ALMA_SetDay\n + * ALRMAR DU LL_RTC_ALMA_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU), + (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos))); +} + +/** + * @brief Get ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll ALRMAR DT LL_RTC_ALMA_GetDay\n + * ALRMAR DU LL_RTC_ALMA_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU)); + return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos)); +} + +/** + * @brief Set ALARM A Weekday + * @rmtoll ALRMAR DU LL_RTC_ALMA_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Get ALARM A Weekday + * @rmtoll ALRMAR DU LL_RTC_ALMA_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set Alarm A time format (AM/24-hour or PM notation) + * @rmtoll ALRMAR PM LL_RTC_ALMA_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat); +} + +/** + * @brief Get Alarm A time format (AM or PM notation) + * @rmtoll ALRMAR PM LL_RTC_ALMA_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); +} + +/** + * @brief Set ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll ALRMAR HT LL_RTC_ALMA_SetHour\n + * ALRMAR HU LL_RTC_ALMA_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU), + (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))); +} + +/** + * @brief Get ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll ALRMAR HT LL_RTC_ALMA_GetHour\n + * ALRMAR HU LL_RTC_ALMA_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU)); + return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos)); +} + +/** + * @brief Set ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll ALRMAR MNT LL_RTC_ALMA_SetMinute\n + * ALRMAR MNU LL_RTC_ALMA_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos))); +} + +/** + * @brief Get ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll ALRMAR MNT LL_RTC_ALMA_GetMinute\n + * ALRMAR MNU LL_RTC_ALMA_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)); + return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos)); +} + +/** + * @brief Set ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll ALRMAR ST LL_RTC_ALMA_SetSecond\n + * ALRMAR SU LL_RTC_ALMA_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos))); +} + +/** + * @brief Get ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll ALRMAR ST LL_RTC_ALMA_GetSecond\n + * ALRMAR SU LL_RTC_ALMA_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); + return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos)); +} + +/** + * @brief Set Alarm A Time (hour, minute and second) in BCD format + * @rmtoll ALRMAR PM LL_RTC_ALMA_ConfigTime\n + * ALRMAR HT LL_RTC_ALMA_ConfigTime\n + * ALRMAR HU LL_RTC_ALMA_ConfigTime\n + * ALRMAR MNT LL_RTC_ALMA_ConfigTime\n + * ALRMAR MNU LL_RTC_ALMA_ConfigTime\n + * ALRMAR ST LL_RTC_ALMA_ConfigTime\n + * ALRMAR SU LL_RTC_ALMA_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +{ + register uint32_t temp = 0U; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll ALRMAR HT LL_RTC_ALMA_GetTime\n + * ALRMAR HU LL_RTC_ALMA_GetTime\n + * ALRMAR MNT LL_RTC_ALMA_GetTime\n + * ALRMAR MNU LL_RTC_ALMA_GetTime\n + * ALRMAR ST LL_RTC_ALMA_GetTime\n + * ALRMAR SU LL_RTC_ALMA_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm A Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRAE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask Value between Min_Data=0x00 and Max_Data=0xF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm A Mask the most-significant bits starting at this bit + * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm A Sub seconds value + * @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond); +} + +/** + * @brief Get Alarm A Sub seconds value + * @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMB ALARMB + * @{ + */ + +/** + * @brief Enable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR ALRBE LL_RTC_ALMB_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Disable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR ALRBE LL_RTC_ALMB_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Specify the Alarm B masks. + * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_SetMask\n + * ALRMBR MSK3 LL_RTC_ALMB_SetMask\n + * ALRMBR MSK2 LL_RTC_ALMB_SetMask\n + * ALRMBR MSK1 LL_RTC_ALMB_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask); +} + +/** + * @brief Get the Alarm B masks. + * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_GetMask\n + * ALRMBR MSK3 LL_RTC_ALMB_GetMask\n + * ALRMBR MSK2 LL_RTC_ALMB_GetMask\n + * ALRMBR MSK1 LL_RTC_ALMB_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); +} + +/** + * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Disable AlarmB Week day selection (DU[3:0] represents the date ) + * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Set ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll ALRMBR DT LL_RTC_ALMB_SetDay\n + * ALRMBR DU LL_RTC_ALMB_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), + (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos))); +} + +/** + * @brief Get ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll ALRMBR DT LL_RTC_ALMB_GetDay\n + * ALRMBR DU LL_RTC_ALMB_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU)); + return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos)); +} + +/** + * @brief Set ALARM B Weekday + * @rmtoll ALRMBR DU LL_RTC_ALMB_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Get ALARM B Weekday + * @rmtoll ALRMBR DU LL_RTC_ALMB_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set ALARM B time format (AM/24-hour or PM notation) + * @rmtoll ALRMBR PM LL_RTC_ALMB_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat); +} + +/** + * @brief Get ALARM B time format (AM or PM notation) + * @rmtoll ALRMBR PM LL_RTC_ALMB_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); +} + +/** + * @brief Set ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll ALRMBR HT LL_RTC_ALMB_SetHour\n + * ALRMBR HU LL_RTC_ALMB_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU), + (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))); +} + +/** + * @brief Get ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll ALRMBR HT LL_RTC_ALMB_GetHour\n + * ALRMBR HU LL_RTC_ALMB_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU)); + return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos)); +} + +/** + * @brief Set ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll ALRMBR MNT LL_RTC_ALMB_SetMinute\n + * ALRMBR MNU LL_RTC_ALMB_SetMinute + * @param RTCx RTC Instance + * @param Minutes between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos))); +} + +/** + * @brief Get ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll ALRMBR MNT LL_RTC_ALMB_GetMinute\n + * ALRMBR MNU LL_RTC_ALMB_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)); + return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos)); +} + +/** + * @brief Set ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll ALRMBR ST LL_RTC_ALMB_SetSecond\n + * ALRMBR SU LL_RTC_ALMB_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos))); +} + +/** + * @brief Get ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll ALRMBR ST LL_RTC_ALMB_GetSecond\n + * ALRMBR SU LL_RTC_ALMB_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +{ + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); + return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos)); +} + +/** + * @brief Set Alarm B Time (hour, minute and second) in BCD format + * @rmtoll ALRMBR PM LL_RTC_ALMB_ConfigTime\n + * ALRMBR HT LL_RTC_ALMB_ConfigTime\n + * ALRMBR HU LL_RTC_ALMB_ConfigTime\n + * ALRMBR MNT LL_RTC_ALMB_ConfigTime\n + * ALRMBR MNU LL_RTC_ALMB_ConfigTime\n + * ALRMBR ST LL_RTC_ALMB_ConfigTime\n + * ALRMBR SU LL_RTC_ALMB_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +{ + register uint32_t temp = 0U; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll ALRMBR HT LL_RTC_ALMB_GetTime\n + * ALRMBR HU LL_RTC_ALMB_GetTime\n + * ALRMBR MNT LL_RTC_ALMB_GetTime\n + * ALRMBR MNU LL_RTC_ALMB_GetTime\n + * ALRMBR ST LL_RTC_ALMB_GetTime\n + * ALRMBR SU LL_RTC_ALMB_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm B Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRBE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask Value between Min_Data=0x00 and Max_Data=0xF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm B Mask the most-significant bits starting at this bit + * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm B Sub seconds value + * @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond); +} + +/** + * @brief Get Alarm B Sub seconds value + * @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Timestamp Timestamp + * @{ + */ + +/** + * @brief Enable internal event timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR ITSE LL_RTC_TS_EnableInternalEvent + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ITSE); +} + +/** + * @brief Disable internal event timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR ITSE LL_RTC_TS_DisableInternalEvent + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ITSE); +} + +/** + * @brief Enable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR TSE LL_RTC_TS_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSE); +} + +/** + * @brief Disable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR TSE LL_RTC_TS_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSE); +} + +/** + * @brief Set Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting + * @rmtoll CR TSEDGE LL_RTC_TS_SetActiveEdge + * @param RTCx RTC Instance + * @param Edge This parameter can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); +} + +/** + * @brief Get Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR TSEDGE LL_RTC_TS_GetActiveEdge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); +} + +/** + * @brief Get Timestamp AM/PM notation (AM or 24-hour format) + * @rmtoll TSTR PM LL_RTC_TS_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TS_TIME_FORMAT_AM + * @arg @ref LL_RTC_TS_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); +} + +/** + * @brief Get Timestamp Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll TSTR HT LL_RTC_TS_GetHour\n + * TSTR HU LL_RTC_TS_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); +} + +/** + * @brief Get Timestamp Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll TSTR MNT LL_RTC_TS_GetMinute\n + * TSTR MNU LL_RTC_TS_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); +} + +/** + * @brief Get Timestamp Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll TSTR ST LL_RTC_TS_GetSecond\n + * TSTR SU LL_RTC_TS_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll TSTR HT LL_RTC_TS_GetTime\n + * TSTR HU LL_RTC_TS_GetTime\n + * TSTR MNT LL_RTC_TS_GetTime\n + * TSTR MNU LL_RTC_TS_GetTime\n + * TSTR ST LL_RTC_TS_GetTime\n + * TSTR SU LL_RTC_TS_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, + RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp Week day + * @rmtoll TSDR WDU LL_RTC_TS_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); +} + +/** + * @brief Get Timestamp Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll TSDR MT LL_RTC_TS_GetMonth\n + * TSDR MU LL_RTC_TS_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); +} + +/** + * @brief Get Timestamp Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll TSDR DT LL_RTC_TS_GetDay\n + * TSDR DU LL_RTC_TS_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll TSDR WDU LL_RTC_TS_GetDate\n + * TSDR MT LL_RTC_TS_GetDate\n + * TSDR MU LL_RTC_TS_GetDate\n + * TSDR DT LL_RTC_TS_GetDate\n + * TSDR DU LL_RTC_TS_GetDate + * @param RTCx RTC Instance + * @retval Combination of Weekday, Day and Month + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get time-stamp sub second value + * @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); +} + +#if defined(RTC_TAMPCR_TAMPTS) +/** + * @brief Activate timestamp on tamper detection event + * @rmtoll TAMPCR TAMPTS LL_RTC_TS_EnableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); +} + +/** + * @brief Disable timestamp on tamper detection event + * @rmtoll TAMPCR TAMPTS LL_RTC_TS_DisableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); +} +#endif /* RTC_TAMPCR_TAMPTS */ + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Tamper Tamper + * @{ + */ + +/** + * @brief Enable RTC_TAMPx input detection + * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Enable\n + * TAMPCR TAMP2E LL_RTC_TAMPER_Enable\n + * TAMPCR TAMP3E LL_RTC_TAMPER_Enable + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + SET_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @brief Clear RTC_TAMPx input detection + * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Disable\n + * TAMPCR TAMP2E LL_RTC_TAMPER_Disable\n + * TAMPCR TAMP3E LL_RTC_TAMPER_Disable + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + CLEAR_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @brief Enable Tamper mask flag + * @note Associated Tamper IT must not enabled when tamper mask is set. + * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_EnableMask\n + * TAMPCR TAMP2MF LL_RTC_TAMPER_EnableMask\n + * TAMPCR TAMP3MF LL_RTC_TAMPER_EnableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + SET_BIT(RTCx->TAMPCR, Mask); +} + +/** + * @brief Disable Tamper mask flag + * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_DisableMask\n + * TAMPCR TAMP2MF LL_RTC_TAMPER_DisableMask\n + * TAMPCR TAMP3MF LL_RTC_TAMPER_DisableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + CLEAR_BIT(RTCx->TAMPCR, Mask); +} + +/** + * @brief Enable backup register erase after Tamper event detection + * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP\n + * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP\n + * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + CLEAR_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @brief Disable backup register erase after Tamper event detection + * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP\n + * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP\n + * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + SET_BIT(RTCx->TAMPCR, Tamper); +} + +#if defined(RTC_TAMPCR_TAMPPUDIS) +/** + * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) + * @rmtoll TAMPCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS); +} + +/** + * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling) + * @rmtoll TAMPCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS); +} +#endif /* RTC_TAMPCR_TAMPPUDIS */ + +#if defined(RTC_TAMPCR_TAMPPRCH) +/** + * @brief Set RTC_TAMPx precharge duration + * @rmtoll TAMPCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge + * @param RTCx RTC Instance + * @param Duration This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration) +{ + MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration); +} + +/** + * @brief Get RTC_TAMPx precharge duration + * @rmtoll TAMPCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH)); +} +#endif /* RTC_TAMPCR_TAMPPRCH */ + +#if defined(RTC_TAMPCR_TAMPFLT) +/** + * @brief Set RTC_TAMPx filter count + * @rmtoll TAMPCR TAMPFLT LL_RTC_TAMPER_SetFilterCount + * @param RTCx RTC Instance + * @param FilterCount This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount) +{ + MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount); +} + +/** + * @brief Get RTC_TAMPx filter count + * @rmtoll TAMPCR TAMPFLT LL_RTC_TAMPER_GetFilterCount + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT)); +} +#endif /* RTC_TAMPCR_TAMPFLT */ + +#if defined(RTC_TAMPCR_TAMPFREQ) +/** + * @brief Set Tamper sampling frequency + * @rmtoll TAMPCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq + * @param RTCx RTC Instance + * @param SamplingFreq This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq) +{ + MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq); +} + +/** + * @brief Get Tamper sampling frequency + * @rmtoll TAMPCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ)); +} +#endif /* RTC_TAMPCR_TAMPFREQ */ + +/** + * @brief Enable Active level for Tamper input + * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n + * TAMPCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel\n + * TAMPCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + SET_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @brief Disable Active level for Tamper input + * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n + * TAMPCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel\n + * TAMPCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + CLEAR_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Wakeup Wakeup + * @{ + */ + +/** + * @brief Enable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR WUTE LL_RTC_WAKEUP_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Disable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR WUTE LL_RTC_WAKEUP_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Check if Wakeup timer is enabled or not + * @rmtoll CR WUTE LL_RTC_WAKEUP_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)); +} + +/** + * @brief Select Wakeup clock + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 + * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock + * @param RTCx RTC Instance + * @param WakeupClock This parameter can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) +{ + MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); +} + +/** + * @brief Get Wakeup clock + * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_GetClock + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); +} + +/** + * @brief Set Wakeup auto-reload value + * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR + * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload + * @param RTCx RTC Instance + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) +{ + MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); +} + +/** + * @brief Get Wakeup auto-reload value + * @rmtoll WUTR WUT LL_RTC_WAKEUP_GetAutoReload + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @rmtoll BKPxR BKP LL_RTC_BAK_SetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @arg @ref LL_RTC_BKP_DR20 + * @arg @ref LL_RTC_BKP_DR21 + * @arg @ref LL_RTC_BKP_DR22 + * @arg @ref LL_RTC_BKP_DR23 + * @arg @ref LL_RTC_BKP_DR24 + * @arg @ref LL_RTC_BKP_DR25 + * @arg @ref LL_RTC_BKP_DR26 + * @arg @ref LL_RTC_BKP_DR27 + * @arg @ref LL_RTC_BKP_DR28 + * @arg @ref LL_RTC_BKP_DR29 + * @arg @ref LL_RTC_BKP_DR30 + * @arg @ref LL_RTC_BKP_DR31 + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) +{ + register uint32_t tmp = 0U; + + tmp = (uint32_t)(&(RTCx->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @rmtoll BKPxR BKP LL_RTC_BAK_GetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @arg @ref LL_RTC_BKP_DR20 + * @arg @ref LL_RTC_BKP_DR21 + * @arg @ref LL_RTC_BKP_DR22 + * @arg @ref LL_RTC_BKP_DR23 + * @arg @ref LL_RTC_BKP_DR24 + * @arg @ref LL_RTC_BKP_DR25 + * @arg @ref LL_RTC_BKP_DR26 + * @arg @ref LL_RTC_BKP_DR27 + * @arg @ref LL_RTC_BKP_DR28 + * @arg @ref LL_RTC_BKP_DR29 + * @arg @ref LL_RTC_BKP_DR30 + * @arg @ref LL_RTC_BKP_DR31 + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) +{ + register uint32_t tmp = 0U; + + tmp = (uint32_t)(&(RTCx->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +/** + * @brief Set Calibration output frequency (1 Hz or 512 Hz) + * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR COE LL_RTC_CAL_SetOutputFreq\n + * CR COSEL LL_RTC_CAL_SetOutputFreq + * @param RTCx RTC Instance + * @param Frequency This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) +{ + MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); +} + +/** + * @brief Get Calibration output frequency (1 Hz or 512 Hz) + * @rmtoll CR COE LL_RTC_CAL_GetOutputFreq\n + * CR COSEL LL_RTC_CAL_GetOutputFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); +} + +/** + * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR + * @rmtoll CALR CALP LL_RTC_CAL_SetPulse + * @param RTCx RTC Instance + * @param Pulse This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE + * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); +} + +/** + * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm) + * @rmtoll CALR CALP LL_RTC_CAL_IsPulseInserted + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)); +} + +/** + * @brief Set the calibration cycle period + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR + * @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n + * CALR CALW16 LL_RTC_CAL_SetPeriod + * @param RTCx RTC Instance + * @param Period This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); +} + +/** + * @brief Get the calibration cycle period + * @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n + * CALR CALW16 LL_RTC_CAL_GetPeriod + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); +} + +/** + * @brief Set Calibration minus + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR + * @rmtoll CALR CALM LL_RTC_CAL_SetMinus + * @param RTCx RTC Instance + * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); +} + +/** + * @brief Get Calibration minus + * @rmtoll CALR CALM LL_RTC_CAL_GetMinus + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Internal Time-stamp flag + * @rmtoll ISR ITSF LL_RTC_IsActiveFlag_ITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)); +} + +/** + * @brief Get Recalibration pending Flag + * @rmtoll ISR RECALPF LL_RTC_IsActiveFlag_RECALP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)); +} + +/** + * @brief Get RTC_TAMP3 detection flag + * @rmtoll ISR TAMP3F LL_RTC_IsActiveFlag_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)); +} + +/** + * @brief Get RTC_TAMP2 detection flag + * @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)); +} + +/** + * @brief Get RTC_TAMP1 detection flag + * @rmtoll ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)); +} + +/** + * @brief Get Time-stamp overflow flag + * @rmtoll ISR TSOVF LL_RTC_IsActiveFlag_TSOV + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)); +} + +/** + * @brief Get Time-stamp flag + * @rmtoll ISR TSF LL_RTC_IsActiveFlag_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)); +} + +/** + * @brief Get Wakeup timer flag + * @rmtoll ISR WUTF LL_RTC_IsActiveFlag_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)); +} + +/** + * @brief Get Alarm B flag + * @rmtoll ISR ALRBF LL_RTC_IsActiveFlag_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)); +} + +/** + * @brief Get Alarm A flag + * @rmtoll ISR ALRAF LL_RTC_IsActiveFlag_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)); +} + +/** + * @brief Clear Internal Time-stamp flag + * @rmtoll ISR ITSF LL_RTC_ClearFlag_ITS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_ITSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear RTC_TAMP3 detection flag + * @rmtoll ISR TAMP3F LL_RTC_ClearFlag_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear RTC_TAMP2 detection flag + * @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear RTC_TAMP1 detection flag + * @rmtoll ISR TAMP1F LL_RTC_ClearFlag_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear Time-stamp overflow flag + * @rmtoll ISR TSOVF LL_RTC_ClearFlag_TSOV + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear Time-stamp flag + * @rmtoll ISR TSF LL_RTC_ClearFlag_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear Wakeup timer flag + * @rmtoll ISR WUTF LL_RTC_ClearFlag_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear Alarm B flag + * @rmtoll ISR ALRBF LL_RTC_ClearFlag_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear Alarm A flag + * @rmtoll ISR ALRAF LL_RTC_ClearFlag_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Get Initialization flag + * @rmtoll ISR INITF LL_RTC_IsActiveFlag_INIT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll ISR RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll ISR RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Get Initialization status flag + * @rmtoll ISR INITS LL_RTC_IsActiveFlag_INITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)); +} + +/** + * @brief Get Shift operation pending flag + * @rmtoll ISR SHPF LL_RTC_IsActiveFlag_SHP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)); +} + +/** + * @brief Get Wakeup timer write flag + * @rmtoll ISR WUTWF LL_RTC_IsActiveFlag_WUTW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)); +} + +/** + * @brief Get Alarm B write flag + * @rmtoll ISR ALRBWF LL_RTC_IsActiveFlag_ALRBW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)); +} + +/** + * @brief Get Alarm A write flag + * @rmtoll ISR ALRAWF LL_RTC_IsActiveFlag_ALRAW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR TSIE LL_RTC_EnableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Disable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR TSIE LL_RTC_DisableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Enable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR WUTIE LL_RTC_EnableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Disable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR WUTIE LL_RTC_DisableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Enable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR ALRBIE LL_RTC_EnableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Disable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR ALRBIE LL_RTC_DisableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Enable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR ALRAIE LL_RTC_EnableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Disable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CR ALRAIE LL_RTC_DisableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Enable Tamper 3 interrupt + * @rmtoll TAMPCR TAMP3IE LL_RTC_EnableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE); +} + +/** + * @brief Disable Tamper 3 interrupt + * @rmtoll TAMPCR TAMP3IE LL_RTC_DisableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE); +} + +/** + * @brief Enable Tamper 2 interrupt + * @rmtoll TAMPCR TAMP2IE LL_RTC_EnableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE); +} + +/** + * @brief Disable Tamper 2 interrupt + * @rmtoll TAMPCR TAMP2IE LL_RTC_DisableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE); +} + +/** + * @brief Enable Tamper 1 interrupt + * @rmtoll TAMPCR TAMP1IE LL_RTC_EnableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE); +} + +/** + * @brief Disable Tamper 1 interrupt + * @rmtoll TAMPCR TAMP1IE LL_RTC_DisableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE); +} + +/** + * @brief Enable all Tamper Interrupt + * @rmtoll TAMPCR TAMPIE LL_RTC_EnableIT_TAMP + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE); +} + +/** + * @brief Disable all Tamper Interrupt + * @rmtoll TAMPCR TAMPIE LL_RTC_DisableIT_TAMP + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE); +} + +/** + * @brief Check if Time-stamp interrupt is enabled or not + * @rmtoll CR TSIE LL_RTC_IsEnabledIT_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)); +} + +/** + * @brief Check if Wakeup timer interrupt is enabled or not + * @rmtoll CR WUTIE LL_RTC_IsEnabledIT_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)); +} + +/** + * @brief Check if Alarm B interrupt is enabled or not + * @rmtoll CR ALRBIE LL_RTC_IsEnabledIT_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)); +} + +/** + * @brief Check if Alarm A interrupt is enabled or not + * @rmtoll CR ALRAIE LL_RTC_IsEnabledIT_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)); +} + +/** + * @brief Check if Tamper 3 interrupt is enabled or not + * @rmtoll TAMPCR TAMP3IE LL_RTC_IsEnabledIT_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->TAMPCR, + RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)); +} + +/** + * @brief Check if Tamper 2 interrupt is enabled or not + * @rmtoll TAMPCR TAMP2IE LL_RTC_IsEnabledIT_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->TAMPCR, + RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)); + +} + +/** + * @brief Check if Tamper 1 interrupt is enabled or not + * @rmtoll TAMPCR TAMP1IE LL_RTC_IsEnabledIT_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->TAMPCR, + RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)); +} + +/** + * @brief Check if all the TAMPER interrupts are enabled or not + * @rmtoll TAMPCR TAMPIE LL_RTC_IsEnabledIT_TAMP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->TAMPCR, + RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); +ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct); +void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct); +ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_RTC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.c index 944f2e7c74c..c53b2d2796f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -92,7 +92,7 @@ (+) To control the DPSM (Data Path State Machine) and send/receive data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), - SDMMC_ReadFIFO(), DIO_WriteFIFO() and SDMMC_GetFIFOCount() functions. + SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions. *** Read Operations *** ======================= @@ -133,6 +133,15 @@ (#) Send the selected Write command. (#) Use the SDMMC flags/interrupts to check the transfer status. + + *** Command management operations *** + ===================================== + [..] + (#) The commands used for Read/Write//Erase operations are managed in + separate functions. + Each function allows to send the needed command with the related argument, + then check the response. + By the same approach, you could implement a command and check the response. @endverbatim ****************************************************************************** @@ -184,6 +193,13 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx); +static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); +static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); +static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); +static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); +static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); + /* Exported functions --------------------------------------------------------*/ /** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions @@ -312,6 +328,10 @@ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) /* Set power state to ON */ SDMMCx->POWER = SDMMC_POWER_PWRCTRL; + /* 1ms: required power up waiting time before starting the SD initialization + sequence */ + HAL_Delay(1); + return HAL_OK; } @@ -418,7 +438,7 @@ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) * that contains the configuration information for the SDMMC data. * @retval HAL status */ -HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data) +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data) { uint32_t tmpreg = 0; @@ -468,7 +488,6 @@ uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) return (SDMMCx->FIFO); } - /** * @brief Sets one of the two options of inserting read wait interval. * @param SDMMCx: Pointer to SDMMC register base @@ -489,6 +508,982 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM return HAL_OK; } +/** + * @} + */ + + +/** @defgroup HAL_SDMMC_LL_Group4 Command management functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Commands management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed commands. + +@endverbatim + * @{ + */ + +/** + * @brief Send the Data Block Lenght command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)BlockSize; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Read Single Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Read Multi Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Write Single Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Write Multi Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Start Address Erase command for SD and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the End Address Erase command for SD and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Start Address Erase command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the End Address Erase command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Erase command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Stop Transfer command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD12 STOP_TRANSMISSION */ + sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, 100000000/*SDMMC_CMDTIMEOUT*/); + + return errorstate; +} + +/** + * @brief Send the Select Deselect command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param addr: Address of the card to be selected + * @retval HAL status + */ +uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD7 SDMMC_SEL_DESEL_CARD */ + sdmmc_cmdinit.Argument = (uint32_t)Addr; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Go Idle State command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdError(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Operating Condition command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD8 to verify SD card interface operating condition */ + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /* CMD Response: R7 */ + sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp7(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Application command to verify that that the next command + * is an application specific com-mand rather than a standard command + * and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = (uint32_t)Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + /* If there is a HAL_ERROR, it is a MMC card, else + it is a SD card: SD card 2.0 (voltage range mismatch) + or SD card 1.x */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the command asking the accessed card to send its operating + * condition register (OCR) + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | SdType; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp3(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Bus Width command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = (uint32_t)BusWidth; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send SCR command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD51 SD_APP_SEND_SCR */ + sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send CID command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD2 ALL_SEND_CID */ + sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = (uint32_t)Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA); + + return errorstate; +} + +/** + * @brief Send the Status command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = (uint32_t)Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Status register command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Sends host capacity support information and activates the card's + * initialization process. Send SDMMC_CMD_SEND_OP_COND command + * @param SDIOx: Pointer to SDIO register base + * @parame Argument: Argument used for the command + * @retval HAL status + */ +uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp3(SDMMCx); + + return errorstate; +} + +/** + * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand + * @param SDIOx: Pointer to SDIO register base + * @parame Argument: Argument used for the command + * @retval HAL status + */ +uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief Checks for error conditions for CMD0. + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + + do + { + if (count-- == 0) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R1 response. + * @param hsd: SD handle + * @param SD_CMD: The sent command index + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) +{ + uint32_t response_r1; + + /* 8 is the number of required instructions cycles for the below loop statement. + The Timeout is expressed in ms */ + register uint32_t count = Timeout * (SystemCoreClock / 8 /1000); + + do + { + if (count-- == 0) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); + + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Check response received is of desired command */ + if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + + /* We have received response, retrieve it for analysis */ + response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) + { + return SDMMC_ERROR_NONE; + } + else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) + { + return SDMMC_ERROR_ADDR_OUT_OF_RANGE; + } + else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) + { + return SDMMC_ERROR_ADDR_MISALIGNED; + } + else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) + { + return SDMMC_ERROR_BLOCK_LEN_ERR; + } + else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) + { + return SDMMC_ERROR_ERASE_SEQ_ERR; + } + else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) + { + return SDMMC_ERROR_BAD_ERASE_PARAM; + } + else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) + { + return SDMMC_ERROR_WRITE_PROT_VIOLATION; + } + else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) + { + return SDMMC_ERROR_LOCK_UNLOCK_FAILED; + } + else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) + { + return SDMMC_ERROR_CARD_ECC_FAILED; + } + else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) + { + return SDMMC_ERROR_CC_ERR; + } + else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) + { + return SDMMC_ERROR_STREAM_READ_UNDERRUN; + } + else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) + { + return SDMMC_ERROR_STREAM_WRITE_OVERRUN; + } + else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) + { + return SDMMC_ERROR_CID_CSD_OVERWRITE; + } + else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) + { + return SDMMC_ERROR_WP_ERASE_SKIP; + } + else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) + { + return SDMMC_ERROR_CARD_ECC_DISABLED; + } + else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) + { + return SDMMC_ERROR_ERASE_RESET; + } + else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) + { + return SDMMC_ERROR_AKE_SEQ_ERR; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + +/** + * @brief Checks for error conditions for R2 (CID or CSD) response. + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + + do + { + if (count-- == 0) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* No error flag set */ + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + } + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R3 (OCR) response. + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + + do + { + if (count-- == 0) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); + + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else + + { + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + } + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R6 (RCA) response. + * @param hsd: SD handle + * @param SD_CMD: The sent command index + * @param pRCA: Pointer to the variable that will contain the SD card relative + * address RCA + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA) +{ + uint32_t response_r1; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + + do + { + if (count-- == 0) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); + + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Check response received is of desired command */ + if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + + /* We have received response, retrieve it. */ + response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) + { + *pRCA = (uint16_t) (response_r1 >> 16); + + return SDMMC_ERROR_NONE; + } + else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + +/** + * @brief Checks for error conditions for R7 response. + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + + do + { + if (count-- == 0) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); + + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + /* Card is SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) + { + /* Card is SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); + } + + return SDMMC_ERROR_NONE; + +} + /** * @} */ @@ -497,7 +1492,7 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM * @} */ -#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */ +#endif /* (HAL_SD_MODULE_ENABLED) */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h index 01c7f673c7d..8d413560758 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention @@ -145,6 +145,196 @@ typedef struct /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants * @{ */ +#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ +#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ +#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ +#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ +#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ +#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ +#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ +#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ +#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ +#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ +#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ +#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ +#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ +#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ +#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ +#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ +#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ +#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ +#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ +#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ +#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ +#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ + +/** + * @brief SDMMC Commands Index + */ +#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its + operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information + and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ +#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands + (read, write, lock). Default block length is fixed to 512 Bytes. Not effective + for SDHS and SDXC. */ +#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by + STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command + system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. + Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by + the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather + than a standard command. */ +#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card + for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ + +/** + * @brief Following commands are SD Card Specific commands. + * SDMMC_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus + widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with + 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to + send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ + +/** + * @brief Following commands are SD Card Specific security commands. + * SDMMC_CMD_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) +#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) +#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) +#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) +#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) +#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) +#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) + +/** + * @brief Masks for errors Card Status R1 (OCR Register) + */ +#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) +#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) +#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) +#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) +#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) +#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) +#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) +#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) +#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) +#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) +#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) +#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) +#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) +#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) +#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) +#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) +#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) +#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) +#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) +#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) + +/** + * @brief Masks for R6 Response + */ +#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) +#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) +#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) + +#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) +#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) +#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) +#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) + +#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) + +#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) + +#define SDMMC_ALLZERO ((uint32_t)0x00000000U) + +#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) +#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) +#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) + +#define SDMMC_DATATIMEOUT ((uint32_t)0x00100000U) + +#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) +#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) +#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) +#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) +#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) + +#define SDMMC_HALFFIFO ((uint32_t)0x00000008U) +#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) + +/** + * @brief Command Class supported + */ +#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) + +#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ +#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ + /** @defgroup SDMMC_LL_Clock_Edge Clock Edge * @{ @@ -153,7 +343,7 @@ typedef struct #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ - ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) + ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) /** * @} */ @@ -165,7 +355,7 @@ typedef struct #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ - ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) + ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) /** * @} */ @@ -177,7 +367,7 @@ typedef struct #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ - ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) + ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) /** * @} */ @@ -190,8 +380,8 @@ typedef struct #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ - ((WIDE) == SDMMC_BUS_WIDE_4B) || \ - ((WIDE) == SDMMC_BUS_WIDE_8B)) + ((WIDE) == SDMMC_BUS_WIDE_4B) || \ + ((WIDE) == SDMMC_BUS_WIDE_8B)) /** * @} */ @@ -203,7 +393,7 @@ typedef struct #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ - ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) + ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) /** * @} */ @@ -232,8 +422,8 @@ typedef struct #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ - ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ - ((RESPONSE) == SDMMC_RESPONSE_LONG)) + ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ + ((RESPONSE) == SDMMC_RESPONSE_LONG)) /** * @} */ @@ -246,8 +436,8 @@ typedef struct #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ - ((WAIT) == SDMMC_WAIT_IT) || \ - ((WAIT) == SDMMC_WAIT_PEND)) + ((WAIT) == SDMMC_WAIT_IT) || \ + ((WAIT) == SDMMC_WAIT_PEND)) /** * @} */ @@ -259,7 +449,7 @@ typedef struct #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ - ((CPSM) == SDMMC_CPSM_ENABLE)) + ((CPSM) == SDMMC_CPSM_ENABLE)) /** * @} */ @@ -273,9 +463,9 @@ typedef struct #define SDMMC_RESP4 ((uint32_t)0x0000000C) #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ - ((RESP) == SDMMC_RESP2) || \ - ((RESP) == SDMMC_RESP3) || \ - ((RESP) == SDMMC_RESP4)) + ((RESP) == SDMMC_RESP2) || \ + ((RESP) == SDMMC_RESP3) || \ + ((RESP) == SDMMC_RESP4)) /** * @} */ @@ -308,20 +498,20 @@ typedef struct #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) + ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) /** * @} */ @@ -333,7 +523,7 @@ typedef struct #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ - ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) + ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) /** * @} */ @@ -345,7 +535,7 @@ typedef struct #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ - ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) + ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) /** * @} */ @@ -357,7 +547,7 @@ typedef struct #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ - ((DPSM) == SDMMC_DPSM_ENABLE)) + ((DPSM) == SDMMC_DPSM_ENABLE)) /** * @} */ @@ -369,7 +559,7 @@ typedef struct #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ - ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) + ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) /** * @} */ @@ -428,6 +618,10 @@ typedef struct #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT +#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ + SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ + SDMMC_FLAG_DBCKEND)) /** * @} */ @@ -464,7 +658,7 @@ typedef struct SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) /* SDMMC Initialization Frequency (400KHz max) */ -#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) +#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* SDMMC Data Transfer Frequency (25MHz max) */ #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) @@ -751,7 +945,6 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); /** @addtogroup HAL_SDMMC_LL_Group2 * @{ */ -/* Blocking mode: Polling */ uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); /** @@ -772,13 +965,40 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); /* SDMMC Cards mode management functions */ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); +/* SDMMC Commands management functions */ +uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); +uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); +uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); +uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); +uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); +uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); +uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); +uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); +uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); +uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); +uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType); +uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); +uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); +uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.c new file mode 100644 index 00000000000..4b781130058 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.c @@ -0,0 +1,589 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_spi.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief SPI LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_spi.h" +#include "stm32f7xx_ll_bus.h" +#include "stm32f7xx_ll_rcc.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) + +/** @addtogroup SPI_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SPI_LL_Private_Constants SPI Private Constants + * @{ + */ +/* SPI registers Masks */ +#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \ + SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \ + SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \ + SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \ + SPI_CR1_BIDIMODE) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Private_Macros SPI Private Macros + * @{ + */ +#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ + || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ + || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ + || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) + +#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ + || ((__VALUE__) == LL_SPI_MODE_SLAVE)) + +#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) + +#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ + || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) + +#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ + || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) + +#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ + || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ + || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) + +#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) + +#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ + || ((__VALUE__) == LL_SPI_MSB_FIRST)) + +#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ + || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) + +#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + +#if defined(SPI1) + if (SPIx == SPI1) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); + + status = SUCCESS; + } +#endif /* SPI1 */ +#if defined(SPI2) + if (SPIx == SPI2) + { + /* Force reset of SPI clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); + + /* Release reset of SPI clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); + + status = SUCCESS; + } +#endif /* SPI2 */ +#if defined(SPI3) + if (SPIx == SPI3) + { + /* Force reset of SPI clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); + + /* Release reset of SPI clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); + + status = SUCCESS; + } +#endif /* SPI3 */ +#if defined(SPI4) + if (SPIx == SPI4) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4); + + status = SUCCESS; + } +#endif /* SPI4 */ +#if defined(SPI5) + if (SPIx == SPI5) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5); + + status = SUCCESS; + } +#endif /* SPI5 */ +#if defined(SPI6) + if (SPIx == SPI6) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6); + + status = SUCCESS; + } +#endif /* SPI6 */ + + return status; +} + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), + * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the SPI Instance SPIx*/ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + + /* Check the SPI parameters from SPI_InitStruct*/ + assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); + assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); + assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); + assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); + assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); + assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); + assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate)); + assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); + assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); + + if (LL_SPI_IsEnabled(SPIx) == 0x00000000U) + { + /*---------------------------- SPIx CR1 Configuration ------------------------ + * Configure SPIx CR1 with parameters: + * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits + * - Master/Slave Mode: SPI_CR1_MSTR bit + * - ClockPolarity: SPI_CR1_CPOL bit + * - ClockPhase: SPI_CR1_CPHA bit + * - NSS management: SPI_CR1_SSM bit + * - BaudRate prescaler: SPI_CR1_BR[2:0] bits + * - BitOrder: SPI_CR1_LSBFIRST bit + * - CRCCalculation: SPI_CR1_CRCEN bit + */ + MODIFY_REG(SPIx->CR1, + SPI_CR1_CLEAR_MASK, + SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | + SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase | + SPI_InitStruct->NSS | SPI_InitStruct->BaudRate | + SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation); + + /*---------------------------- SPIx CR2 Configuration ------------------------ + * Configure SPIx CR2 with parameters: + * - DataWidth: DS[3:0] bits + * - NSS management: SSOE bit + */ + MODIFY_REG(SPIx->CR2, + SPI_CR2_DS | SPI_CR2_SSOE, + SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U)); + + /*---------------------------- SPIx CRCPR Configuration ---------------------- + * Configure SPIx CRCPR with parameters: + * - CRCPoly: CRCPOLY[15:0] bits + */ + if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); + LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); + } + status = SUCCESS; + } + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); + return status; +} + +/** + * @brief Set each @ref LL_SPI_InitTypeDef field to default value. + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) +{ + /* Set SPI_InitStruct fields to default values */ + SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; + SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; + SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; + SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; + SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; + SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; + SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; + SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; + SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + SPI_InitStruct->CRCPoly = 7U; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2S_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Constants I2S Private Constants + * @{ + */ +/* I2S registers Masks */ +#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ + SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) + +#define I2S_I2SPR_CLEAR_MASK 0x0002U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Macros I2S Private Macros + * @{ + */ + +#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) + +#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ + || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) + +#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ + || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) + +#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ + || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) + +#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ + || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) + +#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ + && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ + || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) + +#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) + +#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ + || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI/I2S registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +{ + return LL_SPI_DeInit(SPIx); +} + +/** + * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), + * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are Initialized + * - ERROR: SPI registers are not Initialized + */ +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +{ + uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U; + uint32_t tmp = 0U; + uint32_t sourceclock = 0U; + ErrorStatus status = ERROR; + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); + assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); + assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); + assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); + assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); + assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); + + if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) + { + /*---------------------------- SPIx I2SCFGR Configuration -------------------- + * Configure SPIx I2SCFGR with parameters: + * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit + * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits + * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits + * - ClockPolarity: SPI_I2SCFGR_CKPOL bit + */ + + /* Write to SPIx I2SCFGR */ + MODIFY_REG(SPIx->I2SCFGR, + I2S_I2SCFGR_CLEAR_MASK, + I2S_InitStruct->Mode | I2S_InitStruct->Standard | + I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | + SPI_I2SCFGR_I2SMOD); + + /*---------------------------- SPIx I2SPR Configuration ---------------------- + * Configure SPIx I2SPR with parameters: + * - MCLKOutput: SPI_I2SPR_MCKOE bit + * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits + */ + + /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) + * else, default values are used: i2sodd = 0U, i2sdiv = 2U. + */ + if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) + { + /* Check the frame length (For the Prescaler computing) + * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). + */ + if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) + { + /* Packet length is 32 bits */ + packetlength = 2U; + } + + /* If an external I2S clock has to be used, the specific define should be set + in the project configuration or in the stm32f7xx_ll_rcc.h file */ + /* Get the I2S source clock value */ + sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE); + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + } + + /* Remove the floating point */ + tmp = tmp / 10U; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2U); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t)(i2sodd << 8U); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + { + /* Set the default values */ + i2sdiv = 2U; + i2sodd = 0U; + } + + /* Write to SPIx I2SPR register the computed value */ + WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); + + status = SUCCESS; + } + return status; +} + +/** + * @brief Set each @ref LL_I2S_InitTypeDef field to default value. + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; + I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; + I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; + I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; + I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; + I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; +} + +/** + * @brief Set linear and parity prescaler. + * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n + * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). + * @param SPIx SPI Instance + * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF. + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) +{ + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); + assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); + + /* Write to SPIx I2SPR */ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.h new file mode 100644 index 00000000000..b2ae88c91f8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.h @@ -0,0 +1,2293 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_spi.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_SPI_H +#define __STM32F7xx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. The slave clock does not need to be set. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ +#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ +#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ +#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ +#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ +#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol + * @{ + */ +#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ +#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ +#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ +#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ +#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ +#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ +#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ +#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ +#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */ +#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */ +#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */ +#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */ +#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */ +#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */ +#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */ +#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */ +#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */ +#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */ +#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */ +#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */ +#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + * @{ + */ +#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length + * @{ + */ +#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ +#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold + * @{ + */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level + * @{ + */ +#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ +#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ +#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ +#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level + * @{ + */ +#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ +#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ +#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ +#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity + * @{ + */ +#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ +#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)); +} + +/** + * @brief Set SPI operation mode to Master or Slave + * @note This bit should not be changed when communication is ongoing. + * @rmtoll CR1 MSTR LL_SPI_SetMode\n + * CR1 SSI LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); +} + +/** + * @brief Get SPI operation mode (Master or Slave) + * @rmtoll CR1 MSTR LL_SPI_GetMode\n + * CR1 SSI LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); +} + +/** + * @brief Set serial protocol used + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR2 FRF LL_SPI_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); +} + +/** + * @brief Get serial protocol used + * @rmtoll CR2 FRF LL_SPI_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); +} + +/** + * @brief Set clock phase + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); +} + +/** + * @brief Get clock phase + * @rmtoll CR1 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); +} + +/** + * @brief Set clock polarity + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); +} + +/** + * @brief Get clock polarity + * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); +} + +/** + * @brief Set baud rate prescaler + * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. + * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param BaudRate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); +} + +/** + * @brief Get baud rate prescaler + * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); +} + +/** + * @brief Set transfer bit order + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); +} + +/** + * @brief Get transfer bit order + * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); +} + +/** + * @brief Set transfer direction mode + * @note For Half-Duplex mode, Rx Direction is set by default. + * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. + * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n + * CR1 BIDIMODE LL_SPI_SetTransferDirection\n + * CR1 BIDIOE LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); +} + +/** + * @brief Get transfer direction mode + * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n + * CR1 BIDIMODE LL_SPI_GetTransferDirection\n + * CR1 BIDIOE LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); +} + +/** + * @brief Set frame data width + * @rmtoll CR2 DS LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); +} + +/** + * @brief Get frame data width + * @rmtoll CR2 DS LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); +} + +/** + * @brief Set threshold of RXFIFO that triggers an RXNE event + * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_TH_HALF + * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); +} + +/** + * @brief Get threshold of RXFIFO that triggers an RXNE event + * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_TH_HALF + * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_CRC_Management CRC Management + * @{ + */ + +/** + * @brief Enable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_EnableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Disable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_DisableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Check if CRC is enabled + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)); +} + +/** + * @brief Set CRC Length + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth + * @param SPIx SPI Instance + * @param CRCLength This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); +} + +/** + * @brief Get CRC Length + * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); +} + +/** + * @brief Set CRCNext to transfer CRC on the line + * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. + * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); +} + +/** + * @brief Set polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial + * @param SPIx SPI Instance + * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); +} + +/** + * @brief Get polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPR)); +} + +/** + * @brief Get Rx CRC + * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRCR)); +} + +/** + * @brief Get Tx CRC + * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRCR)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management + * @{ + */ + +/** + * @brief Set NSS mode + * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. + * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); + MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); +} + +/** + * @brief Get NSS mode + * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +{ + register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + return (Ssm | Ssoe); +} + +/** + * @brief Enable NSS pulse management + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_NSSP); +} + +/** + * @brief Disable NSS pulse management + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); +} + +/** + * @brief Check if NSS pulse is enabled + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)); +} + +/** + * @brief Get CRC error flag + * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)); +} + +/** + * @brief Get mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)); +} + +/** + * @brief Get busy flag + * @note The BSY flag is cleared under any one of the following conditions: + * -When the SPI is correctly disabled + * -When a fault is detected in Master mode (MODF bit set to 1) + * -In Master mode, when it finishes a data transmission and no new data is ready to be + * sent + * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between + * each data transfer. + * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)); +} + +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)); +} + +/** + * @brief Get FIFO reception Level + * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_EMPTY + * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL + * @arg @ref LL_SPI_RX_FIFO_HALF_FULL + * @arg @ref LL_SPI_RX_FIFO_FULL + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); +} + +/** + * @brief Get FIFO Transmission Level + * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_TX_FIFO_EMPTY + * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL + * @arg @ref LL_SPI_TX_FIFO_HALF_FULL + * @arg @ref LL_SPI_TX_FIFO_FULL + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); +} + +/** + * @brief Clear CRC error flag + * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); +} + +/** + * @brief Clear mode fault error flag + * @note Clearing this flag is done by a read access to the SPIx_SR + * register followed by a write access to the SPIx_CR1 register + * @rmtoll SR MODF LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; + tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); + (void) tmpreg; +} + +/** + * @brief Clear overrun error flag + * @note Clearing this flag is done by a read access to the SPIx_DR + * register followed by a read access to the SPIx_SR register + * @rmtoll SR OVR LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->DR; + (void) tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @brief Clear frame format error flag + * @note Clearing this flag is done by reading SPIx_SR register + * @rmtoll SR FRE LL_SPI_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable error interrupt + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Enable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Enable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Disable error interrupt + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Disable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Disable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Check if error interrupt is enabled + * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)); +} + +/** + * @brief Check if Rx buffer not empty interrupt is enabled + * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)); +} + +/** + * @brief Check if Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)); +} + +/** + * @brief Set parity of Last DMA reception + * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX + * @param SPIx SPI Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); +} + +/** + * @brief Get parity configuration for Last DMA reception + * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + */ +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); +} + +/** + * @brief Set parity of Last DMA transmission + * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX + * @param SPIx SPI Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); +} + +/** + * @brief Get parity configuration for Last DMA transmission + * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + */ +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll DR DR LL_SPI_DMA_GetRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +{ + return (uint32_t) & (SPIx->DR); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA Management + * @{ + */ + +/** + * @brief Read 8-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +{ + return (uint8_t)(READ_REG(SPIx->DR)); +} + +/** + * @brief Read 16-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +{ + return (uint16_t)(READ_REG(SPIx->DR)); +} + +/** + * @brief Write 8-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ + *((__IO uint8_t *)&SPIx->DR) = TxData; +} + +/** + * @brief Write 16-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + *((__IO uint16_t *)&SPIx->DR) = TxData; +} + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2S_LL I2S + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure + * @{ + */ + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_LL_EC_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_STANDARD + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ + + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ + + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT + + This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ + + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ + + Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity + and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ + + + uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_LL_EC_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ + +} LL_I2S_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2S_ReadReg function + * @{ + */ +#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ +#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ +#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ +#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_DATA_FORMAT Data format + * @{ + */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ +#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_STANDARD I2s Standard + * @{ + */ +#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ +#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ +#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ +#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ +#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ +#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ +#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ +#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor + * @{ + */ +#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output + * @{ + */ +#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ +#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency + * @{ + */ + +#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros + * @{ + */ + +/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Select I2S mode and Enable I2S peripheral + * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n + * I2SCFGR I2SE LL_I2S_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Disable I2S peripheral + * @rmtoll I2SCFGR I2SE LL_I2S_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Check if I2S peripheral is enabled + * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)); +} + +/** + * @brief Set I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n + * I2SCFGR CHLEN LL_I2S_SetDataFormat + * @param SPIx SPI Instance + * @param DataFormat This parameter can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); +} + +/** + * @brief Get I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n + * I2SCFGR CHLEN LL_I2S_GetDataFormat + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); +} + +/** + * @brief Set I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + SET_BIT(SPIx->I2SCFGR, ClockPolarity); +} + +/** + * @brief Get I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); +} + +/** + * @brief Set I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n + * I2SCFGR PCMSYNC LL_I2S_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); +} + +/** + * @brief Get I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n + * I2SCFGR PCMSYNC LL_I2S_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); +} + +/** + * @brief Set I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); +} + +/** + * @brief Get I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); +} + +/** + * @brief Set I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); +} + +/** + * @brief Get I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear + * @param SPIx SPI Instance + * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); +} + +/** + * @brief Set I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity + * @param SPIx SPI Instance + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); +} + +/** + * @brief Get I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); +} + +/** + * @brief Enable the master clock ouput (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Disable the master clock ouput (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Check if the master clock ouput (Pin MCK) is enabled + * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)); +} + +#if defined(SPI_I2SCFGR_ASTRTEN) +/** + * @brief Enable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Disable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Check if asynchronous start is enabled + * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)); +} +#endif /* SPI_I2SCFGR_ASTRTEN */ + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_FLAG FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_RXNE(SPIx); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_TXE(SPIx); +} + +/** + * @brief Get busy flag + * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_BSY(SPIx); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_OVR(SPIx); +} + +/** + * @brief Get underrun error flag + * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)); +} + +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_FRE(SPIx); +} + +/** + * @brief Get channel side flag. + * @note 0: Channel Left has to be transmitted or has been received\n + * 1: Channel Right has to be transmitted or has been received\n + * It has no significance in PCM mode. + * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)); +} + +/** + * @brief Clear overrun error flag + * @rmtoll SR OVR LL_I2S_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_OVR(SPIx); +} + +/** + * @brief Clear underrun error flag + * @rmtoll SR UDR LL_I2S_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void)tmpreg; +} + +/** + * @brief Clear frame format error flag + * @rmtoll SR FRE LL_I2S_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_FRE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_IT Interrupt Management + * @{ + */ + +/** + * @brief Enable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_ERR(SPIx); +} + +/** + * @brief Enable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_RXNE(SPIx); +} + +/** + * @brief Enable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_TXE(SPIx); +} + +/** + * @brief Disable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_ERR(SPIx); +} + +/** + * @brief Disable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_RXNE(SPIx); +} + +/** + * @brief Disable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_TXE(SPIx); +} + +/** + * @brief Check if ERR IT is enabled + * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_ERR(SPIx); +} + +/** + * @brief Check if RXNE IT is enabled + * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_RXNE(SPIx); +} + +/** + * @brief Check if TXE IT is enabled + * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_TXE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DMA DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_RX(SPIx); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_RX(SPIx); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_RX(SPIx); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_TX(SPIx); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_TX(SPIx); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_TX(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DATA DATA Management + * @{ + */ + +/** + * @brief Read 16-Bits in data register + * @rmtoll DR DR LL_I2S_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) +{ + return LL_SPI_ReceiveData16(SPIx); +} + +/** + * @brief Write 16-Bits in data register + * @rmtoll DR DR LL_I2S_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + LL_SPI_TransmitData16(SPIx, TxData); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_system.h new file mode 100644 index 00000000000..175cc7fd68b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_system.h @@ -0,0 +1,1039 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_system.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of SYSTEM LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_SYSTEM_H +#define __STM32F7xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP +* @{ +*/ +#define LL_SYSCFG_REMAP_BOOT0 0x00000000U /*!< Boot information after Reset */ +#define LL_SYSCFG_REMAP_BOOT1 SYSCFG_MEMRMP_MEM_BOOT /*!< Boot information after Reset */ +/** + * @} + */ + + +#if defined(SYSCFG_MEMRMP_SWP_FB) +/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE + * @{ + */ +#define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM) + and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/ + +#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_SWP_FB /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM) + and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */ +/** + * @} + */ +#endif /* SYSCFG_MEMRMP_SWP_FB */ + +#if defined(SYSCFG_PMC_MII_RMII_SEL) + /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC +* @{ +*/ +#define LL_SYSCFG_PMC_ETHMII 0x00000000U /*!< ETH Media MII interface */ +#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */ + +/** + * @} + */ +#endif /* SYSCFG_PMC_MII_RMII_SEL */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#if defined(SYSCFG_PMC_I2C1_FMP) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */ +#endif /* SYSCFG_PMC_I2C1_FMP */ +#if defined(SYSCFG_PMC_I2C4_FMP) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */ +#endif /* SYSCFG_PMC_I2C4_FMP */ +#if defined(SYSCFG_PMC_I2C_PB6_FMP) +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#endif /* SYSCFG_PMC_I2C_PB6_FMP */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ +#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ +#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ +#if defined(GPIOF) +#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ +#endif /* GPIOG */ +#define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ +#if defined(GPIOI) +#define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ +#endif /* GPIOI */ +#if defined(GPIOJ) +#define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */ +#endif /* GPIOJ */ +#if defined(GPIOK) +#define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */ +#endif /* GPIOK */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#if defined(SYSCFG_CBR_CLL) +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the Lockup output (raised during core + lockup state) of Cortex-M7 with Break Input of TIMER1, TIMER8 */ +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection with TIMER1, TIMER8 Break input. + It also locks (write protect) the PVD_EN and PVDSEL[2:0] bits + of the power controller */ +#endif /* SYSCFG_CBR_CLL */ +/** + * @} + */ +/** @defgroup SYSTEM_LL_EC_CMP_PD SYSCFG CMP PD + * @{ + */ +#define LL_SYSCFG_DISABLE_CMP_PD 0x00000000U /*!< I/O compensation cell power-down mode */ +#define LL_SYSCFG_ENABLE_CMP_PD SYSCFG_CMPCR_CMP_PD /*!< I/O compensation cell enabled */ +/** + * @} + */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP /*!< LPTIIM1 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT) +#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */ +#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_CAN3_STOP*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ +#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ +#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ +#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ +#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ +#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ +#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ +#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ +#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ +#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Enables the FMC Memory Mapping Swapping + * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping + * @note SDRAM is accessible at 0x60000000 and NOR/RAM + * is accessible at 0xC0000000 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void) +{ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0); +} + +/** + * @brief Disables the FMC Memory Mapping Swapping + * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping + * @note SDRAM is accessible at 0xC0000000 (default mapping) + * and NOR/RAM is accessible at 0x60000000 (default mapping) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void) +{ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC); +} + +/** + * @brief Enables the Compensation Cell + * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) +{ + SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); +} + +/** + * @brief Disables the Compensation Cell + * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); +} + +/** + * @brief Get Compensation Cell ready Flag + * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) +{ + return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY)); +} + + +/** + * @brief Get the memory boot mapping as configured by user + * @rmtoll SYSCFG_MEMRMP MEM_BOOT LL_SYSCFG_GetRemapMemoryBoot + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_BOOT0 + * @arg @ref LL_SYSCFG_REMAP_BOOT1 + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemoryBoot(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)); +} + +#if defined(SYSCFG_PMC_MII_RMII_SEL) +/** + * @brief Select Ethernet PHY interface + * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface + * @param Interface This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_PMC_ETHMII + * @arg @ref LL_SYSCFG_PMC_ETHRMII + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) +{ + MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface); +} + +/** + * @brief Get Ethernet PHY interface + * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_PMC_ETHMII + * @arg @ref LL_SYSCFG_PMC_ETHRMII + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL)); +} +#endif /* SYSCFG_PMC_MII_RMII_SEL */ + + +#if defined(SYSCFG_MEMRMP_SWP_FB) +/** + * @brief Select Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode + * @param Bank This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) +{ + MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB, Bank); +} + +/** + * @brief Get Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB)); +} + +#endif /* SYSCFG_MEMRMP_SWP_FB */ + +#if defined(SYSCFG_PMC_I2C1_FMP) +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->PMC, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->PMC, ConfigFastModePlus); +} +#endif /* SYSCFG_PMC_I2C1_FMP */ + + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI + * @arg @ref LL_SYSCFG_EXTI_PORTJ + * @arg @ref LL_SYSCFG_EXTI_PORTK + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI + * @arg @ref LL_SYSCFG_EXTI_PORTJ + * @arg @ref LL_SYSCFG_EXTI_PORTK + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U)); +} + +#if defined(SYSCFG_CBR_CLL) +/** + * @brief Set connections to TIM1/8/15/16/17 Break inputs + * SYSCFG_CBR CLL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CBR PVDL LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL, Break); +} + +/** + * @brief Get connections to TIM1/8/15/16/17 Break inputs + * SYSCFG_CBR CLL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CBR PVDL LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL)); +} +#endif /* SYSCFG_CBR_CLL */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @note For STM32F75xxx and STM32F74xxx devices, the device ID is 0x449 + * @note For STM32F77xxx and STM32F76xxx devices, the device ID is 0x451 + * @note For STM32F72xxx and STM32F73xxx devices, the device ID is 0x452 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Set Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + * @param PinAssignment This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); +} + +/** + * @brief Get Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); +} + + + +/** + * @brief Enable ART Accelerator + * @rmtoll FLASH_ACR ARTEN LL_FLASH_EnableART + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableART(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN); +} + +/** + * @brief Disable ART Accelerator + * @rmtoll FLASH_ACR ARTEN LL_FLASH_DisableART + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableART(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN); +} + +/** + * @brief Enable ART Reset + * @rmtoll FLASH_ACR ARTRST LL_FLASH_EnableARTReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableARTReset(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ARTRST); +} + +/** + * @brief Disable ART Reset + * @rmtoll FLASH_ACR ARTRST LL_FLASH_DisableARTReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableARTReset(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTRST); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_SYSTEM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.c new file mode 100644 index 00000000000..774effedf59 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.c @@ -0,0 +1,1396 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_tim.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief TIM LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_tim.h" +#include "stm32f7xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7) + +/** @addtogroup TIM_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup TIM_LL_Private_Macros + * @{ + */ +#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + +#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + +#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ + || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) + +#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ + || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + +#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ + || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + +#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ + || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) + +#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + +#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + +#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) + +#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) + +#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + +#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + +#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + +#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + +#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + +#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) + +#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + +#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup TIM_LL_Private_Functions TIM Private Functions + * @{ + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_LL_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_LL_EF_Init + * @{ + */ + +/** + * @brief Set TIMx registers to their reset values. + * @param TIMx Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: invalid TIMx instance + */ +ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) +{ + ErrorStatus result = SUCCESS; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + + if (TIMx == TIM1) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); + } + else if (TIMx == TIM2) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); + } +#if defined(TIM3) + else if (TIMx == TIM3) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); + } +#endif +#if defined(TIM4) + else if (TIMx == TIM4) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); + } +#endif +#if defined(TIM5) + else if (TIMx == TIM5) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); + } +#endif +#if defined(TIM6) + else if (TIMx == TIM6) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); + } +#endif +#if defined (TIM7) + else if (TIMx == TIM7) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); + } +#endif +#if defined(TIM8) + else if (TIMx == TIM8) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); + } +#endif +#if defined(TIM9) + else if (TIMx == TIM9) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9); + } +#endif +#if defined(TIM10) + else if (TIMx == TIM10) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10); + } +#endif +#if defined(TIM11) + else if (TIMx == TIM11) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11); + } +#endif +#if defined(TIM12) + else if (TIMx == TIM12) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); + } +#endif +#if defined(TIM13) + else if (TIMx == TIM13) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); + } +#endif +#if defined(TIM14) + else if (TIMx == TIM14) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); + } +#endif + else + { + result = ERROR; + } + + return result; +} + +/** + * @brief Set the fields of the time base unit configuration data structure + * to their default values. + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) + * @retval None + */ +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->Prescaler = (uint16_t)0x0000U; + TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct->Autoreload = 0xFFFFFFFFU; + TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U; +} + +/** + * @brief Configure the TIMx time base unit. + * @param TIMx Timer Instance + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) +{ + uint32_t tmpcr1 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); + assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); + + tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); + + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); + } + + /* Write to TIMx CR1 */ + LL_TIM_WriteReg(TIMx, CR1, tmpcr1); + + /* Set the Autoreload value */ + LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); + + /* Set the Prescaler value */ + LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); + } + + /* Generate an update event to reload the Prescaler + and the repetition counter value (if applicable) immediately */ + LL_TIM_GenerateEvent_UPDATE(TIMx); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx output channel configuration data + * structure to their default values. + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) + * @retval None + */ +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + /* Set the default configuration */ + TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; + TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->CompareValue = 0x00000000U; + TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; + TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; +} + +/** + * @brief Configure the TIMx output channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = OC1Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = OC2Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = OC3Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = OC4Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH5: + result = OC5Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH6: + result = OC6Config(TIMx, TIM_OC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Set the fields of the TIMx input channel configuration data + * structure to their default values. + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) + * @retval None + */ +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the TIMx input channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = IC1Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = IC2Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = IC3Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = IC4Config(TIMx, TIM_IC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Fills each TIM_EncoderInitStruct field with its default value + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) + * @retval None + */ +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + /* Set the default configuration */ + TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; + TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the encoder interface of the timer instance. + * @param TIMx Timer Instance + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Configure TI1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + + /* Configure TI2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + + /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Set encoder mode */ + LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx Hall sensor interface configuration data + * structure to their default values. + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) + * @retval None + */ +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + /* Set the default configuration */ + TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_HallSensorInitStruct->CommutationDelay = 0U; +} + +/** + * @brief Configure the Hall sensor interface of the timer instance. + * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR + * to the TI1 input channel + * @note TIMx slave mode controller is configured in reset mode. + Selected internal trigger is TI1F_ED. + * @note Channel 1 is configured as input, IC1 is mapped on TRC. + * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed + * between 2 changes on the inputs. It gives information about motor speed. + * @note Channel 2 is configured in output PWM 2 mode. + * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. + * @note OC2REF is selected as trigger output on TRGO. + * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used + * when TIMx operates in Hall sensor interface mode. + * @param TIMx Timer Instance + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + uint32_t tmpcr2 = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpsmcr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx SMCR register value */ + tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); + + /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ + tmpcr2 |= TIM_CR2_TI1S; + + /* OC2REF signal is used as trigger output (TRGO) */ + tmpcr2 |= LL_TIM_TRGO_OC2REF; + + /* Configure the slave mode controller */ + tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); + tmpsmcr |= LL_TIM_TS_TI1F_ED; + tmpsmcr |= LL_TIM_SLAVEMODE_RESET; + + /* Configure input channel 1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); + + /* Configure input channel 2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); + tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); + + /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx SMCR */ + LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + /* Write to TIMx CCR2 */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); + + return SUCCESS; +} + +/** + * @brief Set the fields of the Break and Dead Time configuration data structure + * to their default values. + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @retval None + */ +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; + TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U; + TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; + TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; + TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; + TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; + TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; +} + +/** + * @brief Configure the Break and Dead Time feature of the timer instance. + * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR + * and DTG[7:0] can be write-locked depending on the LOCK configuration, it + * can be necessary to configure all of them during the first write access to + * the TIMx_BDTR register. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @param TIMx Timer Instance + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Break and Dead Time is initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); + if (IS_TIM_ADVANCED_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + } + + if (IS_TIM_BKIN2_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); + assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); + assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); + + /* Set the BREAK2 input related BDTR bit-fields */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); + } + + /* Set TIMx_BDTR */ + LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); + + return SUCCESS; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_LL_Private_Functions TIM Private Functions + * @brief Private functions + * @{ + */ +/** + * @brief Configure the TIMx output channel 1. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); + + /* Set the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 2. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 3. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 4. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 5. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr3 = 0U; + uint32_t tmpccer = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 5: Reset the CC5E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); + + } + + /* Write to TIMx CCMR3 */ + LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 6. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr3 = 0U; + uint32_t tmpccer = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 5: Reset the CC6E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); + } + + /* Write to TIMx CCMR3 */ + LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 1. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC1E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC1P | TIM_CCER_CC1NP), + (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 2. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC2E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC2P | TIM_CCER_CC2NP), + ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 3. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC3E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC3P | TIM_CCER_CC3NP), + ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 4. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC2E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC4P | TIM_CCER_CC4NP), + ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); + + return SUCCESS; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.h new file mode 100644 index 00000000000..7338ed55762 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.h @@ -0,0 +1,4663 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_tim.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_TIM_H +#define __STM32F7xx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U, /* 6: TIMx_CH4 */ + 0x3CU, /* 7: TIMx_CH5 */ + 0x3CU /* 8: TIMx_CH6 */ +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U, /* 6: OC4M, OC4FE, OC4PE */ + 0U, /* 7: OC5M, OC5FE, OC5PE */ + 8U /* 8: OC6M, OC6FE, OC6PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U, /* 6: CC4S, IC4PSC, IC4F */ + 0U, /* 7: - NA */ + 0U /* 8: - NA */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U, /* 6: CC4P */ + 16U, /* 7: CC5P */ + 20U /* 8: CC6P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U, /* 6: OIS4 */ + 8U, /* 7: OIS5 */ + 10U /* 8: OIS6 */ +}; +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + +#if defined(TIM_BREAK_INPUT_SUPPORT) +/* Defines used for the bit position in the register and perform offsets */ +#define TIM_POSITION_BRK_SOURCE POSITION_VAL(Source) + +/* Generic bit definitions for TIMx_AF1 register */ +#define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKINE input enable */ +#if defined(DFSDM1_Channel0) +#define TIMx_AF1_BKDFBKE TIM1_AF1_BKDFBKE /*!< BRK DFSDM1_BREAK[0] enable */ +#endif /* DFSDM1_Channel0 */ +#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ +/* Generic bit definitions for TIMx_AF2 register */ +#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK B2KINE input enable */ +#if defined(DFSDM1_Channel0) +#define TIMx_AF2_BK2DFBKE TIM1_AF2_BK2DFBKE /*!< BRK DFSDM_BREAK[0] enable */ +#endif /* DFSDM1_Channel0 */ +#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK BK2IN input polarity */ +#endif /* TIM_BREAK_INPUT_SUPPORT */ + +/* Remap mask definitions */ +#define TIMx_OR_RMP_SHIFT 16U +#define TIMx_OR_RMP_MASK 0x0000FFFFU +#define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) +#define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) +#define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7FU) +#define DT_DELAY_2 ((uint8_t)0x3FU) +#define DT_DELAY_3 ((uint8_t)0x1FU) +#define DT_DELAY_4 ((uint8_t)0x1FU) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00U) +#define DT_RANGE_2 ((uint8_t)0x80U) +#define DT_RANGE_3 ((uint8_t)0xC0U) +#define DT_RANGE_4 ((uint8_t)0xE0U) + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ +(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ + + uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ +#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + * @{ + */ +#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ +#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros + * @{ + */ +/** + * @brief HELPER macro retrieving the UIFCPY flag from the counter value. + * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); + * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied + * to TIMx_CNT register bit 31) + * @param __CNT__ Counter value + * @retval UIF status bit + */ +#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ + (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ +((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note For advanced timer instances RepetitionCounter can be up to 65535. + * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel\n + * CCER CC5E LL_TIM_CC_EnableChannel\n + * CCER CC6E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel\n + * CCER CC5E LL_TIM_CC_DisableChannel\n + * CCER CC6E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel\n + * CCER CC5E LL_TIM_CC_IsEnabledChannel\n + * CCER CC6E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + return (READ_BIT(TIMx->CCER, Channels) == (Channels)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CCER CC5P LL_TIM_OC_ConfigOutput\n + * CCER CC6P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput\n + * CR2 OIS5 LL_TIM_OC_ConfigOutput\n + * CR2 OIS6 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode\n + * CCMR3 OC5M LL_TIM_OC_SetMode\n + * CCMR3 OC6M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode\n + * CCMR3 OC5M LL_TIM_OC_GetMode\n + * CCMR3 OC6M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity\n + * CCER CC5P LL_TIM_OC_SetPolarity\n + * CCER CC6P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity\n + * CCER CC5P LL_TIM_OC_GetPolarity\n + * CCER CC6P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState\n + * CR2 OIS5 LL_TIM_OC_SetIdleState\n + * CR2 OIS6 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState\n + * CR2 OIS5 LL_TIM_OC_GetIdleState\n + * CR2 OIS6 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast\n + * CCMR3 OC5FE LL_TIM_OC_EnableFast\n + * CCMR3 OC6FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast\n + * CCMR3 OC5FE LL_TIM_OC_DisableFast\n + * CCMR3 OC6FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return (READ_BIT(*pReg, bitfield) == bitfield); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC6PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC6PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return (READ_BIT(*pReg, bitfield) == bitfield); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear\n + * CCMR3 OC5CE LL_TIM_OC_EnableClear\n + * CCMR3 OC6CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear\n + * CCMR3 OC5CE LL_TIM_OC_DisableClear\n + * CCMR3 OC6CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return (READ_BIT(*pReg, bitfield) == bitfield); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals). + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Set compare value for output channel 5 (TIMx_CCR5). + * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR5, CompareValue); +} + +/** + * @brief Set compare value for output channel 6 (TIMx_CCR6). + * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR6, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @brief Get compare value (TIMx_CCR5) set for output channel 5. + * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR5)); +} + +/** + * @brief Get compare value (TIMx_CCR6) set for output channel 6. + * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR6)); +} + +/** + * @brief Select on which reference signal the OC5REF is combined to. + * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the combined 3-phase PWM mode. + * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels + * @param TIMx Timer instance + * @param GroupCH5 This parameter can be one of the following values: + * @arg @ref LL_TIM_GROUPCH5_NONE + * @arg @ref LL_TIM_GROUPCH5_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_OC3REFC + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) +{ + MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * CCER CC4NP LL_TIM_IC_Config + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * CCER CC4NP LL_TIM_IC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * CCER CC4NP LL_TIM_IC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); +} + +/** + * @brief Get captured value for input channel 1. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . + * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can be used for ADC synchronization. + * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 + * @param TIMx Timer Instance + * @param ADCSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO2_RESET + * @arg @ref LL_TIM_TRGO2_ENABLE + * @arg @ref LL_TIM_TRGO2_UPDATE + * @arg @ref LL_TIM_TRGO2_CC1F + * @arg @ref LL_TIM_TRGO2_OC1 + * @arg @ref LL_TIM_TRGO2_OC2 + * @arg @ref LL_TIM_TRGO2_OC3 + * @arg @ref LL_TIM_TRGO2_OC4 + * @arg @ref LL_TIM_TRGO2_OC5 + * @arg @ref LL_TIM_TRGO2_OC6 + * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Configure the break input. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n + * BDTR BKF LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param BreakFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); +} + +/** + * @brief Enable the break 2 function. + * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Disable the break 2 function. + * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Configure the break 2 input. + * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n + * BDTR BK2F LL_TIM_ConfigBRK2 + * @param TIMx Timer instance + * @param Break2Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param Break2Filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)); +} + +#if defined(TIM_BREAK_INPUT_SUPPORT) +/** + * @brief Enable the signals connected to the designated timer break input. + * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n + * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n + * AF2 BK2INE LL_TIM_EnableBreakInputSource\n + * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + SET_BIT(*pReg , Source); +} + +/** + * @brief Disable the signals connected to the designated timer break input. + * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n + * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n + * AF2 BK2INE LL_TIM_DisableBreakInputSource\n + * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + CLEAR_BIT(*pReg, Source); +} + +/** + * @brief Set the polarity of the break signal for the timer break input. + * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKDFBKE LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2INE LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2DFBKE LL_TIM_SetBreakInputSourcePolarity + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_POLARITY_LOW + * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, + uint32_t Polarity) +{ + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + MODIFY_REG(*pReg, (TIMx_AF1_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE))); +} +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_OR + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) +{ + MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping + * @{ + */ +/** + * @brief Remap TIM inputs (input channel, internal/external triggers). + * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * a some timer inputs can be remapped. + * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n + * TIM5_OR TI4_RMP LL_TIM_SetRemap\n + * TIM11_OR TI1_RMP LL_TIM_SetRemap + * @param TIMx Timer instance + * @param Remap Remap param depends on the TIMx. Description available only + * in CHM version of the User Manual (not in .pdf). + * Otherwise see Reference Manual description of OR registers. + * + * Below description summarizes "Timer Instance" and "Remap" param combinations: + * + * TIM2: one of the following values + * + * ITR1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO + * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP + * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF + * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF + * + * TIM5: one of the following values + * + * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO + * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI + * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE + * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC + * + * TIM11: one of the following values + * + * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX + * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE + * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1 + * + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +{ + MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); +} + +/** + * @} + */ + + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); +} + +/** + * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). + * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); +} + +/** + * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). + * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)); +} + +/** + * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). + * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); +} + +/** + * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). + * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)); +} + +/** + * @brief Clear the break 2 interrupt flag (B2IF). + * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); +} + +/** + * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). + * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); +} + +/** + * @brief Clear the system break interrupt flag (SBIF). + * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); +} + +/** + * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). + * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA-Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @brief Generate break 2 event. + * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_B2G); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_TIM_H */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usart.c new file mode 100644 index 00000000000..0e16022a239 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usart.c @@ -0,0 +1,463 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_usart.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief USART LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_usart.h" +#include "stm32f7xx_ll_rcc.h" +#include "stm32f7xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) + +/** @addtogroup USART_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Constants + * @{ + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Macros + * @{ + */ + +/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available + * divided by the smallest oversampling used on the USART (i.e. 8) */ +#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U) + +/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ +#define IS_LL_USART_BRR(__VALUE__) (((__VALUE__) >= 16U) \ + && ((__VALUE__) <= 0x0000FFFFU)) + +#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + +#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) + +#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + +#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + +#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + +#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + +#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + +#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + +#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) + +#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_LL_Exported_Functions + * @{ + */ + +/** @addtogroup USART_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize USART registers (Registers restored to their default values). + * @param USARTx USART Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are de-initialized + * - ERROR: USART registers are not de-initialized + */ +ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + + if (USARTx == USART1) + { + /* Force reset of USART clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); + + /* Release reset of USART clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); + } + else if (USARTx == USART2) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); + } + else if (USARTx == USART3) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); + } + else if (USARTx == USART6) + { + /* Force reset of USART clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6); + + /* Release reset of USART clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6); + } + else if (USARTx == UART4) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4); + } + else if (USARTx == UART5) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5); + } + else if (USARTx == UART7) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7); + } + else if (USARTx == UART8) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize USART registers according to the specified + * parameters in USART_InitStruct. + * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), + * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). + * @param USARTx USART Instance + * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure + * that contains the configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are initialized according to USART_InitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); + assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); + assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); + assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); + assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); + assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); + assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /*---------------------------- USART CR1 Configuration --------------------- + * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: + * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value + * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value + * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value + * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value. + */ + MODIFY_REG(USARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + (USART_InitStruct->DataWidth | USART_InitStruct->Parity | + USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); + + /*---------------------------- USART CR2 Configuration --------------------- + * Configure USARTx CR2 (Stop bits) with parameters: + * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. + * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). + */ + LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); + + /*---------------------------- USART CR3 Configuration --------------------- + * Configure USARTx CR3 (Hardware Flow Control) with parameters: + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. + */ + LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); + + /*---------------------------- USART BRR Configuration --------------------- + * Retrieve Clock frequency used for USART Peripheral + */ + if (USARTx == USART1) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE); + } + else if (USARTx == USART2) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE); + } + else if (USARTx == USART3) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE); + } + else if (USARTx == USART6) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART6_CLKSOURCE); + } + else if (USARTx == UART4) + { + periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE); + } + else if (USARTx == UART5) + { + periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE); + } + else if (USARTx == UART7) + { + periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART7_CLKSOURCE); + } + else if (USARTx == UART8) + { + periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART8_CLKSOURCE); + } + else + { + /* Nothing to do, as error code is already assigned to ERROR value */ + } + + /* Configure the USART Baud Rate : + - valid baud rate value (different from 0) is required + - Peripheral clock as returned by RCC service, should be valid (different from 0). + */ + if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + && (USART_InitStruct->BaudRate != 0U)) + { + status = SUCCESS; + LL_USART_SetBaudRate(USARTx, + periphclk, + USART_InitStruct->OverSampling, + USART_InitStruct->BaudRate); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR(USARTx->BRR)); + } + } + /* Endif (=> USART not in Disabled state => return ERROR) */ + + return (status); +} + +/** + * @brief Set each @ref LL_USART_InitTypeDef field to default value. + * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) +{ + /* Set USART_InitStruct fields to default values */ + USART_InitStruct->BaudRate = 9600U; + USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct->StopBits = LL_USART_STOPBITS_1; + USART_InitStruct->Parity = LL_USART_PARITY_NONE ; + USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; + USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; +} + +/** + * @brief Initialize USART Clock related settings according to the + * specified parameters in the USART_ClockInitStruct. + * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), + * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param USARTx USART Instance + * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * that contains the Clock configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check USART Instance and Clock signal output parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /*---------------------------- USART CR2 Configuration -----------------------*/ + /* If Clock signal has to be output */ + if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) + { + /* Deactivate Clock signal delivery : + * - Disable Clock Output: USART_CR2_CLKEN cleared + */ + LL_USART_DisableSCLKOutput(USARTx); + } + else + { + /* Ensure USART instance is USART capable */ + assert_param(IS_USART_INSTANCE(USARTx)); + + /* Check clock related parameters */ + assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Clock signal related bits) with parameters: + * - Enable Clock Output: USART_CR2_CLKEN set + * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value + * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value + * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. + */ + MODIFY_REG(USARTx->CR2, + USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | + USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); + } + } + /* Else (USART not in Disabled state => return ERROR */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. + * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + /* Set LL_USART_ClockInitStruct fields with default values */ + USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; + USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usart.h new file mode 100644 index 00000000000..94612c1763e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usart.h @@ -0,0 +1,3560 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_usart.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_USART_H +#define __STM32F7xx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_USART_WriteReg function + * @{ + */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ +#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ +#if defined(USART_TCBGT_SUPPORT) +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */ +#endif +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ +#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ +#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ +#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ +#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ +#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ +#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#if defined(USART_TCBGT_SUPPORT) +#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ +#endif +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ +#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#if defined(USART_TCBGT_SUPPORT) +#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ +#endif +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + * @{ + */ +#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ +#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ +#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_ISR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); +} + + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + * CR1 M1 LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + * CR1 M1 LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_USART_EnableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_USART_DisableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M0 LL_USART_ConfigCharacter\n + * CR1 M1 LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap + * @param USARTx USART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic + * @param USARTx USART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder + * @param USARTx USART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Enable Auto Baud-Rate Detection + * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Disable Auto Baud-Rate Detection + * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled + * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)); +} + +/** + * @brief Set Auto Baud-Rate mode bits + * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode + * @param USARTx USART Instance + * @param AutoBaudRateMode This parameter can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + * @retval None + */ +__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +} + +/** + * @brief Return Auto Baud-Rate mode + * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + */ +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +} + +/** + * @brief Enable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Disable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Indicate if Receiver Timeout feature is enabled + * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n + * CR2 ADDM7 LL_USART_ConfigNodeAddress + * @param USARTx USART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS); +} + + +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, + uint32_t BaudRate) +{ + register uint32_t usartdiv = 0x0U; + register uint32_t brrtemp = 0x0U; + + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + USARTx->BRR = brrtemp; + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +{ + register uint32_t usartdiv = 0x0U; + register uint32_t brrresult = 0x0U; + + usartdiv = USARTx->BRR; + + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + if ((usartdiv & 0xFFF7U) != 0U) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + brrresult = (PeriphClk * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = PeriphClk / usartdiv; + } + } + return (brrresult); +} + +/** + * @brief Set Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_SetRxTimeout + * @param USARTx USART Instance + * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); +} + +/** + * @brief Get Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_GetRxTimeout + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); +} + +/** + * @brief Set Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_SetBlockLength + * @param USARTx USART Instance + * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); +} + +/** + * @brief Get Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_GetBlockLength + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); +} + +/** + * @brief Enable Smartcard mode + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); +} + +/** + * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic retransmission retries, before + * generating a transmission error (FE bit set). + * In reception mode, it specifies the number or erroneous reception trials, before generating a + * reception error (RXNE and PE bits set) + * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_EnableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_DisableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)); +} + +/** + * @brief Select Driver Enable Polarity + * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity + * @param USARTx USART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll ISR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll ISR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll ISR NF LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)); +} + +/** + * @brief Check if the USART Read Data Register Not Empty Flag is set or not + * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)); +} + +/** + * @brief Check if the USART Transmit Data Register Empty Flag is set or not + * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)); +} + +/** + * @brief Check if the USART CTS interrupt Flag is set or not + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)); +} + +/** + * @brief Check if the USART Receiver Time Out Flag is set or not + * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)); +} + +/** + * @brief Check if the USART End Of Block Flag is set or not + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)); +} + +/** + * @brief Check if the USART Auto-Baud Rate Error Flag is set or not + * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)); +} + +/** + * @brief Check if the USART Auto-Baud Rate Flag is set or not + * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)); +} + +/** + * @brief Check if the USART Busy Flag is set or not + * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)); +} + +/** + * @brief Check if the USART Character Match Flag is set or not + * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)); +} + + +/** + * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)); +} + + +#if defined(USART_TCBGT_SUPPORT) +/* Function available only on devices supporting Transmit Complete before Guard Time feature */ +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not + * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)); +} +#endif + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise detected Flag + * @rmtoll ICR NCF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_NCF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCCF); +} + +#if defined(USART_TCBGT_SUPPORT) +/* Function available only on devices supporting Transmit Complete before Guard Time feature */ +/** + * @brief Clear Smartcard Transmission Complete Before Guard Time Flag + * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); +} +#endif + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Receiver Time Out Flag + * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); +} + +/** + * @brief Clear End Of Block Flag + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_USART_ClearFlag_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CMCF); +} + + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Enable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Enable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_EnableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Enable End Of Block Interrupt + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + + +#if defined(USART_TCBGT_SUPPORT) +/* Function available only on devices supporting Transmit Complete before Guard Time feature */ +/** + * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} +#endif + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Disable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Disable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_DisableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Disable End Of Block Interrupt + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + + +#if defined(USART_TCBGT_SUPPORT) +/* Function available only on devices supporting Transmit Complete before Guard Time feature */ +/** + * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} +#endif + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); +} + +/** + * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); +} + +/** + * @brief Check if the USART TX Empty Interrupt is enabled or disabled. + * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); +} + +/** + * @brief Check if the USART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)); +} + +/** + * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. + * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)); +} + +/** + * @brief Check if the USART End Of Block Interrupt is enabled or disabled. + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); +} + + +#if defined(USART_TCBGT_SUPPORT) +/* Function available only on devices supporting Transmit Complete before Guard Time feature */ +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)); +} +#endif + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr + * @param USARTx USART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) +{ + register uint32_t data_reg_addr = 0U; + + if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(USARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(USARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->TDR = Value & 0x1FFU; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request an Automatic Baud Rate measurement on next received data frame + * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, USART_RQR_ABRRQ); +} + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, USART_RQR_SBKRQ); +} + +/** + * @brief Put USART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data flush + * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data flush + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, USART_RQR_TXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_USART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.c index e1ca1385465..5bf9e8f0fb6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.c * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -72,6 +72,10 @@ /* Private functions ---------------------------------------------------------*/ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); +#ifdef USB_HS_PHYC +static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx); +#endif + /* Exported functions --------------------------------------------------------*/ /** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions * @{ @@ -116,6 +120,34 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Reset after a PHY select */ USB_CoreReset(USBx); } +#ifdef USB_HS_PHYC + + else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Init The UTMI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + + /* Select UTMI Interace */ + USBx->GUSBCFG &= ~ USB_OTG_GUSBCFG_ULPI_UTMI_SEL; + USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN; + + /* Enables control of a High Speed USB PHY */ + USB_HS_PHYCInit(USBx); + + if(cfg.use_external_vbus == 1) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + } + /* Reset after a PHY select */ + USB_CoreReset(USBx); + + } +#endif else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ @@ -130,7 +162,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c if(cfg.dma_enable == ENABLE) { - USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2); + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; } @@ -233,6 +265,21 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL); } } + + else if(cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + { + if(cfg.speed == USB_OTG_SPEED_HIGH) + { + /* Set High speed phy */ + USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH); + } + else + { + /* set High speed phy in Full speed mode */ + USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL); + } + } + else { /* Set Full speed phy */ @@ -1108,7 +1155,69 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) return HAL_OK; } +#ifdef USB_HS_PHYC +/** + * @brief Enables control of a High Speed USB PHY�s + * Init the low level hardware : GPIO, CLOCK, NVIC... + * @param USBx : Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t count = 0; + + /* Enable LDO */ + USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; + + /* wait for LDO Ready */ + while((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == RESET) + { + if (++count > 200000) + { + return HAL_TIMEOUT; + } + } + + /* Controls PHY frequency operation selection */ + if (HSE_VALUE == 12000000) /* HSE = 12MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x0 << 1); + } + else if (HSE_VALUE == 12500000) /* HSE = 12.5MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x2 << 1); + } + else if (HSE_VALUE == 16000000) /* HSE = 16MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x3 << 1); + } + + else if (HSE_VALUE == 24000000) /* HSE = 24MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x4 << 1); + } + else if (HSE_VALUE == 25000000) /* HSE = 25MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x5 << 1); + } + else if (HSE_VALUE == 32000000) /* HSE = 32MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x7 << 1); + } + + /* Control the tuning interface of the High Speed PHY */ + USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE; + + /* Enable PLL internal PHY */ + USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; + + /* 2ms Delay required to get internal phy clock stable */ + HAL_Delay(2); + + return HAL_OK; +} +#endif /* USB_HS_PHYC */ /** * @brief USB_HostInit : Initializes the USB OTG controller registers * for Host mode @@ -1225,16 +1334,17 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) { __IO uint32_t hprt0; - + hprt0 = USBx_HPRT0; - hprt0 |= USB_OTG_HPRT_PENA ; - - hprt0 &= ~(USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG |\ - USB_OTG_HPRT_POCCHNG ); - + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); - HAL_Delay (10); /* See Note #1 */ + HAL_Delay (100); /* See Note #1 */ USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay (10); + return HAL_OK; } @@ -1251,11 +1361,10 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) __IO uint32_t hprt0; hprt0 = USBx_HPRT0; - hprt0 |= USB_OTG_HPRT_PENA ; - - hprt0 &= ~(USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG |\ - USB_OTG_HPRT_POCCHNG ); - + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) { USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); @@ -1418,18 +1527,13 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, * 1 : DMA feature used * @retval HAL state */ -#if defined (__CC_ARM) /*!< ARM Compiler */ -#pragma O0 -#elif defined (__GNUC__) /*!< GNU Compiler */ -#pragma GCC optimize ("O0") -#endif /* __CC_ARM */ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) { + static __IO uint32_t tmpreg = 0; uint8_t is_oddframe = 0; uint16_t len_words = 0; uint16_t num_packets = 0; uint16_t max_hc_pkt_count = 256; - uint32_t tmpreg = 0; if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH)) { @@ -1553,7 +1657,8 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) uint32_t count = 0; /* Check for space in the request queue to issue the halt. */ - if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18))) + if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) || + (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK))) { USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.h index 7e24022f405..cabc9d7250b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.h * @author MCD Application Team - * @version V1.1.2 - * @date 23-September-2016 + * @version V1.2.0 + * @date 30-December-2016 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention @@ -125,7 +125,9 @@ typedef struct uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ - + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ @@ -256,6 +258,12 @@ typedef struct */ #define USB_OTG_ULPI_PHY 1U #define USB_OTG_EMBEDDED_PHY 2U +#define USB_OTG_HS_EMBEDDED_PHY 3U + +#if !defined (USB_HS_PHYC_TUNE_VALUE) + #define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */ +#endif /* USB_HS_PHYC_TUNE_VALUE */ + /** * @} */ @@ -382,6 +390,9 @@ typedef struct #define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE)) #define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE)) +#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE)) + + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_utils.c new file mode 100644 index 00000000000..511a8f45928 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_utils.c @@ -0,0 +1,752 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_utils.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief UTILS LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_utils.h" +#include "stm32f7xx_ll_rcc.h" +#include "stm32f7xx_ll_system.h" +#include "stm32f7xx_ll_pwr.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +/** @addtogroup UTILS_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Constants + * @{ + */ +#define UTILS_MAX_FREQUENCY_SCALE1 216000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 180000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE3 144000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ + +/* Defines used for PLL range */ +#define UTILS_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */ +#define UTILS_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */ +#define UTILS_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */ + +/* Defines used for HSE range */ +#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */ + +/* Defines used for FLASH latency according to HCLK Frequency */ +#define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ +#define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ +#define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ +#define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ +#define UTILS_SCALE1_LATENCY6_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 1 with over-drive mode */ +#define UTILS_SCALE1_LATENCY7_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 7 in power scale 1 with over-drive mode */ +#define UTILS_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ +#define UTILS_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ +#define UTILS_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ +#define UTILS_SCALE2_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */ +#define UTILS_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */ +#define UTILS_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ +#define UTILS_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ +#define UTILS_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ +#define UTILS_SCALE3_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Macros + * @{ + */ +#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + +#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + +#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_16)) + +#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_63)) + +#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((50 <= (__VALUE__)) && ((__VALUE__) <= 432)) + +#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \ + || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \ + || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \ + || ((__VALUE__) == LL_RCC_PLLP_DIV_8)) + +#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)) + +#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) + +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ + (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ + ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) + +#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + +#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Functions UTILS Private functions + * @{ + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency); +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +static ErrorStatus UTILS_PLL_IsBusy(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UTILS_LL_EF_DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_Init1msTick(uint32_t HCLKFrequency) +{ + /* Use frequency provided in argument */ + LL_InitTick(HCLKFrequency, 1000U); +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on SysTick counter flag + * @note When a RTOS is used, it is recommended to avoid using blocking delay + * and use rather osDelay service. + * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + * will configure Systick to 1ms + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + + /* Add a period to guaranty minimum wait */ + if(Delay < LL_MAX_DELAY) + { + Delay++; + } + + while (Delay) + { + if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + Delay--; + } + } +} + +/** + * @} + */ + +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 216000000 Hz. + @endverbatim + @internal + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + (++) +------------------------------------------------------------------------------------------------+ + (++) | Wait states | HCLK clock frequency (MHz) | + (++) | |-------------------------------------------------------------------------------| + (++) | (Latency) | voltage range | voltage range | voltage range | voltage range | + (++) | | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.7V | 1.8V - 2.1V | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |0WS(1CPU cycle) | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 22 | 0 < HCLK <= 20 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |1WS(2CPU cycle) | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 22 < HCLK <= 44 | 20 < HCLK <= 44 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |2WS(3CPU cycle) | 60 < HCLK <= 90 | 48 < HCLK <= 72 | 44 < HCLK <= 66 | 40 < HCLK <= 60 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |3WS(4CPU cycle) | 90 < HCLK <= 120 | 72 < HCLK <= 96 | 66 < HCLK <= 88 | 60 < HCLK <= 80 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |4WS(5CPU cycle) | 120 < HCLK <= 150 | 96 < HCLK <= 120 | 88 < HCLK <= 110 | 80 < HCLK <= 100 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |5WS(6CPU cycle) | 150 < HCLK <= 180 | 120 < HCLK <= 144 | 110 < HCLK <= 132 | 100 < HCLK <= 120 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |6WS(7CPU cycle) | 180 < HCLK <= 210 | 144 < HCLK <= 168 | 132 < HCLK <= 154 | 120 < HCLK <= 140 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |7WS(8CPU cycle) | 210 < HCLK <= 216 | 168 < HCLK <= 192 | 154 < HCLK <= 176 | 140 < HCLK <= 160 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |8WS(9CPU cycle) | -- | 192 < HCLK <= 216 | 176 < HCLK <= 198 | 160 < HCLK <= 180 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |9WS(10CPU cycle)| -- | -- | 198 < HCLK <= 216 | -- | + (++) +------------------------------------------------------------------------------------------------+ + + @endinternal + * @{ + */ + +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @retval None + */ +void LL_SetSystemCoreClock(uint32_t HCLKFrequency) +{ + /* HCLK clock frequency */ + SystemCoreClock = HCLKFrequency; +} + +/** + * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) + * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz (PLLVCO_input = HSI frequency / PLLM) + * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN) + * - PLLP: ensure that max frequency at 216000000 Hz is reach (PLLVCO_output / PLLP) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check if one of the PLL is enabled */ + if(UTILS_PLL_IsBusy() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + + /* Enable HSI if not enabled */ + if(LL_RCC_HSI_IsReady() != 1U) + { + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + { + /* Wait for HSI ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, + UTILS_PLLInitStruct->PLLP); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief This function configures system clock with HSE as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP) + * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM) + * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN) + * - PLLP: ensure that max frequency at 216000000 Hz is reached (PLLVCO_output / PLLP) + * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000 + * @param HSEBypass This parameter can be one of the following values: + * @arg @ref LL_UTILS_HSEBYPASS_ON + * @arg @ref LL_UTILS_HSEBYPASS_OFF + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + + /* Check if one of the PLL is enabled */ + if(UTILS_PLL_IsBusy() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + + /* Enable HSE if not enabled */ + if(LL_RCC_HSE_IsReady() != 1U) + { + /* Check if need to enable HSE bypass feature or not */ + if(HSEBypass == LL_UTILS_HSEBYPASS_ON) + { + LL_RCC_HSE_EnableBypass(); + } + else + { + LL_RCC_HSE_DisableBypass(); + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1U) + { + /* Wait for HSE ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, + UTILS_PLLInitStruct->PLLP); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V + * @param HCLK_Frequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) +{ + ErrorStatus status = SUCCESS; + + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + + /* Frequency cannot be equal to 0 */ + if(HCLK_Frequency == 0U) + { + status = ERROR; + } + else + { + if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + { + if(LL_PWR_IsEnabledOverDriveMode() != 0U) + { + if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ) + { + /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */ + latency = LL_FLASH_LATENCY_7; + } + else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */ + { + /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */ + latency = LL_FLASH_LATENCY_6; + } + } + if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0)) + { + /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0)) + { + /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0)) + { + /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0)) + { + /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0)) + { + /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) + { + if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ) + { + /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ) + { + /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) + { + /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) + { + /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + else /* Scale 3 */ + { + if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ) + { + /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) + { + /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) + { + /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) + { + /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(LL_FLASH_GetLatency() != latency) + { + status = ERROR; + } + } + return status; +} + +/** + * @brief Function to check that PLL can be modified + * @param PLL_InputFrequency PLL input frequency (in Hz) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @retval PLL output frequency (in Hz) + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +{ + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); + assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); + assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); + + /* Check different PLL parameters according to RM */ + /* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz. */ + pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos)); + assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq)); + + /* - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz.*/ + pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos)); + assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); + + /* - PLLP: ensure that max frequency at 216000000 Hz is reached */ + pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); + assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + + return pllfreq; +} + +/** + * @brief Function to check that PLL can be modified + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL modification can be done + * - ERROR: PLL is busy + */ +static ErrorStatus UTILS_PLL_IsBusy(void) +{ + ErrorStatus status = SUCCESS; + + /* Check if PLL is busy*/ + if(LL_RCC_PLL_IsReady() != 0U) + { + /* PLL configuration cannot be modified */ + status = ERROR; + } + + /* Check if PLLSAI is busy*/ + if(LL_RCC_PLLSAI_IsReady() != 0U) + { + /* PLLSAI1 configuration cannot be modified */ + status = ERROR; + } + /* Check if PLLI2S is busy*/ + if(LL_RCC_PLLI2S_IsReady() != 0U) + { + /* PLLI2S configuration cannot be modified */ + status = ERROR; + } + return status; +} + +/** + * @brief Function to enable PLL and switch system clock to PLL + * @param SYSCLK_Frequency SYSCLK frequency + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t hclk_frequency = 0U; + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); + + /* Calculate HCLK frequency */ + hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); + + /* Increasing the number of wait states because of higher CPU frequency */ + if(SystemCoreClock < hclk_frequency) + { + /* Set FLASH latency to highest latency */ + status = UTILS_SetFlashLatency(hclk_frequency); + } + + /* Update system clock configuration */ + if(status == SUCCESS) + { + /* Enable PLL */ + LL_RCC_PLL_Enable(); + while (LL_RCC_PLL_IsReady() != 1U) + { + /* Wait for PLL ready */ + } + + /* Sysclk activation on the main PLL */ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + /* Wait for system clock switch to PLL */ + } + + /* Set APB1 & APB2 prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(SystemCoreClock > hclk_frequency) + { + /* Set FLASH latency to lowest latency */ + status = UTILS_SetFlashLatency(hclk_frequency); + } + + /* Update SystemCoreClock variable */ + if(status == SUCCESS) + { + LL_SetSystemCoreClock(hclk_frequency); + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_utils.h new file mode 100644 index 00000000000..351d81ab1a9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_utils.h @@ -0,0 +1,323 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_utils.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_UTILS_H +#define __STM32F7xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLP; /*!< Division for the main system clock. + This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000100U /*!< LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 0x00000200U /*!< LQFP144 or WLCSP143 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 0x00000300U /*!< WLCSP180, LQFP176 or UFBGA176 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 0x00000400U /*!< LQFP176, LQFP208 or TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA216_LQFP176_LQFP208 0x00000500U /*!< LQFP176, LQFP208 or TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_TFBGA216_LQFP208 0x00000600U /*!< LQFP176, LQFP208 or TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP208_LQFP176_TFBGA216 0x00000700U /*!< LQFP176, LQFP208 or TFBGA216 package type */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_UTILS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_wwdg.h new file mode 100644 index 00000000000..dcf9e239f6a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_wwdg.h @@ -0,0 +1,342 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_wwdg.h + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief Header file of WWDG LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_WWDG_H +#define __STM32F7xx_LL_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (WWDG) + +/** @defgroup WWDG_LL WWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants + * @{ + */ + + +/** @defgroup WWDG_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions + * @{ + */ +#define LL_WWDG_CFR_EWI WWDG_CFR_EWI +/** + * @} + */ + +/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER +* @{ +*/ +#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros + * @{ + */ +/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in WWDG register + * @param __INSTANCE__ WWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in WWDG register + * @param __INSTANCE__ WWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions + * @{ + */ + +/** @defgroup WWDG_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable Window Watchdog. The watchdog is always disabled after a reset. + * @note It is enabled by setting the WDGA bit in the WWDG_CR register, + * then it cannot be disabled again except by a reset. + * This bit is set by software and only cleared by hardware after a reset. + * When WDGA = 1, the watchdog can generate a reset. + * @rmtoll CR WDGA LL_WWDG_Enable + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) +{ + SET_BIT(WWDGx->CR, WWDG_CR_WDGA); +} + +/** + * @brief Checks if Window Watchdog is enabled + * @rmtoll CR WDGA LL_WWDG_IsEnabled + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)); +} + +/** + * @brief Set the Watchdog counter value to provided value (7-bits T[6:0]) + * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset + * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles + * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) + * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled) + * @rmtoll CR T LL_WWDG_SetCounter + * @param WWDGx WWDG Instance + * @param Counter 0..0x7F (7 bit counter value) + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) +{ + MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter); +} + +/** + * @brief Return current Watchdog Counter Value (7 bits counter value) + * @rmtoll CR T LL_WWDG_GetCounter + * @param WWDGx WWDG Instance + * @retval 7 bit Watchdog Counter value + */ +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +{ + return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T)); +} + +/** + * @brief Set the time base of the prescaler (WDGTB). + * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter + * is decremented every (4096 x 2expWDGTB) PCLK cycles + * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler + * @param WWDGx WWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler) +{ + MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler); +} + +/** + * @brief Return current Watchdog Prescaler Value + * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler + * @param WWDGx WWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + */ +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +{ + return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); +} + +/** + * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]). + * @note This window value defines when write in the WWDG_CR register + * to program Watchdog counter is allowed. + * Watchdog counter value update must occur only when the counter value + * is lower than the Watchdog window register value. + * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value + * (in the control register) is refreshed before the downcounter has reached + * the watchdog window register value. + * Physically is possible to set the Window lower then 0x40 but it is not recommended. + * To generate an immediate reset, it is possible to set the Counter lower than 0x40. + * @rmtoll CFR W LL_WWDG_SetWindow + * @param WWDGx WWDG Instance + * @param Window 0x00..0x7F (7 bit Window value) + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) +{ + MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window); +} + +/** + * @brief Return current Watchdog Window Value (7 bits value) + * @rmtoll CFR W LL_WWDG_GetWindow + * @param WWDGx WWDG Instance + * @retval 7 bit Watchdog Window value + */ +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +{ + return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W)); +} + +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ +/** + * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not. + * @note This bit is set by hardware when the counter has reached the value 0x40. + * It must be cleared by software by writing 0. + * A write of 1 has no effect. This bit is also set if the interrupt is not enabled. + * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)); +} + +/** + * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF) + * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx) +{ + WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF); +} + +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable the Early Wakeup Interrupt. + * @note When set, an interrupt occurs whenever the counter reaches value 0x40. + * This interrupt is only cleared by hardware after a reset + * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) +{ + SET_BIT(WWDGx->CFR, WWDG_CFR_EWI); +} + +/** + * @brief Check if Early Wakeup Interrupt is enabled + * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WWDG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_WWDG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/hal_tick_32b.c b/targets/TARGET_STM/hal_tick_32b.c index e8370f3c10b..0f9c3dccad2 100644 --- a/targets/TARGET_STM/hal_tick_32b.c +++ b/targets/TARGET_STM/hal_tick_32b.c @@ -101,7 +101,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) #if !TARGET_STM32L1 TimMasterHandle.Init.RepetitionCounter = 0; #endif -#ifdef TARGET_STM32F0 +#if TARGET_STM32F0||TARGET_STM32F7 TimMasterHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; #endif HAL_TIM_OC_Init(&TimMasterHandle); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f1024.h index 304419d8c07..274893c944b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f1024.h @@ -2,10 +2,10 @@ * @file efm32gg230f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG230F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -115,12 +115,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG230F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f512.h index 12971ee07c9..36a44ca1a42 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f512.h @@ -2,10 +2,10 @@ * @file efm32gg230f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG230F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -115,12 +115,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG230F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f1024.h index 03fd2b9f934..49c86eb24ca 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f1024.h @@ -2,10 +2,10 @@ * @file efm32gg232f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG232F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -115,12 +115,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG232F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f512.h index 90332d74c91..27143a3a8c7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f512.h @@ -2,10 +2,10 @@ * @file efm32gg232f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG232F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -115,12 +115,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG232F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f1024.h index 1d8480ec792..d6b0d4b0411 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f1024.h @@ -2,10 +2,10 @@ * @file efm32gg280f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG280F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG280F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f512.h index 8068a401e30..53a510aadc7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f512.h @@ -2,10 +2,10 @@ * @file efm32gg280f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG280F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG280F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f1024.h index b03f61c61a7..41c170adfc6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f1024.h @@ -2,10 +2,10 @@ * @file efm32gg290f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG290F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG290F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f512.h index 6a7c7af70a4..f5c4398494b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f512.h @@ -2,10 +2,10 @@ * @file efm32gg290f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG290F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG290F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f1024.h index 09ef2a73bcb..d576188a8f7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f1024.h @@ -2,10 +2,10 @@ * @file efm32gg295f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG295F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG295F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f512.h index 12cb10ea5b6..40fa214b4c8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f512.h @@ -2,10 +2,10 @@ * @file efm32gg295f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG295F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG295F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f1024.h index 88906ccf12f..2d1957d9ca5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f1024.h @@ -2,10 +2,10 @@ * @file efm32gg330f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG330F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG330F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f512.h index 2414e1c5a21..07cbaceccfe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f512.h @@ -2,10 +2,10 @@ * @file efm32gg330f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG330F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG330F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f1024.h index 8fae90e5864..1ac79e902bb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f1024.h @@ -2,10 +2,10 @@ * @file efm32gg332f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG332F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG332F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f512.h index f22a18f3724..7215bfe811c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f512.h @@ -2,10 +2,10 @@ * @file efm32gg332f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG332F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG332F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f1024.h index bc1b4699307..11d5b71247f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f1024.h @@ -2,10 +2,10 @@ * @file efm32gg380f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG380F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG380F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f512.h index d65dbd561a2..3b460728f9b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f512.h @@ -2,10 +2,10 @@ * @file efm32gg380f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG380F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG380F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f1024.h index cfb18256e7f..ec77d2da7de 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f1024.h @@ -2,10 +2,10 @@ * @file efm32gg390f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG390F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG390F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f512.h index d6ab45ac94d..4906cd57da5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f512.h @@ -2,10 +2,10 @@ * @file efm32gg390f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG390F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG390F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f1024.h index 4b4eef688c2..b28e68d25de 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f1024.h @@ -2,10 +2,10 @@ * @file efm32gg395f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG395F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG395F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f512.h index 52a73d3e193..4b37a151552 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f512.h @@ -2,10 +2,10 @@ * @file efm32gg395f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG395F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG395F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f1024.h index a7d84f435d0..0f9bfaf0031 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f1024.h @@ -2,10 +2,10 @@ * @file efm32gg840f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG840F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG840F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f512.h index 21a6d3f0f31..d4d1a368452 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f512.h @@ -2,10 +2,10 @@ * @file efm32gg840f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG840F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG840F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f1024.h index 5fa0fc5e556..757af1fad89 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f1024.h @@ -2,10 +2,10 @@ * @file efm32gg842f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG842F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG842F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f512.h index 3520c585a89..38da9c1bdda 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f512.h @@ -2,10 +2,10 @@ * @file efm32gg842f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG842F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG842F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f1024.h index e8435964bbd..923d58e5338 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f1024.h @@ -2,10 +2,10 @@ * @file efm32gg880f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG880F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG880F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f512.h index 3243d17dd37..f8d00106079 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f512.h @@ -2,10 +2,10 @@ * @file efm32gg880f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG880F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG880F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f1024.h index ae660728048..484076d93e9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f1024.h @@ -2,10 +2,10 @@ * @file efm32gg890f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG890F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG890F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f512.h index 1bf14d08d53..c7d1341a3e6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f512.h @@ -2,10 +2,10 @@ * @file efm32gg890f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG890F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG890F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f1024.h index 215d05171a2..ebb9f5ea3ae 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f1024.h @@ -2,10 +2,10 @@ * @file efm32gg895f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG895F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG895F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f512.h index 7c8205a4160..b7ca3b09a76 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f512.h @@ -2,10 +2,10 @@ * @file efm32gg895f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG895F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG895F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f1024.h index 6b442e444b6..6b58551d6ba 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f1024.h @@ -2,10 +2,10 @@ * @file efm32gg900f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG900F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG900F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f512.h index 5da1cbf63d6..51edd3ca9de 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f512.h @@ -2,10 +2,10 @@ * @file efm32gg900f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG900F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG900F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f1024.h index c574483f535..038fbbe44b1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f1024.h @@ -2,10 +2,10 @@ * @file efm32gg940f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG940F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG940F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f512.h index a215c9f774d..2dd8032a0b9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f512.h @@ -2,10 +2,10 @@ * @file efm32gg940f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG940F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG940F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f1024.h index 243e8c6303b..b90938ac0f6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f1024.h @@ -2,10 +2,10 @@ * @file efm32gg942f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG942F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG942F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f512.h index ecc9546983b..e7da8054888 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f512.h @@ -2,10 +2,10 @@ * @file efm32gg942f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG942F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG942F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f1024.h index d8f89b75a8f..5ac79249b99 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f1024.h @@ -2,10 +2,10 @@ * @file efm32gg980f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG980F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG980F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f512.h index c50ccca4e9e..99ef7bb750f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f512.h @@ -2,10 +2,10 @@ * @file efm32gg980f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG980F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG980F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f1024.h index 287ef990660..20adfe3b651 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f1024.h @@ -2,10 +2,10 @@ * @file efm32gg990f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG990F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG990F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f512.h index ffd90571147..2437d519836 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f512.h @@ -2,10 +2,10 @@ * @file efm32gg990f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG990F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG990F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f1024.h index ae4e0679195..6ea589419dd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f1024.h @@ -2,10 +2,10 @@ * @file efm32gg995f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG995F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG995F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f512.h index 9e1d9317a49..28217055fd9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f512.h @@ -2,10 +2,10 @@ * @file efm32gg995f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG995F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG995F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_acmp.h index 994e91b3287..1bf9e275847 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_acmp.h * @brief EFM32GG_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_adc.h index 375773ff035..81843f867ca 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_adc.h * @brief EFM32GG_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_aes.h index f70658806e4..4aff9627091 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_aes.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_aes.h * @brief EFM32GG_AES register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_pins.h index 7b4c33068ff..dd4ec98f2da 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_af_pins.h * @brief EFM32GG_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_ports.h index ae9cda5020a..d347591430a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_af_ports.h * @brief EFM32GG_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc.h index 0f2d0bc282c..becaa09942d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_burtc.h * @brief EFM32GG_BURTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc_ret.h index 1f1508d4ade..1d674611947 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc_ret.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc_ret.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_burtc_ret.h * @brief EFM32GG_BURTC_RET register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_calibrate.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_calibrate.h index bacc47992e0..f40d77de481 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_calibrate.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_calibrate.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_calibrate.h * @brief EFM32GG_CALIBRATE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_cmu.h index eca6a542382..01fdbde90b8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_cmu.h * @brief EFM32GG_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dac.h index f7993d17ebd..dae32c66785 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dac.h * @brief EFM32GG_DAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_devinfo.h index 7df832820db..f52a5997ca0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_devinfo.h * @brief EFM32GG_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma.h index be68a96c470..3cd606b0dc1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dma.h * @brief EFM32GG_DMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_ch.h index f38dd4e06b3..4abe5b40045 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dma_ch.h * @brief EFM32GG_DMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_descriptor.h index 781bed3a127..7b08013c1e6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dma_descriptor.h * @brief EFM32GG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmactrl.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmactrl.h index badbfe03572..34d69c07e7f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmactrl.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmactrl.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dmactrl.h * @brief EFM32GG_DMACTRL register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmareq.h index f074dd3f5e6..dc230e19bfe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dmareq.h * @brief EFM32GG_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_ebi.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_ebi.h index bd5ca7b1289..7806b18cef1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_ebi.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_ebi.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_ebi.h * @brief EFM32GG_EBI register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_emu.h index f6a050b8f27..5016536191e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_emu.h * @brief EFM32GG_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_etm.h index 8bbc6e0c640..dc24a206095 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_etm.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_etm.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_etm.h * @brief EFM32GG_ETM register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio.h index 5d280c0f30c..b78033b92fc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_gpio.h * @brief EFM32GG_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio_p.h index 0007874e91e..14689972a89 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_gpio_p.h * @brief EFM32GG_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_i2c.h index 0530b52a2ac..da4faaad009 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_i2c.h * @brief EFM32GG_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lcd.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lcd.h index 6fd4d48fc7b..76b576f597d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lcd.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lcd.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_lcd.h * @brief EFM32GG_LCD register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense.h index 761a0e1edbe..d785aacf14c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_lesense.h * @brief EFM32GG_LESENSE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_buf.h index 5c063b43181..120064fd05e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_buf.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_buf.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_lesense_buf.h * @brief EFM32GG_LESENSE_BUF register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_ch.h index 008f1ab9771..bc5d5661a30 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_lesense_ch.h * @brief EFM32GG_LESENSE_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_st.h index f81323ad1bd..e8be4b3c20d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_st.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_st.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_lesense_st.h * @brief EFM32GG_LESENSE_ST register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_letimer.h index a15ef1f7e6b..420cad96e1e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_letimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_letimer.h * @brief EFM32GG_LETIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_leuart.h index f2455657f29..9a46fad1d03 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_leuart.h * @brief EFM32GG_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_msc.h index ccaa36a6a1a..284c5ac9665 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_msc.h * @brief EFM32GG_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_pcnt.h index 625a6c507a5..b228387cefa 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_pcnt.h * @brief EFM32GG_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs.h index 4a8169f7f46..844590e350c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_prs.h * @brief EFM32GG_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_ch.h index 9d50eb1029d..e0debe019c8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_prs_ch.h * @brief EFM32GG_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_signals.h index 83ca5c305cf..5d6b0a89268 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_prs_signals.h * @brief EFM32GG_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rmu.h index 2913a13f852..a00e094cb22 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_rmu.h * @brief EFM32GG_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_romtable.h index 4db9e2e36e6..ce454cc9c56 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_romtable.h * @brief EFM32GG_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rtc.h index 0fc17841874..5d54586360e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_rtc.h * @brief EFM32GG_RTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer.h index a1913c8f945..611ee7a110d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_timer.h * @brief EFM32GG_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer_cc.h index 700e913e049..2508142c8f1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_timer_cc.h * @brief EFM32GG_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_uart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_uart.h index 2c40fb9ff84..2bf2046da32 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_uart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_uart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_uart.h * @brief EFM32GG_UART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usart.h index 2341301946b..b25c4b612a6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_usart.h * @brief EFM32GG_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb.h index 76e8dae1f88..5cd0a36cbed 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_usb.h * @brief EFM32GG_USB register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_diep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_diep.h index c416641edc2..b2b29834d1f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_diep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_diep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_usb_diep.h * @brief EFM32GG_USB_DIEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_doep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_doep.h index f3dfccccf50..811e5f652a8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_doep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_doep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_usb_doep.h * @brief EFM32GG_USB_DOEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_hc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_hc.h index 16e77b5107c..70366971ee2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_hc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_hc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_usb_hc.h * @brief EFM32GG_USB_HC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_vcmp.h index 291f2c0f43d..563cd3e7b29 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_vcmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_vcmp.h * @brief EFM32GG_VCMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_wdog.h index 0d9543e847c..def53f3b0e9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_wdog.h * @brief EFM32GG_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/em_device.h index 996ab74ecc6..0a2771769b2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.c index 07501db6b4e..99f60f7a752 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32gg.c * @brief CMSIS Cortex-M3 System Layer for EFM32GG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.h index 40e650ae28c..f72dd8a9fae 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32gg.h * @brief CMSIS Cortex-M3 System Layer for EFM32GG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f32.h index 01c9a9ad62e..8100c9a89cb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f32.h @@ -2,10 +2,10 @@ * @file efm32hg108f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG108F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -97,12 +97,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG108F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f64.h index fb7987894e0..b0a39e0a133 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f64.h @@ -2,10 +2,10 @@ * @file efm32hg108f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG108F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -97,12 +97,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG108F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f32.h index c286e86499a..4482a13c12b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f32.h @@ -2,10 +2,10 @@ * @file efm32hg110f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG110F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG110F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f64.h index 74d9ed02a68..dd4c381569d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f64.h @@ -2,10 +2,10 @@ * @file efm32hg110f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG110F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG110F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f32.h index 3656223bbbc..d0b453fc3fd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f32.h @@ -2,10 +2,10 @@ * @file efm32hg210f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG210F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG210F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f64.h index 2b7cfce71f4..51ebc9db8b3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f64.h @@ -2,10 +2,10 @@ * @file efm32hg210f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG210F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG210F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f32.h index 41a5ddcf3a3..1b76246e45a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f32.h @@ -2,10 +2,10 @@ * @file efm32hg222f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG222F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG222F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f64.h index 488c63ac41f..2c8137209f9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f64.h @@ -2,10 +2,10 @@ * @file efm32hg222f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG222F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG222F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f32.h index 7329bb777c6..4ecd799427d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f32.h @@ -2,10 +2,10 @@ * @file efm32hg308f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG308F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -98,12 +98,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG308F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f64.h index d5f91bf956c..3c46c52e926 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f64.h @@ -2,10 +2,10 @@ * @file efm32hg308f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG308F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -98,12 +98,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG308F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f32.h index 9efe29a3d80..d76bf9df697 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f32.h @@ -2,10 +2,10 @@ * @file efm32hg309f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG309F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG309F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f64.h index e494249e666..65bdc0ec5a8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f64.h @@ -2,10 +2,10 @@ * @file efm32hg309f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG309F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG309F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f32.h index c1bd7aea9d7..16a47c4aaa4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f32.h @@ -2,10 +2,10 @@ * @file efm32hg310f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG310F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG310F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f64.h index e17cb952925..830d5091955 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f64.h @@ -2,10 +2,10 @@ * @file efm32hg310f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG310F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG310F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f32.h index fdfb27482ce..c36722c91a3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f32.h @@ -2,10 +2,10 @@ * @file efm32hg321f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG321F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG321F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f64.h index 13c6bdf2af2..a0543bce6ee 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f64.h @@ -2,10 +2,10 @@ * @file efm32hg321f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG321F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG321F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f32.h index 68236667a84..6b7b2709ee1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f32.h @@ -2,10 +2,10 @@ * @file efm32hg322f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG322F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG322F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f64.h index de6b23112f2..be4a5680676 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f64.h @@ -2,10 +2,10 @@ * @file efm32hg322f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG322F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG322F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f32.h index 4b230ef1658..67c2d715f80 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f32.h @@ -2,10 +2,10 @@ * @file efm32hg350f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG350F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG350F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f64.h index 86e92e1e431..4998b6caf1a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f64.h @@ -2,10 +2,10 @@ * @file efm32hg350f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG350F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG350F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_acmp.h index 242362b32fa..a4a9d74da5e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_acmp.h * @brief EFM32HG_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_adc.h index fdfbd2162aa..d0411fa02bd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_adc.h * @brief EFM32HG_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_aes.h index 9d1f6db964b..acddc22c139 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_aes.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_aes.h * @brief EFM32HG_AES register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_pins.h index 3588e78a9f2..7f64dd56230 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_af_pins.h * @brief EFM32HG_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_ports.h index e974f86401d..58aa7579cb3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_af_ports.h * @brief EFM32HG_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_calibrate.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_calibrate.h index 381800add67..f9a14fe090d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_calibrate.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_calibrate.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_calibrate.h * @brief EFM32HG_CALIBRATE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_cmu.h index b9a69134ccf..665a8db28f3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_cmu.h * @brief EFM32HG_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_devinfo.h index b44828c429b..2cdd51b4efc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_devinfo.h * @brief EFM32HG_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma.h index 72ac84d805e..bc49f81b074 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_dma.h * @brief EFM32HG_DMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_ch.h index 1d03460b619..f0bdd8c2714 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_dma_ch.h * @brief EFM32HG_DMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_descriptor.h index 7d3aa0cf7b4..b66b18467d2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_dma_descriptor.h * @brief EFM32HG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmactrl.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmactrl.h index a733daea6ff..9a89dcada87 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmactrl.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmactrl.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_dmactrl.h * @brief EFM32HG_DMACTRL register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmareq.h index 15fa8e993ed..e3ce9d75fe2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_dmareq.h * @brief EFM32HG_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_emu.h index 2ec3c342eec..454218df9b4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_emu.h * @brief EFM32HG_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio.h index 6a0e3e51e65..da58990bc4c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_gpio.h * @brief EFM32HG_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio_p.h index 5ed512138e9..222ff88a6f6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_gpio_p.h * @brief EFM32HG_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_i2c.h index 31105e067fb..1b64b9a84dd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_i2c.h * @brief EFM32HG_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_idac.h index 0a39150d21e..8f5b5aa8d6f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_idac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_idac.h * @brief EFM32HG_IDAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_leuart.h index 9d9a5bcdec8..e9e8b9fe4ff 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_leuart.h * @brief EFM32HG_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_msc.h index b83dbfd4f19..723d4634913 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_msc.h * @brief EFM32HG_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_mtb.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_mtb.h index 24f22894624..487da056704 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_mtb.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_mtb.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_mtb.h * @brief EFM32HG_MTB register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_pcnt.h index 0d60292236d..1b9445793d2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_pcnt.h * @brief EFM32HG_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs.h index 715cc356e14..b0960201097 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_prs.h * @brief EFM32HG_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_ch.h index 46c129f1be8..509257a6550 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_prs_ch.h * @brief EFM32HG_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_signals.h index 8ff72af64eb..97c0a92df8c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_prs_signals.h * @brief EFM32HG_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rmu.h index 0c3d6d12fc1..766063d087f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_rmu.h * @brief EFM32HG_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_romtable.h index 4bd40db98dd..e69b2fef0cd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_romtable.h * @brief EFM32HG_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rtc.h index 767d000a0a5..923af7b2cac 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_rtc.h * @brief EFM32HG_RTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer.h index ab51f66d01a..18f320cd7b0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_timer.h * @brief EFM32HG_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer_cc.h index 6263776a3e3..bb7a5c958a0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_timer_cc.h * @brief EFM32HG_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usart.h index 3fb359ff74d..12471b8c8af 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_usart.h * @brief EFM32HG_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb.h index 223dd494463..e4828139e74 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_usb.h * @brief EFM32HG_USB register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_diep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_diep.h index 05c706f76c8..7e5702ed1aa 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_diep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_diep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_usb_diep.h * @brief EFM32HG_USB_DIEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_doep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_doep.h index 09039271bb0..971f8b76efa 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_doep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_doep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_usb_doep.h * @brief EFM32HG_USB_DOEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_vcmp.h index b1f5f45e7fd..6018dce3ae6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_vcmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_vcmp.h * @brief EFM32HG_VCMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_wdog.h index d0f2ac350ec..c5cdbbceccf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_wdog.h * @brief EFM32HG_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/em_device.h index 9c916dcbf4c..aa59dd2cb1e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.c index f3848b4b05d..5cdead97bb1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32hg.c * @brief CMSIS Cortex-M0+ System Layer for EFM32HG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.h index e1dcaffb89a..ae0e7898302 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file system_efm32hg.h * @brief CMSIS Cortex-M System Layer for EFM32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f128.h index 35b0073e94e..9e4e78ad368 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f128.h @@ -2,10 +2,10 @@ * @file efm32lg230f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG230F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG230F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f256.h index b57fea9255a..4a9e168d110 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f256.h @@ -2,10 +2,10 @@ * @file efm32lg230f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG230F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG230F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f64.h index b29641f0f9a..27ddffca728 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f64.h @@ -2,10 +2,10 @@ * @file efm32lg230f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG230F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG230F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f128.h index 71add6c549c..e0d638891c4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f128.h @@ -2,10 +2,10 @@ * @file efm32lg232f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG232F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG232F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f256.h index fd9611ba025..d6877d205eb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f256.h @@ -2,10 +2,10 @@ * @file efm32lg232f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG232F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG232F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f64.h index 5d4800941cf..e3fdec6028e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f64.h @@ -2,10 +2,10 @@ * @file efm32lg232f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG232F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG232F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f128.h index 47b1c2426fc..a71f42f5cba 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f128.h @@ -2,10 +2,10 @@ * @file efm32lg280f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG280F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG280F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f256.h index ebc3708e50c..f5e96332b8a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f256.h @@ -2,10 +2,10 @@ * @file efm32lg280f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG280F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG280F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f64.h index eda3b05b654..39f55d62ed8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f64.h @@ -2,10 +2,10 @@ * @file efm32lg280f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG280F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG280F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f128.h index 962d9140feb..03bcd469c81 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f128.h @@ -2,10 +2,10 @@ * @file efm32lg290f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG290F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG290F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f256.h index fedbcc7ff57..011abf1b8b6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f256.h @@ -2,10 +2,10 @@ * @file efm32lg290f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG290F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG290F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f64.h index ffb488e2b4b..197484638d0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f64.h @@ -2,10 +2,10 @@ * @file efm32lg290f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG290F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG290F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f128.h index 776f1cb70da..bd38bdc0546 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f128.h @@ -2,10 +2,10 @@ * @file efm32lg295f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG295F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG295F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f256.h index 6f2a5b2041a..ac37db88461 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f256.h @@ -2,10 +2,10 @@ * @file efm32lg295f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG295F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG295F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f64.h index e34aaf38727..33f571ea323 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f64.h @@ -2,10 +2,10 @@ * @file efm32lg295f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG295F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG295F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f128.h index 5cdbc7cf62b..cacc58ba28b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f128.h @@ -2,10 +2,10 @@ * @file efm32lg330f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG330F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG330F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f256.h index 2899451dca0..3051934b07e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f256.h @@ -2,10 +2,10 @@ * @file efm32lg330f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG330F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG330F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f64.h index 41bfa38a050..6b5858b74f5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f64.h @@ -2,10 +2,10 @@ * @file efm32lg330f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG330F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG330F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f128.h index b0c55a4de49..469c35b8035 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f128.h @@ -2,10 +2,10 @@ * @file efm32lg332f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG332F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG332F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f256.h index a8d063de0c9..65ed5a78399 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f256.h @@ -2,10 +2,10 @@ * @file efm32lg332f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG332F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG332F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f64.h index cf5a08fc78e..15623f25191 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f64.h @@ -2,10 +2,10 @@ * @file efm32lg332f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG332F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG332F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f128.h index f1b43d2df78..5d5563303a1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f128.h @@ -2,10 +2,10 @@ * @file efm32lg360f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG360F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG360F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f256.h index 614fe9dbd6b..1fa10d42a44 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f256.h @@ -2,10 +2,10 @@ * @file efm32lg360f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG360F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG360F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f64.h index c373d89d7d5..62269b8e2d9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f64.h @@ -2,10 +2,10 @@ * @file efm32lg360f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG360F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG360F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f128.h index 1413f40b2a0..78b36f0f9d6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f128.h @@ -2,10 +2,10 @@ * @file efm32lg380f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG380F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG380F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f256.h index d24e7cfc33b..087eefaf69e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f256.h @@ -2,10 +2,10 @@ * @file efm32lg380f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG380F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG380F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f64.h index 8bab9e275a3..09d4094e3f3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f64.h @@ -2,10 +2,10 @@ * @file efm32lg380f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG380F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG380F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f128.h index 291d5f519bf..4ce8fd17b0f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f128.h @@ -2,10 +2,10 @@ * @file efm32lg390f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG390F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG390F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f256.h index a19c2916855..8a963800581 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f256.h @@ -2,10 +2,10 @@ * @file efm32lg390f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG390F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG390F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f64.h index d3a3c49ab9e..66be636be9c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f64.h @@ -2,10 +2,10 @@ * @file efm32lg390f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG390F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG390F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f128.h index f40cd8717fb..c3f4abd4cac 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f128.h @@ -2,10 +2,10 @@ * @file efm32lg395f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG395F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG395F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f256.h index 06c2953c32f..57ced454a73 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f256.h @@ -2,10 +2,10 @@ * @file efm32lg395f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG395F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG395F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f64.h index a33b682b87c..aa0f1bad0b8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f64.h @@ -2,10 +2,10 @@ * @file efm32lg395f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG395F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG395F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f128.h index 11f2c7f8e03..56dc58b56b9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f128.h @@ -2,10 +2,10 @@ * @file efm32lg840f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG840F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG840F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f256.h index 2a2fcefa4f2..3240db478f9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f256.h @@ -2,10 +2,10 @@ * @file efm32lg840f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG840F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG840F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f64.h index b2c6030704b..7800c62a741 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f64.h @@ -2,10 +2,10 @@ * @file efm32lg840f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG840F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG840F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f128.h index 0a822f3e346..b248f987edb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f128.h @@ -2,10 +2,10 @@ * @file efm32lg842f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG842F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG842F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f256.h index e5a5cb474db..6bc214eda64 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f256.h @@ -2,10 +2,10 @@ * @file efm32lg842f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG842F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG842F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f64.h index 28f709d71a3..59546f3e5a6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f64.h @@ -2,10 +2,10 @@ * @file efm32lg842f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG842F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG842F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f128.h index c9848854029..57a541c515c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f128.h @@ -2,10 +2,10 @@ * @file efm32lg880f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG880F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG880F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f256.h index 8e9def0b9e9..827567ccba0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f256.h @@ -2,10 +2,10 @@ * @file efm32lg880f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG880F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG880F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f64.h index 784099620d1..ed37542285f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f64.h @@ -2,10 +2,10 @@ * @file efm32lg880f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG880F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG880F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f128.h index 6913d62228c..1f7c474f9a2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f128.h @@ -2,10 +2,10 @@ * @file efm32lg890f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG890F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG890F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f256.h index 9634c9e2f99..4b4dcf18a84 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f256.h @@ -2,10 +2,10 @@ * @file efm32lg890f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG890F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG890F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f64.h index fdb82f5554b..38cb8541065 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f64.h @@ -2,10 +2,10 @@ * @file efm32lg890f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG890F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG890F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f128.h index 1f72cbed08a..3eddf1dacc5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f128.h @@ -2,10 +2,10 @@ * @file efm32lg895f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG895F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG895F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f256.h index b4b2b438864..82150684405 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f256.h @@ -2,10 +2,10 @@ * @file efm32lg895f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG895F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG895F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f64.h index 77a5b3fcb8c..3f287a3631b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f64.h @@ -2,10 +2,10 @@ * @file efm32lg895f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG895F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG895F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg900f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg900f256.h index 7b31945df6c..dea1404748d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg900f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg900f256.h @@ -2,10 +2,10 @@ * @file efm32lg900f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG900F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG900F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f128.h index 3df5c67be7e..e8c8274f48b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f128.h @@ -2,10 +2,10 @@ * @file efm32lg940f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG940F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG940F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f256.h index 4910ef8500f..aa2c9b0a595 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f256.h @@ -2,10 +2,10 @@ * @file efm32lg940f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG940F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG940F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f64.h index 2ceac32b364..8777184a46f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f64.h @@ -2,10 +2,10 @@ * @file efm32lg940f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG940F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG940F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f128.h index c8ba094f703..f902a76e561 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f128.h @@ -2,10 +2,10 @@ * @file efm32lg942f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG942F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG942F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f256.h index dccc95d33b6..c5428fca95c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f256.h @@ -2,10 +2,10 @@ * @file efm32lg942f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG942F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG942F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f64.h index af421a3c65c..66ed5de5fb0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f64.h @@ -2,10 +2,10 @@ * @file efm32lg942f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG942F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG942F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f128.h index f5f205c90ab..5162699e692 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f128.h @@ -2,10 +2,10 @@ * @file efm32lg980f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG980F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG980F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f256.h index 4afb513a8f7..6940beb8448 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f256.h @@ -2,10 +2,10 @@ * @file efm32lg980f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG980F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG980F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f64.h index b59be1ce824..0bed24d8510 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f64.h @@ -2,10 +2,10 @@ * @file efm32lg980f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG980F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG980F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f128.h index 74609a4fe42..b8efa8c2eaa 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f128.h @@ -2,10 +2,10 @@ * @file efm32lg990f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG990F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG990F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f256.h index a27e711abfa..a1baed571f9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f256.h @@ -2,10 +2,10 @@ * @file efm32lg990f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG990F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG990F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f64.h index af427afb3af..bd31cbd004f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f64.h @@ -2,10 +2,10 @@ * @file efm32lg990f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG990F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG990F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f128.h index cc9cd86055a..461fd50dd69 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f128.h @@ -2,10 +2,10 @@ * @file efm32lg995f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG995F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG995F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f256.h index d1398b8b770..0c28f892e10 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f256.h @@ -2,10 +2,10 @@ * @file efm32lg995f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG995F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG995F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f64.h index 17359044e4d..10ad3f8feb9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f64.h @@ -2,10 +2,10 @@ * @file efm32lg995f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG995F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG995F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_acmp.h index 1ad27b82336..9f451866fb9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_acmp.h * @brief EFM32LG_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_adc.h index ee30a4531bb..154c2af3eea 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_adc.h * @brief EFM32LG_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_aes.h index c2ebe218ea8..e53ec353ff2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_aes.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_aes.h * @brief EFM32LG_AES register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_pins.h index 0dc982bf76a..5f779444fa5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_af_pins.h * @brief EFM32LG_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_ports.h index 541240a17d2..d99c8c8e77e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_af_ports.h * @brief EFM32LG_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc.h index 96eb19659c7..0ba56c68382 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_burtc.h * @brief EFM32LG_BURTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc_ret.h index e9ca084c6da..7c0d5aa044b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc_ret.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc_ret.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_burtc_ret.h * @brief EFM32LG_BURTC_RET register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_calibrate.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_calibrate.h index 43b8fa5446c..7864fcfa5f8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_calibrate.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_calibrate.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_calibrate.h * @brief EFM32LG_CALIBRATE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_cmu.h index c6ca47c5280..a5fce199519 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_cmu.h * @brief EFM32LG_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dac.h index 6d46975dfa1..259e446990b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dac.h * @brief EFM32LG_DAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_devinfo.h index e08d2b60455..9fe1e05ca93 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_devinfo.h * @brief EFM32LG_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma.h index a68a1caad02..8ade291b47a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dma.h * @brief EFM32LG_DMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_ch.h index 6abd7a58a8f..56505012961 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dma_ch.h * @brief EFM32LG_DMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_descriptor.h index 3e7618088a0..030fc85688a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dma_descriptor.h * @brief EFM32LG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmactrl.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmactrl.h index 52171bf6e39..ac7e3a8717c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmactrl.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmactrl.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dmactrl.h * @brief EFM32LG_DMACTRL register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmareq.h index 0918a246091..b5db52d44ae 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dmareq.h * @brief EFM32LG_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_ebi.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_ebi.h index 705c6bc6214..1b49d89bfb6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_ebi.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_ebi.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_ebi.h * @brief EFM32LG_EBI register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_emu.h index ac6466c1a1c..28f537af9fe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_emu.h * @brief EFM32LG_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_etm.h index 21112d31f80..c692a0b8def 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_etm.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_etm.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_etm.h * @brief EFM32LG_ETM register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio.h index ea4bc19af02..86a66d533c8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_gpio.h * @brief EFM32LG_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio_p.h index 43e45dd6cc2..8a8694fc65a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_gpio_p.h * @brief EFM32LG_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_i2c.h index 35b1c91413b..7b940193cb7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_i2c.h * @brief EFM32LG_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lcd.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lcd.h index 618f006abb5..29586a380a6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lcd.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lcd.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_lcd.h * @brief EFM32LG_LCD register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense.h index 3ff319ed54a..65d16f59b5e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_lesense.h * @brief EFM32LG_LESENSE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_buf.h index 70a2de6a7ea..3b94d448509 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_buf.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_buf.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_lesense_buf.h * @brief EFM32LG_LESENSE_BUF register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_ch.h index aa754a81078..9f37985ecad 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_lesense_ch.h * @brief EFM32LG_LESENSE_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_st.h index e30555d28ce..f9474858b38 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_st.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_st.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_lesense_st.h * @brief EFM32LG_LESENSE_ST register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_letimer.h index 2f874de534f..473089b3625 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_letimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_letimer.h * @brief EFM32LG_LETIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_leuart.h index 93ff07fb963..53b86b59668 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_leuart.h * @brief EFM32LG_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_msc.h index 919eaf02d5e..2d15ae58f54 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_msc.h * @brief EFM32LG_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_pcnt.h index f369b79a10c..037be6bac4a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_pcnt.h * @brief EFM32LG_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs.h index 8d38d71b01f..f3a9dd383d8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_prs.h * @brief EFM32LG_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_ch.h index 9852c302519..9912e5a70d7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_prs_ch.h * @brief EFM32LG_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_signals.h index f34970d94b5..432b3a68897 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_prs_signals.h * @brief EFM32LG_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rmu.h index 65a0680e011..71b80070327 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_rmu.h * @brief EFM32LG_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_romtable.h index e7a1bc8cf58..372cb8674fb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_romtable.h * @brief EFM32LG_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rtc.h index 35187b66882..6781a4d5746 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_rtc.h * @brief EFM32LG_RTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer.h index a0ad7b44650..15223d4ebc2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_timer.h * @brief EFM32LG_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer_cc.h index df9e7dc0072..88a63c112e5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_timer_cc.h * @brief EFM32LG_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_uart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_uart.h index 99958cf6589..4b71f5a91a9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_uart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_uart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_uart.h * @brief EFM32LG_UART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usart.h index 2d9a73d309a..54945b35a52 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_usart.h * @brief EFM32LG_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb.h index 6106899331a..e013e220d81 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_usb.h * @brief EFM32LG_USB register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_diep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_diep.h index 06ec1d06809..cf40ba8749b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_diep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_diep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_usb_diep.h * @brief EFM32LG_USB_DIEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_doep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_doep.h index f04de8e6263..0f4a62c55c5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_doep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_doep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_usb_doep.h * @brief EFM32LG_USB_DOEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_hc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_hc.h index 8bd79f64680..cb3bf30e532 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_hc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_hc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_usb_hc.h * @brief EFM32LG_USB_HC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_vcmp.h index 2e1b5426b5c..fc1c9265c26 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_vcmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_vcmp.h * @brief EFM32LG_VCMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_wdog.h index a20b80c9f75..8f3e3f98e97 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_wdog.h * @brief EFM32LG_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/em_device.h index 663cb80026c..5acb39d9315 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.c index 79c9f657067..e6d9d4a7b55 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32lg.c * @brief CMSIS Cortex-M3 System Layer for EFM32LG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.h index c3070afddce..7f0b4990963 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32lg.h * @brief CMSIS Cortex-M3 System Layer for EFM32LG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h index baa35e5ba0d..3147299bbdc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h @@ -33,4 +33,25 @@ #define PWM_TIMER_CLOCK cmuClock_TIMER1 #define PWM_ROUTE TIMER_ROUTE_LOCATION_LOC1 +/* Crystal Calibration */ +#if !defined(CMU_HFXOINIT_STK_DEFAULT) +#define CMU_HFXOINIT_STK_DEFAULT \ +{ \ + true, /* Low-power mode for EFM32 */ \ + false, /* Disable auto-start on EM0/1 entry */ \ + false, /* Disable auto-select on EM0/1 entry */ \ + false, /* Disable auto-start and select on RAC wakeup */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + 0x142, /* Steady-state CTUNE for STK boards without load caps */ \ + _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ + 0x20, /* Matching errata fix in CHIP_Init() */ \ + 0x7, /* Recommended steady-state osc core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \ + 0xA, /* Recommended peak detection timeout */ \ + 0x4, /* Recommended steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ +} +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128gm32.h index 29372e57c78..de3a6cb0c08 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128gm32.h @@ -2,10 +2,10 @@ * @file efm32pg1b100f128gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B100F128GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B100F128GM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128im32.h index b1acbc5d1f2..92f170ef7d5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128im32.h @@ -2,10 +2,10 @@ * @file efm32pg1b100f128im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B100F128IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B100F128IM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256gm32.h index d12defc8b55..78d0ae84133 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256gm32.h @@ -2,10 +2,10 @@ * @file efm32pg1b100f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B100F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B100F256GM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256im32.h index e9760e58f5d..ae4861c2224 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256im32.h @@ -2,10 +2,10 @@ * @file efm32pg1b100f256im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B100F256IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B100F256IM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm32.h index 55ec34ce9ed..90f2071948a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm32.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f128gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F128GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F128GM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm48.h index fd7e743b0ed..c2c75f98d2c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm48.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f128gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F128GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F128GM48) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128im32.h index bd050c247e1..ea72bca16cf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128im32.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f128im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F128IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F128IM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm32.h index c2cfb8bd3fa..8c8d894bb42 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm32.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F256GM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm48.h index f65e64ce295..f7c55309254 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm48.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F256GM48) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im32.h index 9e74f655448..c4a351eb06e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im32.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f256im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F256IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F256IM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im48.h index 3078604580e..72b8a6ad657 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im48.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f256im48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F256IM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F256IM48) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_acmp.h index a092855bfed..d2ed5871e7d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_acmp.h * @brief EFM32PG1B_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -329,8 +329,6 @@ typedef struct #define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ @@ -497,8 +495,6 @@ typedef struct #define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */ @@ -667,8 +663,6 @@ typedef struct #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ @@ -835,8 +829,6 @@ typedef struct #define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_adc.h index 4f241bb379a..ba9916f6bd6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_adc.h * @brief EFM32PG1B_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_pins.h index b017fe1c677..e7544078c15 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_af_pins.h * @brief EFM32PG1B_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_ports.h index 72dc23fa7a2..1f1f8c02bc7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_af_ports.h * @brief EFM32PG1B_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cmu.h index 38627ef518b..bd83c0a46c7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_cmu.h * @brief EFM32PG1B_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -56,8 +56,9 @@ typedef struct __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */ __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + __IOM uint32_t ULFRCOCTRL; /**< ULFRCO Control Register */ - uint32_t RESERVED3[5]; /**< Reserved for future use **/ + uint32_t RESERVED3[4]; /**< Reserved for future use **/ __IOM uint32_t CALCTRL; /**< Calibration Control Register */ __IOM uint32_t CALCNT; /**< Calibration Counter Register */ uint32_t RESERVED4[2]; /**< Reserved for future use **/ @@ -637,6 +638,30 @@ typedef struct #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ +/* Bit fields for CMU ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_RESETVALUE 0x00020020UL /**< Default value for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MASK 0x00030C3FUL /**< Mask for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_ULFRCOCTRL_TUNING_MASK 0x3FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_ULFRCOCTRL_TUNING_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_TUNING_DEFAULT (_CMU_ULFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_SHIFT 10 /**< Shift value for CMU_MODE */ +#define _CMU_ULFRCOCTRL_MODE_MASK 0xC00UL /**< Bit mask for CMU_MODE */ +#define _CMU_ULFRCOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_1KHZ 0x00000000UL /**< Mode 1KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_2KHZ 0x00000001UL /**< Mode 2KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_4KHZ 0x00000002UL /**< Mode 4KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_32KHZ 0x00000003UL /**< Mode 32KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_DEFAULT (_CMU_ULFRCOCTRL_MODE_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_1KHZ (_CMU_ULFRCOCTRL_MODE_1KHZ << 10) /**< Shifted mode 1KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_2KHZ (_CMU_ULFRCOCTRL_MODE_2KHZ << 10) /**< Shifted mode 2KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_4KHZ (_CMU_ULFRCOCTRL_MODE_4KHZ << 10) /**< Shifted mode 4KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_32KHZ (_CMU_ULFRCOCTRL_MODE_32KHZ << 10) /**< Shifted mode 32KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_RESTRIM_SHIFT 16 /**< Shift value for CMU_RESTRIM */ +#define _CMU_ULFRCOCTRL_RESTRIM_MASK 0x30000UL /**< Bit mask for CMU_RESTRIM */ +#define _CMU_ULFRCOCTRL_RESTRIM_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_RESTRIM_DEFAULT (_CMU_ULFRCOCTRL_RESTRIM_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ + /* Bit fields for CMU CALCTRL */ #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ #define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */ @@ -902,7 +927,7 @@ typedef struct /* Bit fields for CMU STATUS */ #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ -#define _CMU_STATUS_MASK 0x07C103FFUL /**< Mask for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x07E103FFUL /**< Mask for CMU_STATUS */ #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ @@ -958,6 +983,11 @@ typedef struct #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required by Hardware (e.g. RAC) */ +#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cryotimer.h index ecf546c8333..d093913a42b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cryotimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cryotimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_cryotimer.h * @brief EFM32PG1B_CRYOTIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_crypto.h index d0253d4832f..4c173087dab 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_crypto.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_crypto.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_crypto.h * @brief EFM32PG1B_CRYPTO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -843,7 +843,7 @@ typedef struct /* Bit fields for CRYPTO IFS */ #define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */ -#define _CRYPTO_IFS_MASK 0x0000000FUL /**< Mask for CRYPTO_IFS */ +#define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */ #define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */ #define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -854,20 +854,10 @@ typedef struct #define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ #define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFOF (0x1UL << 2) /**< Set BUFOF Interrupt Flag */ -#define _CRYPTO_IFS_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IFS_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFOF_DEFAULT (_CRYPTO_IFS_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFUF (0x1UL << 3) /**< Set BUFUF Interrupt Flag */ -#define _CRYPTO_IFS_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IFS_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IFS_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFUF_DEFAULT (_CRYPTO_IFS_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IFS */ /* Bit fields for CRYPTO IFC */ #define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */ -#define _CRYPTO_IFC_MASK 0x0000000FUL /**< Mask for CRYPTO_IFC */ +#define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */ #define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */ #define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -878,20 +868,10 @@ typedef struct #define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ #define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFOF (0x1UL << 2) /**< Clear BUFOF Interrupt Flag */ -#define _CRYPTO_IFC_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IFC_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFOF_DEFAULT (_CRYPTO_IFC_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFUF (0x1UL << 3) /**< Clear BUFUF Interrupt Flag */ -#define _CRYPTO_IFC_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IFC_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IFC_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFUF_DEFAULT (_CRYPTO_IFC_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IFC */ /* Bit fields for CRYPTO IEN */ #define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */ -#define _CRYPTO_IEN_MASK 0x0000000FUL /**< Mask for CRYPTO_IEN */ +#define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */ #define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */ #define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -902,16 +882,6 @@ typedef struct #define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ #define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFOF (0x1UL << 2) /**< BUFOF Interrupt Enable */ -#define _CRYPTO_IEN_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IEN_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFOF_DEFAULT (_CRYPTO_IEN_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFUF (0x1UL << 3) /**< BUFUF Interrupt Enable */ -#define _CRYPTO_IEN_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IEN_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IEN_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFUF_DEFAULT (_CRYPTO_IEN_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IEN */ /* Bit fields for CRYPTO SEQ0 */ #define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_devinfo.h index 8f332ed358c..300c732f1e5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_devinfo.h * @brief EFM32PG1B_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dma_descriptor.h index a0944a1d72f..141b29e024a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_dma_descriptor.h * @brief EFM32PG1B_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dmareq.h index cd665476831..1392a44abfc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_dmareq.h * @brief EFM32PG1B_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_emu.h index dcb8164e24e..40f2d3d8f64 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_emu.h * @brief EFM32PG1B_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -63,24 +63,32 @@ typedef struct __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ - - uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ __IOM uint32_t DCDCTIMING; /**< DCDC Controller Timing Value Register */ __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ - uint32_t RESERVED3[1]; /**< Reserved for future use **/ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ - uint32_t RESERVED4[1]; /**< Reserved for future use **/ + uint32_t RESERVED3[1]; /**< Reserved for future use **/ __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ - uint32_t RESERVED5[5]; /**< Reserved for future use **/ + uint32_t RESERVED4[5]; /**< Reserved for future use **/ __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + + uint32_t RESERVED5[49]; /**< Reserved for future use **/ + __IOM uint32_t BIASCONF; /**< Configurations Related to the Bias */ + + uint32_t RESERVED6[10]; /**< Reserved for future use **/ + __IOM uint32_t TESTLOCK; /**< Test Lock Register */ + + uint32_t RESERVED7[2]; /**< Reserved for future use **/ + __IOM uint32_t BIASTESTCTRL; /**< Test Control Register for regulator and BIAS */ } EMU_TypeDef; /** @} */ /**************************************************************************//** @@ -351,7 +359,7 @@ typedef struct /* Bit fields for EMU IFS */ #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ -#define _EMU_IFS_MASK 0xE11FF0FFUL /**< Mask for EMU_IFS */ +#define _EMU_IFS_MASK 0xE11FC0FFUL /**< Mask for EMU_IFS */ #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -392,16 +400,6 @@ typedef struct #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDFALL (0x1UL << 12) /**< Set VMONPAVDDFALL Interrupt Flag */ -#define _EMU_IFS_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IFS_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IFS_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDFALL_DEFAULT (_EMU_IFS_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDRISE (0x1UL << 13) /**< Set VMONPAVDDRISE Interrupt Flag */ -#define _EMU_IFS_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IFS_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IFS_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDRISE_DEFAULT (_EMU_IFS_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -460,7 +458,7 @@ typedef struct /* Bit fields for EMU IFC */ #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ -#define _EMU_IFC_MASK 0xE11FF0FFUL /**< Mask for EMU_IFC */ +#define _EMU_IFC_MASK 0xE11FC0FFUL /**< Mask for EMU_IFC */ #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -501,16 +499,6 @@ typedef struct #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDFALL (0x1UL << 12) /**< Clear VMONPAVDDFALL Interrupt Flag */ -#define _EMU_IFC_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IFC_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IFC_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDFALL_DEFAULT (_EMU_IFC_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDRISE (0x1UL << 13) /**< Clear VMONPAVDDRISE Interrupt Flag */ -#define _EMU_IFC_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IFC_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IFC_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDRISE_DEFAULT (_EMU_IFC_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -569,7 +557,7 @@ typedef struct /* Bit fields for EMU IEN */ #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ -#define _EMU_IEN_MASK 0xE11FF0FFUL /**< Mask for EMU_IEN */ +#define _EMU_IEN_MASK 0xE11FC0FFUL /**< Mask for EMU_IEN */ #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -610,16 +598,6 @@ typedef struct #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDFALL (0x1UL << 12) /**< VMONPAVDDFALL Interrupt Enable */ -#define _EMU_IEN_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IEN_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IEN_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDFALL_DEFAULT (_EMU_IEN_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDRISE (0x1UL << 13) /**< VMONPAVDDRISE Interrupt Enable */ -#define _EMU_IEN_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IEN_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IEN_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDRISE_DEFAULT (_EMU_IEN_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -817,6 +795,34 @@ typedef struct #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + /* Bit fields for EMU DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ @@ -1035,6 +1041,65 @@ typedef struct #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +/* Bit fields for EMU BIASCONF */ +#define _EMU_BIASCONF_RESETVALUE 0x000000F8UL /**< Default value for EMU_BIASCONF */ +#define _EMU_BIASCONF_MASK 0x000000FCUL /**< Mask for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM01 (0x1UL << 2) /**< NA DUTY in EM01 */ +#define _EMU_BIASCONF_NADUTYEM01_SHIFT 2 /**< Shift value for EMU_NADUTYEM01 */ +#define _EMU_BIASCONF_NADUTYEM01_MASK 0x4UL /**< Bit mask for EMU_NADUTYEM01 */ +#define _EMU_BIASCONF_NADUTYEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM01_DEFAULT (_EMU_BIASCONF_NADUTYEM01_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM01 (0x1UL << 3) /**< LP in EM01 */ +#define _EMU_BIASCONF_LPEM01_SHIFT 3 /**< Shift value for EMU_LPEM01 */ +#define _EMU_BIASCONF_LPEM01_MASK 0x8UL /**< Bit mask for EMU_LPEM01 */ +#define _EMU_BIASCONF_LPEM01_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM01_DEFAULT (_EMU_BIASCONF_LPEM01_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_GMCEM23 (0x1UL << 4) /**< GMC in EM234 */ +#define _EMU_BIASCONF_GMCEM23_SHIFT 4 /**< Shift value for EMU_GMCEM23 */ +#define _EMU_BIASCONF_GMCEM23_MASK 0x10UL /**< Bit mask for EMU_GMCEM23 */ +#define _EMU_BIASCONF_GMCEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_GMCEM23_DEFAULT (_EMU_BIASCONF_GMCEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_UADUTYEM23 (0x1UL << 5) /**< UADUTY in EM234 */ +#define _EMU_BIASCONF_UADUTYEM23_SHIFT 5 /**< Shift value for EMU_UADUTYEM23 */ +#define _EMU_BIASCONF_UADUTYEM23_MASK 0x20UL /**< Bit mask for EMU_UADUTYEM23 */ +#define _EMU_BIASCONF_UADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_UADUTYEM23_DEFAULT (_EMU_BIASCONF_UADUTYEM23_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM23 (0x1UL << 6) /**< NA DUTY in EM234 */ +#define _EMU_BIASCONF_NADUTYEM23_SHIFT 6 /**< Shift value for EMU_NADUTYEM23 */ +#define _EMU_BIASCONF_NADUTYEM23_MASK 0x40UL /**< Bit mask for EMU_NADUTYEM23 */ +#define _EMU_BIASCONF_NADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM23_DEFAULT (_EMU_BIASCONF_NADUTYEM23_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM23 (0x1UL << 7) /**< LP in EM234 */ +#define _EMU_BIASCONF_LPEM23_SHIFT 7 /**< Shift value for EMU_LPEM23 */ +#define _EMU_BIASCONF_LPEM23_MASK 0x80UL /**< Bit mask for EMU_LPEM23 */ +#define _EMU_BIASCONF_LPEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM23_DEFAULT (_EMU_BIASCONF_LPEM23_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_BIASCONF */ + +/* Bit fields for EMU TESTLOCK */ +#define _EMU_TESTLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_TESTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_TESTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_DEFAULT (_EMU_TESTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_UNLOCKED (_EMU_TESTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_LOCKED (_EMU_TESTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_UNLOCK (_EMU_TESTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_TESTLOCK */ + +/* Bit fields for EMU BIASTESTCTRL */ +#define _EMU_BIASTESTCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BIASTESTCTRL */ +#define _EMU_BIASTESTCTRL_MASK 0x00000008UL /**< Mask for EMU_BIASTESTCTRL */ +#define EMU_BIASTESTCTRL_BIAS_RIP_RESET (0x1UL << 3) /**< Reset Bias Ripple Counter */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_SHIFT 3 /**< Shift value for EMU_BIAS_RIP_RESET */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_MASK 0x8UL /**< Bit mask for EMU_BIAS_RIP_RESET */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASTESTCTRL */ +#define EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT (_EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASTESTCTRL */ + /** @} End of group EFM32PG1B_EMU */ /** @} End of group Parts */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_fpueh.h index 386e8b6f654..818dec5e60c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_fpueh.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_fpueh.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_fpueh.h * @brief EFM32PG1B_FPUEH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpcrc.h index 8a8445cb285..14a2dba31d1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpcrc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpcrc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_gpcrc.h * @brief EFM32PG1B_GPCRC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio.h index 71655bfe1c6..65a6962fe60 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_gpio.h * @brief EFM32PG1B_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio_p.h index 8c1b0cfbbcc..2bb3d5d116b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_gpio_p.h * @brief EFM32PG1B_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_i2c.h index fcb01990da4..7dd1b19105a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_i2c.h * @brief EFM32PG1B_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_idac.h index 47b2f772f9c..76579247fb0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_idac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_idac.h * @brief EFM32PG1B_IDAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -43,7 +43,7 @@ typedef struct __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CURPROG; /**< Current Programming Register */ uint32_t RESERVED0[1]; /**< Reserved for future use **/ - __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configauration Register */ + __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */ uint32_t RESERVED1[2]; /**< Reserved for future use **/ __IM uint32_t STATUS; /**< Status Register */ @@ -259,12 +259,7 @@ typedef struct /* Bit fields for IDAC IFS */ #define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */ -#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */ -#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */ -#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ -#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */ +#define _IDAC_IFS_MASK 0x00000002UL /**< Mask for IDAC_IFS */ #define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */ #define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ @@ -273,12 +268,7 @@ typedef struct /* Bit fields for IDAC IFC */ #define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */ -#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */ -#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */ -#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ -#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */ +#define _IDAC_IFC_MASK 0x00000002UL /**< Mask for IDAC_IFC */ #define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */ #define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ @@ -287,12 +277,7 @@ typedef struct /* Bit fields for IDAC IEN */ #define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */ -#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */ -#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */ -#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ -#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */ +#define _IDAC_IEN_MASK 0x00000002UL /**< Mask for IDAC_IEN */ #define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */ #define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma.h index 0037bac3da0..aed20157bdf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_ldma.h * @brief EFM32PG1B_LDMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma_ch.h index c7c53a1ad05..3633f4147de 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_ldma_ch.h * @brief EFM32PG1B_LDMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_letimer.h index fba7016b13b..a2680ba9d15 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_letimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_letimer.h * @brief EFM32PG1B_LETIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_leuart.h index 4c821a61598..fdf21dc179a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_leuart.h * @brief EFM32PG1B_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_msc.h index 6543ca80b9b..355ffdaa210 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_msc.h * @brief EFM32PG1B_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_pcnt.h index d3a0b2be4db..21dbf5dcbf9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_pcnt.h * @brief EFM32PG1B_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs.h index 82a561d6434..875f839518b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_prs.h * @brief EFM32PG1B_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -756,6 +756,7 @@ typedef struct #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ @@ -821,6 +822,7 @@ typedef struct #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ @@ -891,6 +893,7 @@ typedef struct #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x00000036UL /**< Mode PCNT0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000003CUL /**< Mode CRYOTIMER for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_CMU 0x0000003DUL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ @@ -908,6 +911,7 @@ typedef struct #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ #define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_ch.h index 4fd64da92e7..4579e7d4dfa 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_prs_ch.h * @brief EFM32PG1B_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_signals.h index 0bc2eca0f38..4ac390db0d0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_prs_signals.h * @brief EFM32PG1B_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -103,6 +103,7 @@ #define PRS_CRYOTIMER_PERIOD ((60 << 8) + 0) /**< PRS CRYOTIMER Output */ #define PRS_CMU_CLKOUT0 ((61 << 8) + 0) /**< PRS Clock Output 0 */ #define PRS_CMU_CLKOUT1 ((61 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ /** @} End of group EFM32PG1B_PRS */ /** @} End of group Parts */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rmu.h index 708b12e8f00..76f1b37b107 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_rmu.h * @brief EFM32PG1B_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_romtable.h index e948d3503fe..008c130c5fb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_romtable.h * @brief EFM32PG1B_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc.h index 788321cb3e9..52f75a100e9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_rtcc.h * @brief EFM32PG1B_RTCC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_cc.h index 402208c0c00..7713190d4ba 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_rtcc_cc.h * @brief EFM32PG1B_RTCC_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_ret.h index 95989994a87..08d37ce0e8a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_ret.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_ret.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_rtcc_ret.h * @brief EFM32PG1B_RTCC_RET register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer.h index f36454350b3..d3375e816a7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_timer.h * @brief EFM32PG1B_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -188,7 +188,7 @@ typedef struct #define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ #define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Ouptut initial State */ +#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ #define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ #define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ #define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer_cc.h index 4c2de40945c..6f59d048bfc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_timer_cc.h * @brief EFM32PG1B_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_usart.h index 703809c891a..bdd63b4acc2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_usart.h * @brief EFM32PG1B_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog.h index 0ae78a240a3..de9d49cf9f2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_wdog.h * @brief EFM32PG1B_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -215,17 +215,17 @@ typedef struct /* Bit fields for WDOG IF */ #define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ #define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ -#define WDOG_IF_TOUT (0x1UL << 0) /**< Wdog Timeout Interrupt Flag */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ #define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ #define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ #define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN (0x1UL << 1) /**< Wdog Warning Timeout Interrupt Flag */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ #define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ #define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ #define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN (0x1UL << 2) /**< Wdog Window Interrupt Flag */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ #define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ #define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ #define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog_pch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog_pch.h index daf5c3d81e6..5c5498d1097 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog_pch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog_pch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_wdog_pch.h * @brief EFM32PG1B_WDOG_PCH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/em_device.h index 53766bba5a9..7d3ac63c372 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.c index d925c0557c0..73c6352b6b6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32pg1b.c * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.h index bf3a225c371..8aa24f12e7a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32pg1b.h * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralNames.h new file mode 100644 index 00000000000..2e5170aef5f --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralNames.h @@ -0,0 +1,69 @@ +/***************************************************************************//** + * @file PeripheralNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "em_adc.h" +#include "em_usart.h" +#include "em_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_0 = ADC0_BASE +} ADCName; + +typedef enum { + I2C_0 = I2C0_BASE, + I2C_1 = I2C1_BASE, +} I2CName; + +typedef enum { + PWM_CH0 = 0, + PWM_CH1 = 1, + PWM_CH2 = 2, + PWM_CH3 = 3 +} PWMName; + +typedef enum { + USART_0 = USART0_BASE, + USART_1 = USART1_BASE, + USART_2 = USART2_BASE, + USART_3 = USART3_BASE, + LEUART_0 = LEUART0_BASE, +} UARTName; + +typedef enum { + SPI_0 = USART0_BASE, + SPI_1 = USART1_BASE, + SPI_2 = USART2_BASE, + SPI_3 = USART3_BASE, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.c new file mode 100644 index 00000000000..95baad0840a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.c @@ -0,0 +1,427 @@ +/***************************************************************************//** + * @file PeripheralPins.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "PeripheralPins.h" + +/************ADC***************/ +/* The third "function" value is used to select the correct ADC channel */ +const PinMap PinMap_ADC[] = { + {PA0, ADC_0, adcPosSelAPORT3XCH8}, + {PA1, ADC_0, adcPosSelAPORT4XCH9}, + {PA2, ADC_0, adcPosSelAPORT3XCH10}, + {PA3, ADC_0, adcPosSelAPORT4XCH11}, + {PA4, ADC_0, adcPosSelAPORT3XCH12}, + {PA5, ADC_0, adcPosSelAPORT4XCH13}, + + {PB11, ADC_0, adcPosSelAPORT4XCH27}, + {PB12, ADC_0, adcPosSelAPORT3XCH28}, + {PB14, ADC_0, adcPosSelAPORT3XCH30}, + {PB15, ADC_0, adcPosSelAPORT4XCH31}, + + {PC6, ADC_0, adcPosSelAPORT1XCH6}, + {PC7, ADC_0, adcPosSelAPORT2XCH7}, + {PC8, ADC_0, adcPosSelAPORT1XCH8}, + {PC9, ADC_0, adcPosSelAPORT2XCH9}, + {PC10, ADC_0, adcPosSelAPORT1XCH10}, + {PC11, ADC_0, adcPosSelAPORT2XCH11}, + + {PD9, ADC_0, adcPosSelAPORT4XCH1}, + {PD10, ADC_0, adcPosSelAPORT3XCH2}, + {PD11, ADC_0, adcPosSelAPORT3YCH3}, + {PD12, ADC_0, adcPosSelAPORT3XCH4}, + {PD13, ADC_0, adcPosSelAPORT3YCH5}, + {PD14, ADC_0, adcPosSelAPORT3XCH6}, + {PD15, ADC_0, adcPosSelAPORT4XCH7}, + + {PF0, ADC_0, adcPosSelAPORT1XCH16}, + {PF1, ADC_0, adcPosSelAPORT2XCH17}, + {PF2, ADC_0, adcPosSelAPORT1XCH18}, + {PF3, ADC_0, adcPosSelAPORT2XCH19}, + {PF4, ADC_0, adcPosSelAPORT1XCH20}, + {PF5, ADC_0, adcPosSelAPORT2XCH21}, + {PF6, ADC_0, adcPosSelAPORT1XCH22}, + {PF7, ADC_0, adcPosSelAPORT2XCH23}, + {NC , NC , NC} +}; + +/************I2C SCL***********/ +const PinMap PinMap_I2C_SCL[] = { + /* I2C0 */ + {PA1, I2C_0, 0}, + {PA2, I2C_0, 1}, + {PA3, I2C_0, 2}, + {PA4, I2C_0, 3}, + {PA5, I2C_0, 4}, + {PB11, I2C_0, 5}, + {PB12, I2C_0, 6}, + {PB13, I2C_0, 7}, + {PB14, I2C_0, 8}, + {PB15, I2C_0, 9}, + {PC6, I2C_0, 10}, + {PC7, I2C_0, 11}, + {PC8, I2C_0, 12}, + {PC9, I2C_0, 13}, + {PC10, I2C_0, 14}, + {PC11, I2C_0, 15}, + {PD9, I2C_0, 16}, + {PD10, I2C_0, 17}, + {PD11, I2C_0, 18}, + {PD12, I2C_0, 19}, + {PD13, I2C_0, 20}, + {PD14, I2C_0, 21}, + {PD15, I2C_0, 22}, + {PF0, I2C_0, 23}, + {PF1, I2C_0, 24}, + {PF2, I2C_0, 25}, + {PF3, I2C_0, 26}, + {PF4, I2C_0, 27}, + {PF5, I2C_0, 28}, + {PF6, I2C_0, 29}, + {PF7, I2C_0, 30}, + {PA0, I2C_0, 31}, + + {NC , NC , NC} +}; + +/************I2C SDA***********/ +const PinMap PinMap_I2C_SDA[] = { + /* I2C0 */ + {PA0, I2C_0, 0}, + {PA1, I2C_0, 1}, + {PA2, I2C_0, 2}, + {PA3, I2C_0, 3}, + {PA4, I2C_0, 4}, + {PA5, I2C_0, 5}, + {PB11, I2C_0, 6}, + {PB12, I2C_0, 7}, + {PB13, I2C_0, 8}, + {PB14, I2C_0, 9}, + {PB15, I2C_0, 10}, + {PC6, I2C_0, 11}, + {PC7, I2C_0, 12}, + {PC8, I2C_0, 13}, + {PC9, I2C_0, 14}, + {PC10, I2C_0, 15}, + {PC11, I2C_0, 16}, + {PD9, I2C_0, 17}, + {PD10, I2C_0, 18}, + {PD11, I2C_0, 19}, + {PD12, I2C_0, 20}, + {PD13, I2C_0, 21}, + {PD14, I2C_0, 22}, + {PD15, I2C_0, 23}, + {PF0, I2C_0, 24}, + {PF1, I2C_0, 25}, + {PF2, I2C_0, 26}, + {PF3, I2C_0, 27}, + {PF4, I2C_0, 28}, + {PF5, I2C_0, 29}, + {PF6, I2C_0, 30}, + {PF7, I2C_0, 31}, + + /* Not connected */ + {NC , NC , NC} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PA0, PWM_CH0, 0}, + {PA1, PWM_CH1, 0}, + {PA2, PWM_CH2, 0}, + {PA3, PWM_CH3, 0}, + {PA4, PWM_CH2, 2}, + {PA5, PWM_CH3, 2}, + {PB11, PWM_CH1, 5}, + {PB12, PWM_CH2, 5}, + {PB13, PWM_CH3, 5}, + {PB14, PWM_CH0, 9}, + {PB15, PWM_CH0, 10}, + {PC6, PWM_CH0, 11}, + {PC7, PWM_CH1, 11}, + {PC8, PWM_CH2, 11}, + {PC9, PWM_CH3, 11}, + {PC10, PWM_CH2, 13}, + {PC11, PWM_CH3, 13}, + {PD9, PWM_CH3, 14}, + {PD10, PWM_CH0, 18}, + {PD11, PWM_CH1, 18}, + {PD12, PWM_CH2, 18}, + {PD13, PWM_CH3, 18}, + {PD14, PWM_CH0, 22}, + {PD15, PWM_CH1, 22}, + {PF0, PWM_CH0, 24}, + {PF1, PWM_CH1, 24}, + {PF2, PWM_CH2, 24}, + {PF3, PWM_CH3, 24}, + {PF4, PWM_CH0, 28}, + {PF5, PWM_CH1, 28}, + {PF6, PWM_CH2, 28}, + {PF7, PWM_CH3, 28}, + + {NC , NC , NC} +}; + +/*************SPI**************/ +const PinMap PinMap_SPI_MOSI[] = { + + /* USART0 */ + {PA0, SPI_0, 0}, + {PA1, SPI_0, 1}, + {PA2, SPI_0, 2}, + {PA3, SPI_0, 3}, + {PA4, SPI_0, 4}, + {PA5, SPI_0, 5}, + {PB11, SPI_0, 6}, + {PB12, SPI_0, 7}, + {PB13, SPI_0, 8}, + {PB14, SPI_0, 9}, + {PB15, SPI_0, 10}, + {PD9, SPI_0, 17}, + {PD10, SPI_0, 18}, + {PD11, SPI_0, 19}, + {PD12, SPI_0, 20}, + {PD13, SPI_0, 21}, + {PD14, SPI_0, 22}, + {PD15, SPI_0, 23}, + + /* USART1 */ + {PC6, SPI_1, 11}, + {PC7, SPI_1, 12}, + {PC8, SPI_1, 13}, + {PC9, SPI_1, 14}, + {PC10, SPI_1, 15}, + {PC11, SPI_1, 16}, + {PF0, SPI_1, 24}, + {PF1, SPI_1, 25}, + {PF2, SPI_1, 26}, + {PF3, SPI_1, 27}, + {PF4, SPI_1, 28}, + {PF5, SPI_1, 29}, + {PF6, SPI_1, 30}, + {PF7, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_MISO[] = { + + /* USART0 */ + {PA0, SPI_0, 31}, + {PA1, SPI_0, 0}, + {PA2, SPI_0, 1}, + {PA3, SPI_0, 2}, + {PA4, SPI_0, 3}, + {PA5, SPI_0, 4}, + {PB11, SPI_0, 5}, + {PB12, SPI_0, 6}, + {PB13, SPI_0, 7}, + {PB14, SPI_0, 8}, + {PB15, SPI_0, 9}, + {PD9, SPI_0, 16}, + {PD10, SPI_0, 17}, + {PD11, SPI_0, 18}, + {PD12, SPI_0, 19}, + {PD13, SPI_0, 20}, + {PD14, SPI_0, 21}, + {PD15, SPI_0, 22}, + + /* USART1 */ + {PC6, SPI_1, 10}, + {PC7, SPI_1, 11}, + {PC8, SPI_1, 12}, + {PC9, SPI_1, 13}, + {PC10, SPI_1, 14}, + {PC11, SPI_1, 15}, + {PF0, SPI_1, 23}, + {PF1, SPI_1, 24}, + {PF2, SPI_1, 25}, + {PF3, SPI_1, 26}, + {PF4, SPI_1, 27}, + {PF5, SPI_1, 28}, + {PF6, SPI_1, 29}, + {PF7, SPI_1, 30}, + {PA0, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_CLK[] = { + + /* USART0 */ + {PA0, SPI_0, 30}, + {PA1, SPI_0, 31}, + {PA2, SPI_0, 0}, + {PA3, SPI_0, 1}, + {PA4, SPI_0, 2}, + {PA5, SPI_0, 3}, + {PB11, SPI_0, 4}, + {PB12, SPI_0, 5}, + {PB13, SPI_0, 6}, + {PB14, SPI_0, 7}, + {PB15, SPI_0, 8}, + {PD9, SPI_0, 15}, + {PD10, SPI_0, 16}, + {PD11, SPI_0, 17}, + {PD12, SPI_0, 18}, + {PD13, SPI_0, 19}, + {PD14, SPI_0, 20}, + {PD15, SPI_0, 21}, + + /* USART1 */ + {PC6, SPI_1, 9}, + {PC7, SPI_1, 10}, + {PC8, SPI_1, 11}, + {PC9, SPI_1, 12}, + {PC10, SPI_1, 13}, + {PC11, SPI_1, 14}, + {PF0, SPI_1, 22}, + {PF1, SPI_1, 23}, + {PF2, SPI_1, 24}, + {PF3, SPI_1, 25}, + {PF4, SPI_1, 26}, + {PF5, SPI_1, 27}, + {PF6, SPI_1, 28}, + {PF7, SPI_1, 29}, + {PA0, SPI_1, 30}, + {PA1, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_CS[] = { + + /* USART0 */ + {PA0, SPI_0, 29}, + {PA1, SPI_0, 30}, + {PA2, SPI_0, 31}, + {PA3, SPI_0, 0}, + {PA4, SPI_0, 1}, + {PA5, SPI_0, 2}, + {PB11, SPI_0, 3}, + {PB12, SPI_0, 4}, + {PB13, SPI_0, 5}, + {PB14, SPI_0, 6}, + {PB15, SPI_0, 7}, + {PD9, SPI_0, 14}, + {PD10, SPI_0, 15}, + {PD11, SPI_0, 16}, + {PD12, SPI_0, 17}, + {PD13, SPI_0, 18}, + {PD14, SPI_0, 19}, + {PD15, SPI_0, 20}, + + /* USART1 */ + {PC6, SPI_1, 8}, + {PC7, SPI_1, 9}, + {PC8, SPI_1, 10}, + {PC9, SPI_1, 11}, + {PC10, SPI_1, 12}, + {PC11, SPI_1, 13}, + {PF0, SPI_1, 21}, + {PF1, SPI_1, 22}, + {PF2, SPI_1, 23}, + {PF3, SPI_1, 24}, + {PF4, SPI_1, 25}, + {PF5, SPI_1, 26}, + {PF6, SPI_1, 27}, + {PF7, SPI_1, 28}, + + {NC , NC , NC} +}; + +/************UART**************/ +const PinMap PinMap_UART_TX[] = { + {PA0, USART_0, 0}, + {PA1, USART_0, 1}, + {PA2, USART_0, 2}, + {PA3, USART_0, 3}, + {PA4, USART_0, 4}, + {PA5, USART_0, 5}, + {PB11, USART_0, 6}, + {PB12, USART_0, 7}, + {PB13, USART_0, 8}, + {PB14, USART_0, 9}, + {PB15, USART_0, 10}, + {PD9, LEUART_0, 17}, + {PD10, LEUART_0, 18}, + {PD11, LEUART_0, 19}, + {PD12, LEUART_0, 20}, + {PD13, LEUART_0, 21}, + {PD14, LEUART_0, 22}, + {PD15, LEUART_0, 23}, + + {PC6, USART_1, 11}, + {PC7, USART_1, 12}, + {PC8, USART_1, 13}, + {PC9, USART_1, 14}, + {PC10, USART_1, 15}, + {PC11, USART_1, 16}, + {PF0, USART_1, 24}, + {PF1, USART_1, 25}, + {PF2, USART_1, 26}, + {PF3, USART_1, 27}, + {PF4, USART_1, 28}, + {PF5, USART_1, 29}, + {PF6, USART_1, 30}, + {PF7, USART_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_UART_RX[] = { + {PA0, USART_0, 31}, + {PA1, USART_0, 0}, + {PA2, USART_0, 1}, + {PA3, USART_0, 2}, + {PA4, USART_0, 3}, + {PA5, USART_0, 4}, + {PB11, USART_0, 5}, + {PB12, USART_0, 6}, + {PB13, USART_0, 7}, + {PB14, USART_0, 8}, + {PB15, USART_0, 9}, + {PD9, LEUART_0, 16}, + {PD10, LEUART_0, 17}, + {PD11, LEUART_0, 18}, + {PD12, LEUART_0, 19}, + {PD13, LEUART_0, 20}, + {PD14, LEUART_0, 21}, + {PD15, LEUART_0, 22}, + + {PC6, USART_1, 10}, + {PC7, USART_1, 11}, + {PC8, USART_1, 12}, + {PC9, USART_1, 13}, + {PC10, USART_1, 14}, + {PC11, USART_1, 15}, + {PF0, USART_1, 23}, + {PF1, USART_1, 24}, + {PF2, USART_1, 25}, + {PF3, USART_1, 26}, + {PF4, USART_1, 27}, + {PF5, USART_1, 28}, + {PF6, USART_1, 29}, + {PF7, USART_1, 30}, + + {NC , NC , NC} +}; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.h new file mode 100644 index 00000000000..79d6072e833 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file PeripheralPins.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************I2C SCL***********/ +extern const PinMap PinMap_I2C_SCL[]; + +/************I2C SDA***********/ +extern const PinMap PinMap_I2C_SDA[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_CLK[]; +extern const PinMap PinMap_SPI_CS[]; + +/************UART**************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +#endif + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/PinNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/PinNames.h new file mode 100644 index 00000000000..8840ceb9dbd --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/PinNames.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file PinNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "CommonPinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + EFM32_STANDARD_PIN_DEFINITIONS, + + /* Starter Kit says LED0 and LED1, but mbed expects 1 and 2. This way using 1 and 2 or 0 and 1 will work. */ + LED0 = PF4, + LED1 = PF5, + LED2 = LED0, + LED3 = LED0, + LED4 = LED1, + + /* Push Buttons */ + SW0 = PF6, + SW1 = PF7, + BTN0 = SW0, + BTN1 = SW1, + + /* Expansion headers */ + EXP3 = PA8, + EXP4 = PC6, + EXP5 = PA9, + EXP6 = PC7, + EXP7 = PF3, + EXP8 = PC8, + EXP9 = PF4, + EXP10 = PC9, + EXP11 = PF5, + EXP12 = PA6, + EXP13 = PF6, + EXP14 = PA7, + EXP15 = PC11, + EXP16 = PC10, + + /* Serial (just some usable pins) */ + SERIAL_TX = PA6, + SERIAL_RX = PA7, + + /* Board Controller UART (USB)*/ + USBTX = PA0, + USBRX = PA1, + + /* Board Controller */ + STDIO_UART_TX = USBTX, + STDIO_UART_RX = USBRX +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h new file mode 100644 index 00000000000..d9cd0fef8a3 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file device_peripherals.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_DEVICE_PERIPHERALS_H +#define MBED_DEVICE_PERIPHERALS_H + +/* us ticker */ +#define US_TICKER_TIMER TIMER0 +#define US_TICKER_TIMER_CLOCK cmuClock_TIMER0 +#define US_TICKER_TIMER_IRQ TIMER0_IRQn + +/* PWM */ +#define PWM_TIMER TIMER1 +#define PWM_TIMER_CLOCK cmuClock_TIMER1 +#define PWM_ROUTE TIMER_ROUTE_LOCATION_LOC1 + +/* Crystal calibration */ +#if !defined(CMU_HFXOINIT_STK_DEFAULT) +#define CMU_HFXOINIT_STK_DEFAULT \ +{ \ + true, /* Low-power mode for EFM32 */ \ + false, /* Disable auto-start on EM0/1 entry */ \ + false, /* Disable auto-select on EM0/1 entry */ \ + false, /* Disable auto-start and select on RAC wakeup */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + 0x142, /* Steady-state CTUNE for STK boards without load caps */ \ + _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ + 0x20, /* Matching errata fix in CHIP_Init() */ \ + 0x7, /* Recommended steady-state osc core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \ + 0xA, /* Recommended peak detection timeout */ \ + 0x4, /* Recommended steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ +} +#endif +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct new file mode 100644 index 00000000000..19a1e790859 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00100000 { ; load region size_region + ER_IROM1 0x00000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x2000010C 0x0003FEF4 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s new file mode 100644 index 00000000000..5405f7cc8e2 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s @@ -0,0 +1,306 @@ +;/**************************************************************************//** +; * @file startup_efm32pg12b.s +; * @brief CMSIS Core Device Startup File for +; * Silicon Labs EFM32PG12B Device Series +; * @version 5.1.2 +; * @date 03. February 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF: __STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00001000 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF: __HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00004000 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY, ALIGN=8 + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD 0 ; 1: Reserved + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD 0 ; 4: Reserved + DCD 0 ; 5: Reserved + DCD 0 ; 6: Reserved + DCD 0 ; 7: Reserved + DCD 0 ; 8: Reserved + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD 0 ; 28: Reserved + DCD 0 ; 29: Reserved + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD 0 ; 31: Reserved + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD 0 ; 33: Reserved + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved + +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT EMU_IRQHandler [WEAK] + EXPORT WDOG0_IRQHandler [WEAK] + EXPORT WDOG1_IRQHandler [WEAK] + EXPORT LDMA_IRQHandler [WEAK] + EXPORT GPIO_EVEN_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT USART0_RX_IRQHandler [WEAK] + EXPORT USART0_TX_IRQHandler [WEAK] + EXPORT ACMP0_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT IDAC0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT GPIO_ODD_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT USART1_RX_IRQHandler [WEAK] + EXPORT USART1_TX_IRQHandler [WEAK] + EXPORT LEUART0_IRQHandler [WEAK] + EXPORT PCNT0_IRQHandler [WEAK] + EXPORT CMU_IRQHandler [WEAK] + EXPORT MSC_IRQHandler [WEAK] + EXPORT CRYPTO0_IRQHandler [WEAK] + EXPORT LETIMER0_IRQHandler [WEAK] + EXPORT RTCC_IRQHandler [WEAK] + EXPORT CRYOTIMER_IRQHandler [WEAK] + EXPORT FPUEH_IRQHandler [WEAK] + EXPORT SMU_IRQHandler [WEAK] + EXPORT WTIMER0_IRQHandler [WEAK] + EXPORT WTIMER1_IRQHandler [WEAK] + EXPORT PCNT1_IRQHandler [WEAK] + EXPORT PCNT2_IRQHandler [WEAK] + EXPORT USART2_RX_IRQHandler [WEAK] + EXPORT USART2_TX_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT USART3_RX_IRQHandler [WEAK] + EXPORT USART3_TX_IRQHandler [WEAK] + EXPORT VDAC0_IRQHandler [WEAK] + EXPORT CSEN_IRQHandler [WEAK] + EXPORT LESENSE_IRQHandler [WEAK] + EXPORT CRYPTO1_IRQHandler [WEAK] + EXPORT TRNG0_IRQHandler [WEAK] + + +EMU_IRQHandler +WDOG0_IRQHandler +WDOG1_IRQHandler +LDMA_IRQHandler +GPIO_EVEN_IRQHandler +TIMER0_IRQHandler +USART0_RX_IRQHandler +USART0_TX_IRQHandler +ACMP0_IRQHandler +ADC0_IRQHandler +IDAC0_IRQHandler +I2C0_IRQHandler +GPIO_ODD_IRQHandler +TIMER1_IRQHandler +USART1_RX_IRQHandler +USART1_TX_IRQHandler +LEUART0_IRQHandler +PCNT0_IRQHandler +CMU_IRQHandler +MSC_IRQHandler +CRYPTO0_IRQHandler +LETIMER0_IRQHandler +RTCC_IRQHandler +CRYOTIMER_IRQHandler +FPUEH_IRQHandler +SMU_IRQHandler +WTIMER0_IRQHandler +WTIMER1_IRQHandler +PCNT1_IRQHandler +PCNT2_IRQHandler +USART2_RX_IRQHandler +USART2_TX_IRQHandler +I2C1_IRQHandler +USART3_RX_IRQHandler +USART3_TX_IRQHandler +VDAC0_IRQHandler +CSEN_IRQHandler +LESENSE_IRQHandler +CRYPTO1_IRQHandler +TRNG0_IRQHandler + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld new file mode 100644 index 00000000000..43cea812793 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld @@ -0,0 +1,215 @@ +/* Linker script for Silicon Labs EFM32PG12B devices */ +/* */ +/* This file is subject to the license terms as defined in ARM's */ +/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of */ +/* Example Code. */ +/* */ +/* Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com */ +/* */ +/* Version 5.1.2 */ +/* */ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 262144 +} + +/* MBED: mbed needs to be able to dynamically set the interrupt vector table. + * We make room for the table at the very beginning of RAM, i.e. at + * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 bytes for EFM32PG */ +__vector_size = 0x10C; + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + PROVIDE( __start_vector_table__ = .); + . += __vector_size; + PROVIDE( __end_vector_table__ = .); + *(vtable) + *(.data*) + . = ALIGN (4); + *(.ram) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if FLASH usage exceeds FLASH size */ + ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") +} diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S new file mode 100644 index 00000000000..0f5b748e1de --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S @@ -0,0 +1,350 @@ +/* @file startup_efm32pg12b.S + * @brief startup file for Silicon Labs EFM32PG12B devices. + * For use with GCC for ARM Embedded Processors + * @version 5.1.2 + * Date: 12 June 2014 + * + */ +/* Copyright (c) 2011 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + .syntax unified + .arch armv7-m + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00004000 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long Default_Handler /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long EMU_IRQHandler /* 0 - EMU */ + .long Default_Handler /* 1 - Reserved */ + .long WDOG0_IRQHandler /* 2 - WDOG0 */ + .long WDOG1_IRQHandler /* 3 - WDOG1 */ + .long Default_Handler /* 4 - Reserved */ + .long Default_Handler /* 5 - Reserved */ + .long Default_Handler /* 6 - Reserved */ + .long Default_Handler /* 7 - Reserved */ + .long Default_Handler /* 8 - Reserved */ + .long LDMA_IRQHandler /* 9 - LDMA */ + .long GPIO_EVEN_IRQHandler /* 10 - GPIO_EVEN */ + .long TIMER0_IRQHandler /* 11 - TIMER0 */ + .long USART0_RX_IRQHandler /* 12 - USART0_RX */ + .long USART0_TX_IRQHandler /* 13 - USART0_TX */ + .long ACMP0_IRQHandler /* 14 - ACMP0 */ + .long ADC0_IRQHandler /* 15 - ADC0 */ + .long IDAC0_IRQHandler /* 16 - IDAC0 */ + .long I2C0_IRQHandler /* 17 - I2C0 */ + .long GPIO_ODD_IRQHandler /* 18 - GPIO_ODD */ + .long TIMER1_IRQHandler /* 19 - TIMER1 */ + .long USART1_RX_IRQHandler /* 20 - USART1_RX */ + .long USART1_TX_IRQHandler /* 21 - USART1_TX */ + .long LEUART0_IRQHandler /* 22 - LEUART0 */ + .long PCNT0_IRQHandler /* 23 - PCNT0 */ + .long CMU_IRQHandler /* 24 - CMU */ + .long MSC_IRQHandler /* 25 - MSC */ + .long CRYPTO0_IRQHandler /* 26 - CRYPTO0 */ + .long LETIMER0_IRQHandler /* 27 - LETIMER0 */ + .long Default_Handler /* 28 - Reserved */ + .long Default_Handler /* 29 - Reserved */ + .long RTCC_IRQHandler /* 30 - RTCC */ + .long Default_Handler /* 31 - Reserved */ + .long CRYOTIMER_IRQHandler /* 32 - CRYOTIMER */ + .long Default_Handler /* 33 - Reserved */ + .long FPUEH_IRQHandler /* 34 - FPUEH */ + .long SMU_IRQHandler /* 35 - SMU */ + .long WTIMER0_IRQHandler /* 36 - WTIMER0 */ + .long WTIMER1_IRQHandler /* 37 - WTIMER1 */ + .long PCNT1_IRQHandler /* 38 - PCNT1 */ + .long PCNT2_IRQHandler /* 39 - PCNT2 */ + .long USART2_RX_IRQHandler /* 40 - USART2_RX */ + .long USART2_TX_IRQHandler /* 41 - USART2_TX */ + .long I2C1_IRQHandler /* 42 - I2C1 */ + .long USART3_RX_IRQHandler /* 43 - USART3_RX */ + .long USART3_TX_IRQHandler /* 44 - USART3_TX */ + .long VDAC0_IRQHandler /* 45 - VDAC0 */ + .long CSEN_IRQHandler /* 46 - CSEN */ + .long LESENSE_IRQHandler /* 47 - LESENSE */ + .long CRYPTO1_IRQHandler /* 48 - CRYPTO1 */ + .long TRNG0_IRQHandler /* 49 - TRNG0 */ + .long Default_Handler /* 50 - Reserved */ + + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +#ifndef __NO_SYSTEM_INIT + ldr r0, =SystemInit + blx r0 +#endif + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __zero_table_start__ and __zero_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + + def_irq_handler EMU_IRQHandler + def_irq_handler WDOG0_IRQHandler + def_irq_handler WDOG1_IRQHandler + def_irq_handler LDMA_IRQHandler + def_irq_handler GPIO_EVEN_IRQHandler + def_irq_handler TIMER0_IRQHandler + def_irq_handler USART0_RX_IRQHandler + def_irq_handler USART0_TX_IRQHandler + def_irq_handler ACMP0_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler IDAC0_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler GPIO_ODD_IRQHandler + def_irq_handler TIMER1_IRQHandler + def_irq_handler USART1_RX_IRQHandler + def_irq_handler USART1_TX_IRQHandler + def_irq_handler LEUART0_IRQHandler + def_irq_handler PCNT0_IRQHandler + def_irq_handler CMU_IRQHandler + def_irq_handler MSC_IRQHandler + def_irq_handler CRYPTO0_IRQHandler + def_irq_handler LETIMER0_IRQHandler + def_irq_handler RTCC_IRQHandler + def_irq_handler CRYOTIMER_IRQHandler + def_irq_handler FPUEH_IRQHandler + def_irq_handler SMU_IRQHandler + def_irq_handler WTIMER0_IRQHandler + def_irq_handler WTIMER1_IRQHandler + def_irq_handler PCNT1_IRQHandler + def_irq_handler PCNT2_IRQHandler + def_irq_handler USART2_RX_IRQHandler + def_irq_handler USART2_TX_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler USART3_RX_IRQHandler + def_irq_handler USART3_TX_IRQHandler + def_irq_handler VDAC0_IRQHandler + def_irq_handler CSEN_IRQHandler + def_irq_handler LESENSE_IRQHandler + def_irq_handler CRYPTO1_IRQHandler + def_irq_handler TRNG0_IRQHandler + + .end diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf new file mode 100644 index 00000000000..ed9fa118f62 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf @@ -0,0 +1,42 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/* Version 5.1.1 */ + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = (0x00000000+0x00100000-1); +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x2000010B; +define symbol __ICFEDIT_region_RAM_start__ = 0x2000010C; +define symbol __ICFEDIT_region_RAM_end__ = (0x20000000+0x00040000-1); + +/*-Sizes-*/ +if ( !isdefinedsymbol( __ICFEDIT_size_cstack__ ) ) +{ define symbol __ICFEDIT_size_cstack__ = 0x1000; } + +if ( !isdefinedsymbol( __ICFEDIT_size_heap__ ) ) +{ define symbol __ICFEDIT_size_heap__ = 0x4000; } + +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, + block HEAP }; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s new file mode 100644 index 00000000000..7a10da7f800 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s @@ -0,0 +1,401 @@ +;/**************************************************************************//** +; * @file startup_efm32pg12b.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32PG12B Device Series +; * @version 5.1.2 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD 0 ; 1: Reserved Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD 0 ; 4: Reserved Interrupt + DCD 0 ; 5: Reserved Interrupt + DCD 0 ; 6: Reserved Interrupt + DCD 0 ; 7: Reserved Interrupt + DCD 0 ; 8: Reserved Interrupt + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD 0 ; 28: Reserved Interrupt + DCD 0 ; 29: Reserved Interrupt + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD 0 ; 31: Reserved Interrupt + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD 0 ; 33: Reserved Interrupt + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved Interrupt + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK WDOG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG0_IRQHandler + B WDOG0_IRQHandler + + PUBWEAK WDOG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG1_IRQHandler + B WDOG1_IRQHandler + + PUBWEAK LDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LDMA_IRQHandler + B LDMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK IDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IDAC0_IRQHandler + B IDAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK CRYPTO0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO0_IRQHandler + B CRYPTO0_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK RTCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCC_IRQHandler + B RTCC_IRQHandler + + PUBWEAK CRYOTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYOTIMER_IRQHandler + B CRYOTIMER_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + PUBWEAK SMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SMU_IRQHandler + B SMU_IRQHandler + + PUBWEAK WTIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER0_IRQHandler + B WTIMER0_IRQHandler + + PUBWEAK WTIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER1_IRQHandler + B WTIMER1_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK USART3_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_RX_IRQHandler + B USART3_RX_IRQHandler + + PUBWEAK USART3_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_TX_IRQHandler + B USART3_TX_IRQHandler + + PUBWEAK VDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VDAC0_IRQHandler + B VDAC0_IRQHandler + + PUBWEAK CSEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CSEN_IRQHandler + B CSEN_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK CRYPTO1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO1_IRQHandler + B CRYPTO1_IRQHandler + + PUBWEAK TRNG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TRNG0_IRQHandler + B TRNG0_IRQHandler + + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024gl125.h new file mode 100644 index 00000000000..d319a858557 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024gl125.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F1024GL125 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F1024GL125_H +#define EFM32PG12B500F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125 EFM32PG12B500F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Core EFM32PG12B500F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F1024GL125_Part EFM32PG12B500F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F1024GL125) +#define EFM32PG12B500F1024GL125 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Peripheral_TypeDefs EFM32PG12B500F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Peripheral_Base EFM32PG12B500F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Peripheral_Declaration EFM32PG12B500F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Peripheral_Offsets EFM32PG12B500F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_BitFields EFM32PG12B500F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_WTIMER_BitFields EFM32PG12B500F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_SYSTICK_BitFields EFM32PG12B500F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_UNLOCK EFM32PG12B500F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F1024GL125_UNLOCK */ + +/** @} End of group EFM32PG12B500F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Alternate_Function EFM32PG12B500F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F1024GL125_Alternate_Function */ + +/** @} End of group EFM32PG12B500F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024gm48.h new file mode 100644 index 00000000000..ebaeb37b560 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024gm48.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F1024GM48 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F1024GM48_H +#define EFM32PG12B500F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48 EFM32PG12B500F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Core EFM32PG12B500F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F1024GM48_Part EFM32PG12B500F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F1024GM48) +#define EFM32PG12B500F1024GM48 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Peripheral_TypeDefs EFM32PG12B500F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Peripheral_Base EFM32PG12B500F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Peripheral_Declaration EFM32PG12B500F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Peripheral_Offsets EFM32PG12B500F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_BitFields EFM32PG12B500F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_WTIMER_BitFields EFM32PG12B500F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_SYSTICK_BitFields EFM32PG12B500F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_UNLOCK EFM32PG12B500F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F1024GM48_UNLOCK */ + +/** @} End of group EFM32PG12B500F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Alternate_Function EFM32PG12B500F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F1024GM48_Alternate_Function */ + +/** @} End of group EFM32PG12B500F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024il125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024il125.h new file mode 100644 index 00000000000..e10fd5e3fcd --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024il125.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f1024il125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F1024IL125 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F1024IL125_H +#define EFM32PG12B500F1024IL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125 EFM32PG12B500F1024IL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Core EFM32PG12B500F1024IL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F1024IL125_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F1024IL125_Part EFM32PG12B500F1024IL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F1024IL125) +#define EFM32PG12B500F1024IL125 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F1024IL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F1024IL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F1024IL125_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Peripheral_TypeDefs EFM32PG12B500F1024IL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F1024IL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Peripheral_Base EFM32PG12B500F1024IL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F1024IL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Peripheral_Declaration EFM32PG12B500F1024IL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F1024IL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Peripheral_Offsets EFM32PG12B500F1024IL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F1024IL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_BitFields EFM32PG12B500F1024IL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_WTIMER_BitFields EFM32PG12B500F1024IL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F1024IL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_SYSTICK_BitFields EFM32PG12B500F1024IL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F1024IL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_UNLOCK EFM32PG12B500F1024IL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F1024IL125_UNLOCK */ + +/** @} End of group EFM32PG12B500F1024IL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Alternate_Function EFM32PG12B500F1024IL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F1024IL125_Alternate_Function */ + +/** @} End of group EFM32PG12B500F1024IL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F1024IL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024im48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024im48.h new file mode 100644 index 00000000000..03d8ba59e1a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024im48.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f1024im48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F1024IM48 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F1024IM48_H +#define EFM32PG12B500F1024IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48 EFM32PG12B500F1024IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Core EFM32PG12B500F1024IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F1024IM48_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F1024IM48_Part EFM32PG12B500F1024IM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F1024IM48) +#define EFM32PG12B500F1024IM48 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F1024IM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F1024IM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F1024IM48_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Peripheral_TypeDefs EFM32PG12B500F1024IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F1024IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Peripheral_Base EFM32PG12B500F1024IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F1024IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Peripheral_Declaration EFM32PG12B500F1024IM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F1024IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Peripheral_Offsets EFM32PG12B500F1024IM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F1024IM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_BitFields EFM32PG12B500F1024IM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_WTIMER_BitFields EFM32PG12B500F1024IM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F1024IM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_SYSTICK_BitFields EFM32PG12B500F1024IM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F1024IM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_UNLOCK EFM32PG12B500F1024IM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F1024IM48_UNLOCK */ + +/** @} End of group EFM32PG12B500F1024IM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Alternate_Function EFM32PG12B500F1024IM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F1024IM48_Alternate_Function */ + +/** @} End of group EFM32PG12B500F1024IM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F1024IM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f512gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f512gl125.h new file mode 100644 index 00000000000..bad099c847e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f512gl125.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f512gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F512GL125 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F512GL125_H +#define EFM32PG12B500F512GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125 EFM32PG12B500F512GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Core EFM32PG12B500F512GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F512GL125_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F512GL125_Part EFM32PG12B500F512GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F512GL125) +#define EFM32PG12B500F512GL125 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F512GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F512GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F512GL125_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Peripheral_TypeDefs EFM32PG12B500F512GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F512GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Peripheral_Base EFM32PG12B500F512GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F512GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Peripheral_Declaration EFM32PG12B500F512GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F512GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Peripheral_Offsets EFM32PG12B500F512GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F512GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_BitFields EFM32PG12B500F512GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_WTIMER_BitFields EFM32PG12B500F512GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F512GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_SYSTICK_BitFields EFM32PG12B500F512GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F512GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_UNLOCK EFM32PG12B500F512GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F512GL125_UNLOCK */ + +/** @} End of group EFM32PG12B500F512GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Alternate_Function EFM32PG12B500F512GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F512GL125_Alternate_Function */ + +/** @} End of group EFM32PG12B500F512GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F512GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f512gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f512gm48.h new file mode 100644 index 00000000000..3d2789f77f4 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f512gm48.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f512gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F512GM48 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F512GM48_H +#define EFM32PG12B500F512GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48 EFM32PG12B500F512GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Core EFM32PG12B500F512GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F512GM48_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F512GM48_Part EFM32PG12B500F512GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F512GM48) +#define EFM32PG12B500F512GM48 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F512GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F512GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F512GM48_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Peripheral_TypeDefs EFM32PG12B500F512GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F512GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Peripheral_Base EFM32PG12B500F512GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F512GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Peripheral_Declaration EFM32PG12B500F512GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F512GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Peripheral_Offsets EFM32PG12B500F512GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F512GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_BitFields EFM32PG12B500F512GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_WTIMER_BitFields EFM32PG12B500F512GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F512GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_SYSTICK_BitFields EFM32PG12B500F512GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F512GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_UNLOCK EFM32PG12B500F512GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F512GM48_UNLOCK */ + +/** @} End of group EFM32PG12B500F512GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Alternate_Function EFM32PG12B500F512GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F512GM48_Alternate_Function */ + +/** @} End of group EFM32PG12B500F512GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F512GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_acmp.h new file mode 100644 index 00000000000..42353250e5d --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_acmp.h @@ -0,0 +1,1420 @@ +/**************************************************************************//** + * @file efm32pg12b_acmp.h + * @brief EFM32PG12B_ACMP register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_ACMP + * @{ + * @brief EFM32PG12B_ACMP Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTSEL; /**< Input Selection Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ + __IOM uint32_t HYSTERESIS0; /**< Hysteresis 0 Register */ + __IOM uint32_t HYSTERESIS1; /**< Hysteresis 1 Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pine Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t EXTIFCTRL; /**< External override interface control */ +} ACMP_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_ACMP_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x07000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0xBF3CF70DUL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */ +#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */ +#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */ +#define ACMP_CTRL_APORTXMASTERDIS (0x1UL << 8) /**< APORT Bus X Master Disable */ +#define _ACMP_CTRL_APORTXMASTERDIS_SHIFT 8 /**< Shift value for ACMP_APORTXMASTERDIS */ +#define _ACMP_CTRL_APORTXMASTERDIS_MASK 0x100UL /**< Bit mask for ACMP_APORTXMASTERDIS */ +#define _ACMP_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTXMASTERDIS_DEFAULT (_ACMP_CTRL_APORTXMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTYMASTERDIS (0x1UL << 9) /**< APORT Bus Y Master Disable */ +#define _ACMP_CTRL_APORTYMASTERDIS_SHIFT 9 /**< Shift value for ACMP_APORTYMASTERDIS */ +#define _ACMP_CTRL_APORTYMASTERDIS_MASK 0x200UL /**< Bit mask for ACMP_APORTYMASTERDIS */ +#define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTYMASTERDIS_DEFAULT (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus selected by VASEL */ +#define _ACMP_CTRL_APORTVMASTERDIS_SHIFT 10 /**< Shift value for ACMP_APORTVMASTERDIS */ +#define _ACMP_CTRL_APORTVMASTERDIS_MASK 0x400UL /**< Bit mask for ACMP_APORTVMASTERDIS */ +#define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTVMASTERDIS_DEFAULT (_ACMP_CTRL_APORTVMASTERDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_SHIFT 12 /**< Shift value for ACMP_PWRSEL */ +#define _ACMP_CTRL_PWRSEL_MASK 0x7000UL /**< Bit mask for ACMP_PWRSEL */ +#define _ACMP_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_AVDD 0x00000000UL /**< Mode AVDD for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_VREGVDD 0x00000001UL /**< Mode VREGVDD for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_IOVDD0 0x00000002UL /**< Mode IOVDD0 for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_IOVDD1 0x00000004UL /**< Mode IOVDD1 for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_DEFAULT (_ACMP_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_AVDD (_ACMP_CTRL_PWRSEL_AVDD << 12) /**< Shifted mode AVDD for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_VREGVDD (_ACMP_CTRL_PWRSEL_VREGVDD << 12) /**< Shifted mode VREGVDD for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_IOVDD0 (_ACMP_CTRL_PWRSEL_IOVDD0 << 12) /**< Shifted mode IOVDD0 for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_IOVDD1 (_ACMP_CTRL_PWRSEL_IOVDD1 << 12) /**< Shifted mode IOVDD1 for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP accuracy mode */ +#define _ACMP_CTRL_ACCURACY_SHIFT 15 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CTRL_ACCURACY_MASK 0x8000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CTRL_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_DEFAULT (_ACMP_CTRL_ACCURACY_DEFAULT << 15) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_LOW (_ACMP_CTRL_ACCURACY_LOW << 15) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_HIGH (_ACMP_CTRL_ACCURACY_HIGH << 15) /**< Shifted mode HIGH for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_SHIFT 18 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CTRL_INPUTRANGE_MASK 0xC0000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CTRL_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_GTVDDDIV2 0x00000001UL /**< Mode GTVDDDIV2 for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 0x00000002UL /**< Mode LTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_DEFAULT (_ACMP_CTRL_INPUTRANGE_DEFAULT << 18) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_FULL (_ACMP_CTRL_INPUTRANGE_FULL << 18) /**< Shifted mode FULL for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_GTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_GTVDDDIV2 << 18) /**< Shifted mode GTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_LTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_LTVDDDIV2 << 18) /**< Shifted mode LTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_IRISE (0x1UL << 20) /**< Rising Edge Interrupt Sense */ +#define _ACMP_CTRL_IRISE_SHIFT 20 /**< Shift value for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_MASK 0x100000UL /**< Bit mask for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 20) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 20) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 20) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL (0x1UL << 21) /**< Falling Edge Interrupt Sense */ +#define _ACMP_CTRL_IFALL_SHIFT 21 /**< Shift value for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_MASK 0x200000UL /**< Bit mask for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 21) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 21) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 21) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_MASK 0x3F000000UL /**< Bit mask for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */ +#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTSEL */ +#define _ACMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_MASK 0x757FFFFFUL /**< Mask for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH0 (_ACMP_INPUTSEL_POSSEL_APORT0XCH0 << 0) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH1 (_ACMP_INPUTSEL_POSSEL_APORT0XCH1 << 0) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH2 (_ACMP_INPUTSEL_POSSEL_APORT0XCH2 << 0) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH3 (_ACMP_INPUTSEL_POSSEL_APORT0XCH3 << 0) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH4 (_ACMP_INPUTSEL_POSSEL_APORT0XCH4 << 0) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH5 (_ACMP_INPUTSEL_POSSEL_APORT0XCH5 << 0) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH6 (_ACMP_INPUTSEL_POSSEL_APORT0XCH6 << 0) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH7 (_ACMP_INPUTSEL_POSSEL_APORT0XCH7 << 0) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH8 (_ACMP_INPUTSEL_POSSEL_APORT0XCH8 << 0) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH9 (_ACMP_INPUTSEL_POSSEL_APORT0XCH9 << 0) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH10 (_ACMP_INPUTSEL_POSSEL_APORT0XCH10 << 0) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH11 (_ACMP_INPUTSEL_POSSEL_APORT0XCH11 << 0) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH12 (_ACMP_INPUTSEL_POSSEL_APORT0XCH12 << 0) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH13 (_ACMP_INPUTSEL_POSSEL_APORT0XCH13 << 0) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH14 (_ACMP_INPUTSEL_POSSEL_APORT0XCH14 << 0) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH15 (_ACMP_INPUTSEL_POSSEL_APORT0XCH15 << 0) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH0 (_ACMP_INPUTSEL_POSSEL_APORT0YCH0 << 0) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH1 (_ACMP_INPUTSEL_POSSEL_APORT0YCH1 << 0) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH2 (_ACMP_INPUTSEL_POSSEL_APORT0YCH2 << 0) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH3 (_ACMP_INPUTSEL_POSSEL_APORT0YCH3 << 0) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH4 (_ACMP_INPUTSEL_POSSEL_APORT0YCH4 << 0) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH5 (_ACMP_INPUTSEL_POSSEL_APORT0YCH5 << 0) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH6 (_ACMP_INPUTSEL_POSSEL_APORT0YCH6 << 0) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH7 (_ACMP_INPUTSEL_POSSEL_APORT0YCH7 << 0) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH8 (_ACMP_INPUTSEL_POSSEL_APORT0YCH8 << 0) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH9 (_ACMP_INPUTSEL_POSSEL_APORT0YCH9 << 0) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH10 (_ACMP_INPUTSEL_POSSEL_APORT0YCH10 << 0) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH11 (_ACMP_INPUTSEL_POSSEL_APORT0YCH11 << 0) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH12 (_ACMP_INPUTSEL_POSSEL_APORT0YCH12 << 0) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH13 (_ACMP_INPUTSEL_POSSEL_APORT0YCH13 << 0) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH14 (_ACMP_INPUTSEL_POSSEL_APORT0YCH14 << 0) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH15 (_ACMP_INPUTSEL_POSSEL_APORT0YCH15 << 0) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH0 (_ACMP_INPUTSEL_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH1 (_ACMP_INPUTSEL_POSSEL_APORT1YCH1 << 0) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH2 (_ACMP_INPUTSEL_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH3 (_ACMP_INPUTSEL_POSSEL_APORT1YCH3 << 0) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH4 (_ACMP_INPUTSEL_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH5 (_ACMP_INPUTSEL_POSSEL_APORT1YCH5 << 0) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH6 (_ACMP_INPUTSEL_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH7 (_ACMP_INPUTSEL_POSSEL_APORT1YCH7 << 0) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH8 (_ACMP_INPUTSEL_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH9 (_ACMP_INPUTSEL_POSSEL_APORT1YCH9 << 0) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH10 (_ACMP_INPUTSEL_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH11 (_ACMP_INPUTSEL_POSSEL_APORT1YCH11 << 0) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH12 (_ACMP_INPUTSEL_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH13 (_ACMP_INPUTSEL_POSSEL_APORT1YCH13 << 0) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH14 (_ACMP_INPUTSEL_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH15 (_ACMP_INPUTSEL_POSSEL_APORT1YCH15 << 0) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH16 (_ACMP_INPUTSEL_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH17 (_ACMP_INPUTSEL_POSSEL_APORT1YCH17 << 0) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH18 (_ACMP_INPUTSEL_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH19 (_ACMP_INPUTSEL_POSSEL_APORT1YCH19 << 0) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH20 (_ACMP_INPUTSEL_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH21 (_ACMP_INPUTSEL_POSSEL_APORT1YCH21 << 0) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH22 (_ACMP_INPUTSEL_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH23 (_ACMP_INPUTSEL_POSSEL_APORT1YCH23 << 0) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH24 (_ACMP_INPUTSEL_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH25 (_ACMP_INPUTSEL_POSSEL_APORT1YCH25 << 0) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH26 (_ACMP_INPUTSEL_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH27 (_ACMP_INPUTSEL_POSSEL_APORT1YCH27 << 0) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH28 (_ACMP_INPUTSEL_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH29 (_ACMP_INPUTSEL_POSSEL_APORT1YCH29 << 0) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH30 (_ACMP_INPUTSEL_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH31 (_ACMP_INPUTSEL_POSSEL_APORT1YCH31 << 0) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH0 (_ACMP_INPUTSEL_POSSEL_APORT2YCH0 << 0) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH1 (_ACMP_INPUTSEL_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH2 (_ACMP_INPUTSEL_POSSEL_APORT2YCH2 << 0) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH3 (_ACMP_INPUTSEL_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH4 (_ACMP_INPUTSEL_POSSEL_APORT2YCH4 << 0) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH5 (_ACMP_INPUTSEL_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH6 (_ACMP_INPUTSEL_POSSEL_APORT2YCH6 << 0) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH7 (_ACMP_INPUTSEL_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH8 (_ACMP_INPUTSEL_POSSEL_APORT2YCH8 << 0) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH9 (_ACMP_INPUTSEL_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH10 (_ACMP_INPUTSEL_POSSEL_APORT2YCH10 << 0) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH11 (_ACMP_INPUTSEL_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH12 (_ACMP_INPUTSEL_POSSEL_APORT2YCH12 << 0) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH13 (_ACMP_INPUTSEL_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH14 (_ACMP_INPUTSEL_POSSEL_APORT2YCH14 << 0) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH15 (_ACMP_INPUTSEL_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH16 (_ACMP_INPUTSEL_POSSEL_APORT2YCH16 << 0) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH17 (_ACMP_INPUTSEL_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH18 (_ACMP_INPUTSEL_POSSEL_APORT2YCH18 << 0) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH19 (_ACMP_INPUTSEL_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH20 (_ACMP_INPUTSEL_POSSEL_APORT2YCH20 << 0) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH21 (_ACMP_INPUTSEL_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH22 (_ACMP_INPUTSEL_POSSEL_APORT2YCH22 << 0) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH23 (_ACMP_INPUTSEL_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH24 (_ACMP_INPUTSEL_POSSEL_APORT2YCH24 << 0) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH25 (_ACMP_INPUTSEL_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH26 (_ACMP_INPUTSEL_POSSEL_APORT2YCH26 << 0) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH27 (_ACMP_INPUTSEL_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH28 (_ACMP_INPUTSEL_POSSEL_APORT2YCH28 << 0) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH29 (_ACMP_INPUTSEL_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH30 (_ACMP_INPUTSEL_POSSEL_APORT2YCH30 << 0) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH31 (_ACMP_INPUTSEL_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH0 (_ACMP_INPUTSEL_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH1 (_ACMP_INPUTSEL_POSSEL_APORT3YCH1 << 0) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH2 (_ACMP_INPUTSEL_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH3 (_ACMP_INPUTSEL_POSSEL_APORT3YCH3 << 0) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH4 (_ACMP_INPUTSEL_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH5 (_ACMP_INPUTSEL_POSSEL_APORT3YCH5 << 0) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH6 (_ACMP_INPUTSEL_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH7 (_ACMP_INPUTSEL_POSSEL_APORT3YCH7 << 0) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH8 (_ACMP_INPUTSEL_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH9 (_ACMP_INPUTSEL_POSSEL_APORT3YCH9 << 0) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH10 (_ACMP_INPUTSEL_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH11 (_ACMP_INPUTSEL_POSSEL_APORT3YCH11 << 0) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH12 (_ACMP_INPUTSEL_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH13 (_ACMP_INPUTSEL_POSSEL_APORT3YCH13 << 0) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH14 (_ACMP_INPUTSEL_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH15 (_ACMP_INPUTSEL_POSSEL_APORT3YCH15 << 0) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH16 (_ACMP_INPUTSEL_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH17 (_ACMP_INPUTSEL_POSSEL_APORT3YCH17 << 0) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH18 (_ACMP_INPUTSEL_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH19 (_ACMP_INPUTSEL_POSSEL_APORT3YCH19 << 0) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH20 (_ACMP_INPUTSEL_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH21 (_ACMP_INPUTSEL_POSSEL_APORT3YCH21 << 0) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH22 (_ACMP_INPUTSEL_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH23 (_ACMP_INPUTSEL_POSSEL_APORT3YCH23 << 0) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH24 (_ACMP_INPUTSEL_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH25 (_ACMP_INPUTSEL_POSSEL_APORT3YCH25 << 0) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH26 (_ACMP_INPUTSEL_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH27 (_ACMP_INPUTSEL_POSSEL_APORT3YCH27 << 0) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH28 (_ACMP_INPUTSEL_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH29 (_ACMP_INPUTSEL_POSSEL_APORT3YCH29 << 0) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH30 (_ACMP_INPUTSEL_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH31 (_ACMP_INPUTSEL_POSSEL_APORT3YCH31 << 0) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH0 (_ACMP_INPUTSEL_POSSEL_APORT4YCH0 << 0) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH1 (_ACMP_INPUTSEL_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH2 (_ACMP_INPUTSEL_POSSEL_APORT4YCH2 << 0) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH3 (_ACMP_INPUTSEL_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH4 (_ACMP_INPUTSEL_POSSEL_APORT4YCH4 << 0) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH5 (_ACMP_INPUTSEL_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH6 (_ACMP_INPUTSEL_POSSEL_APORT4YCH6 << 0) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH7 (_ACMP_INPUTSEL_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH8 (_ACMP_INPUTSEL_POSSEL_APORT4YCH8 << 0) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH9 (_ACMP_INPUTSEL_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH10 (_ACMP_INPUTSEL_POSSEL_APORT4YCH10 << 0) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH19 (_ACMP_INPUTSEL_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH20 (_ACMP_INPUTSEL_POSSEL_APORT4YCH20 << 0) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH21 (_ACMP_INPUTSEL_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH22 (_ACMP_INPUTSEL_POSSEL_APORT4YCH22 << 0) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH23 (_ACMP_INPUTSEL_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH24 (_ACMP_INPUTSEL_POSSEL_APORT4YCH24 << 0) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH25 (_ACMP_INPUTSEL_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH26 (_ACMP_INPUTSEL_POSSEL_APORT4YCH26 << 0) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH27 (_ACMP_INPUTSEL_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VDD (_ACMP_INPUTSEL_POSSEL_VDD << 0) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VSS (_ACMP_INPUTSEL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 8) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VSS (_ACMP_INPUTSEL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_SHIFT 16 /**< Shift value for ACMP_VASEL */ +#define _ACMP_INPUTSEL_VASEL_MASK 0x3F0000UL /**< Bit mask for ACMP_VASEL */ +#define _ACMP_INPUTSEL_VASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_VDD 0x00000000UL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH0 0x00000001UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH2 0x00000003UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH4 0x00000005UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH6 0x00000007UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH8 0x00000009UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH10 0x0000000BUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH12 0x0000000DUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH14 0x0000000FUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH16 0x00000011UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH18 0x00000013UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH20 0x00000015UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH22 0x00000017UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH24 0x00000019UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH26 0x0000001BUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH28 0x0000001DUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH30 0x0000001FUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_DEFAULT (_ACMP_INPUTSEL_VASEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_VDD (_ACMP_INPUTSEL_VASEL_VDD << 16) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH0 (_ACMP_INPUTSEL_VASEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH2 (_ACMP_INPUTSEL_VASEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH4 (_ACMP_INPUTSEL_VASEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH6 (_ACMP_INPUTSEL_VASEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH8 (_ACMP_INPUTSEL_VASEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH10 (_ACMP_INPUTSEL_VASEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH12 (_ACMP_INPUTSEL_VASEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH14 (_ACMP_INPUTSEL_VASEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH16 (_ACMP_INPUTSEL_VASEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH18 (_ACMP_INPUTSEL_VASEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH20 (_ACMP_INPUTSEL_VASEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH22 (_ACMP_INPUTSEL_VASEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH24 (_ACMP_INPUTSEL_VASEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH26 (_ACMP_INPUTSEL_VASEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH28 (_ACMP_INPUTSEL_VASEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH30 (_ACMP_INPUTSEL_VASEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH0 (_ACMP_INPUTSEL_VASEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH1 (_ACMP_INPUTSEL_VASEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH2 (_ACMP_INPUTSEL_VASEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH3 (_ACMP_INPUTSEL_VASEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH4 (_ACMP_INPUTSEL_VASEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH5 (_ACMP_INPUTSEL_VASEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH6 (_ACMP_INPUTSEL_VASEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH7 (_ACMP_INPUTSEL_VASEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH8 (_ACMP_INPUTSEL_VASEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH9 (_ACMP_INPUTSEL_VASEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH10 (_ACMP_INPUTSEL_VASEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH11 (_ACMP_INPUTSEL_VASEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH12 (_ACMP_INPUTSEL_VASEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH13 (_ACMP_INPUTSEL_VASEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH14 (_ACMP_INPUTSEL_VASEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH15 (_ACMP_INPUTSEL_VASEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH16 (_ACMP_INPUTSEL_VASEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH17 (_ACMP_INPUTSEL_VASEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH18 (_ACMP_INPUTSEL_VASEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH19 (_ACMP_INPUTSEL_VASEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH20 (_ACMP_INPUTSEL_VASEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH21 (_ACMP_INPUTSEL_VASEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH22 (_ACMP_INPUTSEL_VASEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH23 (_ACMP_INPUTSEL_VASEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH24 (_ACMP_INPUTSEL_VASEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH25 (_ACMP_INPUTSEL_VASEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH26 (_ACMP_INPUTSEL_VASEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH27 (_ACMP_INPUTSEL_VASEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH28 (_ACMP_INPUTSEL_VASEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH29 (_ACMP_INPUTSEL_VASEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH30 (_ACMP_INPUTSEL_VASEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH31 (_ACMP_INPUTSEL_VASEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL (0x1UL << 22) /**< VB Selection */ +#define _ACMP_INPUTSEL_VBSEL_SHIFT 22 /**< Shift value for ACMP_VBSEL */ +#define _ACMP_INPUTSEL_VBSEL_MASK 0x400000UL /**< Bit mask for ACMP_VBSEL */ +#define _ACMP_INPUTSEL_VBSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VBSEL_1V25 0x00000000UL /**< Mode 1V25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VBSEL_2V5 0x00000001UL /**< Mode 2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_DEFAULT (_ACMP_INPUTSEL_VBSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_1V25 (_ACMP_INPUTSEL_VBSEL_1V25 << 22) /**< Shifted mode 1V25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_2V5 (_ACMP_INPUTSEL_VBSEL_2V5 << 22) /**< Shifted mode 2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL (0x1UL << 24) /**< Low-Power Sampled Voltage Selection */ +#define _ACMP_INPUTSEL_VLPSEL_SHIFT 24 /**< Shift value for ACMP_VLPSEL */ +#define _ACMP_INPUTSEL_VLPSEL_MASK 0x1000000UL /**< Bit mask for ACMP_VLPSEL */ +#define _ACMP_INPUTSEL_VLPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VLPSEL_VADIV 0x00000000UL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VLPSEL_VBDIV 0x00000001UL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_DEFAULT (_ACMP_INPUTSEL_VLPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_VADIV (_ACMP_INPUTSEL_VLPSEL_VADIV << 24) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_VBDIV (_ACMP_INPUTSEL_VLPSEL_VBDIV << 24) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN (0x1UL << 26) /**< Capacitive Sense Mode Internal Resistor Enable */ +#define _ACMP_INPUTSEL_CSRESEN_SHIFT 26 /**< Shift value for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_MASK 0x4000000UL /**< Bit mask for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 26) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES7 0x00000007UL /**< Mode RES7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES4 (_ACMP_INPUTSEL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES5 (_ACMP_INPUTSEL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES6 (_ACMP_INPUTSEL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES7 (_ACMP_INPUTSEL_CSRESSEL_RES7 << 28) /**< Shifted mode RES7 for ACMP_INPUTSEL */ + +/* Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000000FUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */ +#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Output */ +#define _ACMP_STATUS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_STATUS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_APORTCONFLICT_DEFAULT (_ACMP_STATUS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_EXTIFACT (0x1UL << 3) /**< External override interface active. */ +#define _ACMP_STATUS_EXTIFACT_SHIFT 3 /**< Shift value for ACMP_EXTIFACT */ +#define _ACMP_STATUS_EXTIFACT_MASK 0x8UL /**< Bit mask for ACMP_EXTIFACT */ +#define _ACMP_STATUS_EXTIFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_EXTIFACT_DEFAULT (_ACMP_STATUS_EXTIFACT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x00000007UL /**< Mask for ACMP_IF */ +#define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ +#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */ +#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Interrupt Flag */ +#define _ACMP_IF_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IF_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_APORTCONFLICT_DEFAULT (_ACMP_IF_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IFS */ +#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */ +#define _ACMP_IFS_MASK 0x00000007UL /**< Mask for ACMP_IFS */ +#define ACMP_IFS_EDGE (0x1UL << 0) /**< Set EDGE Interrupt Flag */ +#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP (0x1UL << 1) /**< Set WARMUP Interrupt Flag */ +#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_APORTCONFLICT (0x1UL << 2) /**< Set APORTCONFLICT Interrupt Flag */ +#define _ACMP_IFS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IFS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_APORTCONFLICT_DEFAULT (_ACMP_IFS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFS */ + +/* Bit fields for ACMP IFC */ +#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */ +#define _ACMP_IFC_MASK 0x00000007UL /**< Mask for ACMP_IFC */ +#define ACMP_IFC_EDGE (0x1UL << 0) /**< Clear EDGE Interrupt Flag */ +#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP (0x1UL << 1) /**< Clear WARMUP Interrupt Flag */ +#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_APORTCONFLICT (0x1UL << 2) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _ACMP_IFC_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IFC_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_APORTCONFLICT_DEFAULT (_ACMP_IFC_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFC */ + +/* Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x00000007UL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_EDGE (0x1UL << 0) /**< EDGE Interrupt Enable */ +#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP (0x1UL << 1) /**< WARMUP Interrupt Enable */ +#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_APORTCONFLICT (0x1UL << 2) /**< APORTCONFLICT Interrupt Enable */ +#define _ACMP_IEN_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IEN_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_APORTCONFLICT_DEFAULT (_ACMP_IEN_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP APORTREQ */ +#define _ACMP_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTREQ */ +#define _ACMP_APORTREQ_MASK 0x000003FFUL /**< Mask for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */ +#define _ACMP_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ACMP_APORT0XREQ */ +#define _ACMP_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ACMP_APORT0XREQ */ +#define _ACMP_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0XREQ_DEFAULT (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */ +#define _ACMP_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ACMP_APORT0YREQ */ +#define _ACMP_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ACMP_APORT0YREQ */ +#define _ACMP_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0YREQ_DEFAULT (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _ACMP_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ACMP_APORT1XREQ */ +#define _ACMP_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ACMP_APORT1XREQ */ +#define _ACMP_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1XREQ_DEFAULT (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _ACMP_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ACMP_APORT1YREQ */ +#define _ACMP_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ACMP_APORT1YREQ */ +#define _ACMP_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1YREQ_DEFAULT (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _ACMP_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ACMP_APORT2XREQ */ +#define _ACMP_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ACMP_APORT2XREQ */ +#define _ACMP_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2XREQ_DEFAULT (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _ACMP_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ACMP_APORT2YREQ */ +#define _ACMP_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ACMP_APORT2YREQ */ +#define _ACMP_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2YREQ_DEFAULT (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _ACMP_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ACMP_APORT3XREQ */ +#define _ACMP_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ACMP_APORT3XREQ */ +#define _ACMP_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3XREQ_DEFAULT (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _ACMP_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ACMP_APORT3YREQ */ +#define _ACMP_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ACMP_APORT3YREQ */ +#define _ACMP_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3YREQ_DEFAULT (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _ACMP_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ACMP_APORT4XREQ */ +#define _ACMP_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ACMP_APORT4XREQ */ +#define _ACMP_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4XREQ_DEFAULT (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _ACMP_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ACMP_APORT4YREQ */ +#define _ACMP_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ACMP_APORT4YREQ */ +#define _ACMP_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4YREQ_DEFAULT (_ACMP_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ + +/* Bit fields for ACMP APORTCONFLICT */ +#define _ACMP_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTCONFLICT */ +#define _ACMP_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ACMP_APORT0XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ACMP_APORT0XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ACMP_APORT0YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ACMP_APORT0YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORT1XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORT1XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ACMP_APORT1YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_APORT1YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ACMP_APORT2XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ACMP_APORT2XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ACMP_APORT2YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ACMP_APORT2YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ACMP_APORT3XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ACMP_APORT3XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ACMP_APORT3YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ACMP_APORT3YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ACMP_APORT4XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ACMP_APORT4XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ACMP_APORT4YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ACMP_APORT4YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ + +/* Bit fields for ACMP HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ +#define _ACMP_HYSTERESIS0_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ +#define _ACMP_HYSTERESIS0_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_DEFAULT (_ACMP_HYSTERESIS0_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST0 (_ACMP_HYSTERESIS0_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST1 (_ACMP_HYSTERESIS0_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST2 (_ACMP_HYSTERESIS0_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST3 (_ACMP_HYSTERESIS0_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST4 (_ACMP_HYSTERESIS0_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST5 (_ACMP_HYSTERESIS0_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST6 (_ACMP_HYSTERESIS0_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST7 (_ACMP_HYSTERESIS0_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST8 (_ACMP_HYSTERESIS0_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST9 (_ACMP_HYSTERESIS0_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST10 (_ACMP_HYSTERESIS0_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST11 (_ACMP_HYSTERESIS0_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST12 (_ACMP_HYSTERESIS0_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST13 (_ACMP_HYSTERESIS0_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST14 (_ACMP_HYSTERESIS0_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST15 (_ACMP_HYSTERESIS0_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS0_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS0_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_DIVVA_DEFAULT (_ACMP_HYSTERESIS0_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS0_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS0_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_DIVVB_DEFAULT (_ACMP_HYSTERESIS0_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ + +/* Bit fields for ACMP HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ +#define _ACMP_HYSTERESIS1_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ +#define _ACMP_HYSTERESIS1_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_DEFAULT (_ACMP_HYSTERESIS1_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST0 (_ACMP_HYSTERESIS1_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST1 (_ACMP_HYSTERESIS1_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST2 (_ACMP_HYSTERESIS1_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST3 (_ACMP_HYSTERESIS1_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST4 (_ACMP_HYSTERESIS1_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST5 (_ACMP_HYSTERESIS1_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST6 (_ACMP_HYSTERESIS1_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST7 (_ACMP_HYSTERESIS1_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST8 (_ACMP_HYSTERESIS1_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST9 (_ACMP_HYSTERESIS1_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST10 (_ACMP_HYSTERESIS1_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST11 (_ACMP_HYSTERESIS1_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST12 (_ACMP_HYSTERESIS1_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST13 (_ACMP_HYSTERESIS1_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST14 (_ACMP_HYSTERESIS1_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST15 (_ACMP_HYSTERESIS1_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS1_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS1_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_DIVVA_DEFAULT (_ACMP_HYSTERESIS1_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS1_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS1_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_DIVVB_DEFAULT (_ACMP_HYSTERESIS1_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ + +/* Bit fields for ACMP ROUTEPEN */ +#define _ACMP_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTEPEN */ +#define _ACMP_ROUTEPEN_MASK 0x00000001UL /**< Mask for ACMP_ROUTEPEN */ +#define ACMP_ROUTEPEN_OUTPEN (0x1UL << 0) /**< ACMP Output Pin Enable */ +#define _ACMP_ROUTEPEN_OUTPEN_SHIFT 0 /**< Shift value for ACMP_OUTPEN */ +#define _ACMP_ROUTEPEN_OUTPEN_MASK 0x1UL /**< Bit mask for ACMP_OUTPEN */ +#define _ACMP_ROUTEPEN_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTEPEN */ +#define ACMP_ROUTEPEN_OUTPEN_DEFAULT (_ACMP_ROUTEPEN_OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTEPEN */ + +/* Bit fields for ACMP ROUTELOC0 */ +#define _ACMP_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_MASK 0x0000001FUL /**< Mask for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_SHIFT 0 /**< Shift value for ACMP_OUTLOC */ +#define _ACMP_ROUTELOC0_OUTLOC_MASK 0x1FUL /**< Bit mask for ACMP_OUTLOC */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC4 0x00000004UL /**< Mode LOC4 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC5 0x00000005UL /**< Mode LOC5 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC6 0x00000006UL /**< Mode LOC6 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC7 0x00000007UL /**< Mode LOC7 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC8 0x00000008UL /**< Mode LOC8 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC9 0x00000009UL /**< Mode LOC9 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC10 0x0000000AUL /**< Mode LOC10 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC11 0x0000000BUL /**< Mode LOC11 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC12 0x0000000CUL /**< Mode LOC12 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC13 0x0000000DUL /**< Mode LOC13 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC14 0x0000000EUL /**< Mode LOC14 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC15 0x0000000FUL /**< Mode LOC15 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC16 0x00000010UL /**< Mode LOC16 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC17 0x00000011UL /**< Mode LOC17 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC18 0x00000012UL /**< Mode LOC18 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC19 0x00000013UL /**< Mode LOC19 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC20 0x00000014UL /**< Mode LOC20 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC21 0x00000015UL /**< Mode LOC21 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC22 0x00000016UL /**< Mode LOC22 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC23 0x00000017UL /**< Mode LOC23 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC24 0x00000018UL /**< Mode LOC24 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC25 0x00000019UL /**< Mode LOC25 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC26 0x0000001AUL /**< Mode LOC26 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC27 0x0000001BUL /**< Mode LOC27 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC28 0x0000001CUL /**< Mode LOC28 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC29 0x0000001DUL /**< Mode LOC29 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC30 0x0000001EUL /**< Mode LOC30 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC31 0x0000001FUL /**< Mode LOC31 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC0 (_ACMP_ROUTELOC0_OUTLOC_LOC0 << 0) /**< Shifted mode LOC0 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_DEFAULT (_ACMP_ROUTELOC0_OUTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC1 (_ACMP_ROUTELOC0_OUTLOC_LOC1 << 0) /**< Shifted mode LOC1 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC2 (_ACMP_ROUTELOC0_OUTLOC_LOC2 << 0) /**< Shifted mode LOC2 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC3 (_ACMP_ROUTELOC0_OUTLOC_LOC3 << 0) /**< Shifted mode LOC3 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC4 (_ACMP_ROUTELOC0_OUTLOC_LOC4 << 0) /**< Shifted mode LOC4 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC5 (_ACMP_ROUTELOC0_OUTLOC_LOC5 << 0) /**< Shifted mode LOC5 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC6 (_ACMP_ROUTELOC0_OUTLOC_LOC6 << 0) /**< Shifted mode LOC6 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC7 (_ACMP_ROUTELOC0_OUTLOC_LOC7 << 0) /**< Shifted mode LOC7 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC8 (_ACMP_ROUTELOC0_OUTLOC_LOC8 << 0) /**< Shifted mode LOC8 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC9 (_ACMP_ROUTELOC0_OUTLOC_LOC9 << 0) /**< Shifted mode LOC9 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC10 (_ACMP_ROUTELOC0_OUTLOC_LOC10 << 0) /**< Shifted mode LOC10 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC11 (_ACMP_ROUTELOC0_OUTLOC_LOC11 << 0) /**< Shifted mode LOC11 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC12 (_ACMP_ROUTELOC0_OUTLOC_LOC12 << 0) /**< Shifted mode LOC12 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC13 (_ACMP_ROUTELOC0_OUTLOC_LOC13 << 0) /**< Shifted mode LOC13 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC14 (_ACMP_ROUTELOC0_OUTLOC_LOC14 << 0) /**< Shifted mode LOC14 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC15 (_ACMP_ROUTELOC0_OUTLOC_LOC15 << 0) /**< Shifted mode LOC15 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC16 (_ACMP_ROUTELOC0_OUTLOC_LOC16 << 0) /**< Shifted mode LOC16 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC17 (_ACMP_ROUTELOC0_OUTLOC_LOC17 << 0) /**< Shifted mode LOC17 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC18 (_ACMP_ROUTELOC0_OUTLOC_LOC18 << 0) /**< Shifted mode LOC18 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC19 (_ACMP_ROUTELOC0_OUTLOC_LOC19 << 0) /**< Shifted mode LOC19 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC20 (_ACMP_ROUTELOC0_OUTLOC_LOC20 << 0) /**< Shifted mode LOC20 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC21 (_ACMP_ROUTELOC0_OUTLOC_LOC21 << 0) /**< Shifted mode LOC21 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC22 (_ACMP_ROUTELOC0_OUTLOC_LOC22 << 0) /**< Shifted mode LOC22 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC23 (_ACMP_ROUTELOC0_OUTLOC_LOC23 << 0) /**< Shifted mode LOC23 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC24 (_ACMP_ROUTELOC0_OUTLOC_LOC24 << 0) /**< Shifted mode LOC24 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC25 (_ACMP_ROUTELOC0_OUTLOC_LOC25 << 0) /**< Shifted mode LOC25 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC26 (_ACMP_ROUTELOC0_OUTLOC_LOC26 << 0) /**< Shifted mode LOC26 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC27 (_ACMP_ROUTELOC0_OUTLOC_LOC27 << 0) /**< Shifted mode LOC27 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC28 (_ACMP_ROUTELOC0_OUTLOC_LOC28 << 0) /**< Shifted mode LOC28 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC29 (_ACMP_ROUTELOC0_OUTLOC_LOC29 << 0) /**< Shifted mode LOC29 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC30 (_ACMP_ROUTELOC0_OUTLOC_LOC30 << 0) /**< Shifted mode LOC30 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC31 (_ACMP_ROUTELOC0_OUTLOC_LOC31 << 0) /**< Shifted mode LOC31 for ACMP_ROUTELOC0 */ + +/* Bit fields for ACMP EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_MASK 0x000000F1UL /**< Mask for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_EN (0x1UL << 0) /**< Enable external interface. */ +#define _ACMP_EXTIFCTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EXTIFCTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EXTIFCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_EN_DEFAULT (_ACMP_EXTIFCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_SHIFT 4 /**< Shift value for ACMP_APORTSEL */ +#define _ACMP_EXTIFCTRL_APORTSEL_MASK 0xF0UL /**< Bit mask for ACMP_APORTSEL */ +#define _ACMP_EXTIFCTRL_APORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT0X 0x00000000UL /**< Mode APORT0X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT0Y 0x00000001UL /**< Mode APORT0Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1X 0x00000002UL /**< Mode APORT1X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1Y 0x00000003UL /**< Mode APORT1Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1XY 0x00000004UL /**< Mode APORT1XY for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2X 0x00000005UL /**< Mode APORT2X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2Y 0x00000006UL /**< Mode APORT2Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2YX 0x00000007UL /**< Mode APORT2YX for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3X 0x00000008UL /**< Mode APORT3X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3Y 0x00000009UL /**< Mode APORT3Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3XY 0x0000000AUL /**< Mode APORT3XY for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4X 0x0000000BUL /**< Mode APORT4X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4Y 0x0000000CUL /**< Mode APORT4Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4YX 0x0000000DUL /**< Mode APORT4YX for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_DEFAULT (_ACMP_EXTIFCTRL_APORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT0X (_ACMP_EXTIFCTRL_APORTSEL_APORT0X << 4) /**< Shifted mode APORT0X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT0Y (_ACMP_EXTIFCTRL_APORTSEL_APORT0Y << 4) /**< Shifted mode APORT0Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1X (_ACMP_EXTIFCTRL_APORTSEL_APORT1X << 4) /**< Shifted mode APORT1X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1Y (_ACMP_EXTIFCTRL_APORTSEL_APORT1Y << 4) /**< Shifted mode APORT1Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1XY (_ACMP_EXTIFCTRL_APORTSEL_APORT1XY << 4) /**< Shifted mode APORT1XY for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2X (_ACMP_EXTIFCTRL_APORTSEL_APORT2X << 4) /**< Shifted mode APORT2X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2Y (_ACMP_EXTIFCTRL_APORTSEL_APORT2Y << 4) /**< Shifted mode APORT2Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2YX (_ACMP_EXTIFCTRL_APORTSEL_APORT2YX << 4) /**< Shifted mode APORT2YX for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3X (_ACMP_EXTIFCTRL_APORTSEL_APORT3X << 4) /**< Shifted mode APORT3X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3Y (_ACMP_EXTIFCTRL_APORTSEL_APORT3Y << 4) /**< Shifted mode APORT3Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3XY (_ACMP_EXTIFCTRL_APORTSEL_APORT3XY << 4) /**< Shifted mode APORT3XY for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4X (_ACMP_EXTIFCTRL_APORTSEL_APORT4X << 4) /**< Shifted mode APORT4X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4Y (_ACMP_EXTIFCTRL_APORTSEL_APORT4Y << 4) /**< Shifted mode APORT4Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4YX (_ACMP_EXTIFCTRL_APORTSEL_APORT4YX << 4) /**< Shifted mode APORT4YX for ACMP_EXTIFCTRL */ + +/** @} End of group EFM32PG12B_ACMP */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_adc.h new file mode 100644 index 00000000000..0d489319553 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_adc.h @@ -0,0 +1,2371 @@ +/**************************************************************************//** + * @file efm32pg12b_adc.h + * @brief EFM32PG12B_ADC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_ADC + * @{ + * @brief EFM32PG12B_ADC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t SINGLECTRL; /**< Single Channel Control Register */ + __IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register continued */ + __IOM uint32_t SCANCTRL; /**< Scan Control Register */ + __IOM uint32_t SCANCTRLX; /**< Scan Control Register continued */ + __IOM uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */ + __IOM uint32_t SCANINPUTSEL; /**< Input Selection register for Scan mode */ + __IOM uint32_t SCANNEGSEL; /**< Negative Input select register for Scan */ + __IOM uint32_t CMPTHR; /**< Compare Threshold Register */ + __IOM uint32_t BIASPROG; /**< Bias Programming Register for various analog blocks used in ADC operation. */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */ + __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */ + __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */ + __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */ + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IM uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */ + __IM uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */ + + uint32_t RESERVED2[3]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ + __IM uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */ + __IM uint32_t SCANFIFOCOUNT; /**< Scan FIFO Count Register */ + __IOM uint32_t SINGLEFIFOCLEAR; /**< Single FIFO Clear Register */ + __IOM uint32_t SCANFIFOCLEAR; /**< Scan FIFO Clear Register */ + __IOM uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */ +} ADC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_ADC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ADC CTRL */ +#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */ +#define _ADC_CTRL_MASK 0xFF7F7FDFUL /**< Mask for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC 0x00000002UL /**< Mode KEEPINSLOWACC for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 0) /**< Shifted mode KEEPINSTANDBY for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPINSLOWACC (_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC << 0) /**< Shifted mode KEEPINSLOWACC for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_SINGLEDMAWU (0x1UL << 2) /**< SINGLEFIFO DMA Wakeup */ +#define _ADC_CTRL_SINGLEDMAWU_SHIFT 2 /**< Shift value for ADC_SINGLEDMAWU */ +#define _ADC_CTRL_SINGLEDMAWU_MASK 0x4UL /**< Bit mask for ADC_SINGLEDMAWU */ +#define _ADC_CTRL_SINGLEDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SINGLEDMAWU_DEFAULT (_ADC_CTRL_SINGLEDMAWU_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SCANDMAWU (0x1UL << 3) /**< SCANFIFO DMA Wakeup */ +#define _ADC_CTRL_SCANDMAWU_SHIFT 3 /**< Shift value for ADC_SCANDMAWU */ +#define _ADC_CTRL_SCANDMAWU_MASK 0x8UL /**< Bit mask for ADC_SCANDMAWU */ +#define _ADC_CTRL_SCANDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SCANDMAWU_DEFAULT (_ADC_CTRL_SCANDMAWU_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TAILGATE (0x1UL << 4) /**< Conversion Tailgating */ +#define _ADC_CTRL_TAILGATE_SHIFT 4 /**< Shift value for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK enable mode when ADCCLKMODE=1 */ +#define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */ +#define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */ +#define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_ASYNCCLKEN_ASNEEDED 0x00000000UL /**< Mode ASNEEDED for ADC_CTRL */ +#define _ADC_CTRL_ASYNCCLKEN_ALWAYSON 0x00000001UL /**< Mode ALWAYSON for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_DEFAULT (_ADC_CTRL_ASYNCCLKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_ASNEEDED (_ADC_CTRL_ASYNCCLKEN_ASNEEDED << 6) /**< Shifted mode ASNEEDED for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_ALWAYSON (_ADC_CTRL_ASYNCCLKEN_ALWAYSON << 6) /**< Shifted mode ALWAYSON for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE (0x1UL << 7) /**< ADC Clock Mode */ +#define _ADC_CTRL_ADCCLKMODE_SHIFT 7 /**< Shift value for ADC_ADCCLKMODE */ +#define _ADC_CTRL_ADCCLKMODE_MASK 0x80UL /**< Bit mask for ADC_ADCCLKMODE */ +#define _ADC_CTRL_ADCCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_ADCCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for ADC_CTRL */ +#define _ADC_CTRL_ADCCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_DEFAULT (_ADC_CTRL_ADCCLKMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_SYNC (_ADC_CTRL_ADCCLKMODE_SYNC << 7) /**< Shifted mode SYNC for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_ASYNC (_ADC_CTRL_ADCCLKMODE_ASYNC << 7) /**< Shifted mode ASYNC for ADC_CTRL */ +#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */ +#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */ +#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */ +#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */ +#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */ +#define ADC_CTRL_DBGHALT (0x1UL << 28) /**< Debug Mode Halt Enable */ +#define _ADC_CTRL_DBGHALT_SHIFT 28 /**< Shift value for ADC_DBGHALT */ +#define _ADC_CTRL_DBGHALT_MASK 0x10000000UL /**< Bit mask for ADC_DBGHALT */ +#define _ADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_DBGHALT_DEFAULT (_ADC_CTRL_DBGHALT_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE (0x1UL << 29) /**< Channel Connect */ +#define _ADC_CTRL_CHCONMODE_SHIFT 29 /**< Shift value for ADC_CHCONMODE */ +#define _ADC_CTRL_CHCONMODE_MASK 0x20000000UL /**< Bit mask for ADC_CHCONMODE */ +#define _ADC_CTRL_CHCONMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_CHCONMODE_MAXSETTLE 0x00000000UL /**< Mode MAXSETTLE for ADC_CTRL */ +#define _ADC_CTRL_CHCONMODE_MAXRESP 0x00000001UL /**< Mode MAXRESP for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_DEFAULT (_ADC_CTRL_CHCONMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_MAXSETTLE (_ADC_CTRL_CHCONMODE_MAXSETTLE << 29) /**< Shifted mode MAXSETTLE for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_MAXRESP (_ADC_CTRL_CHCONMODE_MAXRESP << 29) /**< Shifted mode MAXRESP for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_SHIFT 30 /**< Shift value for ADC_CHCONREFWARMIDLE */ +#define _ADC_CTRL_CHCONREFWARMIDLE_MASK 0xC0000000UL /**< Bit mask for ADC_CHCONREFWARMIDLE */ +#define _ADC_CTRL_CHCONREFWARMIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN 0x00000000UL /**< Mode PREFSCAN for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE 0x00000001UL /**< Mode PREFSINGLE for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV 0x00000002UL /**< Mode KEEPPREV for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_DEFAULT (_ADC_CTRL_CHCONREFWARMIDLE_DEFAULT << 30) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN (_ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN << 30) /**< Shifted mode PREFSCAN for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE (_ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE << 30) /**< Shifted mode PREFSINGLE for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV (_ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV << 30) /**< Shifted mode KEEPPREV for ADC_CTRL */ + +/* Bit fields for ADC CMD */ +#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */ +#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */ +#define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Channel Conversion Start */ +#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Channel Conversion Stop */ +#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */ +#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */ +#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */ + +/* Bit fields for ADC STATUS */ +#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */ +#define _ADC_STATUS_MASK 0x00031F07UL /**< Mask for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Channel Conversion Active */ +#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */ +#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANPENDING (0x1UL << 2) /**< Scan Conversion Pending */ +#define _ADC_STATUS_SCANPENDING_SHIFT 2 /**< Shift value for ADC_SCANPENDING */ +#define _ADC_STATUS_SCANPENDING_MASK 0x4UL /**< Bit mask for ADC_SCANPENDING */ +#define _ADC_STATUS_SCANPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANPENDING_DEFAULT (_ADC_STATUS_SCANPENDING_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Channel Reference Warmed Up */ +#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */ +#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_SHIFT 10 /**< Shift value for ADC_PROGERR */ +#define _ADC_STATUS_PROGERR_MASK 0xC00UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_STATUS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_BUSCONF 0x00000001UL /**< Mode BUSCONF for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_NEGSELCONF 0x00000002UL /**< Mode NEGSELCONF for ADC_STATUS */ +#define ADC_STATUS_PROGERR_DEFAULT (_ADC_STATUS_PROGERR_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_PROGERR_BUSCONF (_ADC_STATUS_PROGERR_BUSCONF << 10) /**< Shifted mode BUSCONF for ADC_STATUS */ +#define ADC_STATUS_PROGERR_NEGSELCONF (_ADC_STATUS_PROGERR_NEGSELCONF << 10) /**< Shifted mode NEGSELCONF for ADC_STATUS */ +#define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */ +#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */ +#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */ +#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Channel Data Valid */ +#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */ +#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */ + +/* Bit fields for ADC SINGLECTRL */ +#define _ADC_SINGLECTRL_RESETVALUE 0x00FFFF00UL /**< Default value for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_MASK 0xAFFFFFFFUL /**< Mask for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Channel Repetitive Mode */ +#define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ +#define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ +#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Channel Differential Mode */ +#define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Channel Result Adjustment */ +#define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ +#define _ADC_SINGLECTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ +#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ +#define _ADC_SINGLECTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ +#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_5V (_ADC_SINGLECTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_CONF (_ADC_SINGLECTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SHIFT 8 /**< Shift value for ADC_POSSEL */ +#define _ADC_SINGLECTRL_POSSEL_MASK 0xFF00UL /**< Bit mask for ADC_POSSEL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_BU 0x000000E1UL /**< Mode BU for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_AREG 0x000000E2UL /**< Mode AREG for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VREGOUTPA 0x000000E3UL /**< Mode VREGOUTPA for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_PDBU 0x000000E4UL /**< Mode PDBU for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_IO0 0x000000E5UL /**< Mode IO0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_IO1 0x000000E6UL /**< Mode IO1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_OPA2 0x000000F2UL /**< Mode OPA2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_TESTP 0x000000F5UL /**< Mode TESTP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SUBLSB 0x000000F9UL /**< Mode SUBLSB for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_OPA3 0x000000FAUL /**< Mode OPA3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH0 (_ADC_SINGLECTRL_POSSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH1 (_ADC_SINGLECTRL_POSSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH2 (_ADC_SINGLECTRL_POSSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH3 (_ADC_SINGLECTRL_POSSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH4 (_ADC_SINGLECTRL_POSSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH5 (_ADC_SINGLECTRL_POSSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH6 (_ADC_SINGLECTRL_POSSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH7 (_ADC_SINGLECTRL_POSSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH8 (_ADC_SINGLECTRL_POSSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH9 (_ADC_SINGLECTRL_POSSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH10 (_ADC_SINGLECTRL_POSSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH11 (_ADC_SINGLECTRL_POSSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH12 (_ADC_SINGLECTRL_POSSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH13 (_ADC_SINGLECTRL_POSSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH14 (_ADC_SINGLECTRL_POSSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH15 (_ADC_SINGLECTRL_POSSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH0 (_ADC_SINGLECTRL_POSSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH1 (_ADC_SINGLECTRL_POSSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH2 (_ADC_SINGLECTRL_POSSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH3 (_ADC_SINGLECTRL_POSSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH4 (_ADC_SINGLECTRL_POSSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH5 (_ADC_SINGLECTRL_POSSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH6 (_ADC_SINGLECTRL_POSSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH7 (_ADC_SINGLECTRL_POSSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH8 (_ADC_SINGLECTRL_POSSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH9 (_ADC_SINGLECTRL_POSSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH10 (_ADC_SINGLECTRL_POSSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH11 (_ADC_SINGLECTRL_POSSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH12 (_ADC_SINGLECTRL_POSSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH13 (_ADC_SINGLECTRL_POSSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH14 (_ADC_SINGLECTRL_POSSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH15 (_ADC_SINGLECTRL_POSSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH0 (_ADC_SINGLECTRL_POSSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH1 (_ADC_SINGLECTRL_POSSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH2 (_ADC_SINGLECTRL_POSSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH3 (_ADC_SINGLECTRL_POSSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH4 (_ADC_SINGLECTRL_POSSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH5 (_ADC_SINGLECTRL_POSSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH6 (_ADC_SINGLECTRL_POSSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH7 (_ADC_SINGLECTRL_POSSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH8 (_ADC_SINGLECTRL_POSSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH9 (_ADC_SINGLECTRL_POSSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH10 (_ADC_SINGLECTRL_POSSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH11 (_ADC_SINGLECTRL_POSSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH12 (_ADC_SINGLECTRL_POSSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH13 (_ADC_SINGLECTRL_POSSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH14 (_ADC_SINGLECTRL_POSSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH15 (_ADC_SINGLECTRL_POSSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH16 (_ADC_SINGLECTRL_POSSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH17 (_ADC_SINGLECTRL_POSSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH18 (_ADC_SINGLECTRL_POSSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH19 (_ADC_SINGLECTRL_POSSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH20 (_ADC_SINGLECTRL_POSSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH21 (_ADC_SINGLECTRL_POSSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH22 (_ADC_SINGLECTRL_POSSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH23 (_ADC_SINGLECTRL_POSSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH24 (_ADC_SINGLECTRL_POSSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH25 (_ADC_SINGLECTRL_POSSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH26 (_ADC_SINGLECTRL_POSSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH27 (_ADC_SINGLECTRL_POSSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH28 (_ADC_SINGLECTRL_POSSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH29 (_ADC_SINGLECTRL_POSSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH30 (_ADC_SINGLECTRL_POSSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH31 (_ADC_SINGLECTRL_POSSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH0 (_ADC_SINGLECTRL_POSSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH1 (_ADC_SINGLECTRL_POSSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH2 (_ADC_SINGLECTRL_POSSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH3 (_ADC_SINGLECTRL_POSSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH4 (_ADC_SINGLECTRL_POSSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH5 (_ADC_SINGLECTRL_POSSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH6 (_ADC_SINGLECTRL_POSSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH7 (_ADC_SINGLECTRL_POSSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH8 (_ADC_SINGLECTRL_POSSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH9 (_ADC_SINGLECTRL_POSSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH10 (_ADC_SINGLECTRL_POSSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH11 (_ADC_SINGLECTRL_POSSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH12 (_ADC_SINGLECTRL_POSSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH13 (_ADC_SINGLECTRL_POSSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH14 (_ADC_SINGLECTRL_POSSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH15 (_ADC_SINGLECTRL_POSSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH16 (_ADC_SINGLECTRL_POSSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH17 (_ADC_SINGLECTRL_POSSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH18 (_ADC_SINGLECTRL_POSSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH19 (_ADC_SINGLECTRL_POSSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH20 (_ADC_SINGLECTRL_POSSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH21 (_ADC_SINGLECTRL_POSSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH22 (_ADC_SINGLECTRL_POSSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH23 (_ADC_SINGLECTRL_POSSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH24 (_ADC_SINGLECTRL_POSSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH25 (_ADC_SINGLECTRL_POSSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH26 (_ADC_SINGLECTRL_POSSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH27 (_ADC_SINGLECTRL_POSSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH28 (_ADC_SINGLECTRL_POSSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH29 (_ADC_SINGLECTRL_POSSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH30 (_ADC_SINGLECTRL_POSSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH31 (_ADC_SINGLECTRL_POSSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH0 (_ADC_SINGLECTRL_POSSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH1 (_ADC_SINGLECTRL_POSSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH2 (_ADC_SINGLECTRL_POSSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH3 (_ADC_SINGLECTRL_POSSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH4 (_ADC_SINGLECTRL_POSSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH5 (_ADC_SINGLECTRL_POSSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH6 (_ADC_SINGLECTRL_POSSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH7 (_ADC_SINGLECTRL_POSSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH8 (_ADC_SINGLECTRL_POSSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH9 (_ADC_SINGLECTRL_POSSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH10 (_ADC_SINGLECTRL_POSSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH11 (_ADC_SINGLECTRL_POSSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH12 (_ADC_SINGLECTRL_POSSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH13 (_ADC_SINGLECTRL_POSSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH14 (_ADC_SINGLECTRL_POSSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH15 (_ADC_SINGLECTRL_POSSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH16 (_ADC_SINGLECTRL_POSSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH17 (_ADC_SINGLECTRL_POSSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH18 (_ADC_SINGLECTRL_POSSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH19 (_ADC_SINGLECTRL_POSSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH20 (_ADC_SINGLECTRL_POSSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH21 (_ADC_SINGLECTRL_POSSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH22 (_ADC_SINGLECTRL_POSSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH23 (_ADC_SINGLECTRL_POSSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH24 (_ADC_SINGLECTRL_POSSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH25 (_ADC_SINGLECTRL_POSSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH26 (_ADC_SINGLECTRL_POSSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH27 (_ADC_SINGLECTRL_POSSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH28 (_ADC_SINGLECTRL_POSSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH29 (_ADC_SINGLECTRL_POSSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH30 (_ADC_SINGLECTRL_POSSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH31 (_ADC_SINGLECTRL_POSSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH0 (_ADC_SINGLECTRL_POSSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH1 (_ADC_SINGLECTRL_POSSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH2 (_ADC_SINGLECTRL_POSSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH3 (_ADC_SINGLECTRL_POSSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH4 (_ADC_SINGLECTRL_POSSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH5 (_ADC_SINGLECTRL_POSSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH6 (_ADC_SINGLECTRL_POSSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH7 (_ADC_SINGLECTRL_POSSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH8 (_ADC_SINGLECTRL_POSSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH9 (_ADC_SINGLECTRL_POSSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH10 (_ADC_SINGLECTRL_POSSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH11 (_ADC_SINGLECTRL_POSSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH12 (_ADC_SINGLECTRL_POSSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH13 (_ADC_SINGLECTRL_POSSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH14 (_ADC_SINGLECTRL_POSSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH15 (_ADC_SINGLECTRL_POSSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH16 (_ADC_SINGLECTRL_POSSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH17 (_ADC_SINGLECTRL_POSSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH18 (_ADC_SINGLECTRL_POSSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH19 (_ADC_SINGLECTRL_POSSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH20 (_ADC_SINGLECTRL_POSSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH21 (_ADC_SINGLECTRL_POSSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH22 (_ADC_SINGLECTRL_POSSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH23 (_ADC_SINGLECTRL_POSSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH24 (_ADC_SINGLECTRL_POSSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH25 (_ADC_SINGLECTRL_POSSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH26 (_ADC_SINGLECTRL_POSSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH27 (_ADC_SINGLECTRL_POSSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH28 (_ADC_SINGLECTRL_POSSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH29 (_ADC_SINGLECTRL_POSSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_BU (_ADC_SINGLECTRL_POSSEL_BU << 8) /**< Shifted mode BU for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_AREG (_ADC_SINGLECTRL_POSSEL_AREG << 8) /**< Shifted mode AREG for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VREGOUTPA (_ADC_SINGLECTRL_POSSEL_VREGOUTPA << 8) /**< Shifted mode VREGOUTPA for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_PDBU (_ADC_SINGLECTRL_POSSEL_PDBU << 8) /**< Shifted mode PDBU for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_IO0 (_ADC_SINGLECTRL_POSSEL_IO0 << 8) /**< Shifted mode IO0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_IO1 (_ADC_SINGLECTRL_POSSEL_IO1 << 8) /**< Shifted mode IO1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_OPA2 (_ADC_SINGLECTRL_POSSEL_OPA2 << 8) /**< Shifted mode OPA2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_TESTP (_ADC_SINGLECTRL_POSSEL_TESTP << 8) /**< Shifted mode TESTP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SUBLSB (_ADC_SINGLECTRL_POSSEL_SUBLSB << 8) /**< Shifted mode SUBLSB for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_OPA3 (_ADC_SINGLECTRL_POSSEL_OPA3 << 8) /**< Shifted mode OPA3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DEFAULT (_ADC_SINGLECTRL_POSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VSS (_ADC_SINGLECTRL_POSSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_SHIFT 16 /**< Shift value for ADC_NEGSEL */ +#define _ADC_SINGLECTRL_NEGSEL_MASK 0xFF0000UL /**< Bit mask for ADC_NEGSEL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_TESTN 0x000000F5UL /**< Mode TESTN for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH0 << 16) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH1 << 16) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH2 << 16) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH3 << 16) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH4 << 16) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH5 << 16) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH6 << 16) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH7 << 16) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH8 << 16) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH9 << 16) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH10 << 16) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH11 << 16) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH12 << 16) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH13 << 16) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH14 << 16) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH15 << 16) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH0 << 16) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH1 << 16) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH2 << 16) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH3 << 16) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH4 << 16) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH5 << 16) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH6 << 16) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH7 << 16) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH8 << 16) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH9 << 16) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH10 << 16) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH11 << 16) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH12 << 16) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH13 << 16) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH14 << 16) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH15 << 16) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH1 << 16) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH3 << 16) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH5 << 16) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH7 << 16) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH9 << 16) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH11 << 16) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH13 << 16) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH15 << 16) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH17 << 16) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH19 << 16) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH21 << 16) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH23 << 16) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH25 << 16) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH27 << 16) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH29 << 16) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH31 << 16) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH0 << 16) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH2 << 16) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH4 << 16) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH6 << 16) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH8 << 16) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH10 << 16) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH12 << 16) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH14 << 16) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH16 << 16) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH18 << 16) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH20 << 16) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH22 << 16) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH24 << 16) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH26 << 16) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH28 << 16) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH30 << 16) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH1 << 16) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH3 << 16) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH5 << 16) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH7 << 16) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH9 << 16) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH11 << 16) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH13 << 16) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH15 << 16) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH17 << 16) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH19 << 16) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH21 << 16) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH23 << 16) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH25 << 16) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH27 << 16) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH29 << 16) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH31 << 16) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_TESTN (_ADC_SINGLECTRL_NEGSEL_TESTN << 16) /**< Shifted mode TESTN for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_DEFAULT (_ADC_SINGLECTRL_NEGSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_VSS (_ADC_SINGLECTRL_NEGSEL_VSS << 16) /**< Shifted mode VSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ +#define _ADC_SINGLECTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ +#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_3CYCLES (_ADC_SINGLECTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN (0x1UL << 29) /**< Single Channel PRS Trigger Enable */ +#define _ADC_SINGLECTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Single Channel */ +#define _ADC_SINGLECTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ +#define _ADC_SINGLECTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ +#define _ADC_SINGLECTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_CMPEN_DEFAULT (_ADC_SINGLECTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ + +/* Bit fields for ADC SINGLECTRLX */ +#define _ADC_SINGLECTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ +#define _ADC_SINGLECTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ +#define _ADC_SINGLECTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_DEFAULT (_ADC_SINGLECTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VBGR (_ADC_SINGLECTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VDDXWATT (_ADC_SINGLECTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFP (_ADC_SINGLECTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VENTROPY (_ADC_SINGLECTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */ +#define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ +#define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ +#define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATTFIX_DEFAULT (_ADC_SINGLECTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ +#define _ADC_SINGLECTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ +#define _ADC_SINGLECTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATT_DEFAULT (_ADC_SINGLECTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ +#define _ADC_SINGLECTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ +#define _ADC_SINGLECTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VINATT_DEFAULT (_ADC_SINGLECTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ +#define _ADC_SINGLECTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ +#define _ADC_SINGLECTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_DVL_DEFAULT (_ADC_SINGLECTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT (0x1UL << 14) /**< Single Channel FIFO Overflow Action */ +#define _ADC_SINGLECTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ +#define _ADC_SINGLECTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ +#define _ADC_SINGLECTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_DEFAULT (_ADC_SINGLECTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_DISCARD (_ADC_SINGLECTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE (_ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE (0x1UL << 16) /**< Single Channel PRS Trigger Mode */ +#define _ADC_SINGLECTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ +#define _ADC_SINGLECTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ +#define _ADC_SINGLECTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_DEFAULT (_ADC_SINGLECTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_PULSED (_ADC_SINGLECTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_TIMED (_ADC_SINGLECTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ +#define _ADC_SINGLECTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */ +#define _ADC_SINGLECTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_DEFAULT (_ADC_SINGLECTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH0 (_ADC_SINGLECTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH1 (_ADC_SINGLECTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH2 (_ADC_SINGLECTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH3 (_ADC_SINGLECTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH4 (_ADC_SINGLECTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH5 (_ADC_SINGLECTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH6 (_ADC_SINGLECTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH7 (_ADC_SINGLECTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH8 (_ADC_SINGLECTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH9 (_ADC_SINGLECTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH10 (_ADC_SINGLECTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH11 (_ADC_SINGLECTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ +#define _ADC_SINGLECTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ +#define _ADC_SINGLECTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_DEFAULT (_ADC_SINGLECTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_NODELAY (_ADC_SINGLECTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_4CYCLES (_ADC_SINGLECTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_8CYCLES (_ADC_SINGLECTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_16CYCLES (_ADC_SINGLECTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_32CYCLES (_ADC_SINGLECTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_64CYCLES (_ADC_SINGLECTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_128CYCLES (_ADC_SINGLECTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_256CYCLES (_ADC_SINGLECTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SINGLECTRLX */ + +/* Bit fields for ADC SCANCTRL */ +#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_MASK 0xAF0000FFUL /**< Mask for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */ +#define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ +#define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ +#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */ +#define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */ +#define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ +#define _ADC_SCANCTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ +#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ +#define _ADC_SCANCTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ +#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_5V (_ADC_SCANCTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_CONF (_ADC_SCANCTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ +#define _ADC_SCANCTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ +#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_3CYCLES (_ADC_SCANCTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN (0x1UL << 29) /**< Scan Sequence PRS Trigger Enable */ +#define _ADC_SCANCTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Scan */ +#define _ADC_SCANCTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ +#define _ADC_SCANCTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ +#define _ADC_SCANCTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_CMPEN_DEFAULT (_ADC_SCANCTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ + +/* Bit fields for ADC SCANCTRLX */ +#define _ADC_SCANCTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ +#define _ADC_SCANCTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ +#define _ADC_SCANCTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_DEFAULT (_ADC_SCANCTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VBGR (_ADC_SCANCTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VDDXWATT (_ADC_SCANCTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPWATT (_ADC_SCANCTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFP (_ADC_SCANCTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */ +#define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ +#define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ +#define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATTFIX_DEFAULT (_ADC_SCANCTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ +#define _ADC_SCANCTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ +#define _ADC_SCANCTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATT_DEFAULT (_ADC_SCANCTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ +#define _ADC_SCANCTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ +#define _ADC_SCANCTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VINATT_DEFAULT (_ADC_SCANCTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ +#define _ADC_SCANCTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ +#define _ADC_SCANCTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_DVL_DEFAULT (_ADC_SCANCTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT (0x1UL << 14) /**< Scan FIFO Overflow Action */ +#define _ADC_SCANCTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ +#define _ADC_SCANCTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ +#define _ADC_SCANCTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_DEFAULT (_ADC_SCANCTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_DISCARD (_ADC_SCANCTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_OVERWRITE (_ADC_SCANCTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE (0x1UL << 16) /**< Scan PRS Trigger Mode */ +#define _ADC_SCANCTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ +#define _ADC_SCANCTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ +#define _ADC_SCANCTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_DEFAULT (_ADC_SCANCTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_PULSED (_ADC_SCANCTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_TIMED (_ADC_SCANCTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ +#define _ADC_SCANCTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */ +#define _ADC_SCANCTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_DEFAULT (_ADC_SCANCTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH0 (_ADC_SCANCTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH1 (_ADC_SCANCTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH2 (_ADC_SCANCTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH3 (_ADC_SCANCTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH4 (_ADC_SCANCTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH5 (_ADC_SCANCTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH6 (_ADC_SCANCTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH7 (_ADC_SCANCTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH8 (_ADC_SCANCTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH9 (_ADC_SCANCTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH10 (_ADC_SCANCTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH11 (_ADC_SCANCTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ +#define _ADC_SCANCTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ +#define _ADC_SCANCTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_DEFAULT (_ADC_SCANCTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_NODELAY (_ADC_SCANCTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_4CYCLES (_ADC_SCANCTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_8CYCLES (_ADC_SCANCTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_16CYCLES (_ADC_SCANCTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_32CYCLES (_ADC_SCANCTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_64CYCLES (_ADC_SCANCTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_128CYCLES (_ADC_SCANCTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_256CYCLES (_ADC_SCANCTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SCANCTRLX */ + +/* Bit fields for ADC SCANMASK */ +#define _ADC_SCANMASK_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANMASK */ +#define _ADC_SCANMASK_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */ +#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */ +#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */ + +/* Bit fields for ADC SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_MASK 0x1F1F1F1FUL /**< Mask for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT 0 /**< Shift value for ADC_INPUT0TO7SEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_MASK 0x1FUL /**< Bit mask for ADC_INPUT0TO7SEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 << 0) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 << 0) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 << 0) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 << 0) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 << 0) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 << 0) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 << 0) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 << 0) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 << 0) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 << 0) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT 8 /**< Shift value for ADC_INPUT8TO15SEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_MASK 0x1F00UL /**< Bit mask for ADC_INPUT8TO15SEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 << 8) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 << 8) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 << 8) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 << 8) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 << 8) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 << 8) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 << 8) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 << 8) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 << 8) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 << 8) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT 16 /**< Shift value for ADC_INPUT16TO23SEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_MASK 0x1F0000UL /**< Bit mask for ADC_INPUT16TO23SEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 << 16) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 << 16) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 << 16) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 << 16) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 << 16) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 << 16) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 << 16) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 << 16) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 << 16) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 << 16) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT 24 /**< Shift value for ADC_INPUT24TO31SEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_MASK 0x1F000000UL /**< Bit mask for ADC_INPUT24TO31SEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 << 24) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 << 24) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 << 24) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 << 24) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 << 24) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 << 24) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 << 24) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 << 24) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 << 24) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 << 24) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ + +/* Bit fields for ADC SCANNEGSEL */ +#define _ADC_SCANNEGSEL_RESETVALUE 0x000039E4UL /**< Default value for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_MASK 0x0000FFFFUL /**< Mask for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT 0 /**< Shift value for ADC_INPUT0NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK 0x3UL /**< Bit mask for ADC_INPUT0NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT 2 /**< Shift value for ADC_INPUT2NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK 0xCUL /**< Bit mask for ADC_INPUT2NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 << 2) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 << 2) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 << 2) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 << 2) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT 4 /**< Shift value for ADC_INPUT4NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK 0x30UL /**< Bit mask for ADC_INPUT4NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 << 4) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 << 4) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 << 4) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 << 4) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT 6 /**< Shift value for ADC_INPUT6NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK 0xC0UL /**< Bit mask for ADC_INPUT6NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 << 6) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 << 6) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 << 6) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 << 6) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT 8 /**< Shift value for ADC_INPUT9NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK 0x300UL /**< Bit mask for ADC_INPUT9NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 << 8) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 << 8) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 << 8) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 << 8) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT 10 /**< Shift value for ADC_INPUT11NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK 0xC00UL /**< Bit mask for ADC_INPUT11NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 << 10) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 << 10) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 << 10) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 << 10) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT 12 /**< Shift value for ADC_INPUT13NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK 0x3000UL /**< Bit mask for ADC_INPUT13NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 << 12) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 << 12) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 << 12) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 << 12) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT 14 /**< Shift value for ADC_INPUT15NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK 0xC000UL /**< Bit mask for ADC_INPUT15NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 << 14) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 << 14) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 << 14) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 << 14) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ + +/* Bit fields for ADC CMPTHR */ +#define _ADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for ADC_CMPTHR */ +#define _ADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for ADC_CMPTHR */ +#define _ADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for ADC_ADLT */ +#define _ADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for ADC_ADLT */ +#define _ADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ +#define ADC_CMPTHR_ADLT_DEFAULT (_ADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMPTHR */ +#define _ADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for ADC_ADGT */ +#define _ADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for ADC_ADGT */ +#define _ADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ +#define ADC_CMPTHR_ADGT_DEFAULT (_ADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CMPTHR */ + +/* Bit fields for ADC BIASPROG */ +#define _ADC_BIASPROG_RESETVALUE 0x00000000UL /**< Default value for ADC_BIASPROG */ +#define _ADC_BIASPROG_MASK 0x0001100FUL /**< Mask for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SHIFT 0 /**< Shift value for ADC_ADCBIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_MASK 0xFUL /**< Bit mask for ADC_ADCBIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE2 0x00000004UL /**< Mode SCALE2 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE4 0x00000008UL /**< Mode SCALE4 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE8 0x0000000CUL /**< Mode SCALE8 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE16 0x0000000EUL /**< Mode SCALE16 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE32 0x0000000FUL /**< Mode SCALE32 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_DEFAULT (_ADC_BIASPROG_ADCBIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_NORMAL (_ADC_BIASPROG_ADCBIASPROG_NORMAL << 0) /**< Shifted mode NORMAL for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE2 (_ADC_BIASPROG_ADCBIASPROG_SCALE2 << 0) /**< Shifted mode SCALE2 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE4 (_ADC_BIASPROG_ADCBIASPROG_SCALE4 << 0) /**< Shifted mode SCALE4 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */ +#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF flag */ +#define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */ +#define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */ +#define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy setting for the system bias during ADC operation */ +#define _ADC_BIASPROG_GPBIASACC_SHIFT 16 /**< Shift value for ADC_GPBIASACC */ +#define _ADC_BIASPROG_GPBIASACC_MASK 0x10000UL /**< Bit mask for ADC_GPBIASACC */ +#define _ADC_BIASPROG_GPBIASACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_GPBIASACC_HIGHACC 0x00000000UL /**< Mode HIGHACC for ADC_BIASPROG */ +#define _ADC_BIASPROG_GPBIASACC_LOWACC 0x00000001UL /**< Mode LOWACC for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_DEFAULT (_ADC_BIASPROG_GPBIASACC_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_HIGHACC (_ADC_BIASPROG_GPBIASACC_HIGHACC << 16) /**< Shifted mode HIGHACC for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_LOWACC (_ADC_BIASPROG_GPBIASACC_LOWACC << 16) /**< Shifted mode LOWACC for ADC_BIASPROG */ + +/* Bit fields for ADC CAL */ +#define _ADC_CAL_RESETVALUE 0x40784078UL /**< Default value for ADC_CAL */ +#define _ADC_CAL_MASK 0xFFFFFFFFUL /**< Mask for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_MASK 0xFUL /**< Bit mask for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSETINV_SHIFT 4 /**< Shift value for ADC_SINGLEOFFSETINV */ +#define _ADC_CAL_SINGLEOFFSETINV_MASK 0xF0UL /**< Bit mask for ADC_SINGLEOFFSETINV */ +#define _ADC_CAL_SINGLEOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEOFFSETINV_DEFAULT (_ADC_CAL_SINGLEOFFSETINV_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */ +#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative single-ended offset calibration is enabled */ +#define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */ +#define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */ +#define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_OFFSETINVMODE_DEFAULT (_ADC_CAL_OFFSETINVMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_MASK 0xF0000UL /**< Bit mask for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSETINV_SHIFT 20 /**< Shift value for ADC_SCANOFFSETINV */ +#define _ADC_CAL_SCANOFFSETINV_MASK 0xF00000UL /**< Bit mask for ADC_SCANOFFSETINV */ +#define _ADC_CAL_SCANOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANOFFSETINV_DEFAULT (_ADC_CAL_SCANOFFSETINV_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */ +#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration mode is enabled */ +#define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */ +#define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */ +#define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_CALEN_DEFAULT (_ADC_CAL_CALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_CAL */ + +/* Bit fields for ADC IF */ +#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */ +#define _ADC_IF_MASK 0x3F030F03UL /**< Mask for ADC_IF */ +#define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */ +#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */ +#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single FIFO Overflow Interrupt Flag */ +#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF (0x1UL << 9) /**< Scan FIFO Overflow Interrupt Flag */ +#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEUF (0x1UL << 10) /**< Single FIFO Underflow Interrupt Flag */ +#define _ADC_IF_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IF_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IF_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEUF_DEFAULT (_ADC_IF_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANUF (0x1UL << 11) /**< Scan FIFO Underflow Interrupt Flag */ +#define _ADC_IF_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IF_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IF_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANUF_DEFAULT (_ADC_IF_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLECMP (0x1UL << 16) /**< Single Result Compare Match Interrupt Flag */ +#define _ADC_IF_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IF_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLECMP_DEFAULT (_ADC_IF_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANCMP (0x1UL << 17) /**< Scan Result Compare Match Interrupt Flag */ +#define _ADC_IF_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IF_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANCMP_DEFAULT (_ADC_IF_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_VREFOV (0x1UL << 24) /**< VREF Over Voltage Interrupt Flag */ +#define _ADC_IF_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IF_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IF_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_VREFOV_DEFAULT (_ADC_IF_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_PROGERR (0x1UL << 25) /**< Programming Error Interrupt Flag */ +#define _ADC_IF_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IF_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IF_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_PROGERR_DEFAULT (_ADC_IF_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANEXTPEND (0x1UL << 26) /**< External Scan Trigger Pending Flag */ +#define _ADC_IF_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IF_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IF_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANEXTPEND_DEFAULT (_ADC_IF_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANPEND (0x1UL << 27) /**< Scan Trigger Pending Flag */ +#define _ADC_IF_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IF_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IF_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANPEND_DEFAULT (_ADC_IF_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_PRSTIMEDERR (0x1UL << 28) /**< PRS Timed Mode Error Flag */ +#define _ADC_IF_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IF_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IF_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_PRSTIMEDERR_DEFAULT (_ADC_IF_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_EM23ERR (0x1UL << 29) /**< EM23 Entry Error Flag */ +#define _ADC_IF_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IF_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_EM23ERR_DEFAULT (_ADC_IF_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IF */ + +/* Bit fields for ADC IFS */ +#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */ +#define _ADC_IFS_MASK 0x3F030F00UL /**< Mask for ADC_IFS */ +#define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Set SINGLEOF Interrupt Flag */ +#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF (0x1UL << 9) /**< Set SCANOF Interrupt Flag */ +#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEUF (0x1UL << 10) /**< Set SINGLEUF Interrupt Flag */ +#define _ADC_IFS_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IFS_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IFS_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEUF_DEFAULT (_ADC_IFS_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANUF (0x1UL << 11) /**< Set SCANUF Interrupt Flag */ +#define _ADC_IFS_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IFS_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IFS_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANUF_DEFAULT (_ADC_IFS_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLECMP (0x1UL << 16) /**< Set SINGLECMP Interrupt Flag */ +#define _ADC_IFS_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IFS_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IFS_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLECMP_DEFAULT (_ADC_IFS_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANCMP (0x1UL << 17) /**< Set SCANCMP Interrupt Flag */ +#define _ADC_IFS_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IFS_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IFS_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANCMP_DEFAULT (_ADC_IFS_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_VREFOV (0x1UL << 24) /**< Set VREFOV Interrupt Flag */ +#define _ADC_IFS_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IFS_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IFS_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_VREFOV_DEFAULT (_ADC_IFS_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PROGERR (0x1UL << 25) /**< Set PROGERR Interrupt Flag */ +#define _ADC_IFS_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IFS_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IFS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PROGERR_DEFAULT (_ADC_IFS_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANEXTPEND (0x1UL << 26) /**< Set SCANEXTPEND Interrupt Flag */ +#define _ADC_IFS_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IFS_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IFS_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANEXTPEND_DEFAULT (_ADC_IFS_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANPEND (0x1UL << 27) /**< Set SCANPEND Interrupt Flag */ +#define _ADC_IFS_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IFS_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IFS_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANPEND_DEFAULT (_ADC_IFS_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PRSTIMEDERR (0x1UL << 28) /**< Set PRSTIMEDERR Interrupt Flag */ +#define _ADC_IFS_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IFS_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IFS_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PRSTIMEDERR_DEFAULT (_ADC_IFS_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_EM23ERR (0x1UL << 29) /**< Set EM23ERR Interrupt Flag */ +#define _ADC_IFS_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IFS_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_EM23ERR_DEFAULT (_ADC_IFS_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFS */ + +/* Bit fields for ADC IFC */ +#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */ +#define _ADC_IFC_MASK 0x3F030F00UL /**< Mask for ADC_IFC */ +#define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Clear SINGLEOF Interrupt Flag */ +#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF (0x1UL << 9) /**< Clear SCANOF Interrupt Flag */ +#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEUF (0x1UL << 10) /**< Clear SINGLEUF Interrupt Flag */ +#define _ADC_IFC_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IFC_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IFC_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEUF_DEFAULT (_ADC_IFC_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANUF (0x1UL << 11) /**< Clear SCANUF Interrupt Flag */ +#define _ADC_IFC_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IFC_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IFC_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANUF_DEFAULT (_ADC_IFC_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLECMP (0x1UL << 16) /**< Clear SINGLECMP Interrupt Flag */ +#define _ADC_IFC_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IFC_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IFC_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLECMP_DEFAULT (_ADC_IFC_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANCMP (0x1UL << 17) /**< Clear SCANCMP Interrupt Flag */ +#define _ADC_IFC_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IFC_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IFC_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANCMP_DEFAULT (_ADC_IFC_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_VREFOV (0x1UL << 24) /**< Clear VREFOV Interrupt Flag */ +#define _ADC_IFC_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IFC_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IFC_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_VREFOV_DEFAULT (_ADC_IFC_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PROGERR (0x1UL << 25) /**< Clear PROGERR Interrupt Flag */ +#define _ADC_IFC_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IFC_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IFC_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PROGERR_DEFAULT (_ADC_IFC_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANEXTPEND (0x1UL << 26) /**< Clear SCANEXTPEND Interrupt Flag */ +#define _ADC_IFC_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IFC_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IFC_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANEXTPEND_DEFAULT (_ADC_IFC_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANPEND (0x1UL << 27) /**< Clear SCANPEND Interrupt Flag */ +#define _ADC_IFC_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IFC_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IFC_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANPEND_DEFAULT (_ADC_IFC_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PRSTIMEDERR (0x1UL << 28) /**< Clear PRSTIMEDERR Interrupt Flag */ +#define _ADC_IFC_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IFC_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IFC_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PRSTIMEDERR_DEFAULT (_ADC_IFC_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_EM23ERR (0x1UL << 29) /**< Clear EM23ERR Interrupt Flag */ +#define _ADC_IFC_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IFC_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_EM23ERR_DEFAULT (_ADC_IFC_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFC */ + +/* Bit fields for ADC IEN */ +#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */ +#define _ADC_IEN_MASK 0x3F030F03UL /**< Mask for ADC_IEN */ +#define ADC_IEN_SINGLE (0x1UL << 0) /**< SINGLE Interrupt Enable */ +#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN (0x1UL << 1) /**< SCAN Interrupt Enable */ +#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF (0x1UL << 8) /**< SINGLEOF Interrupt Enable */ +#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF (0x1UL << 9) /**< SCANOF Interrupt Enable */ +#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEUF (0x1UL << 10) /**< SINGLEUF Interrupt Enable */ +#define _ADC_IEN_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IEN_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IEN_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEUF_DEFAULT (_ADC_IEN_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANUF (0x1UL << 11) /**< SCANUF Interrupt Enable */ +#define _ADC_IEN_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IEN_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IEN_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANUF_DEFAULT (_ADC_IEN_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLECMP (0x1UL << 16) /**< SINGLECMP Interrupt Enable */ +#define _ADC_IEN_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IEN_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLECMP_DEFAULT (_ADC_IEN_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANCMP (0x1UL << 17) /**< SCANCMP Interrupt Enable */ +#define _ADC_IEN_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IEN_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANCMP_DEFAULT (_ADC_IEN_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_VREFOV (0x1UL << 24) /**< VREFOV Interrupt Enable */ +#define _ADC_IEN_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IEN_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IEN_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_VREFOV_DEFAULT (_ADC_IEN_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PROGERR (0x1UL << 25) /**< PROGERR Interrupt Enable */ +#define _ADC_IEN_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IEN_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IEN_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PROGERR_DEFAULT (_ADC_IEN_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANEXTPEND (0x1UL << 26) /**< SCANEXTPEND Interrupt Enable */ +#define _ADC_IEN_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IEN_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IEN_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANEXTPEND_DEFAULT (_ADC_IEN_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANPEND (0x1UL << 27) /**< SCANPEND Interrupt Enable */ +#define _ADC_IEN_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IEN_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IEN_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANPEND_DEFAULT (_ADC_IEN_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PRSTIMEDERR (0x1UL << 28) /**< PRSTIMEDERR Interrupt Enable */ +#define _ADC_IEN_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IEN_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IEN_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PRSTIMEDERR_DEFAULT (_ADC_IEN_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_EM23ERR (0x1UL << 29) /**< EM23ERR Interrupt Enable */ +#define _ADC_IEN_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IEN_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_EM23ERR_DEFAULT (_ADC_IEN_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IEN */ + +/* Bit fields for ADC SINGLEDATA */ +#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */ +#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */ + +/* Bit fields for ADC SCANDATA */ +#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */ +#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */ +#define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */ +#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */ + +/* Bit fields for ADC SINGLEDATAP */ +#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */ +#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */ + +/* Bit fields for ADC SCANDATAP */ +#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */ +#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */ + +/* Bit fields for ADC SCANDATAX */ +#define _ADC_SCANDATAX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SCANDATAX_DATA_MASK 0xFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SCANDATAX_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ +#define ADC_SCANDATAX_DATA_DEFAULT (_ADC_SCANDATAX_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_SCANINPUTID_SHIFT 16 /**< Shift value for ADC_SCANINPUTID */ +#define _ADC_SCANDATAX_SCANINPUTID_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTID */ +#define _ADC_SCANDATAX_SCANINPUTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ +#define ADC_SCANDATAX_SCANINPUTID_DEFAULT (_ADC_SCANDATAX_SCANINPUTID_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ + +/* Bit fields for ADC SCANDATAXP */ +#define _ADC_SCANDATAXP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SCANDATAXP_DATAP_MASK 0xFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SCANDATAXP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ +#define ADC_SCANDATAXP_DATAP_DEFAULT (_ADC_SCANDATAXP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_SHIFT 16 /**< Shift value for ADC_SCANINPUTIDPEEK */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTIDPEEK */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ +#define ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT (_ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ + +/* Bit fields for ADC APORTREQ */ +#define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */ +#define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */ +#define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */ +#define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */ +#define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */ +#define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */ +#define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */ +#define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT1X is requested */ +#define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */ +#define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */ +#define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */ +#define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */ +#define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */ +#define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */ +#define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */ +#define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */ +#define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */ +#define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */ +#define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */ +#define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */ +#define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */ +#define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */ +#define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */ +#define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */ +#define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */ +#define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4YREQ_DEFAULT (_ADC_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTREQ */ + +/* Bit fields for ADC APORTCONFLICT */ +#define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */ +#define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ + +/* Bit fields for ADC SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_SHIFT 0 /**< Shift value for ADC_SINGLEDC */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_MASK 0x7UL /**< Bit mask for ADC_SINGLEDC */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCOUNT */ +#define ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT (_ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCOUNT */ + +/* Bit fields for ADC SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_SCANDC_SHIFT 0 /**< Shift value for ADC_SCANDC */ +#define _ADC_SCANFIFOCOUNT_SCANDC_MASK 0x7UL /**< Bit mask for ADC_SCANDC */ +#define _ADC_SCANFIFOCOUNT_SCANDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCOUNT */ +#define ADC_SCANFIFOCOUNT_SCANDC_DEFAULT (_ADC_SCANFIFOCOUNT_SCANDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCOUNT */ + +/* Bit fields for ADC SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */ +#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO content */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */ +#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT (_ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCLEAR */ + +/* Bit fields for ADC SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */ +#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO content */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */ +#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT (_ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCLEAR */ + +/* Bit fields for ADC APORTMASTERDIS */ +#define _ADC_APORTMASTERDIS_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTMASTERDIS */ +#define _ADC_APORTMASTERDIS_MASK 0x000003FCUL /**< Mask for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1XMASTERDIS (0x1UL << 2) /**< APORT1X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_SHIFT 2 /**< Shift value for ADC_APORT1XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_MASK 0x4UL /**< Bit mask for ADC_APORT1XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1YMASTERDIS (0x1UL << 3) /**< APORT1Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_SHIFT 3 /**< Shift value for ADC_APORT1YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_MASK 0x8UL /**< Bit mask for ADC_APORT1YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2XMASTERDIS (0x1UL << 4) /**< APORT2X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_SHIFT 4 /**< Shift value for ADC_APORT2XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_MASK 0x10UL /**< Bit mask for ADC_APORT2XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2YMASTERDIS (0x1UL << 5) /**< APORT2Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_SHIFT 5 /**< Shift value for ADC_APORT2YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_MASK 0x20UL /**< Bit mask for ADC_APORT2YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3XMASTERDIS (0x1UL << 6) /**< APORT3X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_SHIFT 6 /**< Shift value for ADC_APORT3XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_MASK 0x40UL /**< Bit mask for ADC_APORT3XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3YMASTERDIS (0x1UL << 7) /**< APORT3Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_SHIFT 7 /**< Shift value for ADC_APORT3YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_MASK 0x80UL /**< Bit mask for ADC_APORT3YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4XMASTERDIS (0x1UL << 8) /**< APORT4X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_SHIFT 8 /**< Shift value for ADC_APORT4XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_MASK 0x100UL /**< Bit mask for ADC_APORT4XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4YMASTERDIS (0x1UL << 9) /**< APORT4Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_SHIFT 9 /**< Shift value for ADC_APORT4YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_MASK 0x200UL /**< Bit mask for ADC_APORT4YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ + +/** @} End of group EFM32PG12B_ADC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_af_pins.h new file mode 100644 index 00000000000..37d8e7466e2 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_af_pins.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efm32pg12b_af_pins.h + * @brief EFM32PG12B_AF_PINS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_AF_Pins + * @{ + *****************************************************************************/ + +/** AF pin number for location number i */ +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1) +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : -1) +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1) +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1) +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1) +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1) +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1) +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1) +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1) +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1) +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1) +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1) +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_TIMER0_CC3_PIN(i) (-1) +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_TIMER0_CDTI3_PIN(i) (-1) +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_TIMER1_CDTI0_PIN(i) (-1) +#define AF_TIMER1_CDTI1_PIN(i) (-1) +#define AF_TIMER1_CDTI2_PIN(i) (-1) +#define AF_TIMER1_CDTI3_PIN(i) (-1) +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 12 : (i) == 13 ? 13 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 6 : (i) == 23 ? 7 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER0_CC3_PIN(i) (-1) +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 11 : (i) == 8 ? 12 : (i) == 9 ? 13 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 12 : (i) == 29 ? 13 : (i) == 30 ? 14 : (i) == 31 ? 15 : -1) +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 8 : (i) == 23 ? 9 : (i) == 24 ? 10 : (i) == 25 ? 11 : (i) == 26 ? 12 : (i) == 27 ? 13 : (i) == 28 ? 14 : (i) == 29 ? 15 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CDTI3_PIN(i) (-1) +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 4 : (i) == 9 ? 5 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 5 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 8 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 11 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 12 : (i) == 31 ? 13 : -1) +#define AF_WTIMER1_CDTI0_PIN(i) (-1) +#define AF_WTIMER1_CDTI1_PIN(i) (-1) +#define AF_WTIMER1_CDTI2_PIN(i) (-1) +#define AF_WTIMER1_CDTI3_PIN(i) (-1) +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 9 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 5 : -1) +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 3 : (i) == 15 ? 4 : (i) == 16 ? 5 : (i) == 17 ? 6 : (i) == 18 ? 7 : (i) == 19 ? 8 : (i) == 20 ? 9 : (i) == 21 ? 10 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 5 : (i) == 31 ? 6 : -1) +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 0 : (i) == 12 ? 1 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 3 : (i) == 13 ? 4 : (i) == 14 ? 5 : (i) == 15 ? 6 : (i) == 16 ? 7 : (i) == 17 ? 8 : (i) == 18 ? 9 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 8 : -1) +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 2 : (i) == 9 ? 3 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 14 : (i) == 16 ? 15 : (i) == 17 ? 0 : (i) == 18 ? 1 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 4 : (i) == 22 ? 5 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 8 : -1) +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 13 : (i) == 3 ? 14 : (i) == 4 ? 15 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 14 : (i) == 14 ? 15 : (i) == 15 ? 0 : (i) == 16 ? 1 : (i) == 17 ? 2 : (i) == 18 ? 3 : (i) == 19 ? 4 : (i) == 20 ? 5 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 8 : (i) == 30 ? 9 : (i) == 31 ? 10 : -1) +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 14 : (i) == 13 ? 15 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 4 : (i) == 19 ? 5 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 8 : (i) == 28 ? 9 : (i) == 29 ? 10 : (i) == 30 ? 11 : (i) == 31 ? 12 : -1) +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 10 : -1) +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 11 : -1) +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 12 : -1) +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 13 : -1) +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 14 : -1) +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 15 : -1) +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 4 : -1) +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 5 : -1) +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 6 : -1) +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 7 : -1) +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 14 : -1) +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 15 : -1) +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1) +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 6 : -1) +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 7 : -1) +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 8 : -1) +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 9 : -1) +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 8 : (i) == 3 ? 10 : -1) + +/** @} End of group EFM32PG12B_AF_Pins */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_af_ports.h new file mode 100644 index 00000000000..8bc4adc9b75 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_af_ports.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efm32pg12b_af_ports.h + * @brief EFM32PG12B_AF_PORTS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_AF_Ports + * @{ + *****************************************************************************/ + +/** AF port number for location number i */ +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 0 : -1) +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1) +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1) +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1) +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1) +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC3_PORT(i) (-1) +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI3_PORT(i) (-1) +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CDTI0_PORT(i) (-1) +#define AF_TIMER1_CDTI1_PORT(i) (-1) +#define AF_TIMER1_CDTI2_PORT(i) (-1) +#define AF_TIMER1_CDTI3_PORT(i) (-1) +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 1 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 2 : (i) == 31 ? 2 : -1) +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CC3_PORT(i) (-1) +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER0_CDTI3_PORT(i) (-1) +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CDTI0_PORT(i) (-1) +#define AF_WTIMER1_CDTI1_PORT(i) (-1) +#define AF_WTIMER1_CDTI2_PORT(i) (-1) +#define AF_WTIMER1_CDTI3_PORT(i) (-1) +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 8 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 5 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : (i) == 8 ? 8 : (i) == 9 ? 8 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 9 : (i) == 17 ? 9 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 9 : (i) == 16 ? 9 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 3 : -1) +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 9 : (i) == 15 ? 9 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 9 : (i) == 14 ? 9 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 9 : (i) == 13 ? 9 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1) +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) + +/** @} End of group EFM32PG12B_AF_Ports */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_cmu.h new file mode 100644 index 00000000000..6dac0d32cb6 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_cmu.h @@ -0,0 +1,2032 @@ +/**************************************************************************//** + * @file efm32pg12b_cmu.h + * @brief EFM32PG12B_CMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_CMU + * @{ + * @brief EFM32PG12B_CMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CMU Control Register */ + + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + + uint32_t RESERVED9[1]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED10[1]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED11[3]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + + uint32_t RESERVED12[7]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[1]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + + uint32_t RESERVED14[1]; /**< Reserved for future use **/ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED15[3]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + + uint32_t RESERVED16[1]; /**< Reserved for future use **/ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED17[1]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + + uint32_t RESERVED18[2]; /**< Reserved for future use **/ + __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED19[1]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED20[1]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect */ + + uint32_t RESERVED21[3]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED22[2]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED23[2]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED24[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED25[1]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_CMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x001101EFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x1E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable duty cycling of vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable comparator chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable dynamic element matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x37000731UL /**< Mask for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE (0x1UL << 0) /**< HFXO Mode */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low power mode control. PSR performance is reduced to enable low current consumption. */ +#define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */ +#define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */ +#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N pin to ground when HFXO oscillator is off. */ +#define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */ +#define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */ +#define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P pin to ground when HFXO oscillator is off. */ +#define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */ +#define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */ +#define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00050020UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FF87FUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30B4507UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000168UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24 /**< Shift value for CMU_REGSELILOW */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables oscillator peak detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28 /**< Shift value for CMU_REGISHUPPER */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHUPPER */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0002A067UL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FF0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16 /**< Shift value for CMU_SHUNTOPTTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL /**< Bit mask for CMU_SHUNTOPTTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000001FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< automatic recovery ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0x70UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x000033FFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000033UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5) /**< HFXO Shunt Current Optimization Start */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5 /**< Shift value for CMU_HFXOSHUNTOPTSTART */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL /**< Bit mask for CMU_HFXOSHUNTOPTSTART */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000001UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x1UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x07E133FFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required by Hardware (e.g. RAC) */ +#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization ready */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO oscillation amplitude is too high */ +#define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */ +#define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */ +#define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO amplitude tuning value too low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO regulator shunt current too low */ +#define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */ +#define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */ +#define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ +#define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ +#define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x8003FF7FUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETERR (0x1UL << 10) /**< HFXO Automatic Peak Detection Error Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */ +#define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0x8003FF7FUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10) /**< Set HFXOPEAKDETERR Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Set HFXOSHUNTOPTRDY Interrupt Flag */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0x8003FF7FUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10) /**< Clear HFXOPEAKDETERR Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x8003FF7FUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10) /**< HFXOPEAKDETERR Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXOSHUNTOPTRDY Interrupt Enable */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x0000007FUL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 0) /**< Advanced Encryption Standard Accelerator 0 Clock Enable */ +#define CMU_HFBUSCLKEN0_CRYPTO CMU_HFBUSCLKEN0_CRYPTO0 /**< Alias for CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 0 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x1UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT /**< Alias for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_MASK _CMU_HFBUSCLKEN0_CRYPTO0_MASK /**< Alias for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT*/ +#define CMU_HFBUSCLKEN0_CRYPTO1 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator 1 Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT 1 /**< Shift value for CMU_CRYPTO1 */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_MASK 0x2UL /**< Bit mask for CMU_CRYPTO1 */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 3) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 3 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x8UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 4) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 4 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x10UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 5) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 5 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x20UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 6) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 6 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x40UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER0 (0x1UL << 2) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_WTIMER0_SHIFT 2 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN0_WTIMER0_MASK 0x4UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN0_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER0_DEFAULT (_CMU_HFPERCLKEN0_WTIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER1 (0x1UL << 3) /**< Wide Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_WTIMER1_SHIFT 3 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN0_WTIMER1_MASK 0x8UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN0_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER1_DEFAULT (_CMU_HFPERCLKEN0_WTIMER1_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 4 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x10UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 5) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 5 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x20UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 6) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 6 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x40UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 7 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x80UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 8) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 8 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x100UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 9) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 9 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x200UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 10) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 10 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x400UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 11) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 11 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x800UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 12) /**< CryoTimer Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 12 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x1000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 13) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 13 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x2000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 14) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 14 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x4000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_VDAC0 (0x1UL << 15) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_VDAC0_SHIFT 15 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN0_VDAC0_MASK 0x8000UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_VDAC0_DEFAULT (_CMU_HFPERCLKEN0_VDAC0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CSEN (0x1UL << 16) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN0_CSEN_SHIFT 16 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN0_CSEN_MASK 0x10000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CSEN_DEFAULT (_CMU_HFPERCLKEN0_CSEN_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 17) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 17 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x20000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 1) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 1 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x2UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 0) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x1UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 1) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 1 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x2UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 2) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 2 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x4UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x01001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x0000003FUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 4 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x30UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x0000033FUL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xFUL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 4 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x30UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 8 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x300UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x3F050055UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x00000130UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert clock selected by ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000003UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00000707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} End of group EFM32PG12B_CMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_cryotimer.h new file mode 100644 index 00000000000..90b5be3765f --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_cryotimer.h @@ -0,0 +1,167 @@ +/**************************************************************************//** + * @file efm32pg12b_cryotimer.h + * @brief EFM32PG12B_CRYOTIMER register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_CRYOTIMER + * @{ + * @brief EFM32PG12B_CRYOTIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t PERIODSEL; /**< Interrupt Duration */ + __IM uint32_t CNT; /**< Counter Value */ + __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} CRYOTIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_CRYOTIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CRYOTIMER CTRL */ +#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_MASK 0x000000EFUL /**< Mask for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */ +#define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */ +#define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */ +#define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */ +#define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */ +#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */ +#define _CRYOTIMER_CTRL_OSCSEL_MASK 0xCUL /**< Bit mask for CRYOTIMER_OSCSEL */ +#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000002UL /**< Mode LFXO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_DISABLED (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2) /**< Shifted mode DISABLED for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */ +#define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */ +#define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */ + +/* Bit fields for CRYOTIMER PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */ +#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */ + +/* Bit fields for CRYOTIMER CNT */ +#define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */ +#define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */ + +/* Bit fields for CRYOTIMER EM4WUEN */ +#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */ +#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */ +#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */ +#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */ +#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */ +#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */ +#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */ + +/* Bit fields for CRYOTIMER IF */ +#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */ +#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */ +#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup event/Interrupt */ +#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */ +#define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */ + +/* Bit fields for CRYOTIMER IFS */ +#define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */ +#define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */ +#define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */ +#define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */ +#define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */ + +/* Bit fields for CRYOTIMER IFC */ +#define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */ +#define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */ +#define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */ +#define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */ +#define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */ + +/* Bit fields for CRYOTIMER IEN */ +#define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */ +#define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */ +#define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */ +#define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */ +#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */ + +/** @} End of group EFM32PG12B_CRYOTIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_crypto.h new file mode 100644 index 00000000000..1b88ff64787 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_crypto.h @@ -0,0 +1,1216 @@ +/**************************************************************************//** + * @file efm32pg12b_crypto.h + * @brief EFM32PG12B_CRYPTO register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_CRYPTO + * @{ + * @brief EFM32PG12B_CRYPTO Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t WAC; /**< Wide Arithmetic Configuration */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t DSTATUS; /**< Data Status Register */ + __IM uint32_t CSTATUS; /**< Control Status Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t KEY; /**< KEY Register Access */ + __IOM uint32_t KEYBUF; /**< KEY Buffer Register Access */ + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IOM uint32_t SEQCTRL; /**< Sequence Control */ + __IOM uint32_t SEQCTRLB; /**< Sequence Control B */ + uint32_t RESERVED3[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< AES Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t SEQ0; /**< Sequence register 0 */ + __IOM uint32_t SEQ1; /**< Sequence Register 1 */ + __IOM uint32_t SEQ2; /**< Sequence Register 2 */ + __IOM uint32_t SEQ3; /**< Sequence Register 3 */ + __IOM uint32_t SEQ4; /**< Sequence Register 4 */ + uint32_t RESERVED4[7]; /**< Reserved for future use **/ + __IOM uint32_t DATA0; /**< DATA0 Register Access */ + __IOM uint32_t DATA1; /**< DATA1 Register Access */ + __IOM uint32_t DATA2; /**< DATA2 Register Access */ + __IOM uint32_t DATA3; /**< DATA3 Register Access */ + uint32_t RESERVED5[4]; /**< Reserved for future use **/ + __IOM uint32_t DATA0XOR; /**< DATA0XOR Register Access */ + uint32_t RESERVED6[3]; /**< Reserved for future use **/ + __IOM uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */ + __IOM uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IOM uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */ + __IOM uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */ + __IOM uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */ + __IOM uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */ + __IOM uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */ + uint32_t RESERVED8[12]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0; /**< DDATA0 Register Access */ + __IOM uint32_t DDATA1; /**< DDATA1 Register Access */ + __IOM uint32_t DDATA2; /**< DDATA2 Register Access */ + __IOM uint32_t DDATA3; /**< DDATA3 Register Access */ + __IOM uint32_t DDATA4; /**< DDATA4 Register Access */ + uint32_t RESERVED9[7]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */ + uint32_t RESERVED10[3]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */ + __IOM uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */ + __IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 access. */ + uint32_t RESERVED11[13]; /**< Reserved for future use **/ + __IOM uint32_t QDATA0; /**< QDATA0 Register Access */ + __IOM uint32_t QDATA1; /**< QDATA1 Register Access */ + uint32_t RESERVED12[7]; /**< Reserved for future use **/ + __IOM uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */ + uint32_t RESERVED13[6]; /**< Reserved for future use **/ + __IOM uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */ + __IOM uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */ +} CRYPTO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_CRYPTO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CRYPTO CTRL */ +#define _CRYPTO_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_MASK 0xB333C407UL /**< Mask for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES (0x1UL << 0) /**< AES Mode */ +#define _CRYPTO_CTRL_AES_SHIFT 0 /**< Shift value for CRYPTO_AES */ +#define _CRYPTO_CTRL_AES_MASK 0x1UL /**< Bit mask for CRYPTO_AES */ +#define _CRYPTO_CTRL_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_AES_AES128 0x00000000UL /**< Mode AES128 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_AES_AES256 0x00000001UL /**< Mode AES256 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_DEFAULT (_CRYPTO_CTRL_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_AES128 (_CRYPTO_CTRL_AES_AES128 << 0) /**< Shifted mode AES128 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_AES256 (_CRYPTO_CTRL_AES_AES256 << 0) /**< Shifted mode AES256 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_KEYBUFDIS (0x1UL << 1) /**< Key Buffer Disable */ +#define _CRYPTO_CTRL_KEYBUFDIS_SHIFT 1 /**< Shift value for CRYPTO_KEYBUFDIS */ +#define _CRYPTO_CTRL_KEYBUFDIS_MASK 0x2UL /**< Bit mask for CRYPTO_KEYBUFDIS */ +#define _CRYPTO_CTRL_KEYBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_KEYBUFDIS_DEFAULT (_CRYPTO_CTRL_KEYBUFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA (0x1UL << 2) /**< SHA Mode */ +#define _CRYPTO_CTRL_SHA_SHIFT 2 /**< Shift value for CRYPTO_SHA */ +#define _CRYPTO_CTRL_SHA_MASK 0x4UL /**< Bit mask for CRYPTO_SHA */ +#define _CRYPTO_CTRL_SHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_SHA_SHA1 0x00000000UL /**< Mode SHA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_SHA_SHA2 0x00000001UL /**< Mode SHA2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_DEFAULT (_CRYPTO_CTRL_SHA_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_SHA1 (_CRYPTO_CTRL_SHA_SHA1 << 2) /**< Shifted mode SHA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_SHA2 (_CRYPTO_CTRL_SHA_SHA2 << 2) /**< Shifted mode SHA2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_NOBUSYSTALL (0x1UL << 10) /**< No Stalling of Bus When Busy */ +#define _CRYPTO_CTRL_NOBUSYSTALL_SHIFT 10 /**< Shift value for CRYPTO_NOBUSYSTALL */ +#define _CRYPTO_CTRL_NOBUSYSTALL_MASK 0x400UL /**< Bit mask for CRYPTO_NOBUSYSTALL */ +#define _CRYPTO_CTRL_NOBUSYSTALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_NOBUSYSTALL_DEFAULT (_CRYPTO_CTRL_NOBUSYSTALL_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_SHIFT 14 /**< Shift value for CRYPTO_INCWIDTH */ +#define _CRYPTO_CTRL_INCWIDTH_MASK 0xC000UL /**< Bit mask for CRYPTO_INCWIDTH */ +#define _CRYPTO_CTRL_INCWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH1 0x00000000UL /**< Mode INCWIDTH1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH2 0x00000001UL /**< Mode INCWIDTH2 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH3 0x00000002UL /**< Mode INCWIDTH3 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH4 0x00000003UL /**< Mode INCWIDTH4 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_DEFAULT (_CRYPTO_CTRL_INCWIDTH_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH1 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH1 << 14) /**< Shifted mode INCWIDTH1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH2 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH2 << 14) /**< Shifted mode INCWIDTH2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH3 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH3 << 14) /**< Shifted mode INCWIDTH3 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH4 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH4 << 14) /**< Shifted mode INCWIDTH4 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_SHIFT 16 /**< Shift value for CRYPTO_DMA0MODE */ +#define _CRYPTO_CTRL_DMA0MODE_MASK 0x30000UL /**< Bit mask for CRYPTO_DMA0MODE */ +#define _CRYPTO_CTRL_DMA0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_DEFAULT (_CRYPTO_CTRL_DMA0MODE_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_FULL (_CRYPTO_CTRL_DMA0MODE_FULL << 16) /**< Shifted mode FULL for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_LENLIMIT (_CRYPTO_CTRL_DMA0MODE_LENLIMIT << 16) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_FULLBYTE (_CRYPTO_CTRL_DMA0MODE_FULLBYTE << 16) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE << 16) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_SHIFT 20 /**< Shift value for CRYPTO_DMA0RSEL */ +#define _CRYPTO_CTRL_DMA0RSEL_MASK 0x300000UL /**< Bit mask for CRYPTO_DMA0RSEL */ +#define _CRYPTO_CTRL_DMA0RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DATA0 0x00000000UL /**< Mode DATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DDATA0 0x00000001UL /**< Mode DDATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DDATA0BIG 0x00000002UL /**< Mode DDATA0BIG for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_QDATA0 0x00000003UL /**< Mode QDATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DEFAULT (_CRYPTO_CTRL_DMA0RSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DATA0 (_CRYPTO_CTRL_DMA0RSEL_DATA0 << 20) /**< Shifted mode DATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DDATA0 (_CRYPTO_CTRL_DMA0RSEL_DDATA0 << 20) /**< Shifted mode DDATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DDATA0BIG (_CRYPTO_CTRL_DMA0RSEL_DDATA0BIG << 20) /**< Shifted mode DDATA0BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_QDATA0 (_CRYPTO_CTRL_DMA0RSEL_QDATA0 << 20) /**< Shifted mode QDATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_SHIFT 24 /**< Shift value for CRYPTO_DMA1MODE */ +#define _CRYPTO_CTRL_DMA1MODE_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA1MODE */ +#define _CRYPTO_CTRL_DMA1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_DEFAULT (_CRYPTO_CTRL_DMA1MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_FULL (_CRYPTO_CTRL_DMA1MODE_FULL << 24) /**< Shifted mode FULL for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_LENLIMIT (_CRYPTO_CTRL_DMA1MODE_LENLIMIT << 24) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_FULLBYTE (_CRYPTO_CTRL_DMA1MODE_FULLBYTE << 24) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE << 24) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_SHIFT 28 /**< Shift value for CRYPTO_DMA1RSEL */ +#define _CRYPTO_CTRL_DMA1RSEL_MASK 0x30000000UL /**< Bit mask for CRYPTO_DMA1RSEL */ +#define _CRYPTO_CTRL_DMA1RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_DATA1 0x00000000UL /**< Mode DATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_QDATA1 0x00000002UL /**< Mode QDATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_QDATA1BIG 0x00000003UL /**< Mode QDATA1BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DEFAULT (_CRYPTO_CTRL_DMA1RSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DATA1 (_CRYPTO_CTRL_DMA1RSEL_DATA1 << 28) /**< Shifted mode DATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DDATA1 (_CRYPTO_CTRL_DMA1RSEL_DDATA1 << 28) /**< Shifted mode DDATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_QDATA1 (_CRYPTO_CTRL_DMA1RSEL_QDATA1 << 28) /**< Shifted mode QDATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_QDATA1BIG (_CRYPTO_CTRL_DMA1RSEL_QDATA1BIG << 28) /**< Shifted mode QDATA1BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_COMBDMA0WEREQ (0x1UL << 31) /**< Combined Data0 Write DMA Request */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_SHIFT 31 /**< Shift value for CRYPTO_COMBDMA0WEREQ */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_MASK 0x80000000UL /**< Bit mask for CRYPTO_COMBDMA0WEREQ */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT (_CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ + +/* Bit fields for CRYPTO WAC */ +#define _CRYPTO_WAC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_WAC */ +#define _CRYPTO_WAC_MASK 0x00000F1FUL /**< Mask for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_SHIFT 0 /**< Shift value for CRYPTO_MODULUS */ +#define _CRYPTO_WAC_MODULUS_MASK 0xFUL /**< Bit mask for CRYPTO_MODULUS */ +#define _CRYPTO_WAC_MODULUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_BIN256 0x00000000UL /**< Mode BIN256 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_BIN128 0x00000001UL /**< Mode BIN128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233P 0x00000002UL /**< Mode ECCBIN233P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163P 0x00000003UL /**< Mode ECCBIN163P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_GCMBIN128 0x00000004UL /**< Mode GCMBIN128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME256P 0x00000005UL /**< Mode ECCPRIME256P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME224P 0x00000006UL /**< Mode ECCPRIME224P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME192P 0x00000007UL /**< Mode ECCPRIME192P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233N 0x00000008UL /**< Mode ECCBIN233N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233KN 0x00000009UL /**< Mode ECCBIN233KN for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163N 0x0000000AUL /**< Mode ECCBIN163N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163KN 0x0000000BUL /**< Mode ECCBIN163KN for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME256N 0x0000000CUL /**< Mode ECCPRIME256N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME224N 0x0000000DUL /**< Mode ECCPRIME224N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME192N 0x0000000EUL /**< Mode ECCPRIME192N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_DEFAULT (_CRYPTO_WAC_MODULUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_BIN256 (_CRYPTO_WAC_MODULUS_BIN256 << 0) /**< Shifted mode BIN256 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_BIN128 (_CRYPTO_WAC_MODULUS_BIN128 << 0) /**< Shifted mode BIN128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233P (_CRYPTO_WAC_MODULUS_ECCBIN233P << 0) /**< Shifted mode ECCBIN233P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163P (_CRYPTO_WAC_MODULUS_ECCBIN163P << 0) /**< Shifted mode ECCBIN163P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_GCMBIN128 (_CRYPTO_WAC_MODULUS_GCMBIN128 << 0) /**< Shifted mode GCMBIN128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME256P (_CRYPTO_WAC_MODULUS_ECCPRIME256P << 0) /**< Shifted mode ECCPRIME256P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME224P (_CRYPTO_WAC_MODULUS_ECCPRIME224P << 0) /**< Shifted mode ECCPRIME224P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME192P (_CRYPTO_WAC_MODULUS_ECCPRIME192P << 0) /**< Shifted mode ECCPRIME192P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233N (_CRYPTO_WAC_MODULUS_ECCBIN233N << 0) /**< Shifted mode ECCBIN233N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233KN (_CRYPTO_WAC_MODULUS_ECCBIN233KN << 0) /**< Shifted mode ECCBIN233KN for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163N (_CRYPTO_WAC_MODULUS_ECCBIN163N << 0) /**< Shifted mode ECCBIN163N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163KN (_CRYPTO_WAC_MODULUS_ECCBIN163KN << 0) /**< Shifted mode ECCBIN163KN for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME256N (_CRYPTO_WAC_MODULUS_ECCPRIME256N << 0) /**< Shifted mode ECCPRIME256N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME224N (_CRYPTO_WAC_MODULUS_ECCPRIME224N << 0) /**< Shifted mode ECCPRIME224N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME192N (_CRYPTO_WAC_MODULUS_ECCPRIME192N << 0) /**< Shifted mode ECCPRIME192N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP (0x1UL << 4) /**< Modular Operation Field Type */ +#define _CRYPTO_WAC_MODOP_SHIFT 4 /**< Shift value for CRYPTO_MODOP */ +#define _CRYPTO_WAC_MODOP_MASK 0x10UL /**< Bit mask for CRYPTO_MODOP */ +#define _CRYPTO_WAC_MODOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODOP_BINARY 0x00000000UL /**< Mode BINARY for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODOP_REGULAR 0x00000001UL /**< Mode REGULAR for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_DEFAULT (_CRYPTO_WAC_MODOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_BINARY (_CRYPTO_WAC_MODOP_BINARY << 4) /**< Shifted mode BINARY for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_REGULAR (_CRYPTO_WAC_MODOP_REGULAR << 4) /**< Shifted mode REGULAR for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_SHIFT 8 /**< Shift value for CRYPTO_MULWIDTH */ +#define _CRYPTO_WAC_MULWIDTH_MASK 0x300UL /**< Bit mask for CRYPTO_MULWIDTH */ +#define _CRYPTO_WAC_MULWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MUL256 0x00000000UL /**< Mode MUL256 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MUL128 0x00000001UL /**< Mode MUL128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MULMOD 0x00000002UL /**< Mode MULMOD for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_DEFAULT (_CRYPTO_WAC_MULWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MUL256 (_CRYPTO_WAC_MULWIDTH_MUL256 << 8) /**< Shifted mode MUL256 for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MUL128 (_CRYPTO_WAC_MULWIDTH_MUL128 << 8) /**< Shifted mode MUL128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MULMOD (_CRYPTO_WAC_MULWIDTH_MULMOD << 8) /**< Shifted mode MULMOD for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_SHIFT 10 /**< Shift value for CRYPTO_RESULTWIDTH */ +#define _CRYPTO_WAC_RESULTWIDTH_MASK 0xC00UL /**< Bit mask for CRYPTO_RESULTWIDTH */ +#define _CRYPTO_WAC_RESULTWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_256BIT 0x00000000UL /**< Mode 256BIT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_128BIT 0x00000001UL /**< Mode 128BIT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_260BIT 0x00000002UL /**< Mode 260BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_DEFAULT (_CRYPTO_WAC_RESULTWIDTH_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_256BIT (_CRYPTO_WAC_RESULTWIDTH_256BIT << 10) /**< Shifted mode 256BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_128BIT (_CRYPTO_WAC_RESULTWIDTH_128BIT << 10) /**< Shifted mode 128BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_260BIT (_CRYPTO_WAC_RESULTWIDTH_260BIT << 10) /**< Shifted mode 260BIT for CRYPTO_WAC */ + +/* Bit fields for CRYPTO CMD */ +#define _CRYPTO_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CMD */ +#define _CRYPTO_CMD_MASK 0x00000EFFUL /**< Mask for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHIFT 0 /**< Shift value for CRYPTO_INSTR */ +#define _CRYPTO_CMD_INSTR_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR */ +#define _CRYPTO_CMD_INSTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_END 0x00000000UL /**< Mode END for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXEC 0x00000001UL /**< Mode EXEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1INC 0x00000003UL /**< Mode DATA1INC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1INCCLR 0x00000004UL /**< Mode DATA1INCCLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_AESENC 0x00000005UL /**< Mode AESENC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_AESDEC 0x00000006UL /**< Mode AESDEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHA 0x00000007UL /**< Mode SHA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADD 0x00000008UL /**< Mode ADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDC 0x00000009UL /**< Mode ADDC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADD 0x0000000AUL /**< Mode LADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDC 0x0000000BUL /**< Mode LADDC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MADD 0x0000000CUL /**< Mode MADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MADD32 0x0000000DUL /**< Mode MADD32 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SUB 0x00000010UL /**< Mode SUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SUBC 0x00000011UL /**< Mode SUBC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LSUB 0x00000012UL /**< Mode LSUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LSUBC 0x00000013UL /**< Mode LSUBC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MSUB 0x00000014UL /**< Mode MSUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MUL 0x00000018UL /**< Mode MUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MULC 0x00000019UL /**< Mode MULC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LMUL 0x0000001AUL /**< Mode LMUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MMUL 0x0000001CUL /**< Mode MMUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MULO 0x0000001DUL /**< Mode MULO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LMULO 0x0000001FUL /**< Mode LMULO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHL 0x00000020UL /**< Mode SHL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHLC 0x00000021UL /**< Mode SHLC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHLB 0x00000022UL /**< Mode SHLB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHL1 0x00000023UL /**< Mode SHL1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHR 0x00000024UL /**< Mode SHR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRC 0x00000025UL /**< Mode SHRC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRB 0x00000026UL /**< Mode SHRB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHR1 0x00000027UL /**< Mode SHR1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDO 0x00000028UL /**< Mode ADDO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDIC 0x00000029UL /**< Mode ADDIC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDO 0x0000002AUL /**< Mode LADDO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDIC 0x0000002BUL /**< Mode LADDIC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CLR 0x00000030UL /**< Mode CLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_XOR 0x00000031UL /**< Mode XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_INV 0x00000032UL /**< Mode INV for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CSET 0x00000034UL /**< Mode CSET for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CCLR 0x00000035UL /**< Mode CCLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BBSWAP128 0x00000036UL /**< Mode BBSWAP128 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_INC 0x00000038UL /**< Mode INC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DEC 0x00000039UL /**< Mode DEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LINC 0x0000003AUL /**< Mode LINC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LDEC 0x0000003BUL /**< Mode LDEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRA 0x0000003EUL /**< Mode SHRA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0 0x00000040UL /**< Mode DATA0TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0XOR 0x00000041UL /**< Mode DATA0TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN 0x00000042UL /**< Mode DATA0TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA1 0x00000044UL /**< Mode DATA0TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA2 0x00000045UL /**< Mode DATA0TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA3 0x00000046UL /**< Mode DATA0TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0 0x00000048UL /**< Mode DATA1TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0XOR 0x00000049UL /**< Mode DATA1TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN 0x0000004AUL /**< Mode DATA1TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA2 0x0000004DUL /**< Mode DATA1TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA3 0x0000004EUL /**< Mode DATA1TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0 0x00000050UL /**< Mode DATA2TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0XOR 0x00000051UL /**< Mode DATA2TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN 0x00000052UL /**< Mode DATA2TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA1 0x00000054UL /**< Mode DATA2TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA3 0x00000056UL /**< Mode DATA2TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0 0x00000058UL /**< Mode DATA3TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0XOR 0x00000059UL /**< Mode DATA3TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN 0x0000005AUL /**< Mode DATA3TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA1 0x0000005CUL /**< Mode DATA3TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA2 0x0000005DUL /**< Mode DATA3TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATATODMA0 0x00000063UL /**< Mode DATATODMA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TOBUF 0x00000064UL /**< Mode DATA0TOBUF for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TOBUFXOR 0x00000065UL /**< Mode DATA0TOBUFXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATATODMA1 0x0000006BUL /**< Mode DATATODMA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TOBUF 0x0000006CUL /**< Mode DATA1TOBUF for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TOBUFXOR 0x0000006DUL /**< Mode DATA1TOBUFXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA0TODATA 0x00000070UL /**< Mode DMA0TODATA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA0TODATAXOR 0x00000071UL /**< Mode DMA0TODATAXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA1TODATA 0x00000072UL /**< Mode DMA1TODATA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA0 0x00000078UL /**< Mode BUFTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA0XOR 0x00000079UL /**< Mode BUFTODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA1 0x0000007AUL /**< Mode BUFTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA1 0x00000081UL /**< Mode DDATA0TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA2 0x00000082UL /**< Mode DDATA0TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA3 0x00000083UL /**< Mode DDATA0TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA4 0x00000084UL /**< Mode DDATA0TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0LTODATA0 0x00000085UL /**< Mode DDATA0LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0HTODATA1 0x00000086UL /**< Mode DDATA0HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0LTODATA2 0x00000087UL /**< Mode DDATA0LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA0 0x00000088UL /**< Mode DDATA1TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA2 0x0000008AUL /**< Mode DDATA1TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA3 0x0000008BUL /**< Mode DDATA1TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA4 0x0000008CUL /**< Mode DDATA1TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1LTODATA0 0x0000008DUL /**< Mode DDATA1LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1HTODATA1 0x0000008EUL /**< Mode DDATA1HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1LTODATA2 0x0000008FUL /**< Mode DDATA1LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA0 0x00000090UL /**< Mode DDATA2TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA1 0x00000091UL /**< Mode DDATA2TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA3 0x00000093UL /**< Mode DDATA2TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA4 0x00000094UL /**< Mode DDATA2TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2LTODATA2 0x00000097UL /**< Mode DDATA2LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA0 0x00000098UL /**< Mode DDATA3TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA1 0x00000099UL /**< Mode DDATA3TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA2 0x0000009AUL /**< Mode DDATA3TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA4 0x0000009CUL /**< Mode DDATA3TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3LTODATA0 0x0000009DUL /**< Mode DDATA3LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3HTODATA1 0x0000009EUL /**< Mode DDATA3HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA0 0x000000A0UL /**< Mode DDATA4TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA1 0x000000A1UL /**< Mode DDATA4TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA2 0x000000A2UL /**< Mode DDATA4TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA3 0x000000A3UL /**< Mode DDATA4TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4LTODATA0 0x000000A5UL /**< Mode DDATA4LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4HTODATA1 0x000000A6UL /**< Mode DDATA4HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4LTODATA2 0x000000A7UL /**< Mode DDATA4LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODDATA0 0x000000A8UL /**< Mode DATA0TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODDATA1 0x000000A9UL /**< Mode DATA0TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODDATA0 0x000000B0UL /**< Mode DATA1TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODDATA1 0x000000B1UL /**< Mode DATA1TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA0 0x000000B8UL /**< Mode DATA2TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA1 0x000000B9UL /**< Mode DATA2TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA2 0x000000BAUL /**< Mode DATA2TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA0 0x000000C0UL /**< Mode SELDDATA0DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA0 0x000000C1UL /**< Mode SELDDATA1DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA0 0x000000C2UL /**< Mode SELDDATA2DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA0 0x000000C3UL /**< Mode SELDDATA3DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA0 0x000000C4UL /**< Mode SELDDATA4DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA0 0x000000C5UL /**< Mode SELDATA0DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA0 0x000000C6UL /**< Mode SELDATA1DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA0 0x000000C7UL /**< Mode SELDATA2DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA1 0x000000C8UL /**< Mode SELDDATA0DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA1 0x000000C9UL /**< Mode SELDDATA1DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA1 0x000000CAUL /**< Mode SELDDATA2DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA1 0x000000CBUL /**< Mode SELDDATA3DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA1 0x000000CCUL /**< Mode SELDDATA4DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA1 0x000000CDUL /**< Mode SELDATA0DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA1 0x000000CEUL /**< Mode SELDATA1DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA1 0x000000CFUL /**< Mode SELDATA2DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA2 0x000000D0UL /**< Mode SELDDATA0DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA2 0x000000D1UL /**< Mode SELDDATA1DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA2 0x000000D2UL /**< Mode SELDDATA2DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA2 0x000000D3UL /**< Mode SELDDATA3DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA2 0x000000D4UL /**< Mode SELDDATA4DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA2 0x000000D5UL /**< Mode SELDATA0DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA2 0x000000D6UL /**< Mode SELDATA1DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA2 0x000000D7UL /**< Mode SELDATA2DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA3 0x000000D8UL /**< Mode SELDDATA0DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA3 0x000000D9UL /**< Mode SELDDATA1DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA3 0x000000DAUL /**< Mode SELDDATA2DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA3 0x000000DBUL /**< Mode SELDDATA3DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA3 0x000000DCUL /**< Mode SELDDATA4DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA3 0x000000DDUL /**< Mode SELDATA0DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA3 0x000000DEUL /**< Mode SELDATA1DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA3 0x000000DFUL /**< Mode SELDATA2DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA4 0x000000E0UL /**< Mode SELDDATA0DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA4 0x000000E1UL /**< Mode SELDDATA1DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA4 0x000000E2UL /**< Mode SELDDATA2DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA4 0x000000E3UL /**< Mode SELDDATA3DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA4 0x000000E4UL /**< Mode SELDDATA4DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA4 0x000000E5UL /**< Mode SELDATA0DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA4 0x000000E6UL /**< Mode SELDATA1DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA4 0x000000E7UL /**< Mode SELDATA2DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DATA0 0x000000E8UL /**< Mode SELDDATA0DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DATA0 0x000000E9UL /**< Mode SELDDATA1DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DATA0 0x000000EAUL /**< Mode SELDDATA2DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DATA0 0x000000EBUL /**< Mode SELDDATA3DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DATA0 0x000000ECUL /**< Mode SELDDATA4DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DATA0 0x000000EDUL /**< Mode SELDATA0DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DATA0 0x000000EEUL /**< Mode SELDATA1DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DATA0 0x000000EFUL /**< Mode SELDATA2DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DATA1 0x000000F0UL /**< Mode SELDDATA0DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DATA1 0x000000F1UL /**< Mode SELDDATA1DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DATA1 0x000000F2UL /**< Mode SELDDATA2DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DATA1 0x000000F3UL /**< Mode SELDDATA3DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DATA1 0x000000F4UL /**< Mode SELDDATA4DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DATA1 0x000000F5UL /**< Mode SELDATA0DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DATA1 0x000000F6UL /**< Mode SELDATA1DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DATA1 0x000000F7UL /**< Mode SELDATA2DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFA 0x000000F8UL /**< Mode EXECIFA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFB 0x000000F9UL /**< Mode EXECIFB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFNLAST 0x000000FAUL /**< Mode EXECIFNLAST for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFLAST 0x000000FBUL /**< Mode EXECIFLAST for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFCARRY 0x000000FCUL /**< Mode EXECIFCARRY for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFNCARRY 0x000000FDUL /**< Mode EXECIFNCARRY for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECALWAYS 0x000000FEUL /**< Mode EXECALWAYS for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DEFAULT (_CRYPTO_CMD_INSTR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_END (_CRYPTO_CMD_INSTR_END << 0) /**< Shifted mode END for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXEC (_CRYPTO_CMD_INSTR_EXEC << 0) /**< Shifted mode EXEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1INC (_CRYPTO_CMD_INSTR_DATA1INC << 0) /**< Shifted mode DATA1INC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1INCCLR (_CRYPTO_CMD_INSTR_DATA1INCCLR << 0) /**< Shifted mode DATA1INCCLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_AESENC (_CRYPTO_CMD_INSTR_AESENC << 0) /**< Shifted mode AESENC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_AESDEC (_CRYPTO_CMD_INSTR_AESDEC << 0) /**< Shifted mode AESDEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHA (_CRYPTO_CMD_INSTR_SHA << 0) /**< Shifted mode SHA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADD (_CRYPTO_CMD_INSTR_ADD << 0) /**< Shifted mode ADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDC (_CRYPTO_CMD_INSTR_ADDC << 0) /**< Shifted mode ADDC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADD (_CRYPTO_CMD_INSTR_LADD << 0) /**< Shifted mode LADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDC (_CRYPTO_CMD_INSTR_LADDC << 0) /**< Shifted mode LADDC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MADD (_CRYPTO_CMD_INSTR_MADD << 0) /**< Shifted mode MADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MADD32 (_CRYPTO_CMD_INSTR_MADD32 << 0) /**< Shifted mode MADD32 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SUB (_CRYPTO_CMD_INSTR_SUB << 0) /**< Shifted mode SUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SUBC (_CRYPTO_CMD_INSTR_SUBC << 0) /**< Shifted mode SUBC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LSUB (_CRYPTO_CMD_INSTR_LSUB << 0) /**< Shifted mode LSUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LSUBC (_CRYPTO_CMD_INSTR_LSUBC << 0) /**< Shifted mode LSUBC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MSUB (_CRYPTO_CMD_INSTR_MSUB << 0) /**< Shifted mode MSUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MUL (_CRYPTO_CMD_INSTR_MUL << 0) /**< Shifted mode MUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MULC (_CRYPTO_CMD_INSTR_MULC << 0) /**< Shifted mode MULC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LMUL (_CRYPTO_CMD_INSTR_LMUL << 0) /**< Shifted mode LMUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MMUL (_CRYPTO_CMD_INSTR_MMUL << 0) /**< Shifted mode MMUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MULO (_CRYPTO_CMD_INSTR_MULO << 0) /**< Shifted mode MULO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LMULO (_CRYPTO_CMD_INSTR_LMULO << 0) /**< Shifted mode LMULO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHL (_CRYPTO_CMD_INSTR_SHL << 0) /**< Shifted mode SHL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHLC (_CRYPTO_CMD_INSTR_SHLC << 0) /**< Shifted mode SHLC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHLB (_CRYPTO_CMD_INSTR_SHLB << 0) /**< Shifted mode SHLB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHL1 (_CRYPTO_CMD_INSTR_SHL1 << 0) /**< Shifted mode SHL1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHR (_CRYPTO_CMD_INSTR_SHR << 0) /**< Shifted mode SHR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRC (_CRYPTO_CMD_INSTR_SHRC << 0) /**< Shifted mode SHRC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRB (_CRYPTO_CMD_INSTR_SHRB << 0) /**< Shifted mode SHRB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHR1 (_CRYPTO_CMD_INSTR_SHR1 << 0) /**< Shifted mode SHR1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDO (_CRYPTO_CMD_INSTR_ADDO << 0) /**< Shifted mode ADDO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDIC (_CRYPTO_CMD_INSTR_ADDIC << 0) /**< Shifted mode ADDIC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDO (_CRYPTO_CMD_INSTR_LADDO << 0) /**< Shifted mode LADDO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDIC (_CRYPTO_CMD_INSTR_LADDIC << 0) /**< Shifted mode LADDIC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CLR (_CRYPTO_CMD_INSTR_CLR << 0) /**< Shifted mode CLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_XOR (_CRYPTO_CMD_INSTR_XOR << 0) /**< Shifted mode XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_INV (_CRYPTO_CMD_INSTR_INV << 0) /**< Shifted mode INV for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CSET (_CRYPTO_CMD_INSTR_CSET << 0) /**< Shifted mode CSET for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CCLR (_CRYPTO_CMD_INSTR_CCLR << 0) /**< Shifted mode CCLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BBSWAP128 (_CRYPTO_CMD_INSTR_BBSWAP128 << 0) /**< Shifted mode BBSWAP128 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_INC (_CRYPTO_CMD_INSTR_INC << 0) /**< Shifted mode INC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DEC (_CRYPTO_CMD_INSTR_DEC << 0) /**< Shifted mode DEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LINC (_CRYPTO_CMD_INSTR_LINC << 0) /**< Shifted mode LINC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LDEC (_CRYPTO_CMD_INSTR_LDEC << 0) /**< Shifted mode LDEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRA (_CRYPTO_CMD_INSTR_SHRA << 0) /**< Shifted mode SHRA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0 (_CRYPTO_CMD_INSTR_DATA0TODATA0 << 0) /**< Shifted mode DATA0TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0XOR (_CRYPTO_CMD_INSTR_DATA0TODATA0XOR << 0) /**< Shifted mode DATA0TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN << 0) /**< Shifted mode DATA0TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA1 (_CRYPTO_CMD_INSTR_DATA0TODATA1 << 0) /**< Shifted mode DATA0TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA2 (_CRYPTO_CMD_INSTR_DATA0TODATA2 << 0) /**< Shifted mode DATA0TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA3 (_CRYPTO_CMD_INSTR_DATA0TODATA3 << 0) /**< Shifted mode DATA0TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0 (_CRYPTO_CMD_INSTR_DATA1TODATA0 << 0) /**< Shifted mode DATA1TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0XOR (_CRYPTO_CMD_INSTR_DATA1TODATA0XOR << 0) /**< Shifted mode DATA1TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN << 0) /**< Shifted mode DATA1TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA2 (_CRYPTO_CMD_INSTR_DATA1TODATA2 << 0) /**< Shifted mode DATA1TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA3 (_CRYPTO_CMD_INSTR_DATA1TODATA3 << 0) /**< Shifted mode DATA1TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0 (_CRYPTO_CMD_INSTR_DATA2TODATA0 << 0) /**< Shifted mode DATA2TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0XOR (_CRYPTO_CMD_INSTR_DATA2TODATA0XOR << 0) /**< Shifted mode DATA2TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN << 0) /**< Shifted mode DATA2TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA1 (_CRYPTO_CMD_INSTR_DATA2TODATA1 << 0) /**< Shifted mode DATA2TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA3 (_CRYPTO_CMD_INSTR_DATA2TODATA3 << 0) /**< Shifted mode DATA2TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0 (_CRYPTO_CMD_INSTR_DATA3TODATA0 << 0) /**< Shifted mode DATA3TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0XOR (_CRYPTO_CMD_INSTR_DATA3TODATA0XOR << 0) /**< Shifted mode DATA3TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN << 0) /**< Shifted mode DATA3TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA1 (_CRYPTO_CMD_INSTR_DATA3TODATA1 << 0) /**< Shifted mode DATA3TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA2 (_CRYPTO_CMD_INSTR_DATA3TODATA2 << 0) /**< Shifted mode DATA3TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATATODMA0 (_CRYPTO_CMD_INSTR_DATATODMA0 << 0) /**< Shifted mode DATATODMA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TOBUF (_CRYPTO_CMD_INSTR_DATA0TOBUF << 0) /**< Shifted mode DATA0TOBUF for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TOBUFXOR (_CRYPTO_CMD_INSTR_DATA0TOBUFXOR << 0) /**< Shifted mode DATA0TOBUFXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATATODMA1 (_CRYPTO_CMD_INSTR_DATATODMA1 << 0) /**< Shifted mode DATATODMA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TOBUF (_CRYPTO_CMD_INSTR_DATA1TOBUF << 0) /**< Shifted mode DATA1TOBUF for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TOBUFXOR (_CRYPTO_CMD_INSTR_DATA1TOBUFXOR << 0) /**< Shifted mode DATA1TOBUFXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA0TODATA (_CRYPTO_CMD_INSTR_DMA0TODATA << 0) /**< Shifted mode DMA0TODATA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA0TODATAXOR (_CRYPTO_CMD_INSTR_DMA0TODATAXOR << 0) /**< Shifted mode DMA0TODATAXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA1TODATA (_CRYPTO_CMD_INSTR_DMA1TODATA << 0) /**< Shifted mode DMA1TODATA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA0 (_CRYPTO_CMD_INSTR_BUFTODATA0 << 0) /**< Shifted mode BUFTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA0XOR (_CRYPTO_CMD_INSTR_BUFTODATA0XOR << 0) /**< Shifted mode BUFTODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA1 (_CRYPTO_CMD_INSTR_BUFTODATA1 << 0) /**< Shifted mode BUFTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA1 (_CRYPTO_CMD_INSTR_DDATA0TODDATA1 << 0) /**< Shifted mode DDATA0TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA2 (_CRYPTO_CMD_INSTR_DDATA0TODDATA2 << 0) /**< Shifted mode DDATA0TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA3 (_CRYPTO_CMD_INSTR_DDATA0TODDATA3 << 0) /**< Shifted mode DDATA0TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA4 (_CRYPTO_CMD_INSTR_DDATA0TODDATA4 << 0) /**< Shifted mode DDATA0TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0LTODATA0 (_CRYPTO_CMD_INSTR_DDATA0LTODATA0 << 0) /**< Shifted mode DDATA0LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0HTODATA1 (_CRYPTO_CMD_INSTR_DDATA0HTODATA1 << 0) /**< Shifted mode DDATA0HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0LTODATA2 (_CRYPTO_CMD_INSTR_DDATA0LTODATA2 << 0) /**< Shifted mode DDATA0LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA0 (_CRYPTO_CMD_INSTR_DDATA1TODDATA0 << 0) /**< Shifted mode DDATA1TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA2 (_CRYPTO_CMD_INSTR_DDATA1TODDATA2 << 0) /**< Shifted mode DDATA1TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA3 (_CRYPTO_CMD_INSTR_DDATA1TODDATA3 << 0) /**< Shifted mode DDATA1TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA4 (_CRYPTO_CMD_INSTR_DDATA1TODDATA4 << 0) /**< Shifted mode DDATA1TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1LTODATA0 (_CRYPTO_CMD_INSTR_DDATA1LTODATA0 << 0) /**< Shifted mode DDATA1LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1HTODATA1 (_CRYPTO_CMD_INSTR_DDATA1HTODATA1 << 0) /**< Shifted mode DDATA1HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1LTODATA2 (_CRYPTO_CMD_INSTR_DDATA1LTODATA2 << 0) /**< Shifted mode DDATA1LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA0 (_CRYPTO_CMD_INSTR_DDATA2TODDATA0 << 0) /**< Shifted mode DDATA2TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA1 (_CRYPTO_CMD_INSTR_DDATA2TODDATA1 << 0) /**< Shifted mode DDATA2TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA3 (_CRYPTO_CMD_INSTR_DDATA2TODDATA3 << 0) /**< Shifted mode DDATA2TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA4 (_CRYPTO_CMD_INSTR_DDATA2TODDATA4 << 0) /**< Shifted mode DDATA2TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2LTODATA2 (_CRYPTO_CMD_INSTR_DDATA2LTODATA2 << 0) /**< Shifted mode DDATA2LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA0 (_CRYPTO_CMD_INSTR_DDATA3TODDATA0 << 0) /**< Shifted mode DDATA3TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA1 (_CRYPTO_CMD_INSTR_DDATA3TODDATA1 << 0) /**< Shifted mode DDATA3TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA2 (_CRYPTO_CMD_INSTR_DDATA3TODDATA2 << 0) /**< Shifted mode DDATA3TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA4 (_CRYPTO_CMD_INSTR_DDATA3TODDATA4 << 0) /**< Shifted mode DDATA3TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3LTODATA0 (_CRYPTO_CMD_INSTR_DDATA3LTODATA0 << 0) /**< Shifted mode DDATA3LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3HTODATA1 (_CRYPTO_CMD_INSTR_DDATA3HTODATA1 << 0) /**< Shifted mode DDATA3HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA0 (_CRYPTO_CMD_INSTR_DDATA4TODDATA0 << 0) /**< Shifted mode DDATA4TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA1 (_CRYPTO_CMD_INSTR_DDATA4TODDATA1 << 0) /**< Shifted mode DDATA4TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA2 (_CRYPTO_CMD_INSTR_DDATA4TODDATA2 << 0) /**< Shifted mode DDATA4TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA3 (_CRYPTO_CMD_INSTR_DDATA4TODDATA3 << 0) /**< Shifted mode DDATA4TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4LTODATA0 (_CRYPTO_CMD_INSTR_DDATA4LTODATA0 << 0) /**< Shifted mode DDATA4LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4HTODATA1 (_CRYPTO_CMD_INSTR_DDATA4HTODATA1 << 0) /**< Shifted mode DDATA4HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4LTODATA2 (_CRYPTO_CMD_INSTR_DDATA4LTODATA2 << 0) /**< Shifted mode DDATA4LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODDATA0 (_CRYPTO_CMD_INSTR_DATA0TODDATA0 << 0) /**< Shifted mode DATA0TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODDATA1 (_CRYPTO_CMD_INSTR_DATA0TODDATA1 << 0) /**< Shifted mode DATA0TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODDATA0 (_CRYPTO_CMD_INSTR_DATA1TODDATA0 << 0) /**< Shifted mode DATA1TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODDATA1 (_CRYPTO_CMD_INSTR_DATA1TODDATA1 << 0) /**< Shifted mode DATA1TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA0 (_CRYPTO_CMD_INSTR_DATA2TODDATA0 << 0) /**< Shifted mode DATA2TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA1 (_CRYPTO_CMD_INSTR_DATA2TODDATA1 << 0) /**< Shifted mode DATA2TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA2 (_CRYPTO_CMD_INSTR_DATA2TODDATA2 << 0) /**< Shifted mode DATA2TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA0 << 0) /**< Shifted mode SELDDATA0DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA0 << 0) /**< Shifted mode SELDDATA1DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA0 << 0) /**< Shifted mode SELDDATA2DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA0 << 0) /**< Shifted mode SELDDATA3DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA0 << 0) /**< Shifted mode SELDDATA4DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDATA0DDATA0 << 0) /**< Shifted mode SELDATA0DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDATA1DDATA0 << 0) /**< Shifted mode SELDATA1DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDATA2DDATA0 << 0) /**< Shifted mode SELDATA2DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA1 << 0) /**< Shifted mode SELDDATA0DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA1 << 0) /**< Shifted mode SELDDATA1DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA1 << 0) /**< Shifted mode SELDDATA2DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA1 << 0) /**< Shifted mode SELDDATA3DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA1 << 0) /**< Shifted mode SELDDATA4DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDATA0DDATA1 << 0) /**< Shifted mode SELDATA0DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDATA1DDATA1 << 0) /**< Shifted mode SELDATA1DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDATA2DDATA1 << 0) /**< Shifted mode SELDATA2DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA2 << 0) /**< Shifted mode SELDDATA0DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA2 << 0) /**< Shifted mode SELDDATA1DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA2 << 0) /**< Shifted mode SELDDATA2DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA2 << 0) /**< Shifted mode SELDDATA3DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA2 << 0) /**< Shifted mode SELDDATA4DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDATA0DDATA2 << 0) /**< Shifted mode SELDATA0DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDATA1DDATA2 << 0) /**< Shifted mode SELDATA1DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDATA2DDATA2 << 0) /**< Shifted mode SELDATA2DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA3 << 0) /**< Shifted mode SELDDATA0DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA3 << 0) /**< Shifted mode SELDDATA1DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA3 << 0) /**< Shifted mode SELDDATA2DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA3 << 0) /**< Shifted mode SELDDATA3DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA3 << 0) /**< Shifted mode SELDDATA4DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDATA0DDATA3 << 0) /**< Shifted mode SELDATA0DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDATA1DDATA3 << 0) /**< Shifted mode SELDATA1DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDATA2DDATA3 << 0) /**< Shifted mode SELDATA2DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA4 << 0) /**< Shifted mode SELDDATA0DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA4 << 0) /**< Shifted mode SELDDATA1DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA4 << 0) /**< Shifted mode SELDDATA2DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA4 << 0) /**< Shifted mode SELDDATA3DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA4 << 0) /**< Shifted mode SELDDATA4DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDATA0DDATA4 << 0) /**< Shifted mode SELDATA0DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDATA1DDATA4 << 0) /**< Shifted mode SELDATA1DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDATA2DDATA4 << 0) /**< Shifted mode SELDATA2DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DATA0 << 0) /**< Shifted mode SELDDATA0DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DATA0 << 0) /**< Shifted mode SELDDATA1DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DATA0 << 0) /**< Shifted mode SELDDATA2DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DATA0 << 0) /**< Shifted mode SELDDATA3DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DATA0 << 0) /**< Shifted mode SELDDATA4DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDATA0DATA0 << 0) /**< Shifted mode SELDATA0DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDATA1DATA0 << 0) /**< Shifted mode SELDATA1DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDATA2DATA0 << 0) /**< Shifted mode SELDATA2DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DATA1 << 0) /**< Shifted mode SELDDATA0DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DATA1 << 0) /**< Shifted mode SELDDATA1DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DATA1 << 0) /**< Shifted mode SELDDATA2DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DATA1 << 0) /**< Shifted mode SELDDATA3DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DATA1 << 0) /**< Shifted mode SELDDATA4DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDATA0DATA1 << 0) /**< Shifted mode SELDATA0DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDATA1DATA1 << 0) /**< Shifted mode SELDATA1DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDATA2DATA1 << 0) /**< Shifted mode SELDATA2DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFA (_CRYPTO_CMD_INSTR_EXECIFA << 0) /**< Shifted mode EXECIFA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFB (_CRYPTO_CMD_INSTR_EXECIFB << 0) /**< Shifted mode EXECIFB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFNLAST (_CRYPTO_CMD_INSTR_EXECIFNLAST << 0) /**< Shifted mode EXECIFNLAST for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFLAST (_CRYPTO_CMD_INSTR_EXECIFLAST << 0) /**< Shifted mode EXECIFLAST for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFCARRY (_CRYPTO_CMD_INSTR_EXECIFCARRY << 0) /**< Shifted mode EXECIFCARRY for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFNCARRY (_CRYPTO_CMD_INSTR_EXECIFNCARRY << 0) /**< Shifted mode EXECIFNCARRY for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECALWAYS (_CRYPTO_CMD_INSTR_EXECALWAYS << 0) /**< Shifted mode EXECALWAYS for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTART (0x1UL << 9) /**< Encryption/Decryption SEQUENCE Start */ +#define _CRYPTO_CMD_SEQSTART_SHIFT 9 /**< Shift value for CRYPTO_SEQSTART */ +#define _CRYPTO_CMD_SEQSTART_MASK 0x200UL /**< Bit mask for CRYPTO_SEQSTART */ +#define _CRYPTO_CMD_SEQSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTART_DEFAULT (_CRYPTO_CMD_SEQSTART_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTOP (0x1UL << 10) /**< Sequence Stop */ +#define _CRYPTO_CMD_SEQSTOP_SHIFT 10 /**< Shift value for CRYPTO_SEQSTOP */ +#define _CRYPTO_CMD_SEQSTOP_MASK 0x400UL /**< Bit mask for CRYPTO_SEQSTOP */ +#define _CRYPTO_CMD_SEQSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTOP_DEFAULT (_CRYPTO_CMD_SEQSTOP_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTEP (0x1UL << 11) /**< Sequence Step */ +#define _CRYPTO_CMD_SEQSTEP_SHIFT 11 /**< Shift value for CRYPTO_SEQSTEP */ +#define _CRYPTO_CMD_SEQSTEP_MASK 0x800UL /**< Bit mask for CRYPTO_SEQSTEP */ +#define _CRYPTO_CMD_SEQSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTEP_DEFAULT (_CRYPTO_CMD_SEQSTEP_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTO_CMD */ + +/* Bit fields for CRYPTO STATUS */ +#define _CRYPTO_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_STATUS */ +#define _CRYPTO_STATUS_MASK 0x00000007UL /**< Mask for CRYPTO_STATUS */ +#define CRYPTO_STATUS_SEQRUNNING (0x1UL << 0) /**< AES SEQUENCE Running */ +#define _CRYPTO_STATUS_SEQRUNNING_SHIFT 0 /**< Shift value for CRYPTO_SEQRUNNING */ +#define _CRYPTO_STATUS_SEQRUNNING_MASK 0x1UL /**< Bit mask for CRYPTO_SEQRUNNING */ +#define _CRYPTO_STATUS_SEQRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_SEQRUNNING_DEFAULT (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is active */ +#define _CRYPTO_STATUS_INSTRRUNNING_SHIFT 1 /**< Shift value for CRYPTO_INSTRRUNNING */ +#define _CRYPTO_STATUS_INSTRRUNNING_MASK 0x2UL /**< Bit mask for CRYPTO_INSTRRUNNING */ +#define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_INSTRRUNNING_DEFAULT (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is active */ +#define _CRYPTO_STATUS_DMAACTIVE_SHIFT 2 /**< Shift value for CRYPTO_DMAACTIVE */ +#define _CRYPTO_STATUS_DMAACTIVE_MASK 0x4UL /**< Bit mask for CRYPTO_DMAACTIVE */ +#define _CRYPTO_STATUS_DMAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_DMAACTIVE_DEFAULT (_CRYPTO_STATUS_DMAACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ + +/* Bit fields for CRYPTO DSTATUS */ +#define _CRYPTO_DSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_MASK 0x011F0F0FUL /**< Mask for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_SHIFT 0 /**< Shift value for CRYPTO_DATA0ZERO */ +#define _CRYPTO_DSTATUS_DATA0ZERO_MASK 0xFUL /**< Bit mask for CRYPTO_DATA0ZERO */ +#define _CRYPTO_DSTATUS_DATA0ZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 0x00000001UL /**< Mode ZERO0TO31 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 0x00000002UL /**< Mode ZERO32TO63 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 0x00000004UL /**< Mode ZERO64TO95 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 0x00000008UL /**< Mode ZERO96TO127 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_DEFAULT (_CRYPTO_DSTATUS_DATA0ZERO_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 << 0) /**< Shifted mode ZERO0TO31 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 << 0) /**< Shifted mode ZERO32TO63 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 << 0) /**< Shifted mode ZERO64TO95 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 << 0) /**< Shifted mode ZERO96TO127 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT 8 /**< Shift value for CRYPTO_DDATA0LSBS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_MASK 0xF00UL /**< Bit mask for CRYPTO_DDATA0LSBS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT 16 /**< Shift value for CRYPTO_DDATA0MSBS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_MASK 0xF0000UL /**< Bit mask for CRYPTO_DDATA0MSBS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA1MSB (0x1UL << 20) /**< MSB in DDATA1 */ +#define _CRYPTO_DSTATUS_DDATA1MSB_SHIFT 20 /**< Shift value for CRYPTO_DDATA1MSB */ +#define _CRYPTO_DSTATUS_DDATA1MSB_MASK 0x100000UL /**< Bit mask for CRYPTO_DDATA1MSB */ +#define _CRYPTO_DSTATUS_DDATA1MSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA1MSB_DEFAULT (_CRYPTO_DSTATUS_DDATA1MSB_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_CARRY (0x1UL << 24) /**< Carry From Arithmetic Operation */ +#define _CRYPTO_DSTATUS_CARRY_SHIFT 24 /**< Shift value for CRYPTO_CARRY */ +#define _CRYPTO_DSTATUS_CARRY_MASK 0x1000000UL /**< Bit mask for CRYPTO_CARRY */ +#define _CRYPTO_DSTATUS_CARRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_CARRY_DEFAULT (_CRYPTO_DSTATUS_CARRY_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ + +/* Bit fields for CRYPTO CSTATUS */ +#define _CRYPTO_CSTATUS_RESETVALUE 0x00000201UL /**< Default value for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_MASK 0x01F30707UL /**< Mask for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_SHIFT 0 /**< Shift value for CRYPTO_V0 */ +#define _CRYPTO_CSTATUS_V0_MASK 0x7UL /**< Bit mask for CRYPTO_V0 */ +#define _CRYPTO_CSTATUS_V0_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA0 (_CRYPTO_CSTATUS_V0_DDATA0 << 0) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DEFAULT (_CRYPTO_CSTATUS_V0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA1 (_CRYPTO_CSTATUS_V0_DDATA1 << 0) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA2 (_CRYPTO_CSTATUS_V0_DDATA2 << 0) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA3 (_CRYPTO_CSTATUS_V0_DDATA3 << 0) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA4 (_CRYPTO_CSTATUS_V0_DDATA4 << 0) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA0 (_CRYPTO_CSTATUS_V0_DATA0 << 0) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA1 (_CRYPTO_CSTATUS_V0_DATA1 << 0) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA2 (_CRYPTO_CSTATUS_V0_DATA2 << 0) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_SHIFT 8 /**< Shift value for CRYPTO_V1 */ +#define _CRYPTO_CSTATUS_V1_MASK 0x700UL /**< Bit mask for CRYPTO_V1 */ +#define _CRYPTO_CSTATUS_V1_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DEFAULT 0x00000002UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA0 (_CRYPTO_CSTATUS_V1_DDATA0 << 8) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA1 (_CRYPTO_CSTATUS_V1_DDATA1 << 8) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DEFAULT (_CRYPTO_CSTATUS_V1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA2 (_CRYPTO_CSTATUS_V1_DDATA2 << 8) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA3 (_CRYPTO_CSTATUS_V1_DDATA3 << 8) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA4 (_CRYPTO_CSTATUS_V1_DDATA4 << 8) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA0 (_CRYPTO_CSTATUS_V1_DATA0 << 8) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA1 (_CRYPTO_CSTATUS_V1_DATA1 << 8) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA2 (_CRYPTO_CSTATUS_V1_DATA2 << 8) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART (0x1UL << 16) /**< Sequence Part */ +#define _CRYPTO_CSTATUS_SEQPART_SHIFT 16 /**< Shift value for CRYPTO_SEQPART */ +#define _CRYPTO_CSTATUS_SEQPART_MASK 0x10000UL /**< Bit mask for CRYPTO_SEQPART */ +#define _CRYPTO_CSTATUS_SEQPART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQPART_SEQA 0x00000000UL /**< Mode SEQA for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQPART_SEQB 0x00000001UL /**< Mode SEQB for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_DEFAULT (_CRYPTO_CSTATUS_SEQPART_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_SEQA (_CRYPTO_CSTATUS_SEQPART_SEQA << 16) /**< Shifted mode SEQA for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_SEQB (_CRYPTO_CSTATUS_SEQPART_SEQB << 16) /**< Shifted mode SEQB for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQSKIP (0x1UL << 17) /**< Sequence Skip Next Instruction */ +#define _CRYPTO_CSTATUS_SEQSKIP_SHIFT 17 /**< Shift value for CRYPTO_SEQSKIP */ +#define _CRYPTO_CSTATUS_SEQSKIP_MASK 0x20000UL /**< Bit mask for CRYPTO_SEQSKIP */ +#define _CRYPTO_CSTATUS_SEQSKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQSKIP_DEFAULT (_CRYPTO_CSTATUS_SEQSKIP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQIP_SHIFT 20 /**< Shift value for CRYPTO_SEQIP */ +#define _CRYPTO_CSTATUS_SEQIP_MASK 0x1F00000UL /**< Bit mask for CRYPTO_SEQIP */ +#define _CRYPTO_CSTATUS_SEQIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQIP_DEFAULT (_CRYPTO_CSTATUS_SEQIP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ + +/* Bit fields for CRYPTO KEY */ +#define _CRYPTO_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEY */ +#define _CRYPTO_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEY */ +#define CRYPTO_KEY_KEY_DEFAULT (_CRYPTO_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEY */ + +/* Bit fields for CRYPTO KEYBUF */ +#define _CRYPTO_KEYBUF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_SHIFT 0 /**< Shift value for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEYBUF */ +#define CRYPTO_KEYBUF_KEYBUF_DEFAULT (_CRYPTO_KEYBUF_KEYBUF_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEYBUF */ + +/* Bit fields for CRYPTO SEQCTRL */ +#define _CRYPTO_SEQCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_MASK 0xBF303FFFUL /**< Mask for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_LENGTHA_SHIFT 0 /**< Shift value for CRYPTO_LENGTHA */ +#define _CRYPTO_SEQCTRL_LENGTHA_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHA */ +#define _CRYPTO_SEQCTRL_LENGTHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_LENGTHA_DEFAULT (_CRYPTO_SEQCTRL_LENGTHA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_SHIFT 20 /**< Shift value for CRYPTO_BLOCKSIZE */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_MASK 0x300000UL /**< Bit mask for CRYPTO_BLOCKSIZE */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES 0x00000000UL /**< Mode 16BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES 0x00000001UL /**< Mode 32BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES 0x00000002UL /**< Mode 64BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT (_CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES << 20) /**< Shifted mode 16BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES << 20) /**< Shifted mode 32BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES << 20) /**< Shifted mode 64BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_SHIFT 24 /**< Shift value for CRYPTO_DMA0SKIP */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA0SKIP */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_SHIFT 26 /**< Shift value for CRYPTO_DMA1SKIP */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_MASK 0xC000000UL /**< Bit mask for CRYPTO_DMA1SKIP */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve A */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESA */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESA */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve A */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESA */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESA */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_HALT (0x1UL << 31) /**< Halt Sequence */ +#define _CRYPTO_SEQCTRL_HALT_SHIFT 31 /**< Shift value for CRYPTO_HALT */ +#define _CRYPTO_SEQCTRL_HALT_MASK 0x80000000UL /**< Bit mask for CRYPTO_HALT */ +#define _CRYPTO_SEQCTRL_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_HALT_DEFAULT (_CRYPTO_SEQCTRL_HALT_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ + +/* Bit fields for CRYPTO SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_MASK 0x30003FFFUL /**< Mask for CRYPTO_SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_SHIFT 0 /**< Shift value for CRYPTO_LENGTHB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_LENGTHB_DEFAULT (_CRYPTO_SEQCTRLB_LENGTHB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA0PRESB (0x1UL << 28) /**< DMA0 Preserve B */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESB */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESB */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA1PRESB (0x1UL << 29) /**< DMA1 Preserve B */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESB */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESB */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ + +/* Bit fields for CRYPTO IF */ +#define _CRYPTO_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IF */ +#define _CRYPTO_IF_MASK 0x00000003UL /**< Mask for CRYPTO_IF */ +#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction done */ +#define _CRYPTO_IF_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IF_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IF_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_INSTRDONE_DEFAULT (_CRYPTO_IF_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_SEQDONE (0x1UL << 1) /**< Sequence Done */ +#define _CRYPTO_IF_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IF_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IF_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_SEQDONE_DEFAULT (_CRYPTO_IF_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IF */ + +/* Bit fields for CRYPTO IFS */ +#define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */ +#define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */ +#define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */ +#define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFS_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_INSTRDONE_DEFAULT (_CRYPTO_IFS_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_SEQDONE (0x1UL << 1) /**< Set SEQDONE Interrupt Flag */ +#define _CRYPTO_IFS_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */ + +/* Bit fields for CRYPTO IFC */ +#define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */ +#define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */ +#define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */ +#define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFC_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_INSTRDONE_DEFAULT (_CRYPTO_IFC_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_SEQDONE (0x1UL << 1) /**< Clear SEQDONE Interrupt Flag */ +#define _CRYPTO_IFC_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */ + +/* Bit fields for CRYPTO IEN */ +#define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */ +#define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */ +#define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */ +#define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IEN_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_INSTRDONE_DEFAULT (_CRYPTO_IEN_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_SEQDONE (0x1UL << 1) /**< SEQDONE Interrupt Enable */ +#define _CRYPTO_IEN_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */ + +/* Bit fields for CRYPTO SEQ0 */ +#define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR0_SHIFT 0 /**< Shift value for CRYPTO_INSTR0 */ +#define _CRYPTO_SEQ0_INSTR0_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR0 */ +#define _CRYPTO_SEQ0_INSTR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR0_DEFAULT (_CRYPTO_SEQ0_INSTR0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR1_SHIFT 8 /**< Shift value for CRYPTO_INSTR1 */ +#define _CRYPTO_SEQ0_INSTR1_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR1 */ +#define _CRYPTO_SEQ0_INSTR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR1_DEFAULT (_CRYPTO_SEQ0_INSTR1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR2_SHIFT 16 /**< Shift value for CRYPTO_INSTR2 */ +#define _CRYPTO_SEQ0_INSTR2_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR2 */ +#define _CRYPTO_SEQ0_INSTR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR2_DEFAULT (_CRYPTO_SEQ0_INSTR2_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR3_SHIFT 24 /**< Shift value for CRYPTO_INSTR3 */ +#define _CRYPTO_SEQ0_INSTR3_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR3 */ +#define _CRYPTO_SEQ0_INSTR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR3_DEFAULT (_CRYPTO_SEQ0_INSTR3_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ + +/* Bit fields for CRYPTO SEQ1 */ +#define _CRYPTO_SEQ1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR4_SHIFT 0 /**< Shift value for CRYPTO_INSTR4 */ +#define _CRYPTO_SEQ1_INSTR4_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR4 */ +#define _CRYPTO_SEQ1_INSTR4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR4_DEFAULT (_CRYPTO_SEQ1_INSTR4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR5_SHIFT 8 /**< Shift value for CRYPTO_INSTR5 */ +#define _CRYPTO_SEQ1_INSTR5_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR5 */ +#define _CRYPTO_SEQ1_INSTR5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR5_DEFAULT (_CRYPTO_SEQ1_INSTR5_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR6_SHIFT 16 /**< Shift value for CRYPTO_INSTR6 */ +#define _CRYPTO_SEQ1_INSTR6_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR6 */ +#define _CRYPTO_SEQ1_INSTR6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR6_DEFAULT (_CRYPTO_SEQ1_INSTR6_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR7_SHIFT 24 /**< Shift value for CRYPTO_INSTR7 */ +#define _CRYPTO_SEQ1_INSTR7_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR7 */ +#define _CRYPTO_SEQ1_INSTR7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR7_DEFAULT (_CRYPTO_SEQ1_INSTR7_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ + +/* Bit fields for CRYPTO SEQ2 */ +#define _CRYPTO_SEQ2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR8_SHIFT 0 /**< Shift value for CRYPTO_INSTR8 */ +#define _CRYPTO_SEQ2_INSTR8_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR8 */ +#define _CRYPTO_SEQ2_INSTR8_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR8_DEFAULT (_CRYPTO_SEQ2_INSTR8_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR9_SHIFT 8 /**< Shift value for CRYPTO_INSTR9 */ +#define _CRYPTO_SEQ2_INSTR9_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR9 */ +#define _CRYPTO_SEQ2_INSTR9_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR9_DEFAULT (_CRYPTO_SEQ2_INSTR9_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR10_SHIFT 16 /**< Shift value for CRYPTO_INSTR10 */ +#define _CRYPTO_SEQ2_INSTR10_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR10 */ +#define _CRYPTO_SEQ2_INSTR10_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR10_DEFAULT (_CRYPTO_SEQ2_INSTR10_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR11_SHIFT 24 /**< Shift value for CRYPTO_INSTR11 */ +#define _CRYPTO_SEQ2_INSTR11_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR11 */ +#define _CRYPTO_SEQ2_INSTR11_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR11_DEFAULT (_CRYPTO_SEQ2_INSTR11_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ + +/* Bit fields for CRYPTO SEQ3 */ +#define _CRYPTO_SEQ3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR12_SHIFT 0 /**< Shift value for CRYPTO_INSTR12 */ +#define _CRYPTO_SEQ3_INSTR12_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR12 */ +#define _CRYPTO_SEQ3_INSTR12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR12_DEFAULT (_CRYPTO_SEQ3_INSTR12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR13_SHIFT 8 /**< Shift value for CRYPTO_INSTR13 */ +#define _CRYPTO_SEQ3_INSTR13_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR13 */ +#define _CRYPTO_SEQ3_INSTR13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR13_DEFAULT (_CRYPTO_SEQ3_INSTR13_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR14_SHIFT 16 /**< Shift value for CRYPTO_INSTR14 */ +#define _CRYPTO_SEQ3_INSTR14_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR14 */ +#define _CRYPTO_SEQ3_INSTR14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR14_DEFAULT (_CRYPTO_SEQ3_INSTR14_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR15_SHIFT 24 /**< Shift value for CRYPTO_INSTR15 */ +#define _CRYPTO_SEQ3_INSTR15_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR15 */ +#define _CRYPTO_SEQ3_INSTR15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR15_DEFAULT (_CRYPTO_SEQ3_INSTR15_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ + +/* Bit fields for CRYPTO SEQ4 */ +#define _CRYPTO_SEQ4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR16_SHIFT 0 /**< Shift value for CRYPTO_INSTR16 */ +#define _CRYPTO_SEQ4_INSTR16_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR16 */ +#define _CRYPTO_SEQ4_INSTR16_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR16_DEFAULT (_CRYPTO_SEQ4_INSTR16_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR17_SHIFT 8 /**< Shift value for CRYPTO_INSTR17 */ +#define _CRYPTO_SEQ4_INSTR17_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR17 */ +#define _CRYPTO_SEQ4_INSTR17_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR17_DEFAULT (_CRYPTO_SEQ4_INSTR17_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR18_SHIFT 16 /**< Shift value for CRYPTO_INSTR18 */ +#define _CRYPTO_SEQ4_INSTR18_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR18 */ +#define _CRYPTO_SEQ4_INSTR18_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR18_DEFAULT (_CRYPTO_SEQ4_INSTR18_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR19_SHIFT 24 /**< Shift value for CRYPTO_INSTR19 */ +#define _CRYPTO_SEQ4_INSTR19_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR19 */ +#define _CRYPTO_SEQ4_INSTR19_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR19_DEFAULT (_CRYPTO_SEQ4_INSTR19_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ + +/* Bit fields for CRYPTO DATA0 */ +#define _CRYPTO_DATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_SHIFT 0 /**< Shift value for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0 */ +#define CRYPTO_DATA0_DATA0_DEFAULT (_CRYPTO_DATA0_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0 */ + +/* Bit fields for CRYPTO DATA1 */ +#define _CRYPTO_DATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_SHIFT 0 /**< Shift value for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1 */ +#define CRYPTO_DATA1_DATA1_DEFAULT (_CRYPTO_DATA1_DATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1 */ + +/* Bit fields for CRYPTO DATA2 */ +#define _CRYPTO_DATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_SHIFT 0 /**< Shift value for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA2 */ +#define CRYPTO_DATA2_DATA2_DEFAULT (_CRYPTO_DATA2_DATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA2 */ + +/* Bit fields for CRYPTO DATA3 */ +#define _CRYPTO_DATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_SHIFT 0 /**< Shift value for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA3 */ +#define CRYPTO_DATA3_DATA3_DEFAULT (_CRYPTO_DATA3_DATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA3 */ + +/* Bit fields for CRYPTO DATA0XOR */ +#define _CRYPTO_DATA0XOR_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_SHIFT 0 /**< Shift value for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XOR */ +#define CRYPTO_DATA0XOR_DATA0XOR_DEFAULT (_CRYPTO_DATA0XOR_DATA0XOR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XOR */ + +/* Bit fields for CRYPTO DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE */ +#define CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT (_CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE */ + +/* Bit fields for CRYPTO DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1BYTE */ +#define CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT (_CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1BYTE */ + +/* Bit fields for CRYPTO DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XORBYTE */ +#define CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT (_CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XORBYTE */ + +/* Bit fields for CRYPTO DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE12 */ +#define CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT (_CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE12 */ + +/* Bit fields for CRYPTO DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE13 */ +#define CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT (_CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE13 */ + +/* Bit fields for CRYPTO DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE14 */ +#define CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT (_CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE14 */ + +/* Bit fields for CRYPTO DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE15 */ +#define CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT (_CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE15 */ + +/* Bit fields for CRYPTO DDATA0 */ +#define _CRYPTO_DDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_SHIFT 0 /**< Shift value for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0 */ +#define CRYPTO_DDATA0_DDATA0_DEFAULT (_CRYPTO_DDATA0_DDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0 */ + +/* Bit fields for CRYPTO DDATA1 */ +#define _CRYPTO_DDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_SHIFT 0 /**< Shift value for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1 */ +#define CRYPTO_DDATA1_DDATA1_DEFAULT (_CRYPTO_DDATA1_DDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1 */ + +/* Bit fields for CRYPTO DDATA2 */ +#define _CRYPTO_DDATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_SHIFT 0 /**< Shift value for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA2 */ +#define CRYPTO_DDATA2_DDATA2_DEFAULT (_CRYPTO_DDATA2_DDATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA2 */ + +/* Bit fields for CRYPTO DDATA3 */ +#define _CRYPTO_DDATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_SHIFT 0 /**< Shift value for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA3 */ +#define CRYPTO_DDATA3_DDATA3_DEFAULT (_CRYPTO_DDATA3_DDATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA3 */ + +/* Bit fields for CRYPTO DDATA4 */ +#define _CRYPTO_DDATA4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_SHIFT 0 /**< Shift value for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA4 */ +#define CRYPTO_DDATA4_DDATA4_DEFAULT (_CRYPTO_DDATA4_DDATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA4 */ + +/* Bit fields for CRYPTO DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BIG */ +#define CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT (_CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BIG */ + +/* Bit fields for CRYPTO DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE */ +#define CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT (_CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE */ + +/* Bit fields for CRYPTO DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1BYTE */ +#define CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT (_CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1BYTE */ + +/* Bit fields for CRYPTO DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_MASK 0x0000000FUL /**< Mask for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK 0xFUL /**< Bit mask for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE32 */ +#define CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT (_CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE32 */ + +/* Bit fields for CRYPTO QDATA0 */ +#define _CRYPTO_QDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_SHIFT 0 /**< Shift value for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0 */ +#define CRYPTO_QDATA0_QDATA0_DEFAULT (_CRYPTO_QDATA0_QDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0 */ + +/* Bit fields for CRYPTO QDATA1 */ +#define _CRYPTO_QDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_SHIFT 0 /**< Shift value for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1 */ +#define CRYPTO_QDATA1_QDATA1_DEFAULT (_CRYPTO_QDATA1_QDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1 */ + +/* Bit fields for CRYPTO QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BIG */ +#define CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT (_CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BIG */ + +/* Bit fields for CRYPTO QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0BYTE */ +#define CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT (_CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0BYTE */ + +/* Bit fields for CRYPTO QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */ +#define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */ + +/** @} End of group EFM32PG12B_CRYPTO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_csen.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_csen.h new file mode 100644 index 00000000000..0ebc373d115 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_csen.h @@ -0,0 +1,1003 @@ +/**************************************************************************//** + * @file efm32pg12b_csen.h + * @brief EFM32PG12B_CSEN register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_CSEN + * @{ + * @brief EFM32PG12B_CSEN Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t TIMCTRL; /**< Timing Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t PRSSEL; /**< Control Register */ + __IOM uint32_t DATA; /**< Control Register */ + __IOM uint32_t SCANMASK0; /**< CSEN Channel Scan Mask */ + __IOM uint32_t SCANINPUTSEL0; /**< Input Channel Configuration register for Scan mode */ + __IOM uint32_t SCANMASK1; /**< CSEN Channel Scan Mask */ + __IOM uint32_t SCANINPUTSEL1; /**< Input Channel Configuration register for Scan mode */ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ + __IOM uint32_t CMPTHR; /**< CSEN Comparator Threshold */ + __IOM uint32_t EMA; /**< Exponential Moving Average */ + __IOM uint32_t EMACTRL; /**< Exponential Moving Average */ + __IOM uint32_t SINGLECTRL; /**< CSEN Single Conversion Control Register */ + __IOM uint32_t DMBASELINE; /**< Control Register */ + __IOM uint32_t DMCFG; /**< Control Register */ + __IOM uint32_t ANACTRL; /**< Analog Control Register */ + + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} CSEN_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_CSEN_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CSEN CTRL */ +#define _CSEN_CTRL_RESETVALUE 0x00030000UL /**< Default value for CSEN_CTRL */ +#define _CSEN_CTRL_MASK 0x1FFFF336UL /**< Mask for CSEN_CTRL */ +#define CSEN_CTRL_EN (0x1UL << 1) /**< CSEN Enable */ +#define _CSEN_CTRL_EN_SHIFT 1 /**< Shift value for CSEN_EN */ +#define _CSEN_CTRL_EN_MASK 0x2UL /**< Bit mask for CSEN_EN */ +#define _CSEN_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_EN_DEFAULT (_CSEN_CTRL_EN_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_EN_DISABLE (_CSEN_CTRL_EN_DISABLE << 1) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_EN_ENABLE (_CSEN_CTRL_EN_ENABLE << 1) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL (0x1UL << 2) /**< CSEN Digital Comparator Polarity Select */ +#define _CSEN_CTRL_CMPPOL_SHIFT 2 /**< Shift value for CSEN_CMPPOL */ +#define _CSEN_CTRL_CMPPOL_MASK 0x4UL /**< Bit mask for CSEN_CMPPOL */ +#define _CSEN_CTRL_CMPPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPPOL_GT 0x00000000UL /**< Mode GT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPPOL_LTE 0x00000001UL /**< Mode LTE for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_DEFAULT (_CSEN_CTRL_CMPPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_GT (_CSEN_CTRL_CMPPOL_GT << 2) /**< Shifted mode GT for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_LTE (_CSEN_CTRL_CMPPOL_LTE << 2) /**< Shifted mode LTE for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SHIFT 4 /**< Shift value for CSEN_CM */ +#define _CSEN_CTRL_CM_MASK 0x30UL /**< Bit mask for CSEN_CM */ +#define _CSEN_CTRL_CM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SGL 0x00000000UL /**< Mode SGL for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SCAN 0x00000001UL /**< Mode SCAN for CSEN_CTRL */ +#define _CSEN_CTRL_CM_CONTSGL 0x00000002UL /**< Mode CONTSGL for CSEN_CTRL */ +#define _CSEN_CTRL_CM_CONTSCAN 0x00000003UL /**< Mode CONTSCAN for CSEN_CTRL */ +#define CSEN_CTRL_CM_DEFAULT (_CSEN_CTRL_CM_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CM_SGL (_CSEN_CTRL_CM_SGL << 4) /**< Shifted mode SGL for CSEN_CTRL */ +#define CSEN_CTRL_CM_SCAN (_CSEN_CTRL_CM_SCAN << 4) /**< Shifted mode SCAN for CSEN_CTRL */ +#define CSEN_CTRL_CM_CONTSGL (_CSEN_CTRL_CM_CONTSGL << 4) /**< Shifted mode CONTSGL for CSEN_CTRL */ +#define CSEN_CTRL_CM_CONTSCAN (_CSEN_CTRL_CM_CONTSCAN << 4) /**< Shifted mode CONTSCAN for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_SHIFT 8 /**< Shift value for CSEN_SARCR */ +#define _CSEN_CTRL_SARCR_MASK 0x300UL /**< Bit mask for CSEN_SARCR */ +#define _CSEN_CTRL_SARCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK10 0x00000000UL /**< Mode CLK10 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK12 0x00000001UL /**< Mode CLK12 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK14 0x00000002UL /**< Mode CLK14 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK16 0x00000003UL /**< Mode CLK16 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_DEFAULT (_CSEN_CTRL_SARCR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK10 (_CSEN_CTRL_SARCR_CLK10 << 8) /**< Shifted mode CLK10 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK12 (_CSEN_CTRL_SARCR_CLK12 << 8) /**< Shifted mode CLK12 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK14 (_CSEN_CTRL_SARCR_CLK14 << 8) /**< Shifted mode CLK14 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK16 (_CSEN_CTRL_SARCR_CLK16 << 8) /**< Shifted mode CLK16 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_SHIFT 12 /**< Shift value for CSEN_ACU */ +#define _CSEN_CTRL_ACU_MASK 0x7000UL /**< Bit mask for CSEN_ACU */ +#define _CSEN_CTRL_ACU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC1 0x00000000UL /**< Mode ACC1 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC2 0x00000001UL /**< Mode ACC2 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC4 0x00000002UL /**< Mode ACC4 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC8 0x00000003UL /**< Mode ACC8 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC16 0x00000004UL /**< Mode ACC16 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC32 0x00000005UL /**< Mode ACC32 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC64 0x00000006UL /**< Mode ACC64 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_DEFAULT (_CSEN_CTRL_ACU_DEFAULT << 12) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC1 (_CSEN_CTRL_ACU_ACC1 << 12) /**< Shifted mode ACC1 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC2 (_CSEN_CTRL_ACU_ACC2 << 12) /**< Shifted mode ACC2 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC4 (_CSEN_CTRL_ACU_ACC4 << 12) /**< Shifted mode ACC4 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC8 (_CSEN_CTRL_ACU_ACC8 << 12) /**< Shifted mode ACC8 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC16 (_CSEN_CTRL_ACU_ACC16 << 12) /**< Shifted mode ACC16 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC32 (_CSEN_CTRL_ACU_ACC32 << 12) /**< Shifted mode ACC32 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC64 (_CSEN_CTRL_ACU_ACC64 << 12) /**< Shifted mode ACC64 for CSEN_CTRL */ +#define CSEN_CTRL_MCEN (0x1UL << 15) /**< CSEN Multiple Channel Enable. */ +#define _CSEN_CTRL_MCEN_SHIFT 15 /**< Shift value for CSEN_MCEN */ +#define _CSEN_CTRL_MCEN_MASK 0x8000UL /**< Bit mask for CSEN_MCEN */ +#define _CSEN_CTRL_MCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_MCEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_MCEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_DEFAULT (_CSEN_CTRL_MCEN_DEFAULT << 15) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_DISABLE (_CSEN_CTRL_MCEN_DISABLE << 15) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_ENABLE (_CSEN_CTRL_MCEN_ENABLE << 15) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define _CSEN_CTRL_STM_SHIFT 16 /**< Shift value for CSEN_STM */ +#define _CSEN_CTRL_STM_MASK 0x30000UL /**< Bit mask for CSEN_STM */ +#define _CSEN_CTRL_STM_PRS 0x00000000UL /**< Mode PRS for CSEN_CTRL */ +#define _CSEN_CTRL_STM_TIMER 0x00000001UL /**< Mode TIMER for CSEN_CTRL */ +#define _CSEN_CTRL_STM_START 0x00000002UL /**< Mode START for CSEN_CTRL */ +#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_STM_PRS (_CSEN_CTRL_STM_PRS << 16) /**< Shifted mode PRS for CSEN_CTRL */ +#define CSEN_CTRL_STM_TIMER (_CSEN_CTRL_STM_TIMER << 16) /**< Shifted mode TIMER for CSEN_CTRL */ +#define CSEN_CTRL_STM_START (_CSEN_CTRL_STM_START << 16) /**< Shifted mode START for CSEN_CTRL */ +#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN (0x1UL << 18) /**< CSEN Digital Comparator Enable Bit. */ +#define _CSEN_CTRL_CMPEN_SHIFT 18 /**< Shift value for CSEN_CMPEN */ +#define _CSEN_CTRL_CMPEN_MASK 0x40000UL /**< Bit mask for CSEN_CMPEN */ +#define _CSEN_CTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_CMPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_DEFAULT (_CSEN_CTRL_CMPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_DISABLE (_CSEN_CTRL_CMPEN_DISABLE << 18) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_ENABLE (_CSEN_CTRL_CMPEN_ENABLE << 18) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF (0x1UL << 19) /**< CSEN Disable Right-Shift. */ +#define _CSEN_CTRL_DRSF_SHIFT 19 /**< Shift value for CSEN_DRSF */ +#define _CSEN_CTRL_DRSF_MASK 0x80000UL /**< Bit mask for CSEN_DRSF */ +#define _CSEN_CTRL_DRSF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_DRSF_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_DRSF_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_DEFAULT (_CSEN_CTRL_DRSF_DEFAULT << 19) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_DISABLE (_CSEN_CTRL_DRSF_DISABLE << 19) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_ENABLE (_CSEN_CTRL_DRSF_ENABLE << 19) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN (0x1UL << 20) /**< CSEN DMA Enable Bit. */ +#define _CSEN_CTRL_DMAEN_SHIFT 20 /**< Shift value for CSEN_DMAEN */ +#define _CSEN_CTRL_DMAEN_MASK 0x100000UL /**< Bit mask for CSEN_DMAEN */ +#define _CSEN_CTRL_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_DEFAULT (_CSEN_CTRL_DMAEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_DISABLE (_CSEN_CTRL_DMAEN_DISABLE << 20) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_ENABLE (_CSEN_CTRL_DMAEN_ENABLE << 20) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL (0x1UL << 21) /**< CSEN Converter Select */ +#define _CSEN_CTRL_CONVSEL_SHIFT 21 /**< Shift value for CSEN_CONVSEL */ +#define _CSEN_CTRL_CONVSEL_MASK 0x200000UL /**< Bit mask for CSEN_CONVSEL */ +#define _CSEN_CTRL_CONVSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CONVSEL_SAR 0x00000000UL /**< Mode SAR for CSEN_CTRL */ +#define _CSEN_CTRL_CONVSEL_DM 0x00000001UL /**< Mode DM for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_DEFAULT (_CSEN_CTRL_CONVSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_SAR (_CSEN_CTRL_CONVSEL_SAR << 21) /**< Shifted mode SAR for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_DM (_CSEN_CTRL_CONVSEL_DM << 21) /**< Shifted mode DM for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN (0x1UL << 22) /**< CSEN Chop Enable */ +#define _CSEN_CTRL_CHOPEN_SHIFT 22 /**< Shift value for CSEN_CHOPEN */ +#define _CSEN_CTRL_CHOPEN_MASK 0x400000UL /**< Bit mask for CSEN_CHOPEN */ +#define _CSEN_CTRL_CHOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CHOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_CHOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_DEFAULT (_CSEN_CTRL_CHOPEN_DEFAULT << 22) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_DISABLE (_CSEN_CTRL_CHOPEN_DISABLE << 22) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_ENABLE (_CSEN_CTRL_CHOPEN_ENABLE << 22) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND (0x1UL << 23) /**< CSEN auto ground enable */ +#define _CSEN_CTRL_AUTOGND_SHIFT 23 /**< Shift value for CSEN_AUTOGND */ +#define _CSEN_CTRL_AUTOGND_MASK 0x800000UL /**< Bit mask for CSEN_AUTOGND */ +#define _CSEN_CTRL_AUTOGND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_AUTOGND_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_AUTOGND_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_DEFAULT (_CSEN_CTRL_AUTOGND_DEFAULT << 23) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_DISABLE (_CSEN_CTRL_AUTOGND_DISABLE << 23) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_ENABLE (_CSEN_CTRL_AUTOGND_ENABLE << 23) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_MXUC (0x1UL << 24) /**< CSEN Mux Disconnect. */ +#define _CSEN_CTRL_MXUC_SHIFT 24 /**< Shift value for CSEN_MXUC */ +#define _CSEN_CTRL_MXUC_MASK 0x1000000UL /**< Bit mask for CSEN_MXUC */ +#define _CSEN_CTRL_MXUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_MXUC_CONN 0x00000000UL /**< Mode CONN for CSEN_CTRL */ +#define _CSEN_CTRL_MXUC_UNC 0x00000001UL /**< Mode UNC for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_DEFAULT (_CSEN_CTRL_MXUC_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_CONN (_CSEN_CTRL_MXUC_CONN << 24) /**< Shifted mode CONN for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_UNC (_CSEN_CTRL_MXUC_UNC << 24) /**< Shifted mode UNC for CSEN_CTRL */ +#define CSEN_CTRL_EMACMPEN (0x1UL << 25) /**< Greater and less than comparison using the exponential moving average (EMA) is enabled. */ +#define _CSEN_CTRL_EMACMPEN_SHIFT 25 /**< Shift value for CSEN_EMACMPEN */ +#define _CSEN_CTRL_EMACMPEN_MASK 0x2000000UL /**< Bit mask for CSEN_EMACMPEN */ +#define _CSEN_CTRL_EMACMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_EMACMPEN_DEFAULT (_CSEN_CTRL_EMACMPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE (0x1UL << 26) /**< Select Warmup mode for CSEN */ +#define _CSEN_CTRL_WARMUPMODE_SHIFT 26 /**< Shift value for CSEN_WARMUPMODE */ +#define _CSEN_CTRL_WARMUPMODE_MASK 0x4000000UL /**< Bit mask for CSEN_WARMUPMODE */ +#define _CSEN_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for CSEN_CTRL */ +#define _CSEN_CTRL_WARMUPMODE_KEEPCSENWARM 0x00000001UL /**< Mode KEEPCSENWARM for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_DEFAULT (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_NORMAL (_CSEN_CTRL_WARMUPMODE_NORMAL << 26) /**< Shifted mode NORMAL for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */ +#define CSEN_CTRL_LOCALSENS (0x1UL << 27) /**< Sense local cap connection instead of the external kelvin connection. */ +#define _CSEN_CTRL_LOCALSENS_SHIFT 27 /**< Shift value for CSEN_LOCALSENS */ +#define _CSEN_CTRL_LOCALSENS_MASK 0x8000000UL /**< Bit mask for CSEN_LOCALSENS */ +#define _CSEN_CTRL_LOCALSENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_LOCALSENS_DEFAULT (_CSEN_CTRL_LOCALSENS_DEFAULT << 27) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY (0x1UL << 28) /**< Sets the accuracy of the charge pump. */ +#define _CSEN_CTRL_CPACCURACY_SHIFT 28 /**< Shift value for CSEN_CPACCURACY */ +#define _CSEN_CTRL_CPACCURACY_MASK 0x10000000UL /**< Bit mask for CSEN_CPACCURACY */ +#define _CSEN_CTRL_CPACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CPACCURACY_LO 0x00000000UL /**< Mode LO for CSEN_CTRL */ +#define _CSEN_CTRL_CPACCURACY_HI 0x00000001UL /**< Mode HI for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_DEFAULT (_CSEN_CTRL_CPACCURACY_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_LO (_CSEN_CTRL_CPACCURACY_LO << 28) /**< Shifted mode LO for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_HI (_CSEN_CTRL_CPACCURACY_HI << 28) /**< Shifted mode HI for CSEN_CTRL */ + +/* Bit fields for CSEN TIMCTRL */ +#define _CSEN_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_MASK 0x0003FF07UL /**< Mask for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_SHIFT 0 /**< Shift value for CSEN_PCPRESC */ +#define _CSEN_TIMCTRL_PCPRESC_MASK 0x7UL /**< Bit mask for CSEN_PCPRESC */ +#define _CSEN_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DEFAULT (_CSEN_TIMCTRL_PCPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV1 (_CSEN_TIMCTRL_PCPRESC_DIV1 << 0) /**< Shifted mode DIV1 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV2 (_CSEN_TIMCTRL_PCPRESC_DIV2 << 0) /**< Shifted mode DIV2 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV4 (_CSEN_TIMCTRL_PCPRESC_DIV4 << 0) /**< Shifted mode DIV4 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV8 (_CSEN_TIMCTRL_PCPRESC_DIV8 << 0) /**< Shifted mode DIV8 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV16 (_CSEN_TIMCTRL_PCPRESC_DIV16 << 0) /**< Shifted mode DIV16 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV32 (_CSEN_TIMCTRL_PCPRESC_DIV32 << 0) /**< Shifted mode DIV32 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) /**< Shifted mode DIV64 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV128 (_CSEN_TIMCTRL_PCPRESC_DIV128 << 0) /**< Shifted mode DIV128 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCTOP_SHIFT 8 /**< Shift value for CSEN_PCTOP */ +#define _CSEN_TIMCTRL_PCTOP_MASK 0xFF00UL /**< Bit mask for CSEN_PCTOP */ +#define _CSEN_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCTOP_DEFAULT (_CSEN_TIMCTRL_PCTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_WARMUPCNT_SHIFT 16 /**< Shift value for CSEN_WARMUPCNT */ +#define _CSEN_TIMCTRL_WARMUPCNT_MASK 0x30000UL /**< Bit mask for CSEN_WARMUPCNT */ +#define _CSEN_TIMCTRL_WARMUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_WARMUPCNT_DEFAULT (_CSEN_TIMCTRL_WARMUPCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ + +/* Bit fields for CSEN CMD */ +#define _CSEN_CMD_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMD */ +#define _CSEN_CMD_MASK 0x00000001UL /**< Mask for CSEN_CMD */ +#define CSEN_CMD_START (0x1UL << 0) /**< Start a CSEN conversion. */ +#define _CSEN_CMD_START_SHIFT 0 /**< Shift value for CSEN_START */ +#define _CSEN_CMD_START_MASK 0x1UL /**< Bit mask for CSEN_START */ +#define _CSEN_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMD */ +#define CSEN_CMD_START_DEFAULT (_CSEN_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMD */ + +/* Bit fields for CSEN STATUS */ +#define _CSEN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CSEN_STATUS */ +#define _CSEN_STATUS_MASK 0x00000001UL /**< Mask for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY (0x1UL << 0) /**< CSEN Busy */ +#define _CSEN_STATUS_CSENBUSY_SHIFT 0 /**< Shift value for CSEN_CSENBUSY */ +#define _CSEN_STATUS_CSENBUSY_MASK 0x1UL /**< Bit mask for CSEN_CSENBUSY */ +#define _CSEN_STATUS_CSENBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_STATUS */ +#define _CSEN_STATUS_CSENBUSY_IDLE 0x00000000UL /**< Mode IDLE for CSEN_STATUS */ +#define _CSEN_STATUS_CSENBUSY_BUSY 0x00000001UL /**< Mode BUSY for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_DEFAULT (_CSEN_STATUS_CSENBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_IDLE (_CSEN_STATUS_CSENBUSY_IDLE << 0) /**< Shifted mode IDLE for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_BUSY (_CSEN_STATUS_CSENBUSY_BUSY << 0) /**< Shifted mode BUSY for CSEN_STATUS */ + +/* Bit fields for CSEN PRSSEL */ +#define _CSEN_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_MASK 0x0000000FUL /**< Mask for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_SHIFT 0 /**< Shift value for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_MASK 0xFUL /**< Bit mask for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_DEFAULT (_CSEN_PRSSEL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH0 (_CSEN_PRSSEL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH1 (_CSEN_PRSSEL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH2 (_CSEN_PRSSEL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH3 (_CSEN_PRSSEL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH4 (_CSEN_PRSSEL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH5 (_CSEN_PRSSEL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH6 (_CSEN_PRSSEL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH7 (_CSEN_PRSSEL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH8 (_CSEN_PRSSEL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH9 (_CSEN_PRSSEL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH10 (_CSEN_PRSSEL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH11 (_CSEN_PRSSEL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for CSEN_PRSSEL */ + +/* Bit fields for CSEN DATA */ +#define _CSEN_DATA_RESETVALUE 0x00000000UL /**< Default value for CSEN_DATA */ +#define _CSEN_DATA_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DATA */ +#define _CSEN_DATA_DATA_SHIFT 0 /**< Shift value for CSEN_DATA */ +#define _CSEN_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_DATA */ +#define _CSEN_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DATA */ +#define CSEN_DATA_DATA_DEFAULT (_CSEN_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DATA */ + +/* Bit fields for CSEN SCANMASK0 */ +#define _CSEN_SCANMASK0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK0 */ +#define _CSEN_SCANMASK0_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK0 */ +#define _CSEN_SCANMASK0_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK0_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK0_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK0 */ +#define CSEN_SCANMASK0_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK0_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK0 */ + +/* Bit fields for CSEN SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT 0 /**< Shift value for CSEN_INPUT0TO7SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT0TO7SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT 8 /**< Shift value for CSEN_INPUT8TO15SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT8TO15SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT 16 /**< Shift value for CSEN_INPUT16TO23SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT16TO23SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT 24 /**< Shift value for CSEN_INPUT24TO31SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT24TO31SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ + +/* Bit fields for CSEN SCANMASK1 */ +#define _CSEN_SCANMASK1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK1 */ +#define _CSEN_SCANMASK1_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK1 */ +#define _CSEN_SCANMASK1_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK1_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK1_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK1 */ +#define CSEN_SCANMASK1_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK1_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK1 */ + +/* Bit fields for CSEN SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT 0 /**< Shift value for CSEN_INPUT32TO39SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT32TO39SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT 8 /**< Shift value for CSEN_INPUT40TO47SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT40TO47SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT 16 /**< Shift value for CSEN_INPUT48TO55SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT48TO55SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT 24 /**< Shift value for CSEN_INPUT56TO63SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT56TO63SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ + +/* Bit fields for CSEN APORTREQ */ +#define _CSEN_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTREQ */ +#define _CSEN_APORTREQ_MASK 0x000003FCUL /**< Mask for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _CSEN_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for CSEN_APORT1XREQ */ +#define _CSEN_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for CSEN_APORT1XREQ */ +#define _CSEN_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1XREQ_DEFAULT (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _CSEN_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for CSEN_APORT1YREQ */ +#define _CSEN_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for CSEN_APORT1YREQ */ +#define _CSEN_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1YREQ_DEFAULT (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _CSEN_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for CSEN_APORT2XREQ */ +#define _CSEN_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for CSEN_APORT2XREQ */ +#define _CSEN_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2XREQ_DEFAULT (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _CSEN_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for CSEN_APORT2YREQ */ +#define _CSEN_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for CSEN_APORT2YREQ */ +#define _CSEN_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2YREQ_DEFAULT (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _CSEN_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for CSEN_APORT3XREQ */ +#define _CSEN_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for CSEN_APORT3XREQ */ +#define _CSEN_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3XREQ_DEFAULT (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _CSEN_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for CSEN_APORT3YREQ */ +#define _CSEN_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for CSEN_APORT3YREQ */ +#define _CSEN_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3YREQ_DEFAULT (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _CSEN_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for CSEN_APORT4XREQ */ +#define _CSEN_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for CSEN_APORT4XREQ */ +#define _CSEN_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4XREQ_DEFAULT (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _CSEN_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for CSEN_APORT4YREQ */ +#define _CSEN_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for CSEN_APORT4YREQ */ +#define _CSEN_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4YREQ_DEFAULT (_CSEN_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ + +/* Bit fields for CSEN APORTCONFLICT */ +#define _CSEN_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTCONFLICT */ +#define _CSEN_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for CSEN_APORT1XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for CSEN_APORT1XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for CSEN_APORT1YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for CSEN_APORT1YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORT2XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORT2XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for CSEN_APORT2YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for CSEN_APORT2YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for CSEN_APORT3XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for CSEN_APORT3XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for CSEN_APORT3YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for CSEN_APORT3YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for CSEN_APORT4XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for CSEN_APORT4XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for CSEN_APORT4YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for CSEN_APORT4YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ + +/* Bit fields for CSEN CMPTHR */ +#define _CSEN_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_MASK 0x0000FFFFUL /**< Mask for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_SHIFT 0 /**< Shift value for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_MASK 0xFFFFUL /**< Bit mask for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMPTHR */ +#define CSEN_CMPTHR_CMPTHR_DEFAULT (_CSEN_CMPTHR_CMPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMPTHR */ + +/* Bit fields for CSEN EMA */ +#define _CSEN_EMA_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMA */ +#define _CSEN_EMA_MASK 0x003FFFFFUL /**< Mask for CSEN_EMA */ +#define _CSEN_EMA_EMA_SHIFT 0 /**< Shift value for CSEN_EMA */ +#define _CSEN_EMA_EMA_MASK 0x3FFFFFUL /**< Bit mask for CSEN_EMA */ +#define _CSEN_EMA_EMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMA */ +#define CSEN_EMA_EMA_DEFAULT (_CSEN_EMA_EMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMA */ + +/* Bit fields for CSEN EMACTRL */ +#define _CSEN_EMACTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_MASK 0x00000007UL /**< Mask for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_SHIFT 0 /**< Shift value for CSEN_EMASAMPLE */ +#define _CSEN_EMACTRL_EMASAMPLE_MASK 0x7UL /**< Bit mask for CSEN_EMASAMPLE */ +#define _CSEN_EMACTRL_EMASAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W1 0x00000000UL /**< Mode W1 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W2 0x00000001UL /**< Mode W2 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W4 0x00000002UL /**< Mode W4 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W8 0x00000003UL /**< Mode W8 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W16 0x00000004UL /**< Mode W16 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W32 0x00000005UL /**< Mode W32 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W64 0x00000006UL /**< Mode W64 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_DEFAULT (_CSEN_EMACTRL_EMASAMPLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W1 (_CSEN_EMACTRL_EMASAMPLE_W1 << 0) /**< Shifted mode W1 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W2 (_CSEN_EMACTRL_EMASAMPLE_W2 << 0) /**< Shifted mode W2 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W4 (_CSEN_EMACTRL_EMASAMPLE_W4 << 0) /**< Shifted mode W4 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W8 (_CSEN_EMACTRL_EMASAMPLE_W8 << 0) /**< Shifted mode W8 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W16 (_CSEN_EMACTRL_EMASAMPLE_W16 << 0) /**< Shifted mode W16 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W32 (_CSEN_EMACTRL_EMASAMPLE_W32 << 0) /**< Shifted mode W32 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W64 (_CSEN_EMACTRL_EMASAMPLE_W64 << 0) /**< Shifted mode W64 for CSEN_EMACTRL */ + +/* Bit fields for CSEN SINGLECTRL */ +#define _CSEN_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_MASK 0x000007F0UL /**< Mask for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_SHIFT 4 /**< Shift value for CSEN_SINGLESEL */ +#define _CSEN_SINGLECTRL_SINGLESEL_MASK 0x7F0UL /**< Bit mask for CSEN_SINGLESEL */ +#define _CSEN_SINGLECTRL_SINGLESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_DEFAULT (_CSEN_SINGLECTRL_SINGLESEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 << 4) /**< Shifted mode APORT3XCH0 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 << 4) /**< Shifted mode APORT3YCH1 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 << 4) /**< Shifted mode APORT3XCH2 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 << 4) /**< Shifted mode APORT3YCH3 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 << 4) /**< Shifted mode APORT3XCH4 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 << 4) /**< Shifted mode APORT3YCH5 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 << 4) /**< Shifted mode APORT3XCH6 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 << 4) /**< Shifted mode APORT3YCH7 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 << 4) /**< Shifted mode APORT3XCH8 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 << 4) /**< Shifted mode APORT3YCH9 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 << 4) /**< Shifted mode APORT3XCH10 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 << 4) /**< Shifted mode APORT3YCH11 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 << 4) /**< Shifted mode APORT3XCH12 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 << 4) /**< Shifted mode APORT3YCH13 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 << 4) /**< Shifted mode APORT3XCH14 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 << 4) /**< Shifted mode APORT3YCH15 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 << 4) /**< Shifted mode APORT3XCH16 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 << 4) /**< Shifted mode APORT3YCH17 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 << 4) /**< Shifted mode APORT3XCH18 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 << 4) /**< Shifted mode APORT3YCH19 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 << 4) /**< Shifted mode APORT3XCH20 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 << 4) /**< Shifted mode APORT3YCH21 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 << 4) /**< Shifted mode APORT3XCH22 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 << 4) /**< Shifted mode APORT3YCH23 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 << 4) /**< Shifted mode APORT3XCH24 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 << 4) /**< Shifted mode APORT3YCH25 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 << 4) /**< Shifted mode APORT3XCH26 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 << 4) /**< Shifted mode APORT3YCH27 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 << 4) /**< Shifted mode APORT3XCH28 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 << 4) /**< Shifted mode APORT3YCH29 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 << 4) /**< Shifted mode APORT3XCH30 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 << 4) /**< Shifted mode APORT3YCH31 for CSEN_SINGLECTRL */ + +/* Bit fields for CSEN DMBASELINE */ +#define _CSEN_DMBASELINE_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_BASELINEUP_SHIFT 0 /**< Shift value for CSEN_BASELINEUP */ +#define _CSEN_DMBASELINE_BASELINEUP_MASK 0xFFFFUL /**< Bit mask for CSEN_BASELINEUP */ +#define _CSEN_DMBASELINE_BASELINEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ +#define CSEN_DMBASELINE_BASELINEUP_DEFAULT (_CSEN_DMBASELINE_BASELINEUP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_BASELINEDN_SHIFT 16 /**< Shift value for CSEN_BASELINEDN */ +#define _CSEN_DMBASELINE_BASELINEDN_MASK 0xFFFF0000UL /**< Bit mask for CSEN_BASELINEDN */ +#define _CSEN_DMBASELINE_BASELINEDN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ +#define CSEN_DMBASELINE_BASELINEDN_DEFAULT (_CSEN_DMBASELINE_BASELINEDN_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ + +/* Bit fields for CSEN DMCFG */ +#define _CSEN_DMCFG_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMCFG */ +#define _CSEN_DMCFG_MASK 0x103F0FFFUL /**< Mask for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMG_SHIFT 0 /**< Shift value for CSEN_DMG */ +#define _CSEN_DMCFG_DMG_MASK 0xFFUL /**< Bit mask for CSEN_DMG */ +#define _CSEN_DMCFG_DMG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMG_DEFAULT (_CSEN_DMCFG_DMG_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMR_SHIFT 8 /**< Shift value for CSEN_DMR */ +#define _CSEN_DMCFG_DMR_MASK 0xF00UL /**< Bit mask for CSEN_DMR */ +#define _CSEN_DMCFG_DMR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMR_DEFAULT (_CSEN_DMCFG_DMR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMCR_SHIFT 16 /**< Shift value for CSEN_DMCR */ +#define _CSEN_DMCFG_DMCR_MASK 0xF0000UL /**< Bit mask for CSEN_DMCR */ +#define _CSEN_DMCFG_DMCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMCR_DEFAULT (_CSEN_DMCFG_DMCR_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_SHIFT 20 /**< Shift value for CSEN_CRMODE */ +#define _CSEN_DMCFG_CRMODE_MASK 0x300000UL /**< Bit mask for CSEN_CRMODE */ +#define _CSEN_DMCFG_CRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM10 0x00000000UL /**< Mode DM10 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM12 0x00000001UL /**< Mode DM12 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM14 0x00000002UL /**< Mode DM14 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM16 0x00000003UL /**< Mode DM16 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DEFAULT (_CSEN_DMCFG_CRMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM10 (_CSEN_DMCFG_CRMODE_DM10 << 20) /**< Shifted mode DM10 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM12 (_CSEN_DMCFG_CRMODE_DM12 << 20) /**< Shifted mode DM12 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM14 (_CSEN_DMCFG_CRMODE_DM14 << 20) /**< Shifted mode DM14 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM16 (_CSEN_DMCFG_CRMODE_DM16 << 20) /**< Shifted mode DM16 for CSEN_DMCFG */ +#define CSEN_DMCFG_DMGRDIS (0x1UL << 28) /**< Disable delta modulator gain reduction. */ +#define _CSEN_DMCFG_DMGRDIS_SHIFT 28 /**< Shift value for CSEN_DMGRDIS */ +#define _CSEN_DMCFG_DMGRDIS_MASK 0x10000000UL /**< Bit mask for CSEN_DMGRDIS */ +#define _CSEN_DMCFG_DMGRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMGRDIS_DEFAULT (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */ + +/* Bit fields for CSEN ANACTRL */ +#define _CSEN_ANACTRL_RESETVALUE 0x00000070UL /**< Default value for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_MASK 0x03730771UL /**< Mask for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF (0x1UL << 0) /**< Reference capacitor divide by half. */ +#define _CSEN_ANACTRL_CREFHALF_SHIFT 0 /**< Shift value for CSEN_CREFHALF */ +#define _CSEN_ANACTRL_CREFHALF_MASK 0x1UL /**< Bit mask for CSEN_CREFHALF */ +#define _CSEN_ANACTRL_CREFHALF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_CREFHALF_FULL 0x00000000UL /**< Mode FULL for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_CREFHALF_HALF 0x00000001UL /**< Mode HALF for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_DEFAULT (_CSEN_ANACTRL_CREFHALF_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_FULL (_CSEN_ANACTRL_CREFHALF_FULL << 0) /**< Shifted mode FULL for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_HALF (_CSEN_ANACTRL_CREFHALF_HALF << 0) /**< Shifted mode HALF for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_IREFPROG_SHIFT 4 /**< Shift value for CSEN_IREFPROG */ +#define _CSEN_ANACTRL_IREFPROG_MASK 0x70UL /**< Bit mask for CSEN_IREFPROG */ +#define _CSEN_ANACTRL_IREFPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_IREFPROG_DEFAULT (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_IDACIREFS_SHIFT 8 /**< Shift value for CSEN_IDACIREFS */ +#define _CSEN_ANACTRL_IDACIREFS_MASK 0x700UL /**< Bit mask for CSEN_IDACIREFS */ +#define _CSEN_ANACTRL_IDACIREFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_IDACIREFS_DEFAULT (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_SHIFT 16 /**< Shift value for CSEN_DUTYSCALE */ +#define _CSEN_ANACTRL_DUTYSCALE_MASK 0x30000UL /**< Bit mask for CSEN_DUTYSCALE */ +#define _CSEN_ANACTRL_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DEFAULT (_CSEN_ANACTRL_DUTYSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV1 (_CSEN_ANACTRL_DUTYSCALE_DIV1 << 16) /**< Shifted mode DIV1 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV2 (_CSEN_ANACTRL_DUTYSCALE_DIV2 << 16) /**< Shifted mode DIV2 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV4 (_CSEN_ANACTRL_DUTYSCALE_DIV4 << 16) /**< Shifted mode DIV4 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV8 (_CSEN_ANACTRL_DUTYSCALE_DIV8 << 16) /**< Shifted mode DIV8 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_TRSTPROG_SHIFT 20 /**< Shift value for CSEN_TRSTPROG */ +#define _CSEN_ANACTRL_TRSTPROG_MASK 0x700000UL /**< Bit mask for CSEN_TRSTPROG */ +#define _CSEN_ANACTRL_TRSTPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_TRSTPROG_DEFAULT (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_SHIFT 24 /**< Shift value for CSEN_BIASPROG */ +#define _CSEN_ANACTRL_BIASPROG_MASK 0x3000000UL /**< Bit mask for CSEN_BIASPROG */ +#define _CSEN_ANACTRL_BIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_ONEX 0x00000000UL /**< Mode ONEX for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_TWOX 0x00000001UL /**< Mode TWOX for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_ONETENTH 0x00000002UL /**< Mode ONETENTH for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_HALF 0x00000003UL /**< Mode HALF for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_DEFAULT (_CSEN_ANACTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_ONEX (_CSEN_ANACTRL_BIASPROG_ONEX << 24) /**< Shifted mode ONEX for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_TWOX (_CSEN_ANACTRL_BIASPROG_TWOX << 24) /**< Shifted mode TWOX for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_ONETENTH (_CSEN_ANACTRL_BIASPROG_ONETENTH << 24) /**< Shifted mode ONETENTH for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_HALF (_CSEN_ANACTRL_BIASPROG_HALF << 24) /**< Shifted mode HALF for CSEN_ANACTRL */ + +/* Bit fields for CSEN IF */ +#define _CSEN_IF_RESETVALUE 0x00000000UL /**< Default value for CSEN_IF */ +#define _CSEN_IF_MASK 0x0000001FUL /**< Mask for CSEN_IF */ +#define CSEN_IF_CMP (0x1UL << 0) /**< CSEN Digital Comparator Interrupt Flag */ +#define _CSEN_IF_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IF_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IF_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CMP_DEFAULT (_CSEN_IF_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CONV (0x1UL << 1) /**< CSEN Conversion Done Interrupt Flag */ +#define _CSEN_IF_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IF_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IF_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CONV_DEFAULT (_CSEN_IF_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_EOS (0x1UL << 2) /**< CSEN End of Scan Interrupt Flag. */ +#define _CSEN_IF_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IF_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IF_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_EOS_DEFAULT (_CSEN_IF_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_DMAOF (0x1UL << 3) /**< CSEN DMA Overflow Interrupt Flag. */ +#define _CSEN_IF_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IF_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IF_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_DMAOF_DEFAULT (_CSEN_IF_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_APORTCONFLICT (0x1UL << 4) /**< APORT Conflict Interrupt Flag */ +#define _CSEN_IF_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IF_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_APORTCONFLICT_DEFAULT (_CSEN_IF_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IF */ + +/* Bit fields for CSEN IFS */ +#define _CSEN_IFS_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFS */ +#define _CSEN_IFS_MASK 0x0000001FUL /**< Mask for CSEN_IFS */ +#define CSEN_IFS_CMP (0x1UL << 0) /**< Set CMP Interrupt Flag */ +#define _CSEN_IFS_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IFS_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IFS_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CMP_DEFAULT (_CSEN_IFS_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CONV (0x1UL << 1) /**< Set CONV Interrupt Flag */ +#define _CSEN_IFS_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IFS_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IFS_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CONV_DEFAULT (_CSEN_IFS_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_EOS (0x1UL << 2) /**< Set EOS Interrupt Flag */ +#define _CSEN_IFS_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IFS_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IFS_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_EOS_DEFAULT (_CSEN_IFS_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_DMAOF (0x1UL << 3) /**< Set DMAOF Interrupt Flag */ +#define _CSEN_IFS_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IFS_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IFS_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_DMAOF_DEFAULT (_CSEN_IFS_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_APORTCONFLICT (0x1UL << 4) /**< Set APORTCONFLICT Interrupt Flag */ +#define _CSEN_IFS_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IFS_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_APORTCONFLICT_DEFAULT (_CSEN_IFS_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFS */ + +/* Bit fields for CSEN IFC */ +#define _CSEN_IFC_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFC */ +#define _CSEN_IFC_MASK 0x0000001FUL /**< Mask for CSEN_IFC */ +#define CSEN_IFC_CMP (0x1UL << 0) /**< Clear CMP Interrupt Flag */ +#define _CSEN_IFC_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IFC_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IFC_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CMP_DEFAULT (_CSEN_IFC_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CONV (0x1UL << 1) /**< Clear CONV Interrupt Flag */ +#define _CSEN_IFC_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IFC_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IFC_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CONV_DEFAULT (_CSEN_IFC_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_EOS (0x1UL << 2) /**< Clear EOS Interrupt Flag */ +#define _CSEN_IFC_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IFC_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IFC_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_EOS_DEFAULT (_CSEN_IFC_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_DMAOF (0x1UL << 3) /**< Clear DMAOF Interrupt Flag */ +#define _CSEN_IFC_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IFC_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IFC_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_DMAOF_DEFAULT (_CSEN_IFC_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_APORTCONFLICT (0x1UL << 4) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _CSEN_IFC_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IFC_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_APORTCONFLICT_DEFAULT (_CSEN_IFC_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFC */ + +/* Bit fields for CSEN IEN */ +#define _CSEN_IEN_RESETVALUE 0x00000000UL /**< Default value for CSEN_IEN */ +#define _CSEN_IEN_MASK 0x0000001FUL /**< Mask for CSEN_IEN */ +#define CSEN_IEN_CMP (0x1UL << 0) /**< CMP Interrupt Enable */ +#define _CSEN_IEN_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IEN_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IEN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CMP_DEFAULT (_CSEN_IEN_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CONV (0x1UL << 1) /**< CONV Interrupt Enable */ +#define _CSEN_IEN_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IEN_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IEN_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CONV_DEFAULT (_CSEN_IEN_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_EOS (0x1UL << 2) /**< EOS Interrupt Enable */ +#define _CSEN_IEN_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IEN_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IEN_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_EOS_DEFAULT (_CSEN_IEN_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_DMAOF (0x1UL << 3) /**< DMAOF Interrupt Enable */ +#define _CSEN_IEN_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IEN_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IEN_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_DMAOF_DEFAULT (_CSEN_IEN_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_APORTCONFLICT (0x1UL << 4) /**< APORTCONFLICT Interrupt Enable */ +#define _CSEN_IEN_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IEN_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_APORTCONFLICT_DEFAULT (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */ + +/** @} End of group EFM32PG12B_CSEN */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_devinfo.h new file mode 100644 index 00000000000..93f0a33b9b7 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_devinfo.h @@ -0,0 +1,1274 @@ +/**************************************************************************//** + * @file efm32pg12b_devinfo.h + * @brief EFM32PG12B_DEVINFO register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_DEVINFO + * @{ + *****************************************************************************/ + +typedef struct +{ + __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */ + uint32_t RESERVED0[7]; /**< Reserved for future use **/ + __IM uint32_t EXTINFO; /**< External Component description */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */ + __IM uint32_t EUI48H; /**< OUI */ + __IM uint32_t CUSTOMINFO; /**< Custom information */ + __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */ + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */ + __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */ + __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */ + __IM uint32_t PART; /**< Part description */ + __IM uint32_t DEVINFOREV; /**< Device information page revision */ + __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */ + uint32_t RESERVED3[2]; /**< Reserved for future use **/ + __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */ + __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */ + __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */ + __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */ + uint32_t RESERVED4[4]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */ + uint32_t RESERVED5[2]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */ + uint32_t RESERVED6[2]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */ + __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */ + __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */ + __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */ + __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */ + uint32_t RESERVED8[11]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */ + uint32_t RESERVED9[2]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */ + uint32_t RESERVED10[2]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */ + __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */ + __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */ + uint32_t RESERVED11[1]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */ + __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */ + __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */ + uint32_t RESERVED12[11]; /**< Reserved for future use **/ + __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */ + __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */ + __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */ + uint32_t RESERVED13[3]; /**< Reserved for future use **/ + __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */ + __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */ + uint32_t RESERVED14[2]; /**< Reserved for future use **/ + __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */ + __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */ + __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */ + __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */ + __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */ + __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */ + __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */ + __IM uint32_t VDAC0MAINCAL; /**< VDAC0 Cals for Main Path */ + __IM uint32_t VDAC0ALTCAL; /**< VDAC0 Cals for Alternate Path */ + __IM uint32_t VDAC0CH1CAL; /**< VDAC0 CH1 Error Cal */ + __IM uint32_t OPA0CAL0; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA0CAL1; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA0CAL2; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA0CAL3; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA1CAL0; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA1CAL1; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA1CAL2; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA1CAL3; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA2CAL0; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA2CAL1; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA2CAL2; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA2CAL3; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t CSENGAINCAL; /**< Cap Sense Gain Adjustment */ + uint32_t RESERVED15[3]; /**< Reserved for future use **/ + __IM uint32_t OPA0CAL4; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA0CAL5; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA0CAL6; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA0CAL7; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t OPA1CAL4; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA1CAL5; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA1CAL6; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA1CAL7; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t OPA2CAL4; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA2CAL5; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA2CAL6; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA2CAL7; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ +} DEVINFO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_DEVINFO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for DEVINFO CAL */ +#define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */ +#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */ +#define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */ +#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */ +#define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */ +#define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */ +#define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */ +#define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */ +#define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */ +#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_BGA (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */ +#define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */ +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */ +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */ + +/* Bit fields for DEVINFO UNIQUEL */ +#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */ +#define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */ + +/* Bit fields for DEVINFO UNIQUEH */ +#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */ +#define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */ +#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */ +#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */ +#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL /**< Mode EFR32MG2P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16) /**< Shifted mode EFR32MG2P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */ +#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */ +#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */ + +/* Bit fields for DEVINFO DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */ + +/* Bit fields for DEVINFO ADC0CAL0 */ +#define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */ +#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */ +#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */ +#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */ +#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */ + +/* Bit fields for DEVINFO ADC0CAL1 */ +#define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */ +#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */ +#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */ +#define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */ +#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */ +#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */ + +/* Bit fields for DEVINFO ADC0CAL2 */ +#define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */ +#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */ + +/* Bit fields for DEVINFO ADC0CAL3 */ +#define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */ +#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */ +#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */ + +/* Bit fields for DEVINFO HFRCOCAL0 */ +#define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */ +#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL3 */ +#define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */ +#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL6 */ +#define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */ +#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL7 */ +#define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */ +#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL8 */ +#define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */ +#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL10 */ +#define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */ +#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL11 */ +#define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */ +#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL12 */ +#define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */ +#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL0 */ +#define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */ +#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL3 */ +#define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */ +#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL6 */ +#define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */ +#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL7 */ +#define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */ +#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL8 */ +#define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */ +#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL10 */ +#define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */ +#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL11 */ +#define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */ +#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL12 */ +#define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */ +#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO VMONCAL0 */ +#define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */ + +/* Bit fields for DEVINFO VMONCAL1 */ +#define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */ + +/* Bit fields for DEVINFO VMONCAL2 */ +#define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */ + +/* Bit fields for DEVINFO IDAC0CAL0 */ +#define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */ + +/* Bit fields for DEVINFO IDAC0CAL1 */ +#define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */ + +/* Bit fields for DEVINFO DCDCLNVCTRL0 */ +#define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL0 */ +#define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL1 */ +#define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL2 */ +#define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL3 */ +#define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */ + +/* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */ + +/* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */ + +/* Bit fields for DEVINFO VDAC0MAINCAL */ +#define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0MAINCAL */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12 /**< Shift value for GAINERRTRIM1V25 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18 /**< Shift value for GAINERRTRIM2V5 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPIN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPIN */ + +/* Bit fields for DEVINFO VDAC0ALTCAL */ +#define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0ALTCAL */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12 /**< Shift value for GAINERRTRIM1V25ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18 /**< Shift value for GAINERRTRIM2V5ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPINALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPINALT */ + +/* Bit fields for DEVINFO VDAC0CH1CAL */ +#define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL /**< Mask for DEVINFO_VDAC0CH1CAL */ +#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for OFFSETTRIM */ +#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for OFFSETTRIM */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4 /**< Shift value for GAINERRTRIMCH1A */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL /**< Bit mask for GAINERRTRIMCH1A */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8 /**< Shift value for GAINERRTRIMCH1B */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL /**< Bit mask for GAINERRTRIMCH1B */ + +/* Bit fields for DEVINFO OPA0CAL0 */ +#define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL0 */ +#define _DEVINFO_OPA0CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL1 */ +#define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL1 */ +#define _DEVINFO_OPA0CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL2 */ +#define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL2 */ +#define _DEVINFO_OPA0CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL3 */ +#define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL3 */ +#define _DEVINFO_OPA0CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL0 */ +#define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL0 */ +#define _DEVINFO_OPA1CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL1 */ +#define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL1 */ +#define _DEVINFO_OPA1CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL2 */ +#define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL2 */ +#define _DEVINFO_OPA1CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL3 */ +#define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL3 */ +#define _DEVINFO_OPA1CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL0 */ +#define _DEVINFO_OPA2CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL0 */ +#define _DEVINFO_OPA2CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL1 */ +#define _DEVINFO_OPA2CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL1 */ +#define _DEVINFO_OPA2CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL2 */ +#define _DEVINFO_OPA2CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL2 */ +#define _DEVINFO_OPA2CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL3 */ +#define _DEVINFO_OPA2CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL3 */ +#define _DEVINFO_OPA2CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO CSENGAINCAL */ +#define _DEVINFO_CSENGAINCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_CSENGAINCAL */ +#define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT 0 /**< Shift value for GAINCAL */ +#define _DEVINFO_CSENGAINCAL_GAINCAL_MASK 0xFFUL /**< Bit mask for GAINCAL */ + +/* Bit fields for DEVINFO OPA0CAL4 */ +#define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL4 */ +#define _DEVINFO_OPA0CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL5 */ +#define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL5 */ +#define _DEVINFO_OPA0CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL6 */ +#define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL6 */ +#define _DEVINFO_OPA0CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL7 */ +#define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL7 */ +#define _DEVINFO_OPA0CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL4 */ +#define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL4 */ +#define _DEVINFO_OPA1CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL5 */ +#define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL5 */ +#define _DEVINFO_OPA1CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL6 */ +#define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL6 */ +#define _DEVINFO_OPA1CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL7 */ +#define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL7 */ +#define _DEVINFO_OPA1CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL4 */ +#define _DEVINFO_OPA2CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL4 */ +#define _DEVINFO_OPA2CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL5 */ +#define _DEVINFO_OPA2CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL5 */ +#define _DEVINFO_OPA2CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL6 */ +#define _DEVINFO_OPA2CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL6 */ +#define _DEVINFO_OPA2CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL7 */ +#define _DEVINFO_OPA2CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL7 */ +#define _DEVINFO_OPA2CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/** @} End of group EFM32PG12B_DEVINFO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_dma_descriptor.h new file mode 100644 index 00000000000..0374bc139c1 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_dma_descriptor.h @@ -0,0 +1,52 @@ +/**************************************************************************//** + * @file efm32pg12b_dma_descriptor.h + * @brief EFM32PG12B_DMA_DESCRIPTOR register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_DMA_DESCRIPTOR + * @{ + *****************************************************************************/ +typedef struct +{ + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_dmareq.h new file mode 100644 index 00000000000..9834e69604d --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_dmareq.h @@ -0,0 +1,110 @@ +/**************************************************************************//** + * @file efm32pg12b_dmareq.h + * @brief EFM32PG12B_DMAREQ register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B_DMAREQ_BitFields + * @{ + *****************************************************************************/ +#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */ +#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */ +#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */ +#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */ +#define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */ +#define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */ +#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */ +#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */ +#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */ +#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */ +#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */ +#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */ +#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */ +#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */ +#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */ +#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */ +#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */ +#define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */ +#define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */ +#define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */ +#define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */ +#define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */ +#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */ +#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */ +#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */ +#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */ +#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */ +#define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */ +#define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */ +#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */ +#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */ +#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */ +#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */ +#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */ +#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */ +#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */ +#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */ +#define DMAREQ_TIMER1_CC3 ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */ +#define DMAREQ_WTIMER0_UFOF ((26 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */ +#define DMAREQ_WTIMER0_CC0 ((26 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */ +#define DMAREQ_WTIMER0_CC1 ((26 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */ +#define DMAREQ_WTIMER0_CC2 ((26 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */ +#define DMAREQ_WTIMER1_UFOF ((27 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */ +#define DMAREQ_WTIMER1_CC0 ((27 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */ +#define DMAREQ_WTIMER1_CC1 ((27 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */ +#define DMAREQ_WTIMER1_CC2 ((27 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */ +#define DMAREQ_WTIMER1_CC3 ((27 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */ +#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */ +#define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */ +#define DMAREQ_CRYPTO_DATA0WR DMAREQ_CRYPTO0_DATA0WR /**< Alias for DMAREQ_CRYPTO0_DATA0WR */ +#define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */ +#define DMAREQ_CRYPTO_DATA0XWR DMAREQ_CRYPTO0_DATA0XWR /**< Alias for DMAREQ_CRYPTO0_DATA0XWR */ +#define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */ +#define DMAREQ_CRYPTO_DATA0RD DMAREQ_CRYPTO0_DATA0RD /**< Alias for DMAREQ_CRYPTO0_DATA0RD */ +#define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */ +#define DMAREQ_CRYPTO_DATA1WR DMAREQ_CRYPTO0_DATA1WR /**< Alias for DMAREQ_CRYPTO0_DATA1WR */ +#define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */ +#define DMAREQ_CRYPTO_DATA1RD DMAREQ_CRYPTO0_DATA1RD /**< Alias for DMAREQ_CRYPTO0_DATA1RD */ +#define DMAREQ_CSEN_DATA ((50 << 16) + 0) /**< DMA channel select for CSEN_DATA */ +#define DMAREQ_CSEN_BSLN ((50 << 16) + 1) /**< DMA channel select for CSEN_BSLN */ +#define DMAREQ_LESENSE_BUFDATAV ((51 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */ +#define DMAREQ_CRYPTO1_DATA0WR ((52 << 16) + 0) /**< DMA channel select for CRYPTO1_DATA0WR */ +#define DMAREQ_CRYPTO1_DATA0XWR ((52 << 16) + 1) /**< DMA channel select for CRYPTO1_DATA0XWR */ +#define DMAREQ_CRYPTO1_DATA0RD ((52 << 16) + 2) /**< DMA channel select for CRYPTO1_DATA0RD */ +#define DMAREQ_CRYPTO1_DATA1WR ((52 << 16) + 3) /**< DMA channel select for CRYPTO1_DATA1WR */ +#define DMAREQ_CRYPTO1_DATA1RD ((52 << 16) + 4) /**< DMA channel select for CRYPTO1_DATA1RD */ + +/** @} End of group EFM32PG12B_DMAREQ */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_emu.h new file mode 100644 index 00000000000..a30a40a5697 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_emu.h @@ -0,0 +1,1437 @@ +/**************************************************************************//** + * @file efm32pg12b_emu.h + * @brief EFM32PG12B_EMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_EMU + * @{ + * @brief EFM32PG12B_EMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */ + __IM uint32_t TEMP; /**< Value of last temperature measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + __IOM uint32_t PWRCFG; /**< Power Configuration Register */ + __IOM uint32_t PWRCTRL; /**< Power Control Register. */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED4[1]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED5[5]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + + uint32_t RESERVED6[5]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + + uint32_t RESERVED7[12]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration bits for low power mode to be applied during EM01, this field is only relevant if LP mode is used in EM01. */ + + uint32_t RESERVED8[4]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears corresponding bits in EM23PERNORETAINSTATUS unlocking access to peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status indicating if peripherals were powered down in EM23, subsequently locking access to it. */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When set corresponding peripherals may get powered down in EM23 */ +} EMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_EMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically configures Flash, Ram and Frequency to wakeup from EM2 or EM3 at low voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x0417011FUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */ +#define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */ +#define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */ +#define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE31FC0FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */ +#define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */ +#define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE31FC0FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE31FC0FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE31FC0FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCFG */ +#define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */ +#define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_UNCONFIGURED 0x00000000UL /**< Mode UNCONFIGURED for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_UNCONFIGURED (_EMU_PWRCFG_PWRCFG_UNCONFIGURED << 0) /**< Shifted mode UNCONFIGURED for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00001420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This field selects the input for the regulator. */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_DVDDBODDIS (0x1UL << 12) /**< DVDD BOD Disable */ +#define _EMU_PWRCTRL_DVDDBODDIS_SHIFT 12 /**< Shift value for EMU_DVDDBODDIS */ +#define _EMU_PWRCTRL_DVDDBODDIS_MASK 0x1000UL /**< Bit mask for EMU_DVDDBODDIS */ +#define _EMU_PWRCTRL_DVDDBODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_DVDDBODDIS_DEFAULT (_EMU_PWRCTRL_DVDDBODDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP mode hysteresis in the state machine control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator threshold on the high side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC into CCM mode immediately, based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP mode duty cycling enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x00000003UL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0x3UL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 0x00000002UL /**< Mode BLK1 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 0x00000003UL /**< Mode BLK0TO1 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 << 0) /**< Shifted mode BLK1 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 << 0) /**< Shifted mode BLK0TO1 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x00000001UL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0x1UL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK 0x00000001UL /**< Mode BLK for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK << 0) /**< Shifted mode BLK for EMU_RAM2CTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears status bit of ACMP0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears status bit of ACMP1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears status bit of PCNT0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears status bit of PCNT1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears status bit of PCNT2 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears status bit of I2C0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears status bit of I2C1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears status bit of DAC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears status bit of IDAC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears status bit of ADC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears status bit of LETIMER0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears status bit of WDOG0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears status bit of WDOG1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears status bit of LESENSE0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears status bit of CSEN and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears status bit of LEUART0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates if ACMP0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates if ACMP1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates if PCNT0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates if PCNT1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates if PCNT2 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates if I2C0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates if I2C1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates if DAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates if IDAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates if ADC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates if LETIMER0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates if WDOG0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates if WDOG1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates if LESENSE0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates if CSEN powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates if LEUART0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow power down of ACMP0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow power down of ACMP1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow power down of PCNT0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow power down of PCNT1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow power down of PCNT2 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow power down of I2C0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow power down of I2C1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_DAC0DIS (0x1UL << 7) /**< Allow power down of DAC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT 7 /**< Shift value for EMU_DAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK 0x80UL /**< Bit mask for EMU_DAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow power down of IDAC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow power down of ADC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow power down of LETIMER0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow power down of WDOG0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow power down of WDOG1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow power down of LESENSE0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow power down of CSEN during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow power down of LEUART0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} End of group EFM32PG12B_EMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_etm.h new file mode 100644 index 00000000000..cc5c1862c5c --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_etm.h @@ -0,0 +1,781 @@ +/**************************************************************************//** + * @file efm32pg12b_etm.h + * @brief EFM32PG12B_ETM register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_ETM + * @{ + * @brief EFM32PG12B_ETM Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t ETMCR; /**< Main Control Register */ + __IM uint32_t ETMCCR; /**< Configuration Code Register */ + __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMSR; /**< ETM Status Register */ + __IM uint32_t ETMSCR; /**< ETM System Configuration Register */ + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */ + __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */ + uint32_t RESERVED3[68]; /**< Reserved for future use **/ + __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */ + uint32_t RESERVED4[39]; /**< Reserved for future use **/ + __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */ + __IM uint32_t ETMIDR; /**< ID Register */ + __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */ + uint32_t RESERVED5[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */ + uint32_t RESERVED6[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */ + uint32_t RESERVED8[1]; /**< Reserved for future use **/ + __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */ + uint32_t RESERVED9[66]; /**< Reserved for future use **/ + __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */ + uint32_t RESERVED10[754]; /**< Reserved for future use **/ + __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */ + uint32_t RESERVED11[1]; /**< Reserved for future use **/ + __IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */ + uint32_t RESERVED12[1]; /**< Reserved for future use **/ + __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */ + uint32_t RESERVED13[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */ + uint32_t RESERVED14[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */ + uint32_t RESERVED15[39]; /**< Reserved for future use **/ + __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */ + __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */ + uint32_t RESERVED16[2]; /**< Reserved for future use **/ + __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */ + __IM uint32_t ETMLSR; /**< Lock Status Register */ + __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */ + uint32_t RESERVED17[4]; /**< Reserved for future use **/ + __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */ + __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */ + __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */ + __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */ + __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */ + __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */ + __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */ + __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */ + __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */ + __IM uint32_t ETMCIDR0; /**< Component ID0 Register */ + __IM uint32_t ETMCIDR1; /**< Component ID1 Register */ + __IM uint32_t ETMCIDR2; /**< Component ID2 Register */ + __IM uint32_t ETMCIDR3; /**< Component ID3 Register */ +} ETM_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_ETM_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ETM ETMCR */ +#define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */ +#define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */ +#define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */ +#define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */ +#define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */ +#define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */ +#define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */ +#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */ +#define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */ +#define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */ +#define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */ +#define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */ +#define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */ + +/* Bit fields for ETM ETMCCR */ +#define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */ +#define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */ +#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */ +#define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */ +#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */ +#define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */ +#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */ +#define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */ + +/* Bit fields for ETM ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ + +/* Bit fields for ETM ETMSR */ +#define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */ +#define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */ +#define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */ +#define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */ +#define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */ +#define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */ +#define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */ + +/* Bit fields for ETM ETMSCR */ +#define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */ +#define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */ +#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */ +#define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */ +#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */ +#define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */ +#define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */ +#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */ + +/* Bit fields for ETM ETMTEEVR */ +#define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ + +/* Bit fields for ETM ETMTECR1 */ +#define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */ +#define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */ +#define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */ + +/* Bit fields for ETM ETMFFLR */ +#define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */ +#define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */ +#define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */ +#define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */ + +/* Bit fields for ETM ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */ +#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */ + +/* Bit fields for ETM ETMSYNCFR */ +#define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */ +#define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */ +#define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */ +#define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */ + +/* Bit fields for ETM ETMIDR */ +#define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */ +#define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */ +#define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */ +#define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */ +#define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */ +#define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */ +#define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */ +#define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */ +#define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */ + +/* Bit fields for ETM ETMCCER */ +#define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */ +#define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */ +#define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */ +#define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */ +#define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */ +#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */ +#define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */ +#define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */ +#define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */ +#define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */ +#define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */ +#define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */ +#define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */ + +/* Bit fields for ETM ETMTESSEICR */ +#define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ + +/* Bit fields for ETM ETMTSEVR */ +#define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ + +/* Bit fields for ETM ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */ +#define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */ + +/* Bit fields for ETM ETMIDR2 */ +#define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */ +#define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */ +#define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */ + +/* Bit fields for ETM ETMPDSR */ +#define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */ +#define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */ +#define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */ +#define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */ +#define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */ + +/* Bit fields for ETM ETMISCIN */ +#define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */ +#define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */ +#define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */ +#define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ + +/* Bit fields for ETM ITTRIGOUT */ +#define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */ +#define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */ +#define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */ +#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */ + +/* Bit fields for ETM ETMITATBCTR2 */ +#define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */ +#define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */ +#define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */ +#define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */ +#define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */ + +/* Bit fields for ETM ETMITATBCTR0 */ +#define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */ +#define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */ +#define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */ +#define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */ +#define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */ + +/* Bit fields for ETM ETMITCTRL */ +#define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */ +#define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */ +#define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */ +#define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */ +#define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */ + +/* Bit fields for ETM ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */ +#define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */ + +/* Bit fields for ETM ETMCLAIMCLR */ +#define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */ +#define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */ +#define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */ +#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */ +#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */ + +/* Bit fields for ETM ETMLAR */ +#define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */ +#define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */ +#define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */ +#define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */ +#define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */ +#define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */ +#define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */ + +/* Bit fields for ETM ETMLSR */ +#define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */ +#define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */ +#define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */ +#define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */ + +/* Bit fields for ETM ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ + +/* Bit fields for ETM ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ + +/* Bit fields for ETM ETMPIDR4 */ +#define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ + +/* Bit fields for ETM ETMPIDR5 */ +#define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */ +#define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */ + +/* Bit fields for ETM ETMPIDR6 */ +#define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */ +#define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */ + +/* Bit fields for ETM ETMPIDR7 */ +#define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */ +#define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */ + +/* Bit fields for ETM ETMPIDR0 */ +#define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */ +#define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */ +#define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */ +#define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */ + +/* Bit fields for ETM ETMPIDR1 */ +#define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ + +/* Bit fields for ETM ETMPIDR2 */ +#define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */ +#define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */ +#define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */ +#define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ + +/* Bit fields for ETM ETMPIDR3 */ +#define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ + +/* Bit fields for ETM ETMCIDR0 */ +#define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */ +#define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */ +#define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */ +#define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */ + +/* Bit fields for ETM ETMCIDR1 */ +#define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */ +#define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */ +#define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */ +#define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */ + +/* Bit fields for ETM ETMCIDR2 */ +#define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */ +#define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */ +#define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */ +#define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */ + +/* Bit fields for ETM ETMCIDR3 */ +#define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */ +#define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */ +#define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */ +#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */ + +/** @} End of group EFM32PG12B_ETM */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_fpueh.h new file mode 100644 index 00000000000..da66b3f2acd --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_fpueh.h @@ -0,0 +1,192 @@ +/**************************************************************************//** + * @file efm32pg12b_fpueh.h + * @brief EFM32PG12B_FPUEH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_FPUEH + * @{ + * @brief EFM32PG12B_FPUEH Register Declaration + *****************************************************************************/ +typedef struct +{ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} FPUEH_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_FPUEH_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for FPUEH IF */ +#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */ +#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */ +#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */ +#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */ +#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */ +#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */ +#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */ +#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */ +#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */ + +/* Bit fields for FPUEH IFS */ +#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */ +#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */ +#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */ +#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */ +#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */ +#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */ +#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */ +#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */ +#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */ + +/* Bit fields for FPUEH IFC */ +#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */ +#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */ +#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */ +#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */ +#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */ +#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */ +#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */ +#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */ +#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */ + +/* Bit fields for FPUEH IEN */ +#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */ +#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */ +#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */ +#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */ +#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */ +#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */ +#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */ +#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */ +#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */ + +/** @} End of group EFM32PG12B_FPUEH */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpcrc.h new file mode 100644 index 00000000000..a8d497ecb40 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpcrc.h @@ -0,0 +1,185 @@ +/**************************************************************************//** + * @file efm32pg12b_gpcrc.h + * @brief EFM32PG12B_GPCRC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_GPCRC + * @{ + * @brief EFM32PG12B_GPCRC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_GPCRC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */ +#define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */ +#define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} End of group EFM32PG12B_GPCRC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpio.h new file mode 100644 index 00000000000..f78983345ad --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpio.h @@ -0,0 +1,1538 @@ +/**************************************************************************//** + * @file efm32pg12b_gpio.h + * @brief EFM32PG12B_GPIO register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_GPIO + * @{ + * @brief EFM32PG12B_GPIO Register Declaration + *****************************************************************************/ +typedef struct +{ + GPIO_P_TypeDef P[12]; /**< Port configuration bits */ + + uint32_t RESERVED0[112]; /**< Reserved for future use **/ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */ + __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High Register */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */ + __IOM uint32_t EXTILEVEL; /**< External Interrupt Level Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wake up Enable Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register 1 */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t INSENSE; /**< Input Sense Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ +} GPIO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_GPIO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for GPIO P_CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00500050UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10711071UL /**< Mask for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive strength for port */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for GPIO_DRIVESTRENGTH */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_MASK 0x1UL /**< Bit mask for GPIO_DRIVESTRENGTH */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_STRONG (_GPIO_P_CTRL_DRIVESTRENGTH_STRONG << 0) /**< Shifted mode STRONG for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_WEAK (_GPIO_P_CTRL_DRIVESTRENGTH_WEAK << 0) /**< Shifted mode WEAK for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate drive strength for port */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT 16 /**< Shift value for GPIO_DRIVESTRENGTHALT */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK 0x10000UL /**< Bit mask for GPIO_DRIVESTRENGTHALT */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG (_GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG << 16) /**< Shifted mode STRONG for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK (_GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK << 16) /**< Shifted mode WEAK for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data In Disable */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO P_MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ + +/* Bit fields for GPIO P_MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */ +#define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */ +#define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULLALT (_GPIO_P_MODEH_MODE8_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALT (_GPIO_P_MODEH_MODE8_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */ +#define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */ +#define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULLALT (_GPIO_P_MODEH_MODE9_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALT (_GPIO_P_MODEH_MODE9_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */ +#define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */ +#define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULLALT (_GPIO_P_MODEH_MODE10_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALT (_GPIO_P_MODEH_MODE10_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */ +#define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */ +#define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULLALT (_GPIO_P_MODEH_MODE11_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALT (_GPIO_P_MODEH_MODE11_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */ +#define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */ +#define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULLALT (_GPIO_P_MODEH_MODE12_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALT (_GPIO_P_MODEH_MODE12_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */ +#define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */ +#define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULLALT (_GPIO_P_MODEH_MODE13_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALT (_GPIO_P_MODEH_MODE13_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */ +#define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */ +#define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULLALT (_GPIO_P_MODEH_MODE14_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALT (_GPIO_P_MODEH_MODE14_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */ +#define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */ +#define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULLALT (_GPIO_P_MODEH_MODE15_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALT (_GPIO_P_MODEH_MODE15_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ + +/* Bit fields for GPIO P_DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */ +#define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */ + +/* Bit fields for GPIO P_DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ + +/* Bit fields for GPIO P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */ +#define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */ + +/* Bit fields for GPIO P_OVTDIS */ +#define _GPIO_P_OVTDIS_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_OVTDIS */ +#define _GPIO_P_OVTDIS_MASK 0x0000FFFFUL /**< Mask for GPIO_P_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_SHIFT 0 /**< Shift value for GPIO_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_MASK 0xFFFFUL /**< Bit mask for GPIO_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_OVTDIS */ +#define GPIO_P_OVTDIS_OVTDIS_DEFAULT (_GPIO_P_OVTDIS_OVTDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_OVTDIS */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTI (_GPIO_EXTIPSELL_EXTIPSEL0_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL0_PORTJ << 0) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTK (_GPIO_EXTIPSELL_EXTIPSEL0_PORTK << 0) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTI (_GPIO_EXTIPSELL_EXTIPSEL1_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL1_PORTJ << 4) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTK (_GPIO_EXTIPSELL_EXTIPSEL1_PORTK << 4) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTI (_GPIO_EXTIPSELL_EXTIPSEL2_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL2_PORTJ << 8) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTK (_GPIO_EXTIPSELL_EXTIPSEL2_PORTK << 8) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTI (_GPIO_EXTIPSELL_EXTIPSEL3_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL3_PORTJ << 12) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTK (_GPIO_EXTIPSELL_EXTIPSEL3_PORTK << 12) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTI (_GPIO_EXTIPSELL_EXTIPSEL4_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL4_PORTJ << 16) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTK (_GPIO_EXTIPSELL_EXTIPSEL4_PORTK << 16) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTI (_GPIO_EXTIPSELL_EXTIPSEL5_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL5_PORTJ << 20) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTK (_GPIO_EXTIPSELL_EXTIPSEL5_PORTK << 20) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTI (_GPIO_EXTIPSELL_EXTIPSEL6_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL6_PORTJ << 24) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTK (_GPIO_EXTIPSELL_EXTIPSEL6_PORTK << 24) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTI (_GPIO_EXTIPSELL_EXTIPSEL7_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL7_PORTJ << 28) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTK (_GPIO_EXTIPSELL_EXTIPSEL7_PORTK << 28) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL8 */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTI (_GPIO_EXTIPSELH_EXTIPSEL8_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL8_PORTJ << 0) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTK (_GPIO_EXTIPSELH_EXTIPSEL8_PORTK << 0) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL9 */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTI (_GPIO_EXTIPSELH_EXTIPSEL9_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL9_PORTJ << 4) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTK (_GPIO_EXTIPSELH_EXTIPSEL9_PORTK << 4) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL10 */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTI (_GPIO_EXTIPSELH_EXTIPSEL10_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL10_PORTJ << 8) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTK (_GPIO_EXTIPSELH_EXTIPSEL10_PORTK << 8) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL11 */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTI (_GPIO_EXTIPSELH_EXTIPSEL11_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL11_PORTJ << 12) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTK (_GPIO_EXTIPSELH_EXTIPSEL11_PORTK << 12) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL12 */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTI (_GPIO_EXTIPSELH_EXTIPSEL12_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL12_PORTJ << 16) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTK (_GPIO_EXTIPSELH_EXTIPSEL12_PORTK << 16) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL13 */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTI (_GPIO_EXTIPSELH_EXTIPSEL13_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL13_PORTJ << 20) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTK (_GPIO_EXTIPSELH_EXTIPSEL13_PORTK << 20) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL14 */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTI (_GPIO_EXTIPSELH_EXTIPSEL14_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL14_PORTJ << 24) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTK (_GPIO_EXTIPSELH_EXTIPSEL14_PORTK << 24) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL15 */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL15 */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTI (_GPIO_EXTIPSELH_EXTIPSEL15_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL15_PORTJ << 28) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTK (_GPIO_EXTIPSELH_EXTIPSEL15_PORTK << 28) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 << 16) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 << 16) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 << 16) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 << 16) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 << 20) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 << 20) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 << 20) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 << 20) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 << 24) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 << 24) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 << 24) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 << 24) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 << 28) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 << 28) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 << 28) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 << 28) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL8 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL8 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL9 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL9 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL10 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL10 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL11 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL11 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL12 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL12 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 << 16) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 << 16) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 << 16) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 << 16) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL13 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL13 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 << 20) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 << 20) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 << 20) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 << 20) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL14 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL14 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 << 24) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 << 24) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 << 24) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 << 24) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL15 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL15 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 << 28) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 << 28) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 << 28) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 << 28) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO EXTILEVEL */ +#define _GPIO_EXTILEVEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTILEVEL */ +#define _GPIO_EXTILEVEL_MASK 0x13130000UL /**< Mask for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU0 (0x1UL << 16) /**< EM4 Wake Up Level for EM4WU0 Pin */ +#define _GPIO_EXTILEVEL_EM4WU0_SHIFT 16 /**< Shift value for GPIO_EM4WU0 */ +#define _GPIO_EXTILEVEL_EM4WU0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WU0 */ +#define _GPIO_EXTILEVEL_EM4WU0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU0_DEFAULT (_GPIO_EXTILEVEL_EM4WU0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU1 (0x1UL << 17) /**< EM4 Wake Up Level for EM4WU1 Pin */ +#define _GPIO_EXTILEVEL_EM4WU1_SHIFT 17 /**< Shift value for GPIO_EM4WU1 */ +#define _GPIO_EXTILEVEL_EM4WU1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WU1 */ +#define _GPIO_EXTILEVEL_EM4WU1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU1_DEFAULT (_GPIO_EXTILEVEL_EM4WU1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU4 (0x1UL << 20) /**< EM4 Wake Up Level for EM4WU4 Pin */ +#define _GPIO_EXTILEVEL_EM4WU4_SHIFT 20 /**< Shift value for GPIO_EM4WU4 */ +#define _GPIO_EXTILEVEL_EM4WU4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WU4 */ +#define _GPIO_EXTILEVEL_EM4WU4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU4_DEFAULT (_GPIO_EXTILEVEL_EM4WU4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU8 (0x1UL << 24) /**< EM4 Wake Up Level for EM4WU8 Pin */ +#define _GPIO_EXTILEVEL_EM4WU8_SHIFT 24 /**< Shift value for GPIO_EM4WU8 */ +#define _GPIO_EXTILEVEL_EM4WU8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WU8 */ +#define _GPIO_EXTILEVEL_EM4WU8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU8_DEFAULT (_GPIO_EXTILEVEL_EM4WU8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU9 (0x1UL << 25) /**< EM4 Wake Up Level for EM4WU9 Pin */ +#define _GPIO_EXTILEVEL_EM4WU9_SHIFT 25 /**< Shift value for GPIO_EM4WU9 */ +#define _GPIO_EXTILEVEL_EM4WU9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WU9 */ +#define _GPIO_EXTILEVEL_EM4WU9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU9_DEFAULT (_GPIO_EXTILEVEL_EM4WU9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU12 (0x1UL << 28) /**< EM4 Wake Up Level for EM4WU12 Pin */ +#define _GPIO_EXTILEVEL_EM4WU12_SHIFT 28 /**< Shift value for GPIO_EM4WU12 */ +#define _GPIO_EXTILEVEL_EM4WU12_MASK 0x10000000UL /**< Bit mask for GPIO_EM4WU12 */ +#define _GPIO_EXTILEVEL_EM4WU12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU12_DEFAULT (_GPIO_EXTILEVEL_EM4WU12_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IF */ +#define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IFS */ +#define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */ +#define _GPIO_IFS_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFS */ +#define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ +#define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFS */ +#define _GPIO_IFS_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IFS_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IFS_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ +#define GPIO_IFS_EM4WU_DEFAULT (_GPIO_IFS_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFS */ + +/* Bit fields for GPIO IFC */ +#define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */ +#define _GPIO_IFC_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFC */ +#define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ +#define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFC */ +#define _GPIO_IFC_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IFC_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IFC_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ +#define GPIO_IFC_EM4WU_DEFAULT (_GPIO_IFC_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFC */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IEN */ +#define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define _GPIO_IEN_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IEN_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WU_DEFAULT (_GPIO_IEN_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0xFFFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO ROUTEPEN */ +#define _GPIO_ROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_ROUTEPEN */ +#define _GPIO_ROUTEPEN_MASK 0x001F001FUL /**< Mask for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Serial Wire Clock and JTAG Test Clock Pin Enable */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Serial Wire Data and JTAG Test Mode Select Pin Enable */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_ROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_ROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_ROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDOPEN_DEFAULT (_GPIO_ROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_ROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_ROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_ROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDIPEN_DEFAULT (_GPIO_ROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWVPEN (0x1UL << 4) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_ROUTEPEN_SWVPEN_SHIFT 4 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_ROUTEPEN_SWVPEN_MASK 0x10UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_ROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWVPEN_DEFAULT (_GPIO_ROUTEPEN_SWVPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTCLKPEN (0x1UL << 16) /**< ETM Trace Clock Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_SHIFT 16 /**< Shift value for GPIO_ETMTCLKPEN */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_MASK 0x10000UL /**< Bit mask for GPIO_ETMTCLKPEN */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT (_GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD0PEN (0x1UL << 17) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_SHIFT 17 /**< Shift value for GPIO_ETMTD0PEN */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_MASK 0x20000UL /**< Bit mask for GPIO_ETMTD0PEN */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD1PEN (0x1UL << 18) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_SHIFT 18 /**< Shift value for GPIO_ETMTD1PEN */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_MASK 0x40000UL /**< Bit mask for GPIO_ETMTD1PEN */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD2PEN (0x1UL << 19) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_SHIFT 19 /**< Shift value for GPIO_ETMTD2PEN */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_MASK 0x80000UL /**< Bit mask for GPIO_ETMTD2PEN */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD3PEN (0x1UL << 20) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_SHIFT 20 /**< Shift value for GPIO_ETMTD3PEN */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_MASK 0x100000UL /**< Bit mask for GPIO_ETMTD3PEN */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ + +/* Bit fields for GPIO ROUTELOC0 */ +#define _GPIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_MASK 0x00000003UL /**< Mask for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_SHIFT 0 /**< Shift value for GPIO_SWVLOC */ +#define _GPIO_ROUTELOC0_SWVLOC_MASK 0x3UL /**< Bit mask for GPIO_SWVLOC */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC0 (_GPIO_ROUTELOC0_SWVLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_DEFAULT (_GPIO_ROUTELOC0_SWVLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC1 (_GPIO_ROUTELOC0_SWVLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC2 (_GPIO_ROUTELOC0_SWVLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC3 (_GPIO_ROUTELOC0_SWVLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC0 */ + +/* Bit fields for GPIO ROUTELOC1 */ +#define _GPIO_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_MASK 0x0C30C303UL /**< Mask for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_SHIFT 0 /**< Shift value for GPIO_ETMTCLKLOC */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_MASK 0x3UL /**< Bit mask for GPIO_ETMTCLKLOC */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT (_GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_SHIFT 8 /**< Shift value for GPIO_ETMTD0LOC */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_MASK 0x300UL /**< Bit mask for GPIO_ETMTD0LOC */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC0 << 8) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC1 << 8) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC2 << 8) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC3 << 8) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_SHIFT 14 /**< Shift value for GPIO_ETMTD1LOC */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_MASK 0xC000UL /**< Bit mask for GPIO_ETMTD1LOC */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC0 << 14) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC1 << 14) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC2 << 14) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC3 << 14) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_SHIFT 20 /**< Shift value for GPIO_ETMTD2LOC */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_MASK 0x300000UL /**< Bit mask for GPIO_ETMTD2LOC */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC0 << 20) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC1 << 20) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC2 << 20) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC3 << 20) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_SHIFT 26 /**< Shift value for GPIO_ETMTD3LOC */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_MASK 0xC000000UL /**< Bit mask for GPIO_ETMTD3LOC */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC0 << 26) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC1 << 26) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC2 << 26) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC3 << 26) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ + +/* Bit fields for GPIO INSENSE */ +#define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */ +#define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */ +#define GPIO_INSENSE_INT (0x1UL << 0) /**< Interrupt Sense Enable */ +#define _GPIO_INSENSE_INT_SHIFT 0 /**< Shift value for GPIO_INT */ +#define _GPIO_INSENSE_INT_MASK 0x1UL /**< Bit mask for GPIO_INT */ +#define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_EM4WU (0x1UL << 1) /**< EM4WU Interrupt Sense Enable */ +#define _GPIO_INSENSE_EM4WU_SHIFT 1 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_INSENSE_EM4WU_MASK 0x2UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_INSENSE_EM4WU_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_EM4WU_DEFAULT (_GPIO_INSENSE_EM4WU_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/** @} End of group EFM32PG12B_GPIO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpio_p.h new file mode 100644 index 00000000000..832c4e77e8d --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpio_p.h @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file efm32pg12b_gpio_p.h + * @brief EFM32PG12B_GPIO_P register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief GPIO_P EFM32PG12B GPIO P + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Port Control Register */ + __IOM uint32_t MODEL; /**< Port Pin Mode Low Register */ + __IOM uint32_t MODEH; /**< Port Pin Mode High Register */ + __IOM uint32_t DOUT; /**< Port Data Out Register */ + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */ + __IM uint32_t DIN; /**< Port Data In Register */ + __IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t OVTDIS; /**< Over Voltage Disable for all modes */ + uint32_t RESERVED2[1]; /**< Reserved future */ +} GPIO_P_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_i2c.h new file mode 100644 index 00000000000..0498ae42756 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_i2c.h @@ -0,0 +1,921 @@ +/**************************************************************************//** + * @file efm32pg12b_i2c.h + * @brief EFM32PG12B_I2C register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_I2C + * @{ + * @brief EFM32PG12B_I2C Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Slave Address Register */ + __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ +} I2C_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_I2C_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */ +#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IFS */ +#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */ +#define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */ +#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */ +#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */ +#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */ +#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */ +#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */ +#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */ +#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */ +#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */ +#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */ +#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */ +#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */ +#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */ +#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */ +#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */ +#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */ +#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */ +#define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */ +#define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */ + +/* Bit fields for I2C IFC */ +#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */ +#define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */ +#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */ +#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */ +#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */ +#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */ +#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */ +#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */ +#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */ +#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */ +#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */ +#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */ +#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */ +#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */ +#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */ +#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */ +#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */ +#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */ +#define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */ +#define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ + +/* Bit fields for I2C ROUTEPEN */ +#define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */ +#define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */ +#define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */ +#define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */ +#define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */ +#define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */ +#define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */ +#define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ + +/* Bit fields for I2C ROUTELOC0 */ +#define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */ +#define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */ +#define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */ +#define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */ +#define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ + +/** @} End of group EFM32PG12B_I2C */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_idac.h new file mode 100644 index 00000000000..e8620a05ae4 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_idac.h @@ -0,0 +1,352 @@ +/**************************************************************************//** + * @file efm32pg12b_idac.h + * @brief EFM32PG12B_IDAC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_IDAC + * @{ + * @brief EFM32PG12B_IDAC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CURPROG; /**< Current Programming Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ +} IDAC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_IDAC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for IDAC CTRL */ +#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */ +#define _IDAC_CTRL_MASK 0x00FD7FFFUL /**< Mask for IDAC_CTRL */ +#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */ +#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */ +#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */ +#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */ +#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */ +#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */ +#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */ +#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */ +#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */ +#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */ +#define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */ +#define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */ +#define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */ +#define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */ +#define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */ +#define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */ +#define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */ +#define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */ +#define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */ +#define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */ +#define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */ +#define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */ +#define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */ +#define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */ +#define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */ +#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */ +#define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */ +#define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */ +#define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTEN (0x1UL << 18) /**< Output Enable */ +#define _IDAC_CTRL_MAINOUTEN_SHIFT 18 /**< Shift value for IDAC_MAINOUTEN */ +#define _IDAC_CTRL_MAINOUTEN_MASK 0x40000UL /**< Bit mask for IDAC_MAINOUTEN */ +#define _IDAC_CTRL_MAINOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTEN_DEFAULT (_IDAC_CTRL_MAINOUTEN_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTENPRS (0x1UL << 19) /**< PRS Controlled Main Pad Output Enable */ +#define _IDAC_CTRL_MAINOUTENPRS_SHIFT 19 /**< Shift value for IDAC_MAINOUTENPRS */ +#define _IDAC_CTRL_MAINOUTENPRS_MASK 0x80000UL /**< Bit mask for IDAC_MAINOUTENPRS */ +#define _IDAC_CTRL_MAINOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTENPRS_DEFAULT (_IDAC_CTRL_MAINOUTENPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */ +#define _IDAC_CTRL_PRSSEL_MASK 0xF00000UL /**< Bit mask for IDAC_PRSSEL */ +#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */ + +/* Bit fields for IDAC CURPROG */ +#define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */ +#define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */ +#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */ +#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */ +#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */ +#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */ +#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */ +#define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */ +#define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */ +#define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */ + +/* Bit fields for IDAC DUTYCONFIG */ +#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */ +#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */ +#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable. */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */ +#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */ + +/* Bit fields for IDAC STATUS */ +#define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */ +#define _IDAC_STATUS_MASK 0x00000003UL /**< Mask for IDAC_STATUS */ +#define IDAC_STATUS_CURSTABLE (0x1UL << 0) /**< IDAC Output Current Stable */ +#define _IDAC_STATUS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_STATUS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_STATUS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_CURSTABLE_DEFAULT (_IDAC_STATUS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */ +#define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */ + +/* Bit fields for IDAC IF */ +#define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */ +#define _IDAC_IF_MASK 0x00000003UL /**< Mask for IDAC_IF */ +#define IDAC_IF_CURSTABLE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ +#define _IDAC_IF_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IF_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IF_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ +#define IDAC_IF_CURSTABLE_DEFAULT (_IDAC_IF_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IF */ +#define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */ +#define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ +#define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */ + +/* Bit fields for IDAC IFS */ +#define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */ +#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */ +#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */ +#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */ +#define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */ + +/* Bit fields for IDAC IFC */ +#define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */ +#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */ +#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */ +#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */ + +/* Bit fields for IDAC IEN */ +#define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */ +#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */ +#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */ +#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */ +#define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */ + +/* Bit fields for IDAC APORTREQ */ +#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */ +#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the APORT bus connected to APORT1X is requested */ +#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */ +#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */ +#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */ +#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */ +#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */ +#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ + +/* Bit fields for IDAC APORTCONFLICT */ +#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */ +#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ + +/** @} End of group EFM32PG12B_IDAC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_ldma.h new file mode 100644 index 00000000000..c2024268ebb --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_ldma.h @@ -0,0 +1,643 @@ +/**************************************************************************//** + * @file efm32pg12b_ldma.h + * @brief EFM32PG12B_LDMA register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_LDMA + * @{ + * @brief EFM32PG12B_LDMA Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */ + uint32_t RESERVED0[5]; /**< Reserved for future use **/ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + uint32_t RESERVED1[7]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable register */ + + uint32_t RESERVED2[4]; /**< Reserved registers */ + LDMA_CH_TypeDef CH[8]; /**< DMA Channel Registers */ +} LDMA_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_LDMA_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x0700FFFFUL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */ +#define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */ +#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */ +#define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */ +#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F073BUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0x38UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x700UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNC */ +#define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */ +#define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */ +#define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */ +#define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ +#define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IF_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IFS */ +#define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */ +#define _LDMA_IFS_MASK 0x800000FFUL /**< Mask for LDMA_IFS */ +#define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */ +#define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */ + +/* Bit fields for LDMA IFC */ +#define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */ +#define _LDMA_IFC_MASK 0x800000FFUL /**< Mask for LDMA_IFC */ +#define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */ +#define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_REQSEL */ +#define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV 0x00000000UL /**< Mode USART3RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF 0x00000000UL /**< Mode WTIMER1UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR /**< Alias for mode CRYPTO0DATA0WR */ +#define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR 0x00000000UL /**< Mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBL 0x00000001UL /**< Mode USART3TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 0x00000001UL /**< Mode WTIMER1CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR /**< Alias for mode CRYPTO0DATA0XWR */ +#define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR 0x00000001UL /**< Mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY 0x00000002UL /**< Mode USART3TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 0x00000002UL /**< Mode WTIMER1CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD /**< Alias for mode CRYPTO0DATA0RD */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD 0x00000002UL /**< Mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT 0x00000003UL /**< Mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 0x00000003UL /**< Mode WTIMER1CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR /**< Alias for mode CRYPTO0DATA1WR */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR 0x00000003UL /**< Mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT 0x00000004UL /**< Mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 0x00000004UL /**< Mode WTIMER1CC3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD /**< Alias for mode CRYPTO0DATA1RD */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD 0x00000004UL /**< Mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF << 0) /**< Shifted mode WTIMER1UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR << 0) /**< Shifted mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXBL (_LDMA_CH_REQSEL_SIGSEL_USART3TXBL << 0) /**< Shifted mode USART3TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR << 0) /**< Shifted mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY << 0) /**< Shifted mode USART3TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD << 0) /**< Shifted mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT << 0) /**< Shifted mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR << 0) /**< Shifted mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT << 0) /**< Shifted mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD << 0) /**< Shifted mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART3 0x0000000FUL /**< Mode USART3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x0000001AUL /**< Mode WTIMER0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER1 0x0000001BUL /**< Mode WTIMER1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 /**< Alias for mode CRYPTO0 */ +#define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x00000032UL /**< Mode CSEN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x00000033UL /**< Mode LESENSE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 0x00000034UL /**< Mode CRYPTO1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART3 (_LDMA_CH_REQSEL_SOURCESEL_USART3 << 16) /**< Shifted mode USART3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER1 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER1 << 16) /**< Shifted mode WTIMER1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 << 16) /**< Shifted mode CRYPTO1 for LDMA_CH_REQSEL */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */ +#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */ +#define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */ +#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} End of group EFM32PG12B_LDMA */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_ldma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_ldma_ch.h new file mode 100644 index 00000000000..4fe331c8bcb --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_ldma_ch.h @@ -0,0 +1,53 @@ +/**************************************************************************//** + * @file efm32pg12b_ldma_ch.h + * @brief EFM32PG12B_LDMA_CH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LDMA_CH EFM32PG12B LDMA CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */ + uint32_t RESERVED0[5]; /**< Reserved future */ +} LDMA_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense.h new file mode 100644 index 00000000000..b3444ee1fe2 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense.h @@ -0,0 +1,1867 @@ +/**************************************************************************//** + * @file efm32pg12b_lesense.h + * @brief EFM32PG12B_LESENSE register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_LESENSE + * @{ + * @brief EFM32PG12B_LESENSE Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t TIMCTRL; /**< Timing Control Register */ + __IOM uint32_t PERCTRL; /**< Peripheral Control Register */ + __IOM uint32_t DECCTRL; /**< Decoder control Register */ + __IOM uint32_t BIASCTRL; /**< Bias Control Register */ + __IOM uint32_t EVALCTRL; /**< LESENSE evaluation control */ + __IOM uint32_t PRSCTRL; /**< PRS control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t CHEN; /**< Channel enable Register */ + __IOM uint32_t SCANRES; /**< Scan result register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t PTR; /**< Result buffer pointers */ + __IM uint32_t BUFDATA; /**< Result buffer data register */ + __IM uint32_t CURCH; /**< Current channel index */ + __IOM uint32_t DECSTATE; /**< Current decoder state */ + __IOM uint32_t SENSORSTATE; /**< Decoder input register */ + __IOM uint32_t IDLECONF; /**< GPIO Idle phase configuration */ + __IOM uint32_t ALTEXCONF; /**< Alternative excite pin configuration */ + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Register */ + + uint32_t RESERVED1[38]; /**< Reserved registers */ + LESENSE_ST_TypeDef ST[32]; /**< Decoding states */ + + LESENSE_BUF_TypeDef BUF[16]; /**< Scanresult */ + + LESENSE_CH_TypeDef CH[16]; /**< Scanconfig */ +} LESENSE_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_LESENSE_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LESENSE CTRL */ +#define _LESENSE_CTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CTRL */ +#define _LESENSE_CTRL_MASK 0x007B29BFUL /**< Mask for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_DEFAULT (_LESENSE_CTRL_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PERIODIC (_LESENSE_CTRL_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_ONESHOT (_LESENSE_CTRL_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PRS (_LESENSE_CTRL_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_SHIFT 2 /**< Shift value for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_MASK 0x3CUL /**< Bit mask for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_DEFAULT (_LESENSE_CTRL_PRSSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH0 (_LESENSE_CTRL_PRSSEL_PRSCH0 << 2) /**< Shifted mode PRSCH0 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH1 (_LESENSE_CTRL_PRSSEL_PRSCH1 << 2) /**< Shifted mode PRSCH1 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH2 (_LESENSE_CTRL_PRSSEL_PRSCH2 << 2) /**< Shifted mode PRSCH2 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH3 (_LESENSE_CTRL_PRSSEL_PRSCH3 << 2) /**< Shifted mode PRSCH3 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH4 (_LESENSE_CTRL_PRSSEL_PRSCH4 << 2) /**< Shifted mode PRSCH4 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH5 (_LESENSE_CTRL_PRSSEL_PRSCH5 << 2) /**< Shifted mode PRSCH5 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH6 (_LESENSE_CTRL_PRSSEL_PRSCH6 << 2) /**< Shifted mode PRSCH6 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH7 (_LESENSE_CTRL_PRSSEL_PRSCH7 << 2) /**< Shifted mode PRSCH7 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH8 (_LESENSE_CTRL_PRSSEL_PRSCH8 << 2) /**< Shifted mode PRSCH8 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH9 (_LESENSE_CTRL_PRSSEL_PRSCH9 << 2) /**< Shifted mode PRSCH9 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH10 (_LESENSE_CTRL_PRSSEL_PRSCH10 << 2) /**< Shifted mode PRSCH10 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH11 (_LESENSE_CTRL_PRSSEL_PRSCH11 << 2) /**< Shifted mode PRSCH11 for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_SHIFT 7 /**< Shift value for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_MASK 0x180UL /**< Bit mask for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DEFAULT (_LESENSE_CTRL_SCANCONF_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DIRMAP (_LESENSE_CTRL_SCANCONF_DIRMAP << 7) /**< Shifted mode DIRMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_INVMAP (_LESENSE_CTRL_SCANCONF_INVMAP << 7) /**< Shifted mode INVMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_TOGGLE (_LESENSE_CTRL_SCANCONF_TOGGLE << 7) /**< Shifted mode TOGGLE for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DECDEF (_LESENSE_CTRL_SCANCONF_DECDEF << 7) /**< Shifted mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP (0x1UL << 11) /**< Alternative excitation map */ +#define _LESENSE_CTRL_ALTEXMAP_SHIFT 11 /**< Shift value for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_MASK 0x800UL /**< Bit mask for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_ALTEX 0x00000000UL /**< Mode ALTEX for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_CH 0x00000001UL /**< Mode CH for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_DEFAULT (_LESENSE_CTRL_ALTEXMAP_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_ALTEX (_LESENSE_CTRL_ALTEXMAP_ALTEX << 11) /**< Shifted mode ALTEX for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_CH (_LESENSE_CTRL_ALTEXMAP_CH << 11) /**< Shifted mode CH for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE (0x1UL << 13) /**< Enable dual sample mode */ +#define _LESENSE_CTRL_DUALSAMPLE_SHIFT 13 /**< Shift value for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_MASK 0x2000UL /**< Bit mask for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE_DEFAULT (_LESENSE_CTRL_DUALSAMPLE_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW (0x1UL << 16) /**< Result buffer overwrite */ +#define _LESENSE_CTRL_BUFOW_SHIFT 16 /**< Shift value for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_MASK 0x10000UL /**< Bit mask for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW_DEFAULT (_LESENSE_CTRL_BUFOW_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES (0x1UL << 17) /**< Enable storing of SCANRES */ +#define _LESENSE_CTRL_STRSCANRES_SHIFT 17 /**< Shift value for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_MASK 0x20000UL /**< Bit mask for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES_DEFAULT (_LESENSE_CTRL_STRSCANRES_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL (0x1UL << 19) /**< Result buffer interrupt and DMA trigger level */ +#define _LESENSE_CTRL_BUFIDL_SHIFT 19 /**< Shift value for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_MASK 0x80000UL /**< Bit mask for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_HALFFULL 0x00000000UL /**< Mode HALFFULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_FULL 0x00000001UL /**< Mode FULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_DEFAULT (_LESENSE_CTRL_BUFIDL_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_HALFFULL (_LESENSE_CTRL_BUFIDL_HALFFULL << 19) /**< Shifted mode HALFFULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_FULL (_LESENSE_CTRL_BUFIDL_FULL << 19) /**< Shifted mode FULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_SHIFT 20 /**< Shift value for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_MASK 0x300000UL /**< Bit mask for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFDATAV 0x00000001UL /**< Mode BUFDATAV for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFLEVEL 0x00000002UL /**< Mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DEFAULT (_LESENSE_CTRL_DMAWU_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DISABLE (_LESENSE_CTRL_DMAWU_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFDATAV (_LESENSE_CTRL_DMAWU_BUFDATAV << 20) /**< Shifted mode BUFDATAV for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFLEVEL (_LESENSE_CTRL_DMAWU_BUFLEVEL << 20) /**< Shifted mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN (0x1UL << 22) /**< Debug Mode Run Enable */ +#define _LESENSE_CTRL_DEBUGRUN_SHIFT 22 /**< Shift value for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_MASK 0x400000UL /**< Bit mask for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN_DEFAULT (_LESENSE_CTRL_DEBUGRUN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_CTRL */ + +/* Bit fields for LESENSE TIMCTRL */ +#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUXHFRCO startup configuration */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */ + +/* Bit fields for LESENSE PERCTRL */ +#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_MASK 0x3FF0014FUL /**< Mask for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0EN (0x1UL << 0) /**< VDAC CH0 enable. */ +#define _LESENSE_PERCTRL_DACCH0EN_SHIFT 0 /**< Shift value for LESENSE_DACCH0EN */ +#define _LESENSE_PERCTRL_DACCH0EN_MASK 0x1UL /**< Bit mask for LESENSE_DACCH0EN */ +#define _LESENSE_PERCTRL_DACCH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0EN_DEFAULT (_LESENSE_PERCTRL_DACCH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1EN (0x1UL << 1) /**< VDAC CH1 enable. */ +#define _LESENSE_PERCTRL_DACCH1EN_SHIFT 1 /**< Shift value for LESENSE_DACCH1EN */ +#define _LESENSE_PERCTRL_DACCH1EN_MASK 0x2UL /**< Bit mask for LESENSE_DACCH1EN */ +#define _LESENSE_PERCTRL_DACCH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1EN_DEFAULT (_LESENSE_PERCTRL_DACCH1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< VDAC CH0 data selection. */ +#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA (0x1UL << 3) /**< VDAC CH1 data selection. */ +#define _LESENSE_PERCTRL_DACCH1DATA_SHIFT 3 /**< Shift value for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_MASK 0x8UL /**< Bit mask for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DEFAULT (_LESENSE_PERCTRL_DACCH1DATA_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DACDATA (_LESENSE_PERCTRL_DACCH1DATA_DACDATA << 3) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_THRES (_LESENSE_PERCTRL_DACCH1DATA_THRES << 3) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< VDAC startup configuration */ +#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< VDAC conversion trigger configuration */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x300000UL /**< Bit mask for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DISABLE (_LESENSE_PERCTRL_ACMP0MODE_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0xC00000UL /**< Bit mask for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DISABLE (_LESENSE_PERCTRL_ACMP1MODE_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert analog comparator 0 output */ +#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert analog comparator 1 output */ +#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0HYSTEN (0x1UL << 26) /**< ACMP0 hysteresis enable */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_SHIFT 26 /**< Shift value for LESENSE_ACMP0HYSTEN */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_MASK 0x4000000UL /**< Bit mask for LESENSE_ACMP0HYSTEN */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1HYSTEN (0x1UL << 27) /**< ACMP1 hysteresis enable */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_SHIFT 27 /**< Shift value for LESENSE_ACMP1HYSTEN */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_MASK 0x8000000UL /**< Bit mask for LESENSE_ACMP1HYSTEN */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT << 27) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_SHIFT 28 /**< Shift value for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_MASK 0x30000000UL /**< Bit mask for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM 0x00000001UL /**< Mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM 0x00000002UL /**< Mode KEEPDACWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM 0x00000003UL /**< Mode KEEPACMPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_DEFAULT (_LESENSE_PERCTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_NORMAL (_LESENSE_PERCTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM << 28) /**< Shifted mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM << 28) /**< Shifted mode KEEPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM << 28) /**< Shifted mode KEEPACMPDACWARM for LESENSE_PERCTRL */ + +/* Bit fields for LESENSE DECCTRL */ +#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_MASK 0x1EF7BDFFUL /**< Mask for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DISABLE (0x1UL << 0) /**< Disable the decoder */ +#define _LESENSE_DECCTRL_DISABLE_SHIFT 0 /**< Shift value for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_MASK 0x1UL /**< Bit mask for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DISABLE_DEFAULT (_LESENSE_DECCTRL_DISABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK (0x1UL << 1) /**< Enable check of current state */ +#define _LESENSE_DECCTRL_ERRCHK_SHIFT 1 /**< Shift value for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_MASK 0x2UL /**< Bit mask for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK_DEFAULT (_LESENSE_DECCTRL_ERRCHK_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable decoder to channel interrupt mapping */ +#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable decoder hysteresis on PRS0 output */ +#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable decoder hysteresis on PRS1 output */ +#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable decoder hysteresis on PRS2 output */ +#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable decoder hysteresis on interrupt requests */ +#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable count mode on decoder PRS channels 0 and 1 */ +#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT (0x1UL << 8) /**< LESENSE decoder input configuration */ +#define _LESENSE_DECCTRL_INPUT_SHIFT 8 /**< Shift value for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_MASK 0x100UL /**< Bit mask for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_SENSORSTATE 0x00000000UL /**< Mode SENSORSTATE for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_PRS 0x00000001UL /**< Mode PRS for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_DEFAULT (_LESENSE_DECCTRL_INPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_SENSORSTATE (_LESENSE_DECCTRL_INPUT_SENSORSTATE << 8) /**< Shifted mode SENSORSTATE for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_PRS (_LESENSE_DECCTRL_INPUT_PRS << 8) /**< Shifted mode PRS for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_SHIFT 10 /**< Shift value for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_MASK 0x3C00UL /**< Bit mask for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_DEFAULT (_LESENSE_DECCTRL_PRSSEL0_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH0 (_LESENSE_DECCTRL_PRSSEL0_PRSCH0 << 10) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH1 (_LESENSE_DECCTRL_PRSSEL0_PRSCH1 << 10) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH2 (_LESENSE_DECCTRL_PRSSEL0_PRSCH2 << 10) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH3 (_LESENSE_DECCTRL_PRSSEL0_PRSCH3 << 10) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH4 (_LESENSE_DECCTRL_PRSSEL0_PRSCH4 << 10) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH5 (_LESENSE_DECCTRL_PRSSEL0_PRSCH5 << 10) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH6 (_LESENSE_DECCTRL_PRSSEL0_PRSCH6 << 10) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH7 (_LESENSE_DECCTRL_PRSSEL0_PRSCH7 << 10) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH8 (_LESENSE_DECCTRL_PRSSEL0_PRSCH8 << 10) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH9 (_LESENSE_DECCTRL_PRSSEL0_PRSCH9 << 10) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH10 (_LESENSE_DECCTRL_PRSSEL0_PRSCH10 << 10) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH11 (_LESENSE_DECCTRL_PRSSEL0_PRSCH11 << 10) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_SHIFT 15 /**< Shift value for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_MASK 0x78000UL /**< Bit mask for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_DEFAULT (_LESENSE_DECCTRL_PRSSEL1_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH0 (_LESENSE_DECCTRL_PRSSEL1_PRSCH0 << 15) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH1 (_LESENSE_DECCTRL_PRSSEL1_PRSCH1 << 15) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH2 (_LESENSE_DECCTRL_PRSSEL1_PRSCH2 << 15) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH3 (_LESENSE_DECCTRL_PRSSEL1_PRSCH3 << 15) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH4 (_LESENSE_DECCTRL_PRSSEL1_PRSCH4 << 15) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH5 (_LESENSE_DECCTRL_PRSSEL1_PRSCH5 << 15) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH6 (_LESENSE_DECCTRL_PRSSEL1_PRSCH6 << 15) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH7 (_LESENSE_DECCTRL_PRSSEL1_PRSCH7 << 15) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH8 (_LESENSE_DECCTRL_PRSSEL1_PRSCH8 << 15) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH9 (_LESENSE_DECCTRL_PRSSEL1_PRSCH9 << 15) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH10 (_LESENSE_DECCTRL_PRSSEL1_PRSCH10 << 15) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH11 (_LESENSE_DECCTRL_PRSSEL1_PRSCH11 << 15) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_SHIFT 20 /**< Shift value for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_MASK 0xF00000UL /**< Bit mask for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_DEFAULT (_LESENSE_DECCTRL_PRSSEL2_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH0 (_LESENSE_DECCTRL_PRSSEL2_PRSCH0 << 20) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH1 (_LESENSE_DECCTRL_PRSSEL2_PRSCH1 << 20) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH2 (_LESENSE_DECCTRL_PRSSEL2_PRSCH2 << 20) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH3 (_LESENSE_DECCTRL_PRSSEL2_PRSCH3 << 20) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH4 (_LESENSE_DECCTRL_PRSSEL2_PRSCH4 << 20) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH5 (_LESENSE_DECCTRL_PRSSEL2_PRSCH5 << 20) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH6 (_LESENSE_DECCTRL_PRSSEL2_PRSCH6 << 20) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH7 (_LESENSE_DECCTRL_PRSSEL2_PRSCH7 << 20) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH8 (_LESENSE_DECCTRL_PRSSEL2_PRSCH8 << 20) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH9 (_LESENSE_DECCTRL_PRSSEL2_PRSCH9 << 20) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH10 (_LESENSE_DECCTRL_PRSSEL2_PRSCH10 << 20) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH11 (_LESENSE_DECCTRL_PRSSEL2_PRSCH11 << 20) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_SHIFT 25 /**< Shift value for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_MASK 0x1E000000UL /**< Bit mask for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_DEFAULT (_LESENSE_DECCTRL_PRSSEL3_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH0 (_LESENSE_DECCTRL_PRSSEL3_PRSCH0 << 25) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH1 (_LESENSE_DECCTRL_PRSSEL3_PRSCH1 << 25) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH2 (_LESENSE_DECCTRL_PRSSEL3_PRSCH2 << 25) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH3 (_LESENSE_DECCTRL_PRSSEL3_PRSCH3 << 25) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH4 (_LESENSE_DECCTRL_PRSSEL3_PRSCH4 << 25) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH5 (_LESENSE_DECCTRL_PRSSEL3_PRSCH5 << 25) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH6 (_LESENSE_DECCTRL_PRSSEL3_PRSCH6 << 25) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH7 (_LESENSE_DECCTRL_PRSSEL3_PRSCH7 << 25) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH8 (_LESENSE_DECCTRL_PRSSEL3_PRSCH8 << 25) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH9 (_LESENSE_DECCTRL_PRSSEL3_PRSCH9 << 25) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH10 (_LESENSE_DECCTRL_PRSSEL3_PRSCH10 << 25) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH11 (_LESENSE_DECCTRL_PRSSEL3_PRSCH11 << 25) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ + +/* Bit fields for LESENSE BIASCTRL */ +#define _LESENSE_BIASCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_MASK 0x00000003UL /**< Mask for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_SHIFT 0 /**< Shift value for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_MASK 0x3UL /**< Bit mask for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DONTTOUCH 0x00000000UL /**< Mode DONTTOUCH for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE 0x00000001UL /**< Mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_HIGHACC 0x00000002UL /**< Mode HIGHACC for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DEFAULT (_LESENSE_BIASCTRL_BIASMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DONTTOUCH (_LESENSE_BIASCTRL_BIASMODE_DONTTOUCH << 0) /**< Shifted mode DONTTOUCH for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE (_LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE << 0) /**< Shifted mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_HIGHACC (_LESENSE_BIASCTRL_BIASMODE_HIGHACC << 0) /**< Shifted mode HIGHACC for LESENSE_BIASCTRL */ + +/* Bit fields for LESENSE EVALCTRL */ +#define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */ +#define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */ + +/* Bit fields for LESENSE PRSCTRL */ +#define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS output DECCMP */ +#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ + +/* Bit fields for LESENSE CMD */ +#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */ +#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */ +#define LESENSE_CMD_START (0x1UL << 0) /**< Start scanning of sensors. */ +#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */ +#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */ +#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop scanning of sensors */ +#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start decoder */ +#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear result buffer */ +#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */ + +/* Bit fields for LESENSE CHEN */ +#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */ +#define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */ +#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */ + +/* Bit fields for LESENSE SCANRES */ +#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ + +/* Bit fields for LESENSE STATUS */ +#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */ +#define _LESENSE_STATUS_MASK 0x0000003FUL /**< Mask for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFDATAV (0x1UL << 0) /**< Result data valid */ +#define _LESENSE_STATUS_BUFDATAV_SHIFT 0 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_MASK 0x1UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFDATAV_DEFAULT (_LESENSE_STATUS_BUFDATAV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL (0x1UL << 1) /**< Result buffer half full */ +#define _LESENSE_STATUS_BUFHALFFULL_SHIFT 1 /**< Shift value for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_MASK 0x2UL /**< Bit mask for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL_DEFAULT (_LESENSE_STATUS_BUFHALFFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL (0x1UL << 2) /**< Result buffer full */ +#define _LESENSE_STATUS_BUFFULL_SHIFT 2 /**< Shift value for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_MASK 0x4UL /**< Bit mask for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL_DEFAULT (_LESENSE_STATUS_BUFFULL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING (0x1UL << 3) /**< LESENSE periodic counter running */ +#define _LESENSE_STATUS_RUNNING_SHIFT 3 /**< Shift value for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_MASK 0x8UL /**< Bit mask for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE (0x1UL << 4) /**< LESENSE scan active */ +#define _LESENSE_STATUS_SCANACTIVE_SHIFT 4 /**< Shift value for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_MASK 0x10UL /**< Bit mask for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE (0x1UL << 5) /**< LESENSE VDAC interface is active */ +#define _LESENSE_STATUS_DACACTIVE_SHIFT 5 /**< Shift value for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_MASK 0x20UL /**< Bit mask for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE_DEFAULT (_LESENSE_STATUS_DACACTIVE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */ + +/* Bit fields for LESENSE PTR */ +#define _LESENSE_PTR_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PTR */ +#define _LESENSE_PTR_MASK 0x000000FFUL /**< Mask for LESENSE_PTR */ +#define _LESENSE_PTR_RD_SHIFT 0 /**< Shift value for LESENSE_RD */ +#define _LESENSE_PTR_RD_MASK 0xFUL /**< Bit mask for LESENSE_RD */ +#define _LESENSE_PTR_RD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_RD_DEFAULT (_LESENSE_PTR_RD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PTR */ +#define _LESENSE_PTR_WR_SHIFT 4 /**< Shift value for LESENSE_WR */ +#define _LESENSE_PTR_WR_MASK 0xF0UL /**< Bit mask for LESENSE_WR */ +#define _LESENSE_PTR_WR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_WR_DEFAULT (_LESENSE_PTR_WR_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_PTR */ + +/* Bit fields for LESENSE BUFDATA */ +#define _LESENSE_BUFDATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_SHIFT 0 /**< Shift value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ +#define LESENSE_BUFDATA_BUFDATA_DEFAULT (_LESENSE_BUFDATA_BUFDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATASRC_SHIFT 16 /**< Shift value for LESENSE_BUFDATASRC */ +#define _LESENSE_BUFDATA_BUFDATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_BUFDATASRC */ +#define _LESENSE_BUFDATA_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ +#define LESENSE_BUFDATA_BUFDATASRC_DEFAULT (_LESENSE_BUFDATA_BUFDATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ + +/* Bit fields for LESENSE CURCH */ +#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */ +#define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */ +#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */ + +/* Bit fields for LESENSE DECSTATE */ +#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */ +#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */ + +/* Bit fields for LESENSE SENSORSTATE */ +#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */ +#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE */ + +/* Bit fields for LESENSE IDLECONF */ +#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_MASK 0x3UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DEFAULT (_LESENSE_IDLECONF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DISABLE (_LESENSE_IDLECONF_CH0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_HIGH (_LESENSE_IDLECONF_CH0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_LOW (_LESENSE_IDLECONF_CH0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DAC (_LESENSE_IDLECONF_CH0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_SHIFT 2 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_MASK 0xCUL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DEFAULT (_LESENSE_IDLECONF_CH1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DISABLE (_LESENSE_IDLECONF_CH1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_HIGH (_LESENSE_IDLECONF_CH1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_LOW (_LESENSE_IDLECONF_CH1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DAC (_LESENSE_IDLECONF_CH1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_SHIFT 4 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_MASK 0x30UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DEFAULT (_LESENSE_IDLECONF_CH2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DISABLE (_LESENSE_IDLECONF_CH2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_HIGH (_LESENSE_IDLECONF_CH2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_LOW (_LESENSE_IDLECONF_CH2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DAC (_LESENSE_IDLECONF_CH2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_SHIFT 6 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_MASK 0xC0UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DEFAULT (_LESENSE_IDLECONF_CH3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DISABLE (_LESENSE_IDLECONF_CH3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_HIGH (_LESENSE_IDLECONF_CH3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_LOW (_LESENSE_IDLECONF_CH3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DAC (_LESENSE_IDLECONF_CH3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_SHIFT 8 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_MASK 0x300UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DEFAULT (_LESENSE_IDLECONF_CH4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DISABLE (_LESENSE_IDLECONF_CH4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_HIGH (_LESENSE_IDLECONF_CH4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_LOW (_LESENSE_IDLECONF_CH4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DAC (_LESENSE_IDLECONF_CH4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_SHIFT 10 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_MASK 0xC00UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DEFAULT (_LESENSE_IDLECONF_CH5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DISABLE (_LESENSE_IDLECONF_CH5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_HIGH (_LESENSE_IDLECONF_CH5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_LOW (_LESENSE_IDLECONF_CH5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DAC (_LESENSE_IDLECONF_CH5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_SHIFT 12 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_MASK 0x3000UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DEFAULT (_LESENSE_IDLECONF_CH6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DISABLE (_LESENSE_IDLECONF_CH6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_HIGH (_LESENSE_IDLECONF_CH6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_LOW (_LESENSE_IDLECONF_CH6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DAC (_LESENSE_IDLECONF_CH6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_SHIFT 14 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_MASK 0xC000UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DEFAULT (_LESENSE_IDLECONF_CH7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DISABLE (_LESENSE_IDLECONF_CH7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_HIGH (_LESENSE_IDLECONF_CH7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_LOW (_LESENSE_IDLECONF_CH7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DAC (_LESENSE_IDLECONF_CH7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_SHIFT 16 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_MASK 0x30000UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DEFAULT (_LESENSE_IDLECONF_CH8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DISABLE (_LESENSE_IDLECONF_CH8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_HIGH (_LESENSE_IDLECONF_CH8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_LOW (_LESENSE_IDLECONF_CH8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DAC (_LESENSE_IDLECONF_CH8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_SHIFT 18 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_MASK 0xC0000UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DEFAULT (_LESENSE_IDLECONF_CH9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DISABLE (_LESENSE_IDLECONF_CH9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_HIGH (_LESENSE_IDLECONF_CH9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_LOW (_LESENSE_IDLECONF_CH9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DAC (_LESENSE_IDLECONF_CH9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_SHIFT 20 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_MASK 0x300000UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DEFAULT (_LESENSE_IDLECONF_CH10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DISABLE (_LESENSE_IDLECONF_CH10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_HIGH (_LESENSE_IDLECONF_CH10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_LOW (_LESENSE_IDLECONF_CH10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DAC (_LESENSE_IDLECONF_CH10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_SHIFT 22 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_MASK 0xC00000UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DEFAULT (_LESENSE_IDLECONF_CH11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DISABLE (_LESENSE_IDLECONF_CH11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_HIGH (_LESENSE_IDLECONF_CH11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_LOW (_LESENSE_IDLECONF_CH11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DAC (_LESENSE_IDLECONF_CH11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_SHIFT 24 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_MASK 0x3000000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DEFAULT (_LESENSE_IDLECONF_CH12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DISABLE (_LESENSE_IDLECONF_CH12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_HIGH (_LESENSE_IDLECONF_CH12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_LOW (_LESENSE_IDLECONF_CH12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DAC (_LESENSE_IDLECONF_CH12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_SHIFT 26 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_MASK 0xC000000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DEFAULT (_LESENSE_IDLECONF_CH13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DISABLE (_LESENSE_IDLECONF_CH13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_HIGH (_LESENSE_IDLECONF_CH13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_LOW (_LESENSE_IDLECONF_CH13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DAC (_LESENSE_IDLECONF_CH13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_SHIFT 28 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_MASK 0x30000000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DEFAULT (_LESENSE_IDLECONF_CH14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DISABLE (_LESENSE_IDLECONF_CH14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_HIGH (_LESENSE_IDLECONF_CH14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_LOW (_LESENSE_IDLECONF_CH14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DAC (_LESENSE_IDLECONF_CH14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_SHIFT 30 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DEFAULT (_LESENSE_IDLECONF_CH15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DISABLE (_LESENSE_IDLECONF_CH15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_HIGH (_LESENSE_IDLECONF_CH15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_LOW (_LESENSE_IDLECONF_CH15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DAC (_LESENSE_IDLECONF_CH15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */ + +/* Bit fields for LESENSE ALTEXCONF */ +#define _LESENSE_ALTEXCONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_SHIFT 0 /**< Shift value for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_MASK 0x3UL /**< Bit mask for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DISABLE (_LESENSE_ALTEXCONF_IDLECONF0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_HIGH (_LESENSE_ALTEXCONF_IDLECONF0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_LOW (_LESENSE_ALTEXCONF_IDLECONF0_LOW << 0) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_SHIFT 2 /**< Shift value for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_MASK 0xCUL /**< Bit mask for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DISABLE (_LESENSE_ALTEXCONF_IDLECONF1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_HIGH (_LESENSE_ALTEXCONF_IDLECONF1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_LOW (_LESENSE_ALTEXCONF_IDLECONF1_LOW << 2) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_SHIFT 4 /**< Shift value for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_MASK 0x30UL /**< Bit mask for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DISABLE (_LESENSE_ALTEXCONF_IDLECONF2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_HIGH (_LESENSE_ALTEXCONF_IDLECONF2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_LOW (_LESENSE_ALTEXCONF_IDLECONF2_LOW << 4) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_SHIFT 6 /**< Shift value for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_MASK 0xC0UL /**< Bit mask for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DISABLE (_LESENSE_ALTEXCONF_IDLECONF3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_HIGH (_LESENSE_ALTEXCONF_IDLECONF3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_LOW (_LESENSE_ALTEXCONF_IDLECONF3_LOW << 6) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_SHIFT 8 /**< Shift value for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_MASK 0x300UL /**< Bit mask for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DISABLE (_LESENSE_ALTEXCONF_IDLECONF4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_HIGH (_LESENSE_ALTEXCONF_IDLECONF4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_LOW (_LESENSE_ALTEXCONF_IDLECONF4_LOW << 8) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_SHIFT 10 /**< Shift value for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_MASK 0xC00UL /**< Bit mask for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DISABLE (_LESENSE_ALTEXCONF_IDLECONF5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_HIGH (_LESENSE_ALTEXCONF_IDLECONF5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_LOW (_LESENSE_ALTEXCONF_IDLECONF5_LOW << 10) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_SHIFT 12 /**< Shift value for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_MASK 0x3000UL /**< Bit mask for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DISABLE (_LESENSE_ALTEXCONF_IDLECONF6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_HIGH (_LESENSE_ALTEXCONF_IDLECONF6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_LOW (_LESENSE_ALTEXCONF_IDLECONF6_LOW << 12) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_SHIFT 14 /**< Shift value for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_MASK 0xC000UL /**< Bit mask for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DISABLE (_LESENSE_ALTEXCONF_IDLECONF7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_HIGH (_LESENSE_ALTEXCONF_IDLECONF7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_LOW (_LESENSE_ALTEXCONF_IDLECONF7_LOW << 14) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0 (0x1UL << 16) /**< ALTEX0 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX0_SHIFT 16 /**< Shift value for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_MASK 0x10000UL /**< Bit mask for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0_DEFAULT (_LESENSE_ALTEXCONF_AEX0_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1 (0x1UL << 17) /**< ALTEX1 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX1_SHIFT 17 /**< Shift value for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_MASK 0x20000UL /**< Bit mask for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1_DEFAULT (_LESENSE_ALTEXCONF_AEX1_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2 (0x1UL << 18) /**< ALTEX2 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX2_SHIFT 18 /**< Shift value for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_MASK 0x40000UL /**< Bit mask for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2_DEFAULT (_LESENSE_ALTEXCONF_AEX2_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3 (0x1UL << 19) /**< ALTEX3 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX3_SHIFT 19 /**< Shift value for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_MASK 0x80000UL /**< Bit mask for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3_DEFAULT (_LESENSE_ALTEXCONF_AEX3_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4 (0x1UL << 20) /**< ALTEX4 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX4_SHIFT 20 /**< Shift value for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_MASK 0x100000UL /**< Bit mask for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4_DEFAULT (_LESENSE_ALTEXCONF_AEX4_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5 (0x1UL << 21) /**< ALTEX5 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX5_SHIFT 21 /**< Shift value for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_MASK 0x200000UL /**< Bit mask for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5_DEFAULT (_LESENSE_ALTEXCONF_AEX5_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6 (0x1UL << 22) /**< ALTEX6 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX6_SHIFT 22 /**< Shift value for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_MASK 0x400000UL /**< Bit mask for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6_DEFAULT (_LESENSE_ALTEXCONF_AEX6_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7 (0x1UL << 23) /**< ALTEX7 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX7_SHIFT 23 /**< Shift value for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_MASK 0x800000UL /**< Bit mask for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7_DEFAULT (_LESENSE_ALTEXCONF_AEX7_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ + +/* Bit fields for LESENSE IF */ +#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */ +#define _LESENSE_IF_MASK 0x007FFFFFUL /**< Mask for LESENSE_IF */ +#define LESENSE_IF_CH0 (0x1UL << 0) /**< CH0 interrupt flag */ +#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1 (0x1UL << 1) /**< CH1 interrupt flag */ +#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2 (0x1UL << 2) /**< CH2 interrupt flag */ +#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3 (0x1UL << 3) /**< CH3 interrupt flag */ +#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4 (0x1UL << 4) /**< CH4 interrupt flag */ +#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5 (0x1UL << 5) /**< CH5 interrupt flag */ +#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6 (0x1UL << 6) /**< CH6 interrupt flag */ +#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7 (0x1UL << 7) /**< CH7 interrupt flag */ +#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8 (0x1UL << 8) /**< CH8 interrupt flag */ +#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9 (0x1UL << 9) /**< CH9 interrupt flag */ +#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10 (0x1UL << 10) /**< CH10 interrupt flag */ +#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11 (0x1UL << 11) /**< CH11 interrupt flag */ +#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12 (0x1UL << 12) /**< CH12 interrupt flag */ +#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13 (0x1UL << 13) /**< CH13 interrupt flag */ +#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14 (0x1UL << 14) /**< CH14 interrupt flag */ +#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15 (0x1UL << 15) /**< CH15 interrupt flag */ +#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE interrupt flag */ +#define _LESENSE_IF_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE_DEFAULT (_LESENSE_IF_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC (0x1UL << 17) /**< DEC interrupt flag */ +#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR (0x1UL << 18) /**< DECERR interrupt flag */ +#define _LESENSE_IF_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR_DEFAULT (_LESENSE_IF_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV (0x1UL << 19) /**< BUFDATAV interrupt flag */ +#define _LESENSE_IF_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV_DEFAULT (_LESENSE_IF_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL interrupt flag */ +#define _LESENSE_IF_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL_DEFAULT (_LESENSE_IF_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF (0x1UL << 21) /**< BUFOF interrupt flag */ +#define _LESENSE_IF_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF_DEFAULT (_LESENSE_IF_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF (0x1UL << 22) /**< CNTOF interrupt flag */ +#define _LESENSE_IF_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IF */ + +/* Bit fields for LESENSE IFS */ +#define _LESENSE_IFS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFS */ +#define _LESENSE_IFS_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFS */ +#define LESENSE_IFS_CH0 (0x1UL << 0) /**< Set CH0 Interrupt Flag */ +#define _LESENSE_IFS_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH0_DEFAULT (_LESENSE_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1 (0x1UL << 1) /**< Set CH1 Interrupt Flag */ +#define _LESENSE_IFS_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1_DEFAULT (_LESENSE_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2 (0x1UL << 2) /**< Set CH2 Interrupt Flag */ +#define _LESENSE_IFS_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2_DEFAULT (_LESENSE_IFS_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3 (0x1UL << 3) /**< Set CH3 Interrupt Flag */ +#define _LESENSE_IFS_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3_DEFAULT (_LESENSE_IFS_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4 (0x1UL << 4) /**< Set CH4 Interrupt Flag */ +#define _LESENSE_IFS_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4_DEFAULT (_LESENSE_IFS_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5 (0x1UL << 5) /**< Set CH5 Interrupt Flag */ +#define _LESENSE_IFS_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5_DEFAULT (_LESENSE_IFS_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6 (0x1UL << 6) /**< Set CH6 Interrupt Flag */ +#define _LESENSE_IFS_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6_DEFAULT (_LESENSE_IFS_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7 (0x1UL << 7) /**< Set CH7 Interrupt Flag */ +#define _LESENSE_IFS_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7_DEFAULT (_LESENSE_IFS_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8 (0x1UL << 8) /**< Set CH8 Interrupt Flag */ +#define _LESENSE_IFS_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8_DEFAULT (_LESENSE_IFS_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9 (0x1UL << 9) /**< Set CH9 Interrupt Flag */ +#define _LESENSE_IFS_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9_DEFAULT (_LESENSE_IFS_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10 (0x1UL << 10) /**< Set CH10 Interrupt Flag */ +#define _LESENSE_IFS_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10_DEFAULT (_LESENSE_IFS_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11 (0x1UL << 11) /**< Set CH11 Interrupt Flag */ +#define _LESENSE_IFS_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11_DEFAULT (_LESENSE_IFS_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12 (0x1UL << 12) /**< Set CH12 Interrupt Flag */ +#define _LESENSE_IFS_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12_DEFAULT (_LESENSE_IFS_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13 (0x1UL << 13) /**< Set CH13 Interrupt Flag */ +#define _LESENSE_IFS_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13_DEFAULT (_LESENSE_IFS_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14 (0x1UL << 14) /**< Set CH14 Interrupt Flag */ +#define _LESENSE_IFS_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14_DEFAULT (_LESENSE_IFS_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15 (0x1UL << 15) /**< Set CH15 Interrupt Flag */ +#define _LESENSE_IFS_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15_DEFAULT (_LESENSE_IFS_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE (0x1UL << 16) /**< Set SCANCOMPLETE Interrupt Flag */ +#define _LESENSE_IFS_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE_DEFAULT (_LESENSE_IFS_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC (0x1UL << 17) /**< Set DEC Interrupt Flag */ +#define _LESENSE_IFS_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC_DEFAULT (_LESENSE_IFS_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR (0x1UL << 18) /**< Set DECERR Interrupt Flag */ +#define _LESENSE_IFS_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR_DEFAULT (_LESENSE_IFS_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV (0x1UL << 19) /**< Set BUFDATAV Interrupt Flag */ +#define _LESENSE_IFS_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV_DEFAULT (_LESENSE_IFS_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL (0x1UL << 20) /**< Set BUFLEVEL Interrupt Flag */ +#define _LESENSE_IFS_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL_DEFAULT (_LESENSE_IFS_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF (0x1UL << 21) /**< Set BUFOF Interrupt Flag */ +#define _LESENSE_IFS_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF_DEFAULT (_LESENSE_IFS_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF (0x1UL << 22) /**< Set CNTOF Interrupt Flag */ +#define _LESENSE_IFS_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF_DEFAULT (_LESENSE_IFS_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFS */ + +/* Bit fields for LESENSE IFC */ +#define _LESENSE_IFC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFC */ +#define _LESENSE_IFC_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFC */ +#define LESENSE_IFC_CH0 (0x1UL << 0) /**< Clear CH0 Interrupt Flag */ +#define _LESENSE_IFC_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH0_DEFAULT (_LESENSE_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1 (0x1UL << 1) /**< Clear CH1 Interrupt Flag */ +#define _LESENSE_IFC_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1_DEFAULT (_LESENSE_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2 (0x1UL << 2) /**< Clear CH2 Interrupt Flag */ +#define _LESENSE_IFC_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2_DEFAULT (_LESENSE_IFC_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3 (0x1UL << 3) /**< Clear CH3 Interrupt Flag */ +#define _LESENSE_IFC_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3_DEFAULT (_LESENSE_IFC_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4 (0x1UL << 4) /**< Clear CH4 Interrupt Flag */ +#define _LESENSE_IFC_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4_DEFAULT (_LESENSE_IFC_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5 (0x1UL << 5) /**< Clear CH5 Interrupt Flag */ +#define _LESENSE_IFC_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5_DEFAULT (_LESENSE_IFC_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6 (0x1UL << 6) /**< Clear CH6 Interrupt Flag */ +#define _LESENSE_IFC_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6_DEFAULT (_LESENSE_IFC_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7 (0x1UL << 7) /**< Clear CH7 Interrupt Flag */ +#define _LESENSE_IFC_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7_DEFAULT (_LESENSE_IFC_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8 (0x1UL << 8) /**< Clear CH8 Interrupt Flag */ +#define _LESENSE_IFC_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8_DEFAULT (_LESENSE_IFC_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9 (0x1UL << 9) /**< Clear CH9 Interrupt Flag */ +#define _LESENSE_IFC_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9_DEFAULT (_LESENSE_IFC_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10 (0x1UL << 10) /**< Clear CH10 Interrupt Flag */ +#define _LESENSE_IFC_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10_DEFAULT (_LESENSE_IFC_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11 (0x1UL << 11) /**< Clear CH11 Interrupt Flag */ +#define _LESENSE_IFC_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11_DEFAULT (_LESENSE_IFC_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12 (0x1UL << 12) /**< Clear CH12 Interrupt Flag */ +#define _LESENSE_IFC_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12_DEFAULT (_LESENSE_IFC_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13 (0x1UL << 13) /**< Clear CH13 Interrupt Flag */ +#define _LESENSE_IFC_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13_DEFAULT (_LESENSE_IFC_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14 (0x1UL << 14) /**< Clear CH14 Interrupt Flag */ +#define _LESENSE_IFC_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14_DEFAULT (_LESENSE_IFC_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15 (0x1UL << 15) /**< Clear CH15 Interrupt Flag */ +#define _LESENSE_IFC_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15_DEFAULT (_LESENSE_IFC_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE (0x1UL << 16) /**< Clear SCANCOMPLETE Interrupt Flag */ +#define _LESENSE_IFC_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE_DEFAULT (_LESENSE_IFC_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC (0x1UL << 17) /**< Clear DEC Interrupt Flag */ +#define _LESENSE_IFC_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC_DEFAULT (_LESENSE_IFC_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR (0x1UL << 18) /**< Clear DECERR Interrupt Flag */ +#define _LESENSE_IFC_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR_DEFAULT (_LESENSE_IFC_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV (0x1UL << 19) /**< Clear BUFDATAV Interrupt Flag */ +#define _LESENSE_IFC_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV_DEFAULT (_LESENSE_IFC_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL (0x1UL << 20) /**< Clear BUFLEVEL Interrupt Flag */ +#define _LESENSE_IFC_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL_DEFAULT (_LESENSE_IFC_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF (0x1UL << 21) /**< Clear BUFOF Interrupt Flag */ +#define _LESENSE_IFC_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF_DEFAULT (_LESENSE_IFC_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF (0x1UL << 22) /**< Clear CNTOF Interrupt Flag */ +#define _LESENSE_IFC_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF_DEFAULT (_LESENSE_IFC_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFC */ + +/* Bit fields for LESENSE IEN */ +#define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */ +#define _LESENSE_IEN_MASK 0x007FFFFFUL /**< Mask for LESENSE_IEN */ +#define LESENSE_IEN_CH0 (0x1UL << 0) /**< CH0 Interrupt Enable */ +#define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1 (0x1UL << 1) /**< CH1 Interrupt Enable */ +#define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2 (0x1UL << 2) /**< CH2 Interrupt Enable */ +#define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3 (0x1UL << 3) /**< CH3 Interrupt Enable */ +#define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4 (0x1UL << 4) /**< CH4 Interrupt Enable */ +#define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5 (0x1UL << 5) /**< CH5 Interrupt Enable */ +#define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6 (0x1UL << 6) /**< CH6 Interrupt Enable */ +#define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7 (0x1UL << 7) /**< CH7 Interrupt Enable */ +#define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8 (0x1UL << 8) /**< CH8 Interrupt Enable */ +#define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9 (0x1UL << 9) /**< CH9 Interrupt Enable */ +#define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10 (0x1UL << 10) /**< CH10 Interrupt Enable */ +#define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11 (0x1UL << 11) /**< CH11 Interrupt Enable */ +#define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12 (0x1UL << 12) /**< CH12 Interrupt Enable */ +#define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13 (0x1UL << 13) /**< CH13 Interrupt Enable */ +#define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14 (0x1UL << 14) /**< CH14 Interrupt Enable */ +#define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15 (0x1UL << 15) /**< CH15 Interrupt Enable */ +#define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE Interrupt Enable */ +#define _LESENSE_IEN_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE_DEFAULT (_LESENSE_IEN_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC (0x1UL << 17) /**< DEC Interrupt Enable */ +#define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR (0x1UL << 18) /**< DECERR Interrupt Enable */ +#define _LESENSE_IEN_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR_DEFAULT (_LESENSE_IEN_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV (0x1UL << 19) /**< BUFDATAV Interrupt Enable */ +#define _LESENSE_IEN_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV_DEFAULT (_LESENSE_IEN_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL Interrupt Enable */ +#define _LESENSE_IEN_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL_DEFAULT (_LESENSE_IEN_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF (0x1UL << 21) /**< BUFOF Interrupt Enable */ +#define _LESENSE_IEN_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF_DEFAULT (_LESENSE_IEN_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF (0x1UL << 22) /**< CNTOF Interrupt Enable */ +#define _LESENSE_IEN_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IEN */ + +/* Bit fields for LESENSE SYNCBUSY */ +#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */ +#define _LESENSE_SYNCBUSY_MASK 0x00000080UL /**< Mask for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD (0x1UL << 7) /**< CMD Register Busy */ +#define _LESENSE_SYNCBUSY_CMD_SHIFT 7 /**< Shift value for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_MASK 0x80UL /**< Bit mask for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */ + +/* Bit fields for LESENSE ROUTEPEN */ +#define _LESENSE_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ROUTEPEN */ +#define _LESENSE_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for LESENSE_CH0PEN */ +#define _LESENSE_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for LESENSE_CH0PEN */ +#define _LESENSE_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH0PEN_DEFAULT (_LESENSE_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH0 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for LESENSE_CH1PEN */ +#define _LESENSE_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for LESENSE_CH1PEN */ +#define _LESENSE_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH1PEN_DEFAULT (_LESENSE_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for LESENSE_CH2PEN */ +#define _LESENSE_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for LESENSE_CH2PEN */ +#define _LESENSE_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH2PEN_DEFAULT (_LESENSE_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for LESENSE_CH3PEN */ +#define _LESENSE_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for LESENSE_CH3PEN */ +#define _LESENSE_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH3PEN_DEFAULT (_LESENSE_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for LESENSE_CH4PEN */ +#define _LESENSE_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for LESENSE_CH4PEN */ +#define _LESENSE_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH4PEN_DEFAULT (_LESENSE_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for LESENSE_CH5PEN */ +#define _LESENSE_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for LESENSE_CH5PEN */ +#define _LESENSE_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH5PEN_DEFAULT (_LESENSE_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for LESENSE_CH6PEN */ +#define _LESENSE_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for LESENSE_CH6PEN */ +#define _LESENSE_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH6PEN_DEFAULT (_LESENSE_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for LESENSE_CH7PEN */ +#define _LESENSE_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for LESENSE_CH7PEN */ +#define _LESENSE_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH7PEN_DEFAULT (_LESENSE_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for LESENSE_CH8PEN */ +#define _LESENSE_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for LESENSE_CH8PEN */ +#define _LESENSE_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH8PEN_DEFAULT (_LESENSE_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for LESENSE_CH9PEN */ +#define _LESENSE_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for LESENSE_CH9PEN */ +#define _LESENSE_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH9PEN_DEFAULT (_LESENSE_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for LESENSE_CH10PEN */ +#define _LESENSE_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for LESENSE_CH10PEN */ +#define _LESENSE_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH10PEN_DEFAULT (_LESENSE_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for LESENSE_CH11PEN */ +#define _LESENSE_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for LESENSE_CH11PEN */ +#define _LESENSE_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH11PEN_DEFAULT (_LESENSE_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for LESENSE_CH12PEN */ +#define _LESENSE_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for LESENSE_CH12PEN */ +#define _LESENSE_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH12PEN_DEFAULT (_LESENSE_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for LESENSE_CH13PEN */ +#define _LESENSE_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for LESENSE_CH13PEN */ +#define _LESENSE_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH13PEN_DEFAULT (_LESENSE_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for LESENSE_CH14PEN */ +#define _LESENSE_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for LESENSE_CH14PEN */ +#define _LESENSE_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH14PEN_DEFAULT (_LESENSE_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for LESENSE_CH15PEN */ +#define _LESENSE_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for LESENSE_CH15PEN */ +#define _LESENSE_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH15PEN_DEFAULT (_LESENSE_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX0PEN (0x1UL << 16) /**< ALTEX0 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_SHIFT 16 /**< Shift value for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_MASK 0x10000UL /**< Bit mask for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX1PEN (0x1UL << 17) /**< ALTEX1 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_SHIFT 17 /**< Shift value for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_MASK 0x20000UL /**< Bit mask for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX2PEN (0x1UL << 18) /**< ALTEX2 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_SHIFT 18 /**< Shift value for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX3PEN (0x1UL << 19) /**< ALTEX3 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_SHIFT 19 /**< Shift value for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_MASK 0x80000UL /**< Bit mask for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX4PEN (0x1UL << 20) /**< ALTEX4 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_SHIFT 20 /**< Shift value for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_MASK 0x100000UL /**< Bit mask for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX5PEN (0x1UL << 21) /**< ALTEX5 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_SHIFT 21 /**< Shift value for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX6PEN (0x1UL << 22) /**< ALTEX6 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_SHIFT 22 /**< Shift value for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_MASK 0x400000UL /**< Bit mask for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX7PEN (0x1UL << 23) /**< ALTEX7 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_SHIFT 23 /**< Shift value for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_MASK 0x800000UL /**< Bit mask for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ + +/* Bit fields for LESENSE ST_TCONFA */ +#define _LESENSE_ST_TCONFA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK 0x0007DFFFUL /**< Mask for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_COMP_DEFAULT (_LESENSE_ST_TCONFA_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_MASK_DEFAULT (_LESENSE_ST_TCONFA_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN (0x1UL << 14) /**< Enable state descriptor chaining */ +#define _LESENSE_ST_TCONFA_CHAIN_SHIFT 14 /**< Shift value for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_MASK 0x4000UL /**< Bit mask for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN_DEFAULT (_LESENSE_ST_TCONFA_CHAIN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF (0x1UL << 15) /**< Set interrupt flag enable */ +#define _LESENSE_ST_TCONFA_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF_DEFAULT (_LESENSE_ST_TCONFA_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */ + +/* Bit fields for LESENSE ST_TCONFB */ +#define _LESENSE_ST_TCONFB_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK 0x00079FFFUL /**< Mask for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_COMP_DEFAULT (_LESENSE_ST_TCONFB_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_MASK_DEFAULT (_LESENSE_ST_TCONFB_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF (0x1UL << 15) /**< Set interrupt flag */ +#define _LESENSE_ST_TCONFB_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF_DEFAULT (_LESENSE_ST_TCONFB_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */ + +/* Bit fields for LESENSE BUF_DATA */ +#define _LESENSE_BUF_DATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_DATA_SHIFT 0 /**< Shift value for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ +#define LESENSE_BUF_DATA_DATA_DEFAULT (_LESENSE_BUF_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_DATASRC_SHIFT 16 /**< Shift value for LESENSE_DATASRC */ +#define _LESENSE_BUF_DATA_DATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_DATASRC */ +#define _LESENSE_BUF_DATA_DATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ +#define LESENSE_BUF_DATA_DATASRC_DEFAULT (_LESENSE_BUF_DATA_DATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ + +/* Bit fields for LESENSE CH_TIMING */ +#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ + +/* Bit fields for LESENSE CH_INTERACT */ +#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_MASK 0x003FFFFFUL /**< Mask for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 12 /**< Shift value for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x3000UL /**< Bit mask for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 12) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 12) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 12) /**< Shifted mode ADC for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 12) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_SHIFT 14 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_MASK 0x1C000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 14) /**< Shifted mode NONE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 14) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 14) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 14) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 14) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 17 /**< Shift value for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x60000UL /**< Bit mask for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 17) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 17) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 17) /**< Shifted mode LOW for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 17) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 19) /**< Select clock used for excitation timing */ +#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 19 /**< Shift value for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x80000UL /**< Bit mask for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 20) /**< Select clock used for timing of sample delay */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 20 /**< Shift value for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x100000UL /**< Bit mask for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 21) /**< Use alternative excite pin */ +#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 21 /**< Shift value for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ + +/* Bit fields for LESENSE CH_EVAL */ +#define _LESENSE_CH_EVAL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MASK 0x007FFFFFUL /**< Mask for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMPTHRES_SHIFT 0 /**< Shift value for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMPTHRES_DEFAULT (_LESENSE_CH_EVAL_COMPTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP (0x1UL << 16) /**< Select mode for threshold comparison */ +#define _LESENSE_CH_EVAL_COMP_SHIFT 16 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_MASK 0x10000UL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_DEFAULT (_LESENSE_CH_EVAL_COMP_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_LESS (_LESENSE_CH_EVAL_COMP_LESS << 16) /**< Shifted mode LESS for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_GE (_LESENSE_CH_EVAL_COMP_GE << 16) /**< Shifted mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE (0x1UL << 17) /**< Send result to decoder */ +#define _LESENSE_CH_EVAL_DECODE_SHIFT 17 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_MASK 0x20000UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE_DEFAULT (_LESENSE_CH_EVAL_DECODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_SHIFT 18 /**< Shift value for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_MASK 0xC0000UL /**< Bit mask for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DEFAULT (_LESENSE_CH_EVAL_STRSAMPLE_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DISABLE (_LESENSE_CH_EVAL_STRSAMPLE_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DATA (_LESENSE_CH_EVAL_STRSAMPLE_DATA << 18) /**< Shifted mode DATA for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DATASRC (_LESENSE_CH_EVAL_STRSAMPLE_DATASRC << 18) /**< Shifted mode DATASRC for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV (0x1UL << 20) /**< Enable inversion of result */ +#define _LESENSE_CH_EVAL_SCANRESINV_SHIFT 20 /**< Shift value for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_MASK 0x100000UL /**< Bit mask for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV_DEFAULT (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_SHIFT 21 /**< Shift value for LESENSE_MODE */ +#define _LESENSE_CH_EVAL_MODE_MASK 0x600000UL /**< Bit mask for LESENSE_MODE */ +#define _LESENSE_CH_EVAL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_DEFAULT (_LESENSE_CH_EVAL_MODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_THRES (_LESENSE_CH_EVAL_MODE_THRES << 21) /**< Shifted mode THRES for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_SLIDINGWIN (_LESENSE_CH_EVAL_MODE_SLIDINGWIN << 21) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_STEPDET (_LESENSE_CH_EVAL_MODE_STEPDET << 21) /**< Shifted mode STEPDET for LESENSE_CH_EVAL */ + +/** @} End of group EFM32PG12B_LESENSE */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_buf.h new file mode 100644 index 00000000000..2d4dc6bb581 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_buf.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efm32pg12b_lesense_buf.h + * @brief EFM32PG12B_LESENSE_BUF register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_BUF EFM32PG12B LESENSE BUF + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t DATA; /**< Scan results */ +} LESENSE_BUF_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_ch.h new file mode 100644 index 00000000000..219d835d0e6 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_ch.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efm32pg12b_lesense_ch.h + * @brief EFM32PG12B_LESENSE_CH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_CH EFM32PG12B LESENSE CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t TIMING; /**< Scan configuration */ + __IOM uint32_t INTERACT; /**< Scan configuration */ + __IOM uint32_t EVAL; /**< Scan configuration */ + uint32_t RESERVED0[1]; /**< Reserved future */ +} LESENSE_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_st.h new file mode 100644 index 00000000000..d1fa3a040b5 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_st.h @@ -0,0 +1,47 @@ +/**************************************************************************//** + * @file efm32pg12b_lesense_st.h + * @brief EFM32PG12B_LESENSE_ST register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_ST EFM32PG12B LESENSE ST + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t TCONFA; /**< State transition configuration A */ + __IOM uint32_t TCONFB; /**< State transition configuration B */ +} LESENSE_ST_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_letimer.h new file mode 100644 index 00000000000..1554f37d2ed --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_letimer.h @@ -0,0 +1,620 @@ +/**************************************************************************//** + * @file efm32pg12b_letimer.h + * @brief EFM32PG12B_LETIMER register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_LETIMER + * @{ + * @brief EFM32PG12B_LETIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IOM uint32_t PRSSEL; /**< PRS Input Select Register */ +} LETIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_LETIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000013FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IFS */ +#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */ +#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */ +#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set COMP0 Interrupt Flag */ +#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set COMP1 Interrupt Flag */ +#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF (0x1UL << 2) /**< Set UF Interrupt Flag */ +#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set REP0 Interrupt Flag */ +#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set REP1 Interrupt Flag */ +#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */ + +/* Bit fields for LETIMER IFC */ +#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */ +#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */ +#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear COMP0 Interrupt Flag */ +#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear COMP1 Interrupt Flag */ +#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear UF Interrupt Flag */ +#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear REP0 Interrupt Flag */ +#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear REP1 Interrupt Flag */ +#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< COMP0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< COMP1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< UF Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< REP0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< REP1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x00000002UL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER ROUTEPEN */ +#define _LETIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTEPEN */ +#define _LETIMER_ROUTEPEN_MASK 0x00000003UL /**< Mask for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */ +#define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTEPEN_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */ +#define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTEPEN_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ + +/* Bit fields for LETIMER ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT 0 /**< Shift value for LETIMER_OUT0LOC */ +#define _LETIMER_ROUTELOC0_OUT0LOC_MASK 0x1FUL /**< Bit mask for LETIMER_OUT0LOC */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC0 (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC1 (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC2 (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC3 (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC4 (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC5 (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC6 (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC7 (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC8 (_LETIMER_ROUTELOC0_OUT0LOC_LOC8 << 0) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC9 (_LETIMER_ROUTELOC0_OUT0LOC_LOC9 << 0) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC10 (_LETIMER_ROUTELOC0_OUT0LOC_LOC10 << 0) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC11 (_LETIMER_ROUTELOC0_OUT0LOC_LOC11 << 0) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC12 (_LETIMER_ROUTELOC0_OUT0LOC_LOC12 << 0) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC13 (_LETIMER_ROUTELOC0_OUT0LOC_LOC13 << 0) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC14 (_LETIMER_ROUTELOC0_OUT0LOC_LOC14 << 0) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC15 (_LETIMER_ROUTELOC0_OUT0LOC_LOC15 << 0) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC16 (_LETIMER_ROUTELOC0_OUT0LOC_LOC16 << 0) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC17 (_LETIMER_ROUTELOC0_OUT0LOC_LOC17 << 0) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC18 (_LETIMER_ROUTELOC0_OUT0LOC_LOC18 << 0) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC19 (_LETIMER_ROUTELOC0_OUT0LOC_LOC19 << 0) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC20 (_LETIMER_ROUTELOC0_OUT0LOC_LOC20 << 0) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC21 (_LETIMER_ROUTELOC0_OUT0LOC_LOC21 << 0) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC22 (_LETIMER_ROUTELOC0_OUT0LOC_LOC22 << 0) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC23 (_LETIMER_ROUTELOC0_OUT0LOC_LOC23 << 0) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC24 (_LETIMER_ROUTELOC0_OUT0LOC_LOC24 << 0) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC25 (_LETIMER_ROUTELOC0_OUT0LOC_LOC25 << 0) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC26 (_LETIMER_ROUTELOC0_OUT0LOC_LOC26 << 0) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC27 (_LETIMER_ROUTELOC0_OUT0LOC_LOC27 << 0) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC28 (_LETIMER_ROUTELOC0_OUT0LOC_LOC28 << 0) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC29 (_LETIMER_ROUTELOC0_OUT0LOC_LOC29 << 0) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC30 (_LETIMER_ROUTELOC0_OUT0LOC_LOC30 << 0) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC31 (_LETIMER_ROUTELOC0_OUT0LOC_LOC31 << 0) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT 8 /**< Shift value for LETIMER_OUT1LOC */ +#define _LETIMER_ROUTELOC0_OUT1LOC_MASK 0x1F00UL /**< Bit mask for LETIMER_OUT1LOC */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC0 (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC1 (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC2 (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC3 (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC4 (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC5 (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC6 (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC7 (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC8 (_LETIMER_ROUTELOC0_OUT1LOC_LOC8 << 8) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC9 (_LETIMER_ROUTELOC0_OUT1LOC_LOC9 << 8) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC10 (_LETIMER_ROUTELOC0_OUT1LOC_LOC10 << 8) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC11 (_LETIMER_ROUTELOC0_OUT1LOC_LOC11 << 8) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC12 (_LETIMER_ROUTELOC0_OUT1LOC_LOC12 << 8) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC13 (_LETIMER_ROUTELOC0_OUT1LOC_LOC13 << 8) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC14 (_LETIMER_ROUTELOC0_OUT1LOC_LOC14 << 8) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC15 (_LETIMER_ROUTELOC0_OUT1LOC_LOC15 << 8) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC16 (_LETIMER_ROUTELOC0_OUT1LOC_LOC16 << 8) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC17 (_LETIMER_ROUTELOC0_OUT1LOC_LOC17 << 8) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC18 (_LETIMER_ROUTELOC0_OUT1LOC_LOC18 << 8) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC19 (_LETIMER_ROUTELOC0_OUT1LOC_LOC19 << 8) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC20 (_LETIMER_ROUTELOC0_OUT1LOC_LOC20 << 8) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC21 (_LETIMER_ROUTELOC0_OUT1LOC_LOC21 << 8) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC22 (_LETIMER_ROUTELOC0_OUT1LOC_LOC22 << 8) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC23 (_LETIMER_ROUTELOC0_OUT1LOC_LOC23 << 8) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC24 (_LETIMER_ROUTELOC0_OUT1LOC_LOC24 << 8) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC25 (_LETIMER_ROUTELOC0_OUT1LOC_LOC25 << 8) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC26 (_LETIMER_ROUTELOC0_OUT1LOC_LOC26 << 8) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC27 (_LETIMER_ROUTELOC0_OUT1LOC_LOC27 << 8) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC28 (_LETIMER_ROUTELOC0_OUT1LOC_LOC28 << 8) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC29 (_LETIMER_ROUTELOC0_OUT1LOC_LOC29 << 8) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC30 (_LETIMER_ROUTELOC0_OUT1LOC_LOC30 << 8) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC31 (_LETIMER_ROUTELOC0_OUT1LOC_LOC31 << 8) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */ + +/* Bit fields for LETIMER PRSSEL */ +#define _LETIMER_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_MASK 0x0CCCF3CFUL /**< Mask for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT 0 /**< Shift value for LETIMER_PRSSTARTSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_MASK 0xFUL /**< Bit mask for LETIMER_PRSSTARTSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT 6 /**< Shift value for LETIMER_PRSSTOPSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_MASK 0x3C0UL /**< Bit mask for LETIMER_PRSSTOPSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT 12 /**< Shift value for LETIMER_PRSCLEARSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_MASK 0xF000UL /**< Bit mask for LETIMER_PRSCLEARSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_NONE (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_RISING (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_FALLING (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_BOTH (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_NONE (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_RISING (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_FALLING (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_BOTH (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_NONE (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_RISING (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */ + +/** @} End of group EFM32PG12B_LETIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_leuart.h new file mode 100644 index 00000000000..348761e48e3 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_leuart.h @@ -0,0 +1,835 @@ +/**************************************************************************//** + * @file efm32pg12b_leuart.h + * @brief EFM32PG12B_LEUART register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_LEUART + * @{ + * @brief EFM32PG12B_LEUART Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IOM uint32_t STARTFRAME; /**< Start Frame Register */ + __IOM uint32_t SIGFRAME; /**< Signal Frame Register */ + __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */ + __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PULSECTRL; /**< Pulse Control Register */ + + __IOM uint32_t FREEZE; /**< Freeze Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t INPUT; /**< LEUART Input Register */ +} LEUART_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_LEUART_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LEUART CTRL */ +#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */ +#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */ +#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */ +#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */ +#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */ +#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */ +#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */ +#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */ +#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */ +#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */ +#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */ +#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */ +#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */ +#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */ +#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */ +#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */ +#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */ +#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */ +#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */ +#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */ +#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */ +#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */ +#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */ +#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */ +#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */ +#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */ +#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */ +#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */ +#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */ +#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */ +#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */ +#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */ +#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */ +#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */ +#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */ +#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */ +#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */ +#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */ +#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */ +#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */ +#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */ +#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */ +#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */ +#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */ + +/* Bit fields for LEUART CMD */ +#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */ +#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */ +#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */ +#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */ +#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */ +#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */ +#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */ +#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */ +#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */ +#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */ +#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */ +#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */ +#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */ +#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */ +#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */ +#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */ +#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */ +#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */ +#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */ +#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */ + +/* Bit fields for LEUART STATUS */ +#define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */ +#define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */ +#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */ +#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */ +#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */ +#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */ +#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */ +#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */ +#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */ +#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */ +#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */ +#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */ +#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */ +#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */ +#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */ +#define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */ +#define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */ +#define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */ + +/* Bit fields for LEUART CLKDIV */ +#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */ +#define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */ +#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */ +#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */ + +/* Bit fields for LEUART STARTFRAME */ +#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */ +#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */ + +/* Bit fields for LEUART SIGFRAME */ +#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */ +#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */ + +/* Bit fields for LEUART RXDATAX */ +#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */ +#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */ +#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */ +#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */ +#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */ +#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ + +/* Bit fields for LEUART RXDATA */ +#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */ +#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */ +#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */ + +/* Bit fields for LEUART RXDATAXP */ +#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */ +#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */ +#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */ +#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */ +#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */ +#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */ +#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */ +#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */ +#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ + +/* Bit fields for LEUART TXDATAX */ +#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */ +#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */ +#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */ +#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */ +#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */ +#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */ +#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */ +#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ + +/* Bit fields for LEUART TXDATA */ +#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */ +#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */ +#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */ + +/* Bit fields for LEUART IF */ +#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */ +#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */ +#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */ +#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */ +#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */ +#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */ +#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */ +#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */ +#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */ +#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */ + +/* Bit fields for LEUART IFS */ +#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */ +#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */ +#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ +#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */ +#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */ +#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */ +#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */ +#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */ +#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */ +#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */ +#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */ +#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */ + +/* Bit fields for LEUART IFC */ +#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */ +#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */ +#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ +#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */ +#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */ +#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */ +#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */ +#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */ +#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */ +#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */ +#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */ +#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */ + +/* Bit fields for LEUART IEN */ +#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */ +#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */ +#define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ +#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ +#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ +#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */ +#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */ +#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */ +#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */ +#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */ +#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */ +#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */ +#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */ +#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */ + +/* Bit fields for LEUART PULSECTRL */ +#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */ +#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */ +#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */ +#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */ +#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */ +#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */ +#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */ +#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */ +#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ + +/* Bit fields for LEUART FREEZE */ +#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */ +#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */ +#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */ +#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */ + +/* Bit fields for LEUART SYNCBUSY */ +#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */ +#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */ +#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */ +#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */ +#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */ +#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */ +#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */ +#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */ +#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */ +#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */ +#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */ +#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */ +#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */ +#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */ +#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */ +#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */ +#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */ +#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */ +#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ + +/* Bit fields for LEUART ROUTEPEN */ +#define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */ +#define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ +#define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */ +#define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */ +#define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ +#define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */ +#define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */ +#define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ + +/* Bit fields for LEUART ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */ +#define _LEUART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for LEUART_RXLOC */ +#define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC6 (_LEUART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC7 (_LEUART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC8 (_LEUART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC9 (_LEUART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC10 (_LEUART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC11 (_LEUART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC12 (_LEUART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC13 (_LEUART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC14 (_LEUART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC15 (_LEUART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC16 (_LEUART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC17 (_LEUART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC18 (_LEUART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC19 (_LEUART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC20 (_LEUART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC21 (_LEUART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC22 (_LEUART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC23 (_LEUART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC24 (_LEUART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC25 (_LEUART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC26 (_LEUART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC27 (_LEUART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC28 (_LEUART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC29 (_LEUART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC30 (_LEUART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC31 (_LEUART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */ +#define _LEUART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for LEUART_TXLOC */ +#define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC6 (_LEUART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC7 (_LEUART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC8 (_LEUART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC9 (_LEUART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC10 (_LEUART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC11 (_LEUART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC12 (_LEUART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC13 (_LEUART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC14 (_LEUART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC15 (_LEUART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC16 (_LEUART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC17 (_LEUART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC18 (_LEUART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC19 (_LEUART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC20 (_LEUART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC21 (_LEUART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC22 (_LEUART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC23 (_LEUART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC24 (_LEUART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC25 (_LEUART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC26 (_LEUART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC27 (_LEUART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC28 (_LEUART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC29 (_LEUART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC30 (_LEUART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC31 (_LEUART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ + +/* Bit fields for LEUART INPUT */ +#define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */ +#define _LEUART_INPUT_MASK 0x0000002FUL /**< Mask for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */ +#define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */ +#define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */ +#define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */ +#define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */ +#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ +#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */ + +/** @} End of group EFM32PG12B_LEUART */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_msc.h new file mode 100644 index 00000000000..4864b6f19b6 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_msc.h @@ -0,0 +1,664 @@ +/**************************************************************************//** + * @file efm32pg12b_msc.h + * @brief EFM32PG12B_MSC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_MSC + * @{ + * @brief EFM32PG12B_MSC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader read and write enable, write once register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control enable Register */ +} MSC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_MSC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000001FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up On Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass erase region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x0000017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< iCache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash controller write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x0000017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x0000017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x0000017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Enable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Eanble */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software unlock AAP command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00090101UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMCACHEEN (0x1UL << 0) /**< RAM CACHE Enable */ +#define _MSC_RAMCTRL_RAMCACHEEN_SHIFT 0 /**< Shift value for MSC_RAMCACHEEN */ +#define _MSC_RAMCTRL_RAMCACHEEN_MASK 0x1UL /**< Bit mask for MSC_RAMCACHEEN */ +#define _MSC_RAMCTRL_RAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMCACHEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1CACHEEN (0x1UL << 8) /**< RAM1 CACHE Enable */ +#define _MSC_RAMCTRL_RAM1CACHEEN_SHIFT 8 /**< Shift value for MSC_RAM1CACHEEN */ +#define _MSC_RAMCTRL_RAM1CACHEEN_MASK 0x100UL /**< Bit mask for MSC_RAM1CACHEEN */ +#define _MSC_RAMCTRL_RAM1CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM1CACHEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMSEQCACHEEN (0x1UL << 19) /**< RAMSEQ CACHE Enable */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_SHIFT 19 /**< Shift value for MSC_RAMSEQCACHEEN */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_MASK 0x80000UL /**< Bit mask for MSC_RAMSEQCACHEEN */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/** @} End of group EFM32PG12B_MSC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_pcnt.h new file mode 100644 index 00000000000..d7ae695a975 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_pcnt.h @@ -0,0 +1,706 @@ +/**************************************************************************//** + * @file efm32pg12b_pcnt.h + * @brief EFM32PG12B_PCNT register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_PCNT + * @{ + * @brief EFM32PG12B_PCNT Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t TOP; /**< Top Value Register */ + __IOM uint32_t TOPB; /**< Top Value Buffer Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t FREEZE; /**< Freeze Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED2[7]; /**< Reserved for future use **/ + __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ + __IOM uint32_t INPUT; /**< PCNT Input Register */ + __IOM uint32_t OVSCFG; /**< Oversampling Config Register */ +} PCNT_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_PCNT_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for PCNT CTRL */ +#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ +#define _PCNT_CTRL_MASK 0xBFDBFFFFUL /**< Mask for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ +#define _PCNT_CTRL_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ +#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD1X 0x00000004UL /**< Mode OVSQUAD1X for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD2X 0x00000005UL /**< Mode OVSQUAD2X for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD4X 0x00000006UL /**< Mode OVSQUAD4X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD1X (_PCNT_CTRL_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD2X (_PCNT_CTRL_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD4X (_PCNT_CTRL_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CTRL */ +#define PCNT_CTRL_FILT (0x1UL << 3) /**< Enable Digital Pulse Width Filter */ +#define _PCNT_CTRL_FILT_SHIFT 3 /**< Shift value for PCNT_FILT */ +#define _PCNT_CTRL_FILT_MASK 0x8UL /**< Bit mask for PCNT_FILT */ +#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN (0x1UL << 4) /**< Enable PCNT Clock Domain Reset */ +#define _PCNT_CTRL_RSTEN_SHIFT 4 /**< Shift value for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_MASK 0x10UL /**< Bit mask for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTRSTEN (0x1UL << 5) /**< Enable CNT Reset */ +#define _PCNT_CTRL_CNTRSTEN_SHIFT 5 /**< Shift value for PCNT_CNTRSTEN */ +#define _PCNT_CTRL_CNTRSTEN_MASK 0x20UL /**< Bit mask for PCNT_CNTRSTEN */ +#define _PCNT_CTRL_CNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTRSTEN_DEFAULT (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTRSTEN (0x1UL << 6) /**< Enable AUXCNT Reset */ +#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT 6 /**< Shift value for PCNT_AUXCNTRSTEN */ +#define _PCNT_CTRL_AUXCNTRSTEN_MASK 0x40UL /**< Bit mask for PCNT_AUXCNTRSTEN */ +#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_DEBUGHALT (0x1UL << 7) /**< Debug Mode Halt Enable */ +#define _PCNT_CTRL_DEBUGHALT_SHIFT 7 /**< Shift value for PCNT_DEBUGHALT */ +#define _PCNT_CTRL_DEBUGHALT_MASK 0x80UL /**< Bit mask for PCNT_DEBUGHALT */ +#define _PCNT_CTRL_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_DEBUGHALT_DEFAULT (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */ +#define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */ +#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */ +#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count direction determined by S1 */ +#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_SHIFT 12 /**< Shift value for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_MASK 0x3000UL /**< Bit mask for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 12) /**< Shifted mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 12) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 12) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 12) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR (0x1UL << 14) /**< Non-Quadrature Mode Counter Direction Control */ +#define _PCNT_CTRL_CNTDIR_SHIFT 14 /**< Shift value for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_MASK 0x4000UL /**< Bit mask for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 14) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_EDGE (0x1UL << 15) /**< Edge Select */ +#define _PCNT_CTRL_EDGE_SHIFT 15 /**< Shift value for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_MASK 0x8000UL /**< Bit mask for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 15) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 15) /**< Shifted mode POS for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 15) /**< Shifted mode NEG for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_SHIFT 16 /**< Shift value for PCNT_TCCMODE */ +#define _PCNT_CTRL_TCCMODE_MASK 0x30000UL /**< Bit mask for PCNT_TCCMODE */ +#define _PCNT_CTRL_TCCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_DISABLED 0x00000000UL /**< Mode DISABLED for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_LFA 0x00000001UL /**< Mode LFA for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_PRS 0x00000002UL /**< Mode PRS for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_DEFAULT (_PCNT_CTRL_TCCMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_DISABLED (_PCNT_CTRL_TCCMODE_DISABLED << 16) /**< Shifted mode DISABLED for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_LFA (_PCNT_CTRL_TCCMODE_LFA << 16) /**< Shifted mode LFA for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_PRS (_PCNT_CTRL_TCCMODE_PRS << 16) /**< Shifted mode PRS for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_SHIFT 19 /**< Shift value for PCNT_TCCPRESC */ +#define _PCNT_CTRL_TCCPRESC_MASK 0x180000UL /**< Bit mask for PCNT_TCCPRESC */ +#define _PCNT_CTRL_TCCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DEFAULT (_PCNT_CTRL_TCCPRESC_DEFAULT << 19) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV1 (_PCNT_CTRL_TCCPRESC_DIV1 << 19) /**< Shifted mode DIV1 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV2 (_PCNT_CTRL_TCCPRESC_DIV2 << 19) /**< Shifted mode DIV2 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV4 (_PCNT_CTRL_TCCPRESC_DIV4 << 19) /**< Shifted mode DIV4 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV8 (_PCNT_CTRL_TCCPRESC_DIV8 << 19) /**< Shifted mode DIV8 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_SHIFT 22 /**< Shift value for PCNT_TCCCOMP */ +#define _PCNT_CTRL_TCCCOMP_MASK 0xC00000UL /**< Bit mask for PCNT_TCCCOMP */ +#define _PCNT_CTRL_TCCCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_LTOE 0x00000000UL /**< Mode LTOE for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_GTOE 0x00000001UL /**< Mode GTOE for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_RANGE 0x00000002UL /**< Mode RANGE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_DEFAULT (_PCNT_CTRL_TCCCOMP_DEFAULT << 22) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */ +#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS gate enable */ +#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */ +#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */ +#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS polarity select */ +#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */ +#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */ +#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSPOL_RISING 0x00000000UL /**< Mode RISING for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSPOL_FALLING 0x00000001UL /**< Mode FALLING for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_DEFAULT (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_RISING (_PCNT_CTRL_TCCPRSPOL_RISING << 25) /**< Shifted mode RISING for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_FALLING (_PCNT_CTRL_TCCPRSPOL_FALLING << 25) /**< Shifted mode FALLING for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_SHIFT 26 /**< Shift value for PCNT_TCCPRSSEL */ +#define _PCNT_CTRL_TCCPRSSEL_MASK 0x3C000000UL /**< Bit mask for PCNT_TCCPRSSEL */ +#define _PCNT_CTRL_TCCPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_DEFAULT (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH0 (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26) /**< Shifted mode PRSCH0 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH1 (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26) /**< Shifted mode PRSCH1 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH2 (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26) /**< Shifted mode PRSCH2 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH3 (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26) /**< Shifted mode PRSCH3 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH4 (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26) /**< Shifted mode PRSCH4 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH5 (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26) /**< Shifted mode PRSCH5 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH6 (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26) /**< Shifted mode PRSCH6 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH7 (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26) /**< Shifted mode PRSCH7 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH8 (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26) /**< Shifted mode PRSCH8 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */ +#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High frequency value select */ +#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */ +#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */ +#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TOPBHFSEL_DEFAULT (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31) /**< Shifted mode DEFAULT for PCNT_CTRL */ + +/* Bit fields for PCNT CMD */ +#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ +#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */ +#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */ +#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */ +#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ + +/* Bit fields for PCNT STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ + +/* Bit fields for PCNT CNT */ +#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ +#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ +#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ +#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ + +/* Bit fields for PCNT TOP */ +#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ +#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ +#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ +#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ + +/* Bit fields for PCNT TOPB */ +#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ +#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ +#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ + +/* Bit fields for PCNT IF */ +#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ +#define _PCNT_IF_MASK 0x0000003FUL /**< Mask for PCNT_IF */ +#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered compare Interrupt Read Flag */ +#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_TCC_DEFAULT (_PCNT_IF_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR (0x1UL << 5) /**< Oversampling Quadrature State Error Interrupt */ +#define _PCNT_IF_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */ + +/* Bit fields for PCNT IFS */ +#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */ +#define _PCNT_IFS_MASK 0x0000003FUL /**< Mask for PCNT_IFS */ +#define PCNT_IFS_UF (0x1UL << 0) /**< Set UF Interrupt Flag */ +#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF (0x1UL << 1) /**< Set OF Interrupt Flag */ +#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Set DIRCNG Interrupt Flag */ +#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF (0x1UL << 3) /**< Set AUXOF Interrupt Flag */ +#define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_TCC (0x1UL << 4) /**< Set TCC Interrupt Flag */ +#define _PCNT_IFS_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IFS_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IFS_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_TCC_DEFAULT (_PCNT_IFS_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OQSTERR (0x1UL << 5) /**< Set OQSTERR Interrupt Flag */ +#define _PCNT_IFS_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IFS_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IFS_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OQSTERR_DEFAULT (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */ + +/* Bit fields for PCNT IFC */ +#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */ +#define _PCNT_IFC_MASK 0x0000003FUL /**< Mask for PCNT_IFC */ +#define PCNT_IFC_UF (0x1UL << 0) /**< Clear UF Interrupt Flag */ +#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF (0x1UL << 1) /**< Clear OF Interrupt Flag */ +#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Clear DIRCNG Interrupt Flag */ +#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF (0x1UL << 3) /**< Clear AUXOF Interrupt Flag */ +#define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_TCC (0x1UL << 4) /**< Clear TCC Interrupt Flag */ +#define _PCNT_IFC_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IFC_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IFC_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_TCC_DEFAULT (_PCNT_IFC_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OQSTERR (0x1UL << 5) /**< Clear OQSTERR Interrupt Flag */ +#define _PCNT_IFC_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IFC_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IFC_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OQSTERR_DEFAULT (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */ + +/* Bit fields for PCNT IEN */ +#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ +#define _PCNT_IEN_MASK 0x0000003FUL /**< Mask for PCNT_IEN */ +#define PCNT_IEN_UF (0x1UL << 0) /**< UF Interrupt Enable */ +#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF (0x1UL << 1) /**< OF Interrupt Enable */ +#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< DIRCNG Interrupt Enable */ +#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF (0x1UL << 3) /**< AUXOF Interrupt Enable */ +#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_TCC (0x1UL << 4) /**< TCC Interrupt Enable */ +#define _PCNT_IEN_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IEN_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IEN_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_TCC_DEFAULT (_PCNT_IEN_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR (0x1UL << 5) /**< OQSTERR Interrupt Enable */ +#define _PCNT_IEN_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */ + +/* Bit fields for PCNT ROUTELOC0 */ +#define _PCNT_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_SHIFT 0 /**< Shift value for PCNT_S0INLOC */ +#define _PCNT_ROUTELOC0_S0INLOC_MASK 0x1FUL /**< Bit mask for PCNT_S0INLOC */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC0 (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_DEFAULT (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC1 (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC2 (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC3 (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC4 (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC5 (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC6 (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC7 (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC8 (_PCNT_ROUTELOC0_S0INLOC_LOC8 << 0) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC9 (_PCNT_ROUTELOC0_S0INLOC_LOC9 << 0) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC10 (_PCNT_ROUTELOC0_S0INLOC_LOC10 << 0) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC11 (_PCNT_ROUTELOC0_S0INLOC_LOC11 << 0) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC12 (_PCNT_ROUTELOC0_S0INLOC_LOC12 << 0) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC13 (_PCNT_ROUTELOC0_S0INLOC_LOC13 << 0) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC14 (_PCNT_ROUTELOC0_S0INLOC_LOC14 << 0) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC15 (_PCNT_ROUTELOC0_S0INLOC_LOC15 << 0) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC16 (_PCNT_ROUTELOC0_S0INLOC_LOC16 << 0) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC17 (_PCNT_ROUTELOC0_S0INLOC_LOC17 << 0) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC18 (_PCNT_ROUTELOC0_S0INLOC_LOC18 << 0) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC19 (_PCNT_ROUTELOC0_S0INLOC_LOC19 << 0) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC20 (_PCNT_ROUTELOC0_S0INLOC_LOC20 << 0) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC21 (_PCNT_ROUTELOC0_S0INLOC_LOC21 << 0) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC22 (_PCNT_ROUTELOC0_S0INLOC_LOC22 << 0) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC23 (_PCNT_ROUTELOC0_S0INLOC_LOC23 << 0) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC24 (_PCNT_ROUTELOC0_S0INLOC_LOC24 << 0) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC25 (_PCNT_ROUTELOC0_S0INLOC_LOC25 << 0) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC26 (_PCNT_ROUTELOC0_S0INLOC_LOC26 << 0) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC27 (_PCNT_ROUTELOC0_S0INLOC_LOC27 << 0) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC28 (_PCNT_ROUTELOC0_S0INLOC_LOC28 << 0) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC29 (_PCNT_ROUTELOC0_S0INLOC_LOC29 << 0) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC30 (_PCNT_ROUTELOC0_S0INLOC_LOC30 << 0) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC31 (_PCNT_ROUTELOC0_S0INLOC_LOC31 << 0) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_SHIFT 8 /**< Shift value for PCNT_S1INLOC */ +#define _PCNT_ROUTELOC0_S1INLOC_MASK 0x1F00UL /**< Bit mask for PCNT_S1INLOC */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC0 (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_DEFAULT (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC1 (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC2 (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC3 (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC4 (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC5 (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC6 (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC7 (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC8 (_PCNT_ROUTELOC0_S1INLOC_LOC8 << 8) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC9 (_PCNT_ROUTELOC0_S1INLOC_LOC9 << 8) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC10 (_PCNT_ROUTELOC0_S1INLOC_LOC10 << 8) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC11 (_PCNT_ROUTELOC0_S1INLOC_LOC11 << 8) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC12 (_PCNT_ROUTELOC0_S1INLOC_LOC12 << 8) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC13 (_PCNT_ROUTELOC0_S1INLOC_LOC13 << 8) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC14 (_PCNT_ROUTELOC0_S1INLOC_LOC14 << 8) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC15 (_PCNT_ROUTELOC0_S1INLOC_LOC15 << 8) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC16 (_PCNT_ROUTELOC0_S1INLOC_LOC16 << 8) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC17 (_PCNT_ROUTELOC0_S1INLOC_LOC17 << 8) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC18 (_PCNT_ROUTELOC0_S1INLOC_LOC18 << 8) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC19 (_PCNT_ROUTELOC0_S1INLOC_LOC19 << 8) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC20 (_PCNT_ROUTELOC0_S1INLOC_LOC20 << 8) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC21 (_PCNT_ROUTELOC0_S1INLOC_LOC21 << 8) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC22 (_PCNT_ROUTELOC0_S1INLOC_LOC22 << 8) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC23 (_PCNT_ROUTELOC0_S1INLOC_LOC23 << 8) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC24 (_PCNT_ROUTELOC0_S1INLOC_LOC24 << 8) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC25 (_PCNT_ROUTELOC0_S1INLOC_LOC25 << 8) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC26 (_PCNT_ROUTELOC0_S1INLOC_LOC26 << 8) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC27 (_PCNT_ROUTELOC0_S1INLOC_LOC27 << 8) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC28 (_PCNT_ROUTELOC0_S1INLOC_LOC28 << 8) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC29 (_PCNT_ROUTELOC0_S1INLOC_LOC29 << 8) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC30 (_PCNT_ROUTELOC0_S1INLOC_LOC30 << 8) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC31 (_PCNT_ROUTELOC0_S1INLOC_LOC31 << 8) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */ + +/* Bit fields for PCNT FREEZE */ +#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */ +#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */ + +/* Bit fields for PCNT SYNCBUSY */ +#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_MASK 0x0000000FUL /**< Mask for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */ +#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCFG (0x1UL << 3) /**< OVSCFG Register Busy */ +#define _PCNT_SYNCBUSY_OVSCFG_SHIFT 3 /**< Shift value for PCNT_OVSCFG */ +#define _PCNT_SYNCBUSY_OVSCFG_MASK 0x8UL /**< Bit mask for PCNT_OVSCFG */ +#define _PCNT_SYNCBUSY_OVSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCFG_DEFAULT (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ + +/* Bit fields for PCNT AUXCNT */ +#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ +#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ + +/* Bit fields for PCNT INPUT */ +#define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */ +#define _PCNT_INPUT_MASK 0x00000BEFUL /**< Mask for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /**< Bit mask for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN (0x1UL << 5) /**< S0IN PRS Enable */ +#define _PCNT_INPUT_S0PRSEN_SHIFT 5 /**< Shift value for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_MASK 0x20UL /**< Bit mask for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /**< Bit mask for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN (0x1UL << 11) /**< S1IN PRS Enable */ +#define _PCNT_INPUT_S1PRSEN_SHIFT 11 /**< Shift value for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_MASK 0x800UL /**< Bit mask for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */ + +/* Bit fields for PCNT OVSCFG */ +#define _PCNT_OVSCFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCFG */ +#define _PCNT_OVSCFG_MASK 0x000010FFUL /**< Mask for PCNT_OVSCFG */ +#define _PCNT_OVSCFG_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ +#define _PCNT_OVSCFG_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ +#define _PCNT_OVSCFG_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FILTLEN_DEFAULT (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ +#define _PCNT_OVSCFG_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ +#define _PCNT_OVSCFG_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ +#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ + +/** @} End of group EFM32PG12B_PCNT */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs.h new file mode 100644 index 00000000000..969bfbc7718 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs.h @@ -0,0 +1,1089 @@ +/**************************************************************************//** + * @file efm32pg12b_prs.h + * @brief EFM32PG12B_PRS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_PRS + * @{ + * @brief EFM32PG12B_PRS Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + + uint32_t RESERVED1[5]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3]; /**< Reserved registers */ + PRS_CH_TypeDef CH[12]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_PRS_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00000FFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x0F07070FUL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0xFUL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC4 (_PRS_ROUTELOC0_CH0LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC5 (_PRS_ROUTELOC0_CH0LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC6 (_PRS_ROUTELOC0_CH0LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC7 (_PRS_ROUTELOC0_CH0LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC8 (_PRS_ROUTELOC0_CH0LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC9 (_PRS_ROUTELOC0_CH0LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC10 (_PRS_ROUTELOC0_CH0LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC11 (_PRS_ROUTELOC0_CH0LOC_LOC11 << 0) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC12 (_PRS_ROUTELOC0_CH0LOC_LOC12 << 0) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC13 (_PRS_ROUTELOC0_CH0LOC_LOC13 << 0) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x700UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC4 (_PRS_ROUTELOC0_CH1LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC5 (_PRS_ROUTELOC0_CH1LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC6 (_PRS_ROUTELOC0_CH1LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC7 (_PRS_ROUTELOC0_CH1LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x70000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC4 (_PRS_ROUTELOC0_CH2LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC5 (_PRS_ROUTELOC0_CH2LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC6 (_PRS_ROUTELOC0_CH2LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC7 (_PRS_ROUTELOC0_CH2LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC4 (_PRS_ROUTELOC0_CH3LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC5 (_PRS_ROUTELOC0_CH3LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC6 (_PRS_ROUTELOC0_CH3LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC7 (_PRS_ROUTELOC0_CH3LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC8 (_PRS_ROUTELOC0_CH3LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC9 (_PRS_ROUTELOC0_CH3LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC10 (_PRS_ROUTELOC0_CH3LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC11 (_PRS_ROUTELOC0_CH3LOC_LOC11 << 24) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC12 (_PRS_ROUTELOC0_CH3LOC_LOC12 << 24) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC13 (_PRS_ROUTELOC0_CH3LOC_LOC13 << 24) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC14 (_PRS_ROUTELOC0_CH3LOC_LOC14 << 24) /**< Shifted mode LOC14 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x0F1F0707UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x7UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC3 (_PRS_ROUTELOC1_CH4LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC4 (_PRS_ROUTELOC1_CH4LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC5 (_PRS_ROUTELOC1_CH4LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC6 (_PRS_ROUTELOC1_CH4LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x700UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC3 (_PRS_ROUTELOC1_CH5LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC4 (_PRS_ROUTELOC1_CH5LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC5 (_PRS_ROUTELOC1_CH5LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC6 (_PRS_ROUTELOC1_CH5LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x1F0000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC17 0x00000011UL /**< Mode LOC17 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC3 (_PRS_ROUTELOC1_CH6LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC4 (_PRS_ROUTELOC1_CH6LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC5 (_PRS_ROUTELOC1_CH6LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC6 (_PRS_ROUTELOC1_CH6LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC7 (_PRS_ROUTELOC1_CH6LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC8 (_PRS_ROUTELOC1_CH6LOC_LOC8 << 16) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC9 (_PRS_ROUTELOC1_CH6LOC_LOC9 << 16) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC10 (_PRS_ROUTELOC1_CH6LOC_LOC10 << 16) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC11 (_PRS_ROUTELOC1_CH6LOC_LOC11 << 16) /**< Shifted mode LOC11 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC12 (_PRS_ROUTELOC1_CH6LOC_LOC12 << 16) /**< Shifted mode LOC12 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC13 (_PRS_ROUTELOC1_CH6LOC_LOC13 << 16) /**< Shifted mode LOC13 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC14 (_PRS_ROUTELOC1_CH6LOC_LOC14 << 16) /**< Shifted mode LOC14 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC15 (_PRS_ROUTELOC1_CH6LOC_LOC15 << 16) /**< Shifted mode LOC15 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC16 (_PRS_ROUTELOC1_CH6LOC_LOC16 << 16) /**< Shifted mode LOC16 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC17 (_PRS_ROUTELOC1_CH6LOC_LOC17 << 16) /**< Shifted mode LOC17 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC3 (_PRS_ROUTELOC1_CH7LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC4 (_PRS_ROUTELOC1_CH7LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC5 (_PRS_ROUTELOC1_CH7LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC6 (_PRS_ROUTELOC1_CH7LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC7 (_PRS_ROUTELOC1_CH7LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC8 (_PRS_ROUTELOC1_CH7LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC9 (_PRS_ROUTELOC1_CH7LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC10 (_PRS_ROUTELOC1_CH7LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x07071F0FUL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0xFUL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC3 (_PRS_ROUTELOC2_CH8LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC4 (_PRS_ROUTELOC2_CH8LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC5 (_PRS_ROUTELOC2_CH8LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC6 (_PRS_ROUTELOC2_CH8LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC7 (_PRS_ROUTELOC2_CH8LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC8 (_PRS_ROUTELOC2_CH8LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC9 (_PRS_ROUTELOC2_CH8LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC10 (_PRS_ROUTELOC2_CH8LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x1F00UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC3 (_PRS_ROUTELOC2_CH9LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC4 (_PRS_ROUTELOC2_CH9LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC5 (_PRS_ROUTELOC2_CH9LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC6 (_PRS_ROUTELOC2_CH9LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC7 (_PRS_ROUTELOC2_CH9LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC8 (_PRS_ROUTELOC2_CH9LOC_LOC8 << 8) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC9 (_PRS_ROUTELOC2_CH9LOC_LOC9 << 8) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC10 (_PRS_ROUTELOC2_CH9LOC_LOC10 << 8) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC11 (_PRS_ROUTELOC2_CH9LOC_LOC11 << 8) /**< Shifted mode LOC11 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC12 (_PRS_ROUTELOC2_CH9LOC_LOC12 << 8) /**< Shifted mode LOC12 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC13 (_PRS_ROUTELOC2_CH9LOC_LOC13 << 8) /**< Shifted mode LOC13 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC14 (_PRS_ROUTELOC2_CH9LOC_LOC14 << 8) /**< Shifted mode LOC14 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC15 (_PRS_ROUTELOC2_CH9LOC_LOC15 << 8) /**< Shifted mode LOC15 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC16 (_PRS_ROUTELOC2_CH9LOC_LOC16 << 8) /**< Shifted mode LOC16 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x70000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC3 (_PRS_ROUTELOC2_CH10LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC4 (_PRS_ROUTELOC2_CH10LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC5 (_PRS_ROUTELOC2_CH10LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x7000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC3 (_PRS_ROUTELOC2_CH11LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC4 (_PRS_ROUTELOC2_CH11LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC5 (_PRS_ROUTELOC2_CH11LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000001FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x1EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000002UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000003UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000004UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000005UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000007UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000008UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x00000009UL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000000AUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x0000000BUL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x0000000CUL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000DUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000EUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000FUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x00000010UL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x00000011UL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000012UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000018UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000001AUL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x0000003EUL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x0000003FUL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} End of group EFM32PG12B_PRS */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs_ch.h new file mode 100644 index 00000000000..59bdce89ab2 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs_ch.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efm32pg12b_prs_ch.h + * @brief EFM32PG12B_PRS_CH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief PRS_CH EFM32PG12B PRS CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Channel Control Register */ +} PRS_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs_signals.h new file mode 100644 index 00000000000..38f4b3dca24 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs_signals.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efm32pg12b_prs_signals.h + * @brief EFM32PG12B_PRS_SIGNALS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @addtogroup EFM32PG12B_PRS_Signals + * @{ + * @brief PRS Signal names + *****************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_ACMP0_OUT ((3 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((5 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((5 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_LESENSE_SCANRES0 ((7 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((7 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((7 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((7 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((7 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((7 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((7 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((7 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((8 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((8 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((8 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((8 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((8 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((8 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((8 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((8 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((9 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((9 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((9 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((9 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((10 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_RTCC_CCV0 ((11 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((11 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((11 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((12 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((12 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((12 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((12 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((12 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((12 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((12 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((12 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((13 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((13 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((13 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((13 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((13 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((13 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((13 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((13 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((14 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((14 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((15 << 8) + 0) /**< PRS PCNT0 Triggered compare match */ +#define PRS_PCNT0_UFOF ((15 << 8) + 1) /**< PRS PCNT0 Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((15 << 8) + 2) /**< PRS PCNT0 Counter direction */ +#define PRS_PCNT1_TCC ((16 << 8) + 0) /**< PRS PCNT1 Triggered compare match */ +#define PRS_PCNT1_UFOF ((16 << 8) + 1) /**< PRS PCNT1 Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((16 << 8) + 2) /**< PRS PCNT1 Counter direction */ +#define PRS_PCNT2_TCC ((17 << 8) + 0) /**< PRS PCNT2 Triggered compare match */ +#define PRS_PCNT2_UFOF ((17 << 8) + 1) /**< PRS PCNT2 Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((17 << 8) + 2) /**< PRS PCNT2 Counter direction */ +#define PRS_CMU_CLKOUT0 ((18 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((18 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_VDAC0_CH0 ((24 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((24 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((24 << 8) + 2) /**< PRS OPA0 warmedup or outputvalid based on OPA0PRSOUTMODE mode in OPACTRL. */ +#define PRS_VDAC0_OPA1 ((24 << 8) + 3) /**< PRS OPA1 warmedup or outputvalid based on OPA1PRSOUTMODE mode in OPACTRL. */ +#define PRS_VDAC0_OPA2 ((24 << 8) + 4) /**< PRS OPA2 warmedup or outputvalid based on OPA2PRSOUTMODE mode in OPACTRL. */ +#define PRS_CRYOTIMER_PERIOD ((26 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS USART 0 IRDA out */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS USART 0 TX complete */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS USART 0 RX Data Valid */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS USART 0 RTS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS USART 0 TX */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS USART 0 CS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS USART 1 TX complete */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS USART 1 RX Data Valid */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS USART 1 RTS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS USART 1 TX */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS USART 1 CS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS USART 2 TX complete */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS USART 2 RX Data Valid */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS USART 2 RTS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS USART 2 TX */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS USART 2 CS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS USART 3 TX complete */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS USART 3 RX Data Valid */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS USART 3 RTS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS USART 3 TX */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS USART 3 CS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS Timer 0 Underflow */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS Timer 0 Overflow */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS Timer 1 Underflow */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS Timer 1 Overflow */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */ +#define PRS_WTIMER0_UF ((62 << 8) + 0) /**< PRS Timer 2 Underflow */ +#define PRS_WTIMER0_OF ((62 << 8) + 1) /**< PRS Timer 2 Overflow */ +#define PRS_WTIMER0_CC0 ((62 << 8) + 2) /**< PRS Timer 2 Compare/Capture 0 */ +#define PRS_WTIMER0_CC1 ((62 << 8) + 3) /**< PRS Timer 2 Compare/Capture 1 */ +#define PRS_WTIMER0_CC2 ((62 << 8) + 4) /**< PRS Timer 2 Compare/Capture 2 */ +#define PRS_WTIMER1_UF ((63 << 8) + 0) /**< PRS Timer 3 Underflow */ +#define PRS_WTIMER1_OF ((63 << 8) + 1) /**< PRS Timer 3 Overflow */ +#define PRS_WTIMER1_CC0 ((63 << 8) + 2) /**< PRS Timer 3 Compare/Capture 0 */ +#define PRS_WTIMER1_CC1 ((63 << 8) + 3) /**< PRS Timer 3 Compare/Capture 1 */ +#define PRS_WTIMER1_CC2 ((63 << 8) + 4) /**< PRS Timer 3 Compare/Capture 2 */ +#define PRS_WTIMER1_CC3 ((63 << 8) + 5) /**< PRS Timer 3 Compare/Capture 3 */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ + +/** @} End of group EFM32PG12B_PRS */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rmu.h new file mode 100644 index 00000000000..c7e01b16ff0 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rmu.h @@ -0,0 +1,191 @@ +/**************************************************************************//** + * @file efm32pg12b_rmu.h + * @brief EFM32PG12B_RMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_RMU + * @{ + * @brief EFM32PG12B_RMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t RSTCAUSE; /**< Reset Cause Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t RST; /**< Reset Control Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ +} RMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_RMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for RMU CTRL */ +#define _RMU_CTRL_RESETVALUE 0x00004204UL /**< Default value for RMU_CTRL */ +#define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */ +#define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */ +#define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */ +#define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */ +#define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */ +#define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */ +#define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */ +#define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */ +#define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */ +#define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */ +#define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */ + +/* Bit fields for RMU RSTCAUSE */ +#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */ +#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */ +#define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */ +#define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */ +#define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */ +#define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */ +#define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */ +#define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */ +#define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */ +#define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */ +#define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */ +#define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */ +#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */ +#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */ +#define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */ +#define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ + +/* Bit fields for RMU CMD */ +#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */ +#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */ +#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */ +#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */ +#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */ + +/* Bit fields for RMU RST */ +#define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */ +#define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */ + +/* Bit fields for RMU LOCK */ +#define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */ +#define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */ +#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */ +#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */ + +/** @} End of group EFM32PG12B_RMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_romtable.h new file mode 100644 index 00000000000..6c1c2920e5a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_romtable.h @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file efm32pg12b_romtable.h + * @brief EFM32PG12B_ROMTABLE register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_ROMTABLE + * @{ + * @brief Chip Information, Revision numbers + *****************************************************************************/ +typedef struct +{ + __IM uint32_t PID4; /**< JEP_106_BANK */ + __IM uint32_t PID5; /**< Unused */ + __IM uint32_t PID6; /**< Unused */ + __IM uint32_t PID7; /**< Unused */ + __IM uint32_t PID0; /**< Chip family LSB, chip major revision */ + __IM uint32_t PID1; /**< JEP_106_NO, Chip family MSB */ + __IM uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */ + __IM uint32_t PID3; /**< Chip minor rev LSB */ + __IM uint32_t CID0; /**< Unused */ +} ROMTABLE_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_ROMTABLE_BitFields + * @{ + *****************************************************************************/ +/* Bit fields for EFM32PG12B_ROMTABLE */ +#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */ +#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */ +#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */ +#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */ +#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */ + +/** @} End of group EFM32PG12B_ROMTABLE */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc.h new file mode 100644 index 00000000000..9b2746102a4 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc.h @@ -0,0 +1,695 @@ +/**************************************************************************//** + * @file efm32pg12b_rtcc.h + * @brief EFM32PG12B_RTCC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_RTCC + * @{ + * @brief EFM32PG12B_RTCC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */ + __IOM uint32_t TIME; /**< Time of day register */ + __IOM uint32_t DATE; /**< Date register */ + __IM uint32_t IF; /**< RTCC Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t POWERDOWN; /**< Retention RAM power-down register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ + + RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */ + + uint32_t RESERVED0[37]; /**< Reserved registers */ + RTCC_RET_TypeDef RET[32]; /**< RetentionReg */ +} RTCC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_RTCC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for RTCC CTRL */ +#define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */ +#define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */ +#define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */ +#define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */ +#define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */ +#define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */ +#define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */ +#define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */ +#define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 top value enable. */ +#define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */ +#define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */ +#define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 top value enable */ +#define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */ +#define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */ +#define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */ +#define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */ +#define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter prescaler mode. */ +#define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */ +#define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */ +#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator failure detection enable */ +#define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */ +#define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */ +#define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main counter mode */ +#define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */ +#define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */ +#define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */ +#define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */ +#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap year correction disabled. */ +#define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */ +#define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */ +#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */ + +/* Bit fields for RTCC PRECNT */ +#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ +#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ +#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ + +/* Bit fields for RTCC CNT */ +#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ +#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ +#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ +#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ + +/* Bit fields for RTCC COMBCNT */ +#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ + +/* Bit fields for RTCC TIME */ +#define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */ +#define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */ +#define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */ +#define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */ +#define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */ +#define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */ +#define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */ +#define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */ +#define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */ +#define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */ +#define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */ +#define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */ +#define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */ +#define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */ +#define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */ + +/* Bit fields for RTCC DATE */ +#define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */ +#define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */ +#define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */ +#define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */ +#define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */ +#define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */ +#define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */ +#define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */ +#define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */ +#define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */ +#define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */ +#define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */ +#define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */ +#define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */ +#define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */ +#define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */ +#define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */ +#define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */ + +/* Bit fields for RTCC IF */ +#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ +#define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */ +#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */ +#define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */ +#define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */ +#define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator failure Interrupt Flag */ +#define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main counter tick */ +#define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute tick */ +#define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour tick */ +#define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day tick */ +#define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of week overflow */ +#define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month tick */ +#define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */ + +/* Bit fields for RTCC IFS */ +#define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */ +#define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */ +#define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */ +#define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */ +#define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */ +#define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */ +#define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */ +#define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */ +#define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */ +#define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */ +#define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */ +#define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */ +#define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */ + +/* Bit fields for RTCC IFC */ +#define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */ +#define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */ +#define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */ +#define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */ +#define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */ +#define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */ +#define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */ +#define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */ +#define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */ +#define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */ +#define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */ +#define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */ +#define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */ + +/* Bit fields for RTCC IEN */ +#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ +#define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */ +#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */ +#define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */ +#define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */ +#define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */ +#define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */ +#define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */ +#define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */ +#define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */ +#define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */ +#define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */ +#define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */ + +/* Bit fields for RTCC STATUS */ +#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ +#define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */ + +/* Bit fields for RTCC CMD */ +#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ +#define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */ +#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS register. */ +#define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */ +#define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */ +#define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ + +/* Bit fields for RTCC SYNCBUSY */ +#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ +#define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */ +#define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */ +#define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */ +#define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ + +/* Bit fields for RTCC POWERDOWN */ +#define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */ +#define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */ +#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */ +#define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */ +#define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */ +#define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */ +#define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */ + +/* Bit fields for RTCC LOCK */ +#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ +#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ + +/* Bit fields for RTCC EM4WUEN */ +#define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */ +#define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */ +#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */ +#define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */ +#define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */ +#define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */ +#define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */ + +/* Bit fields for RTCC CC_CTRL */ +#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */ +#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */ +#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */ +#define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */ +#define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture compare channel comparison base. */ +#define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */ +#define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */ +#define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare selection */ +#define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */ +#define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */ +#define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */ + +/* Bit fields for RTCC CC_CCV */ +#define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */ +#define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */ +#define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */ +#define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */ +#define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */ +#define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */ + +/* Bit fields for RTCC CC_TIME */ +#define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */ +#define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */ +#define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */ +#define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */ +#define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */ +#define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */ +#define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */ +#define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */ +#define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */ +#define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */ +#define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */ +#define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */ +#define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ + +/* Bit fields for RTCC CC_DATE */ +#define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */ +#define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */ +#define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */ +#define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */ +#define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */ +#define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */ +#define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */ +#define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */ +#define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */ +#define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ + +/* Bit fields for RTCC RET_REG */ +#define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */ +#define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */ +#define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */ +#define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */ +#define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */ +#define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */ + +/** @} End of group EFM32PG12B_RTCC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc_cc.h new file mode 100644 index 00000000000..b799cad536c --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc_cc.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efm32pg12b_rtcc_cc.h + * @brief EFM32PG12B_RTCC_CC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief RTCC_CC EFM32PG12B RTCC CC + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t CCV; /**< Capture/Compare Value Register */ + __IOM uint32_t TIME; /**< Capture/Compare Time Register */ + __IOM uint32_t DATE; /**< Capture/Compare Date Register */ +} RTCC_CC_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc_ret.h new file mode 100644 index 00000000000..025cbd11ad0 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc_ret.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efm32pg12b_rtcc_ret.h + * @brief EFM32PG12B_RTCC_RET register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief RTCC_RET EFM32PG12B RTCC RET + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t REG; /**< Retention register */ +} RTCC_RET_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_smu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_smu.h new file mode 100644 index 00000000000..6340d9e2e08 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_smu.h @@ -0,0 +1,400 @@ +/**************************************************************************//** + * @file efm32pg12b_smu.h + * @brief EFM32PG12B_SMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_SMU + * @{ + * @brief EFM32PG12B_SMU Register Declaration + *****************************************************************************/ +typedef struct +{ + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + + uint32_t RESERVED3[14]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_SMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0x3BFF7FA7UL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 2) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 2 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x4UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 5) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 5 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x20UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CryoTimer access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 8) /**< Advanced Encryption Standard Accelerator 0 access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 8 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x100UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO1 (0x1UL << 9) /**< Advanced Encryption Standard Accelerator 1 access control bit */ +#define _SMU_PPUPATD0_CRYPTO1_SHIFT 9 /**< Shift value for SMU_CRYPTO1 */ +#define _SMU_PPUPATD0_CRYPTO1_MASK 0x200UL /**< Bit mask for SMU_CRYPTO1 */ +#define _SMU_PPUPATD0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO1_DEFAULT (_SMU_PPUPATD0_CRYPTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 10) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 10 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x400UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 11) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 11 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x800UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 12) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 13) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 13 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 14) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 14 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x4000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 16) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 16 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 17) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 17 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x20000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 18) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 18 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x40000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 19) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 19 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x80000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 20) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 20 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x100000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 21) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 21 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x200000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 22) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 22 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x400000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 23) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 23 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x800000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 24) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 24 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x1000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 25) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 25 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x2000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT0 (0x1UL << 27) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD0_PCNT0_SHIFT 27 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD0_PCNT0_MASK 0x8000000UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD0_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT0_DEFAULT (_SMU_PPUPATD0_PCNT0_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT1 (0x1UL << 28) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD0_PCNT1_SHIFT 28 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD0_PCNT1_MASK 0x10000000UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD0_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT1_DEFAULT (_SMU_PPUPATD0_PCNT1_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT2 (0x1UL << 29) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD0_PCNT2_SHIFT 29 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD0_PCNT2_MASK 0x20000000UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD0_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT2_DEFAULT (_SMU_PPUPATD0_PCNT2_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x0000FFEEUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 1) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 1 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x2UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 2) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 2 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x4UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 3) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 5) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 5 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x20UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 6) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 6 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x40UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 7) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 7 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x80UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 8 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x100UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 9 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x200UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 10 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x400UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 11 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x800UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 12) /**< Watchdog 0 access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 12 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x1000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 13) /**< Watchdog 1 access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 13 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x2000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 14) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 14 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x4000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 15) /**< Wide Timer 1 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 15 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x8000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000002UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000005UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000007UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000008UL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO1 0x00000009UL /**< Mode CRYPTO1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000AUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000BUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000DUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000EUL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000014UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x00000016UL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x00000017UL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000018UL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x00000019UL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x0000001BUL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x0000001CUL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x0000001DUL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000021UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000022UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000023UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000025UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x00000026UL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000027UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000028UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000029UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x0000002AUL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x0000002BUL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000002CUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000002DUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000002EUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000002FUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO1 (_SMU_PPUFS_PERIPHID_CRYPTO1 << 0) /**< Shifted mode CRYPTO1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ + +/** @} End of group EFM32PG12B_SMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_timer.h new file mode 100644 index 00000000000..5750bf9d408 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_timer.h @@ -0,0 +1,1575 @@ +/**************************************************************************//** + * @file efm32pg12b_timer.h + * @brief EFM32PG12B_TIMER register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_TIMER + * @{ + * @brief EFM32PG12B_TIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + + uint32_t RESERVED2[8]; /**< Reserved registers */ + TIMER_CC_TypeDef CC[4]; /**< Compare/Capture Channel */ + + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTTIME; /**< DTI Time Control Register */ + __IOM uint32_t DTFC; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_TIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _TIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _TIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _TIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV3_DEFAULT (_TIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _TIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _TIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _TIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV3_DEFAULT (_TIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _TIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _TIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _TIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_DEFAULT (_TIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_LOWRISE (_TIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_HIGHFALL (_TIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x00000FF7UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _TIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC3_DEFAULT (_TIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF3_DEFAULT (_TIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IFS */ +#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */ +#define _TIMER_IFS_MASK 0x00000FF7UL /**< Mask for TIMER_IFS */ +#define TIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _TIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_DIRCHG_DEFAULT (_TIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _TIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC3_DEFAULT (_TIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _TIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF3_DEFAULT (_TIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFS */ + +/* Bit fields for TIMER IFC */ +#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */ +#define _TIMER_IFC_MASK 0x00000FF7UL /**< Mask for TIMER_IFC */ +#define TIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _TIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_DIRCHG_DEFAULT (_TIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _TIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC3_DEFAULT (_TIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _TIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF3_DEFAULT (_TIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFC */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x00000FF7UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _TIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC3_DEFAULT (_TIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _TIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF3_DEFAULT (_TIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER ROUTEPEN */ +#define _TIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTEPEN */ +#define _TIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _TIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _TIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _TIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC0PEN_DEFAULT (_TIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _TIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _TIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _TIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC1PEN_DEFAULT (_TIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _TIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _TIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _TIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC2PEN_DEFAULT (_TIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _TIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _TIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _TIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC3PEN_DEFAULT (_TIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _TIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _TIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _TIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _TIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _TIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _TIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ + +/* Bit fields for TIMER ROUTELOC0 */ +#define _TIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _TIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC0 (_TIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_DEFAULT (_TIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC1 (_TIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC2 (_TIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC3 (_TIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC4 (_TIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC5 (_TIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC6 (_TIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC7 (_TIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC8 (_TIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC9 (_TIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC10 (_TIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC11 (_TIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC12 (_TIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC13 (_TIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC14 (_TIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC15 (_TIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC16 (_TIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC17 (_TIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC18 (_TIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC19 (_TIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC20 (_TIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC21 (_TIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC22 (_TIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC23 (_TIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC24 (_TIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC25 (_TIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC26 (_TIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC27 (_TIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC28 (_TIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC29 (_TIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC30 (_TIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC31 (_TIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _TIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC0 (_TIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_DEFAULT (_TIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC1 (_TIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC2 (_TIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC3 (_TIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC4 (_TIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC5 (_TIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC6 (_TIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC7 (_TIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC8 (_TIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC9 (_TIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC10 (_TIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC11 (_TIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC12 (_TIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC13 (_TIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC14 (_TIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC15 (_TIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC16 (_TIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC17 (_TIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC18 (_TIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC19 (_TIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC20 (_TIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC21 (_TIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC22 (_TIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC23 (_TIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC24 (_TIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC25 (_TIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC26 (_TIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC27 (_TIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC28 (_TIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC29 (_TIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC30 (_TIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC31 (_TIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _TIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC0 (_TIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_DEFAULT (_TIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC1 (_TIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC2 (_TIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC3 (_TIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC4 (_TIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC5 (_TIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC6 (_TIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC7 (_TIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC8 (_TIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC9 (_TIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC10 (_TIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC11 (_TIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC12 (_TIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC13 (_TIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC14 (_TIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC15 (_TIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC16 (_TIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC17 (_TIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC18 (_TIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC19 (_TIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC20 (_TIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC21 (_TIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC22 (_TIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC23 (_TIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC24 (_TIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC25 (_TIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC26 (_TIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC27 (_TIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC28 (_TIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC29 (_TIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC30 (_TIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC31 (_TIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _TIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC0 (_TIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_DEFAULT (_TIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC1 (_TIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC2 (_TIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC3 (_TIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC4 (_TIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC5 (_TIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC6 (_TIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC7 (_TIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC8 (_TIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC9 (_TIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC10 (_TIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC11 (_TIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC12 (_TIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC13 (_TIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC14 (_TIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC15 (_TIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC16 (_TIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC17 (_TIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC18 (_TIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC19 (_TIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC20 (_TIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC21 (_TIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC22 (_TIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC23 (_TIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC24 (_TIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC25 (_TIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC26 (_TIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC27 (_TIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC28 (_TIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC29 (_TIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC30 (_TIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC31 (_TIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ + +/* Bit fields for TIMER ROUTELOC2 */ +#define _TIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _TIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC0 (_TIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC1 (_TIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC2 (_TIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC3 (_TIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC4 (_TIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC5 (_TIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC6 (_TIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC7 (_TIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC8 (_TIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC9 (_TIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC10 (_TIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC11 (_TIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC12 (_TIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC13 (_TIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC14 (_TIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC15 (_TIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC16 (_TIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC17 (_TIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC18 (_TIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC19 (_TIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC20 (_TIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC21 (_TIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC22 (_TIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC23 (_TIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC24 (_TIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC25 (_TIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC26 (_TIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC27 (_TIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC28 (_TIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC29 (_TIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC30 (_TIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC31 (_TIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _TIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC0 (_TIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC1 (_TIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC2 (_TIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC3 (_TIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC4 (_TIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC5 (_TIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC6 (_TIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC7 (_TIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC8 (_TIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC9 (_TIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC10 (_TIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC11 (_TIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC12 (_TIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC13 (_TIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC14 (_TIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC15 (_TIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC16 (_TIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC17 (_TIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC18 (_TIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC19 (_TIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC20 (_TIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC21 (_TIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC22 (_TIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC23 (_TIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC24 (_TIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC25 (_TIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC26 (_TIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC27 (_TIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC28 (_TIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC29 (_TIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC30 (_TIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC31 (_TIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _TIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC0 (_TIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC1 (_TIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC2 (_TIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC3 (_TIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC4 (_TIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC5 (_TIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC6 (_TIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC7 (_TIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC8 (_TIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC9 (_TIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC10 (_TIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC11 (_TIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC12 (_TIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC13 (_TIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC14 (_TIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC15 (_TIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC16 (_TIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC17 (_TIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC18 (_TIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC19 (_TIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC20 (_TIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC21 (_TIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC22 (_TIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC23 (_TIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC24 (_TIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC25 (_TIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC26 (_TIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC27 (_TIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC28 (_TIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC29 (_TIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC30 (_TIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC31 (_TIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _TIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_DEFAULT (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_PULSE (_TIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_LEVEL (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _TIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _TIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_CCV */ +#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */ +#define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */ + +/* Bit fields for TIMER CC_CCVP */ +#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */ +#define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */ + +/* Bit fields for TIMER CC_CCVB */ +#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */ +#define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTAR_DEFAULT (_TIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTFATS_DEFAULT (_TIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTTIME */ +#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */ +#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */ + +/* Bit fields for TIMER DTFC */ +#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */ +#define _TIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH8 (_TIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH9 (_TIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH10 (_TIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH11 (_TIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH8 (_TIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH9 (_TIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH10 (_TIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH11 (_TIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} End of group EFM32PG12B_TIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_timer_cc.h new file mode 100644 index 00000000000..aa5c7b26dda --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_timer_cc.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efm32pg12b_timer_cc.h + * @brief EFM32PG12B_TIMER_CC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief TIMER_CC EFM32PG12B TIMER CC + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t CCV; /**< CC Channel Value Register */ + __IM uint32_t CCVP; /**< CC Channel Value Peek Register */ + __IOM uint32_t CCVB; /**< CC Channel Buffer Register */ +} TIMER_CC_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_trng.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_trng.h new file mode 100644 index 00000000000..5a60ff82766 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_trng.h @@ -0,0 +1,279 @@ +/**************************************************************************//** + * @file efm32pg12b_trng.h + * @brief EFM32PG12B_TRNG register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_TRNG + * @{ + * @brief EFM32PG12B_TRNG Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CONTROL; /**< Main Control Register */ + __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */ + __IOM uint32_t KEY0; /**< Key Register 0 */ + __IOM uint32_t KEY1; /**< Key Register 1 */ + __IOM uint32_t KEY2; /**< Key Register 2 */ + __IOM uint32_t KEY3; /**< Key Register 3 */ + __IOM uint32_t TESTDATA; /**< Test Data Register */ + + uint32_t RESERVED1[3]; /**< Reserved for future use **/ + __IOM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */ + uint32_t RESERVED2[50]; /**< Reserved for future use **/ + __IM uint32_t FIFO; /**< FIFO Data */ +} TRNG_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_TRNG_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for TRNG CONTROL */ +#define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */ +#define _TRNG_CONTROL_MASK 0x00003FFDUL /**< Mask for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */ +#define _TRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for TRNG_ENABLE */ +#define _TRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for TRNG_ENABLE */ +#define _TRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for TRNG_CONTROL */ +#define _TRNG_CONTROL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_DEFAULT (_TRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_DISABLED (_TRNG_CONTROL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_ENABLED (_TRNG_CONTROL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN (0x1UL << 2) /**< Test Enable */ +#define _TRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for TRNG_TESTEN */ +#define _TRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for TRNG_TESTEN */ +#define _TRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for TRNG_CONTROL */ +#define _TRNG_CONTROL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_DEFAULT (_TRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_NOISE (_TRNG_CONTROL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_TESTDATA (_TRNG_CONTROL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */ +#define _TRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for TRNG_CONDBYPASS */ +#define _TRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for TRNG_CONDBYPASS */ +#define _TRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt enable for Repetition Count Test failure */ +#define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */ +#define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */ +#define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt enable for Adaptive Proportion Test failure (64-sample window) */ +#define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */ +#define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */ +#define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt enable for Adaptive Proportion Test failure (4096-sample window) */ +#define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */ +#define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */ +#define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt enable for FIFO full */ +#define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */ +#define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */ +#define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FULLIEN_DEFAULT (_TRNG_CONTROL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET (0x1UL << 8) /**< Software Reset */ +#define _TRNG_CONTROL_SOFTRESET_SHIFT 8 /**< Shift value for TRNG_SOFTRESET */ +#define _TRNG_CONTROL_SOFTRESET_MASK 0x100UL /**< Bit mask for TRNG_SOFTRESET */ +#define _TRNG_CONTROL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_DEFAULT (_TRNG_CONTROL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_NORMAL (_TRNG_CONTROL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_RESET (_TRNG_CONTROL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for TRNG_CONTROL */ +#define TRNG_CONTROL_PREIEN (0x1UL << 9) /**< Interrupt enable for AIS31 preliminary noise alarm */ +#define _TRNG_CONTROL_PREIEN_SHIFT 9 /**< Shift value for TRNG_PREIEN */ +#define _TRNG_CONTROL_PREIEN_MASK 0x200UL /**< Bit mask for TRNG_PREIEN */ +#define _TRNG_CONTROL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_PREIEN_DEFAULT (_TRNG_CONTROL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ALMIEN (0x1UL << 10) /**< Interrupt enable for AIS31 noise alarm */ +#define _TRNG_CONTROL_ALMIEN_SHIFT 10 /**< Shift value for TRNG_ALMIEN */ +#define _TRNG_CONTROL_ALMIEN_MASK 0x400UL /**< Bit mask for TRNG_ALMIEN */ +#define _TRNG_CONTROL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ALMIEN_DEFAULT (_TRNG_CONTROL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */ +#define _TRNG_CONTROL_FORCERUN_SHIFT 11 /**< Shift value for TRNG_FORCERUN */ +#define _TRNG_CONTROL_FORCERUN_MASK 0x800UL /**< Bit mask for TRNG_FORCERUN */ +#define _TRNG_CONTROL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_DEFAULT (_TRNG_CONTROL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_NORMAL (_TRNG_CONTROL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_RUN (_TRNG_CONTROL_FORCERUN_RUN << 11) /**< Shifted mode RUN for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */ +#define _TRNG_CONTROL_BYPNIST_SHIFT 12 /**< Shift value for TRNG_BYPNIST */ +#define _TRNG_CONTROL_BYPNIST_MASK 0x1000UL /**< Bit mask for TRNG_BYPNIST */ +#define _TRNG_CONTROL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_DEFAULT (_TRNG_CONTROL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_NORMAL (_TRNG_CONTROL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_BYPASS (_TRNG_CONTROL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */ +#define _TRNG_CONTROL_BYPAIS31_SHIFT 13 /**< Shift value for TRNG_BYPAIS31 */ +#define _TRNG_CONTROL_BYPAIS31_MASK 0x2000UL /**< Bit mask for TRNG_BYPAIS31 */ +#define _TRNG_CONTROL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_DEFAULT (_TRNG_CONTROL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_NORMAL (_TRNG_CONTROL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_BYPASS (_TRNG_CONTROL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for TRNG_CONTROL */ + +/* Bit fields for TRNG FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFOLEVEL_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFOLEVEL_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFOLEVEL */ +#define TRNG_FIFOLEVEL_VALUE_DEFAULT (_TRNG_FIFOLEVEL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFOLEVEL */ + +/* Bit fields for TRNG FIFODEPTH */ +#define _TRNG_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for TRNG_FIFODEPTH */ +#define _TRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFODEPTH */ +#define _TRNG_FIFODEPTH_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFODEPTH_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFODEPTH_VALUE_DEFAULT 0x00000040UL /**< Mode DEFAULT for TRNG_FIFODEPTH */ +#define TRNG_FIFODEPTH_VALUE_DEFAULT (_TRNG_FIFODEPTH_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFODEPTH */ + +/* Bit fields for TRNG KEY0 */ +#define _TRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY0 */ +#define _TRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY0 */ +#define _TRNG_KEY0_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY0_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY0_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY0 */ +#define TRNG_KEY0_VALUE_DEFAULT (_TRNG_KEY0_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY0 */ + +/* Bit fields for TRNG KEY1 */ +#define _TRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY1 */ +#define _TRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY1 */ +#define _TRNG_KEY1_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY1_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY1_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY1 */ +#define TRNG_KEY1_VALUE_DEFAULT (_TRNG_KEY1_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY1 */ + +/* Bit fields for TRNG KEY2 */ +#define _TRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY2 */ +#define _TRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY2 */ +#define _TRNG_KEY2_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY2_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY2_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY2 */ +#define TRNG_KEY2_VALUE_DEFAULT (_TRNG_KEY2_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY2 */ + +/* Bit fields for TRNG KEY3 */ +#define _TRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY3 */ +#define _TRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY3 */ +#define _TRNG_KEY3_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY3_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY3_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY3 */ +#define TRNG_KEY3_VALUE_DEFAULT (_TRNG_KEY3_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY3 */ + +/* Bit fields for TRNG TESTDATA */ +#define _TRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for TRNG_TESTDATA */ +#define _TRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for TRNG_TESTDATA */ +#define _TRNG_TESTDATA_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_TESTDATA */ +#define TRNG_TESTDATA_VALUE_DEFAULT (_TRNG_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_TESTDATA */ + +/* Bit fields for TRNG STATUS */ +#define _TRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for TRNG_STATUS */ +#define _TRNG_STATUS_MASK 0x000003F1UL /**< Mask for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */ +#define _TRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for TRNG_TESTDATABUSY */ +#define _TRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for TRNG_TESTDATABUSY */ +#define _TRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define _TRNG_STATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for TRNG_STATUS */ +#define _TRNG_STATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */ +#define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */ +#define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */ +#define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */ +#define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_REPCOUNTIF_DEFAULT (_TRNG_STATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT64IF (0x1UL << 5) /**< Adaptive Proportion test failure (64-sample window) interrupt status */ +#define _TRNG_STATUS_APT64IF_SHIFT 5 /**< Shift value for TRNG_APT64IF */ +#define _TRNG_STATUS_APT64IF_MASK 0x20UL /**< Bit mask for TRNG_APT64IF */ +#define _TRNG_STATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT64IF_DEFAULT (_TRNG_STATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT4096IF (0x1UL << 6) /**< Adaptive Proportion test failure (4096-sample window) interrupt status */ +#define _TRNG_STATUS_APT4096IF_SHIFT 6 /**< Shift value for TRNG_APT4096IF */ +#define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */ +#define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */ +#define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */ +#define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */ +#define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_FULLIF_DEFAULT (_TRNG_STATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm interrupt status */ +#define _TRNG_STATUS_PREIF_SHIFT 8 /**< Shift value for TRNG_PREIF */ +#define _TRNG_STATUS_PREIF_MASK 0x100UL /**< Bit mask for TRNG_PREIF */ +#define _TRNG_STATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_PREIF_DEFAULT (_TRNG_STATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */ +#define _TRNG_STATUS_ALMIF_SHIFT 9 /**< Shift value for TRNG_ALMIF */ +#define _TRNG_STATUS_ALMIF_MASK 0x200UL /**< Bit mask for TRNG_ALMIF */ +#define _TRNG_STATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_ALMIF_DEFAULT (_TRNG_STATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_STATUS */ + +/* Bit fields for TRNG INITWAITVAL */ +#define _TRNG_INITWAITVAL_RESETVALUE 0x000000FFUL /**< Default value for TRNG_INITWAITVAL */ +#define _TRNG_INITWAITVAL_MASK 0x000000FFUL /**< Mask for TRNG_INITWAITVAL */ +#define _TRNG_INITWAITVAL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_INITWAITVAL_VALUE_MASK 0xFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_INITWAITVAL_VALUE_DEFAULT 0x000000FFUL /**< Mode DEFAULT for TRNG_INITWAITVAL */ +#define TRNG_INITWAITVAL_VALUE_DEFAULT (_TRNG_INITWAITVAL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_INITWAITVAL */ + +/* Bit fields for TRNG FIFO */ +#define _TRNG_FIFO_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFO */ +#define _TRNG_FIFO_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFO */ +#define _TRNG_FIFO_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFO_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */ +#define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */ + +/** @} End of group EFM32PG12B_TRNG */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_usart.h new file mode 100644 index 00000000000..1942df3840a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_usart.h @@ -0,0 +1,1972 @@ +/**************************************************************************//** + * @file efm32pg12b_usart.h + * @brief EFM32PG12B_USART register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_USART + * @{ + * @brief EFM32PG12B_USART Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t INPUT; /**< USART Input Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Used to generate interrupts and various delays */ + __IOM uint32_t TIMECMP1; /**< Used to generate interrupts and various delays */ + __IOM uint32_t TIMECMP2; /**< Used to generate interrupts and various delays */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ +} USART_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_USART_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */ +#define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */ +#define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IFS */ +#define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */ +#define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */ +#define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ +#define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */ +#define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */ +#define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */ +#define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */ +#define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */ +#define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */ +#define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */ +#define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */ +#define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */ +#define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */ +#define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */ +#define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */ +#define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */ +#define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */ +#define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */ + +/* Bit fields for USART IFC */ +#define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */ +#define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */ +#define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ +#define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */ +#define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */ +#define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */ +#define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */ +#define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */ +#define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */ +#define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */ +#define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */ +#define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */ +#define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */ +#define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */ +#define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */ +#define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */ +#define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */ +#define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ +#define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ +#define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ +#define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */ +#define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */ +#define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */ + +/* Bit fields for USART INPUT */ +#define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */ +#define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ +#define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */ +#define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */ +#define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */ +#define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */ +#define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */ +#define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */ +#define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */ +#define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ + +/* Bit fields for USART ROUTEPEN */ +#define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */ +#define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ +#define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ +#define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ +#define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ +#define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ +#define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ +#define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */ +#define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ +#define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ +#define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ +#define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ +#define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ +#define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */ +#define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */ +#define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */ +#define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */ +#define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */ +#define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */ +#define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ + +/* Bit fields for USART ROUTELOC0 */ +#define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */ +#define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */ +#define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */ +#define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */ +#define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */ +#define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */ +#define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */ +#define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */ +#define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ + +/* Bit fields for USART ROUTELOC1 */ +#define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */ +#define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */ +#define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */ +#define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */ +#define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ + +/** @} End of group EFM32PG12B_USART */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_vdac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_vdac.h new file mode 100644 index 00000000000..a75ff395733 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_vdac.h @@ -0,0 +1,1539 @@ +/**************************************************************************//** + * @file efm32pg12b_vdac.h + * @brief EFM32PG12B_VDAC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_VDAC + * @{ + * @brief EFM32PG12B_VDAC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */ + __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */ + __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */ + __IOM uint32_t COMBDATA; /**< Combined Data Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + + uint32_t RESERVED0[27]; /**< Reserved registers */ + VDAC_OPA_TypeDef OPA[3]; /**< OPA Registers */ +} VDAC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_VDAC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for VDAC CTRL */ +#define _VDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CTRL */ +#define _VDAC_CTRL_MASK 0x937F0771UL /**< Mask for VDAC_CTRL */ +#define VDAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */ +#define _VDAC_CTRL_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ +#define _VDAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ +#define _VDAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_DIFF_DEFAULT (_VDAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_SINEMODE (0x1UL << 4) /**< Sine Mode */ +#define _VDAC_CTRL_SINEMODE_SHIFT 4 /**< Shift value for VDAC_SINEMODE */ +#define _VDAC_CTRL_SINEMODE_MASK 0x10UL /**< Bit mask for VDAC_SINEMODE */ +#define _VDAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_SINEMODE_DEFAULT (_VDAC_CTRL_SINEMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_OUTENPRS (0x1UL << 5) /**< PRS Controlled Output Enable */ +#define _VDAC_CTRL_OUTENPRS_SHIFT 5 /**< Shift value for VDAC_OUTENPRS */ +#define _VDAC_CTRL_OUTENPRS_MASK 0x20UL /**< Bit mask for VDAC_OUTENPRS */ +#define _VDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_OUTENPRS_DEFAULT (_VDAC_CTRL_OUTENPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_CH0PRESCRST (0x1UL << 6) /**< Channel 0 Start Reset Prescaler */ +#define _VDAC_CTRL_CH0PRESCRST_SHIFT 6 /**< Shift value for VDAC_CH0PRESCRST */ +#define _VDAC_CTRL_CH0PRESCRST_MASK 0x40UL /**< Bit mask for VDAC_CH0PRESCRST */ +#define _VDAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_CH0PRESCRST_DEFAULT (_VDAC_CTRL_CH0PRESCRST_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for VDAC_REFSEL */ +#define _VDAC_CTRL_REFSEL_MASK 0x700UL /**< Bit mask for VDAC_REFSEL */ +#define _VDAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_1V25LN 0x00000000UL /**< Mode 1V25LN for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_2V5LN 0x00000001UL /**< Mode 2V5LN for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_1V25 0x00000002UL /**< Mode 1V25 for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_2V5 0x00000003UL /**< Mode 2V5 for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_VDD 0x00000004UL /**< Mode VDD for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_EXT 0x00000006UL /**< Mode EXT for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_DEFAULT (_VDAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_1V25LN (_VDAC_CTRL_REFSEL_1V25LN << 8) /**< Shifted mode 1V25LN for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_2V5LN (_VDAC_CTRL_REFSEL_2V5LN << 8) /**< Shifted mode 2V5LN for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_1V25 (_VDAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_2V5 (_VDAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_VDD (_VDAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_EXT (_VDAC_CTRL_REFSEL_EXT << 8) /**< Shifted mode EXT for VDAC_CTRL */ +#define _VDAC_CTRL_PRESC_SHIFT 16 /**< Shift value for VDAC_PRESC */ +#define _VDAC_CTRL_PRESC_MASK 0x7F0000UL /**< Bit mask for VDAC_PRESC */ +#define _VDAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for VDAC_CTRL */ +#define VDAC_CTRL_PRESC_DEFAULT (_VDAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_PRESC_NODIVISION (_VDAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_SHIFT 24 /**< Shift value for VDAC_REFRESHPERIOD */ +#define _VDAC_CTRL_REFRESHPERIOD_MASK 0x3000000UL /**< Bit mask for VDAC_REFRESHPERIOD */ +#define _VDAC_CTRL_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_8CYCLES 0x00000000UL /**< Mode 8CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_16CYCLES 0x00000001UL /**< Mode 16CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_32CYCLES 0x00000002UL /**< Mode 32CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_64CYCLES 0x00000003UL /**< Mode 64CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_DEFAULT (_VDAC_CTRL_REFRESHPERIOD_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_8CYCLES (_VDAC_CTRL_REFRESHPERIOD_8CYCLES << 24) /**< Shifted mode 8CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_16CYCLES (_VDAC_CTRL_REFRESHPERIOD_16CYCLES << 24) /**< Shifted mode 16CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_32CYCLES (_VDAC_CTRL_REFRESHPERIOD_32CYCLES << 24) /**< Shifted mode 32CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_64CYCLES (_VDAC_CTRL_REFRESHPERIOD_64CYCLES << 24) /**< Shifted mode 64CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE (0x1UL << 28) /**< Warm-up Mode */ +#define _VDAC_CTRL_WARMUPMODE_SHIFT 28 /**< Shift value for VDAC_WARMUPMODE */ +#define _VDAC_CTRL_WARMUPMODE_MASK 0x10000000UL /**< Bit mask for VDAC_WARMUPMODE */ +#define _VDAC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CTRL */ +#define _VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_DEFAULT (_VDAC_CTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_NORMAL (_VDAC_CTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY (_VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY << 28) /**< Shifted mode KEEPINSTANDBY for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE (0x1UL << 31) /**< Clock Mode */ +#define _VDAC_CTRL_DACCLKMODE_SHIFT 31 /**< Shift value for VDAC_DACCLKMODE */ +#define _VDAC_CTRL_DACCLKMODE_MASK 0x80000000UL /**< Bit mask for VDAC_DACCLKMODE */ +#define _VDAC_CTRL_DACCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_DACCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for VDAC_CTRL */ +#define _VDAC_CTRL_DACCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_DEFAULT (_VDAC_CTRL_DACCLKMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_SYNC (_VDAC_CTRL_DACCLKMODE_SYNC << 31) /**< Shifted mode SYNC for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_ASYNC (_VDAC_CTRL_DACCLKMODE_ASYNC << 31) /**< Shifted mode ASYNC for VDAC_CTRL */ + +/* Bit fields for VDAC STATUS */ +#define _VDAC_STATUS_RESETVALUE 0x0000000CUL /**< Default value for VDAC_STATUS */ +#define _VDAC_STATUS_MASK 0x7777003FUL /**< Mask for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ +#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ +#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0BL (0x1UL << 2) /**< Channel 0 Buffer Level */ +#define _VDAC_STATUS_CH0BL_SHIFT 2 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_STATUS_CH0BL_MASK 0x4UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_STATUS_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0BL_DEFAULT (_VDAC_STATUS_CH0BL_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1BL (0x1UL << 3) /**< Channel 1 Buffer Level */ +#define _VDAC_STATUS_CH1BL_SHIFT 3 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_STATUS_CH1BL_MASK 0x8UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_STATUS_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1BL_DEFAULT (_VDAC_STATUS_CH1BL_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warm */ +#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warm */ +#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0ENS (0x1UL << 20) /**< OPA0 Enabled Status */ +#define _VDAC_STATUS_OPA0ENS_SHIFT 20 /**< Shift value for VDAC_OPA0ENS */ +#define _VDAC_STATUS_OPA0ENS_MASK 0x100000UL /**< Bit mask for VDAC_OPA0ENS */ +#define _VDAC_STATUS_OPA0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0ENS_DEFAULT (_VDAC_STATUS_OPA0ENS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1ENS (0x1UL << 21) /**< OPA1 Enabled Status */ +#define _VDAC_STATUS_OPA1ENS_SHIFT 21 /**< Shift value for VDAC_OPA1ENS */ +#define _VDAC_STATUS_OPA1ENS_MASK 0x200000UL /**< Bit mask for VDAC_OPA1ENS */ +#define _VDAC_STATUS_OPA1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1ENS_DEFAULT (_VDAC_STATUS_OPA1ENS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2ENS (0x1UL << 22) /**< OPA2 Enabled Status */ +#define _VDAC_STATUS_OPA2ENS_SHIFT 22 /**< Shift value for VDAC_OPA2ENS */ +#define _VDAC_STATUS_OPA2ENS_MASK 0x400000UL /**< Bit mask for VDAC_OPA2ENS */ +#define _VDAC_STATUS_OPA2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2ENS_DEFAULT (_VDAC_STATUS_OPA2ENS_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0WARM (0x1UL << 24) /**< OPA0 Warm Status */ +#define _VDAC_STATUS_OPA0WARM_SHIFT 24 /**< Shift value for VDAC_OPA0WARM */ +#define _VDAC_STATUS_OPA0WARM_MASK 0x1000000UL /**< Bit mask for VDAC_OPA0WARM */ +#define _VDAC_STATUS_OPA0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0WARM_DEFAULT (_VDAC_STATUS_OPA0WARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1WARM (0x1UL << 25) /**< OPA1 Warm Status */ +#define _VDAC_STATUS_OPA1WARM_SHIFT 25 /**< Shift value for VDAC_OPA1WARM */ +#define _VDAC_STATUS_OPA1WARM_MASK 0x2000000UL /**< Bit mask for VDAC_OPA1WARM */ +#define _VDAC_STATUS_OPA1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1WARM_DEFAULT (_VDAC_STATUS_OPA1WARM_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2WARM (0x1UL << 26) /**< OPA2 Warm Status */ +#define _VDAC_STATUS_OPA2WARM_SHIFT 26 /**< Shift value for VDAC_OPA2WARM */ +#define _VDAC_STATUS_OPA2WARM_MASK 0x4000000UL /**< Bit mask for VDAC_OPA2WARM */ +#define _VDAC_STATUS_OPA2WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2WARM_DEFAULT (_VDAC_STATUS_OPA2WARM_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Status */ +#define _VDAC_STATUS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_STATUS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_STATUS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0OUTVALID_DEFAULT (_VDAC_STATUS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Status */ +#define _VDAC_STATUS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_STATUS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_STATUS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1OUTVALID_DEFAULT (_VDAC_STATUS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2OUTVALID (0x1UL << 30) /**< OPA2 Output Valid Status */ +#define _VDAC_STATUS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_STATUS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_STATUS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2OUTVALID_DEFAULT (_VDAC_STATUS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ + +/* Bit fields for VDAC CH0CTRL */ +#define _VDAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ +#define _VDAC_CH0CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH0CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH0CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_DEFAULT (_VDAC_CH0CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_CONTINUOUS (_VDAC_CH0CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH0CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH0CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH0CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_DEFAULT (_VDAC_CH0CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SW (_VDAC_CH0CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_PRS (_VDAC_CH0CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_REFRESH (_VDAC_CH0CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SWPRS (_VDAC_CH0CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SWREFRESH (_VDAC_CH0CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_LESENSE (_VDAC_CH0CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSASYNC (0x1UL << 8) /**< Channel 0 PRS Asynchronous Enable */ +#define _VDAC_CH0CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ +#define _VDAC_CH0CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ +#define _VDAC_CH0CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSASYNC_DEFAULT (_VDAC_CH0CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ +#define _VDAC_CH0CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ +#define _VDAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_DEFAULT (_VDAC_CH0CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH0 (_VDAC_CH0CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH1 (_VDAC_CH0CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH2 (_VDAC_CH0CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH3 (_VDAC_CH0CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH4 (_VDAC_CH0CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH5 (_VDAC_CH0CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH6 (_VDAC_CH0CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH7 (_VDAC_CH0CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH8 (_VDAC_CH0CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH9 (_VDAC_CH0CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH10 (_VDAC_CH0CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH11 (_VDAC_CH0CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH0CTRL */ + +/* Bit fields for VDAC CH1CTRL */ +#define _VDAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ +#define _VDAC_CH1CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH1CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH1CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_DEFAULT (_VDAC_CH1CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_CONTINUOUS (_VDAC_CH1CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH1CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH1CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH1CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_DEFAULT (_VDAC_CH1CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SW (_VDAC_CH1CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_PRS (_VDAC_CH1CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_REFRESH (_VDAC_CH1CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SWPRS (_VDAC_CH1CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SWREFRESH (_VDAC_CH1CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_LESENSE (_VDAC_CH1CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSASYNC (0x1UL << 8) /**< Channel 1 PRS Asynchronous Enable */ +#define _VDAC_CH1CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ +#define _VDAC_CH1CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ +#define _VDAC_CH1CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSASYNC_DEFAULT (_VDAC_CH1CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ +#define _VDAC_CH1CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ +#define _VDAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_DEFAULT (_VDAC_CH1CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH0 (_VDAC_CH1CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH1 (_VDAC_CH1CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH2 (_VDAC_CH1CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH3 (_VDAC_CH1CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH4 (_VDAC_CH1CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH5 (_VDAC_CH1CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH6 (_VDAC_CH1CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH7 (_VDAC_CH1CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH8 (_VDAC_CH1CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH9 (_VDAC_CH1CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH10 (_VDAC_CH1CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH11 (_VDAC_CH1CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH1CTRL */ + +/* Bit fields for VDAC CMD */ +#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ +#define _VDAC_CMD_MASK 0x003F000FUL /**< Mask for VDAC_CMD */ +#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ +#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ +#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN (0x1UL << 2) /**< DAC Channel 1 Enable */ +#define _VDAC_CMD_CH1EN_SHIFT 2 /**< Shift value for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_MASK 0x4UL /**< Bit mask for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS (0x1UL << 3) /**< DAC Channel 1 Disable */ +#define _VDAC_CMD_CH1DIS_SHIFT 3 /**< Shift value for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_MASK 0x8UL /**< Bit mask for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0EN (0x1UL << 16) /**< OPA0 Enable */ +#define _VDAC_CMD_OPA0EN_SHIFT 16 /**< Shift value for VDAC_OPA0EN */ +#define _VDAC_CMD_OPA0EN_MASK 0x10000UL /**< Bit mask for VDAC_OPA0EN */ +#define _VDAC_CMD_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0EN_DEFAULT (_VDAC_CMD_OPA0EN_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0DIS (0x1UL << 17) /**< OPA0 Disable */ +#define _VDAC_CMD_OPA0DIS_SHIFT 17 /**< Shift value for VDAC_OPA0DIS */ +#define _VDAC_CMD_OPA0DIS_MASK 0x20000UL /**< Bit mask for VDAC_OPA0DIS */ +#define _VDAC_CMD_OPA0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0DIS_DEFAULT (_VDAC_CMD_OPA0DIS_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1EN (0x1UL << 18) /**< OPA1 Enable */ +#define _VDAC_CMD_OPA1EN_SHIFT 18 /**< Shift value for VDAC_OPA1EN */ +#define _VDAC_CMD_OPA1EN_MASK 0x40000UL /**< Bit mask for VDAC_OPA1EN */ +#define _VDAC_CMD_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1EN_DEFAULT (_VDAC_CMD_OPA1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1DIS (0x1UL << 19) /**< OPA1 Disable */ +#define _VDAC_CMD_OPA1DIS_SHIFT 19 /**< Shift value for VDAC_OPA1DIS */ +#define _VDAC_CMD_OPA1DIS_MASK 0x80000UL /**< Bit mask for VDAC_OPA1DIS */ +#define _VDAC_CMD_OPA1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1DIS_DEFAULT (_VDAC_CMD_OPA1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2EN (0x1UL << 20) /**< OPA2 Enable */ +#define _VDAC_CMD_OPA2EN_SHIFT 20 /**< Shift value for VDAC_OPA2EN */ +#define _VDAC_CMD_OPA2EN_MASK 0x100000UL /**< Bit mask for VDAC_OPA2EN */ +#define _VDAC_CMD_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2EN_DEFAULT (_VDAC_CMD_OPA2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2DIS (0x1UL << 21) /**< OPA2 Disable */ +#define _VDAC_CMD_OPA2DIS_SHIFT 21 /**< Shift value for VDAC_OPA2DIS */ +#define _VDAC_CMD_OPA2DIS_MASK 0x200000UL /**< Bit mask for VDAC_OPA2DIS */ +#define _VDAC_CMD_OPA2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2DIS_DEFAULT (_VDAC_CMD_OPA2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_CMD */ + +/* Bit fields for VDAC IF */ +#define _VDAC_IF_RESETVALUE 0x000000C0UL /**< Default value for VDAC_IF */ +#define _VDAC_IF_MASK 0x707780FFUL /**< Mask for VDAC_IF */ +#define VDAC_IF_CH0CD (0x1UL << 0) /**< Channel 0 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD (0x1UL << 1) /**< Channel 1 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF (0x1UL << 2) /**< Channel 0 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF (0x1UL << 3) /**< Channel 1 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0BL (0x1UL << 6) /**< Channel 0 Buffer Level Interrupt Flag */ +#define _VDAC_IF_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_IF_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_IF_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0BL_DEFAULT (_VDAC_IF_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1BL (0x1UL << 7) /**< Channel 1 Buffer Level Interrupt Flag */ +#define _VDAC_IF_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_IF_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_IF_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1BL_DEFAULT (_VDAC_IF_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_EM23ERR (0x1UL << 15) /**< EM2/3 Entry Error Flag */ +#define _VDAC_IF_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IF_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_EM23ERR_DEFAULT (_VDAC_IF_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IF_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IF_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0APORTCONFLICT_DEFAULT (_VDAC_IF_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IF_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IF_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1APORTCONFLICT_DEFAULT (_VDAC_IF_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IF_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IF_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2APORTCONFLICT_DEFAULT (_VDAC_IF_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IF_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IF_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IF_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IF_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IF_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IF_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IF_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IF_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0OUTVALID_DEFAULT (_VDAC_IF_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IF_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IF_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1OUTVALID_DEFAULT (_VDAC_IF_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2OUTVALID (0x1UL << 30) /**< OPA3 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IF_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IF_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2OUTVALID_DEFAULT (_VDAC_IF_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IF */ + +/* Bit fields for VDAC IFS */ +#define _VDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFS */ +#define _VDAC_IFS_MASK 0x7077803FUL /**< Mask for VDAC_IFS */ +#define VDAC_IFS_CH0CD (0x1UL << 0) /**< Set CH0CD Interrupt Flag */ +#define _VDAC_IFS_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IFS_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IFS_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0CD_DEFAULT (_VDAC_IFS_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1CD (0x1UL << 1) /**< Set CH1CD Interrupt Flag */ +#define _VDAC_IFS_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IFS_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IFS_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1CD_DEFAULT (_VDAC_IFS_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0OF (0x1UL << 2) /**< Set CH0OF Interrupt Flag */ +#define _VDAC_IFS_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IFS_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IFS_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0OF_DEFAULT (_VDAC_IFS_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1OF (0x1UL << 3) /**< Set CH1OF Interrupt Flag */ +#define _VDAC_IFS_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IFS_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IFS_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1OF_DEFAULT (_VDAC_IFS_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0UF (0x1UL << 4) /**< Set CH0UF Interrupt Flag */ +#define _VDAC_IFS_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0UF_DEFAULT (_VDAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1UF (0x1UL << 5) /**< Set CH1UF Interrupt Flag */ +#define _VDAC_IFS_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1UF_DEFAULT (_VDAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_EM23ERR (0x1UL << 15) /**< Set EM23ERR Interrupt Flag */ +#define _VDAC_IFS_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IFS_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_EM23ERR_DEFAULT (_VDAC_IFS_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0APORTCONFLICT (0x1UL << 16) /**< Set OPA0APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1APORTCONFLICT (0x1UL << 17) /**< Set OPA1APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2APORTCONFLICT (0x1UL << 18) /**< Set OPA2APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0PRSTIMEDERR (0x1UL << 20) /**< Set OPA0PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1PRSTIMEDERR (0x1UL << 21) /**< Set OPA1PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2PRSTIMEDERR (0x1UL << 22) /**< Set OPA2PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0OUTVALID (0x1UL << 28) /**< Set OPA0OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IFS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IFS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0OUTVALID_DEFAULT (_VDAC_IFS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1OUTVALID (0x1UL << 29) /**< Set OPA1OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IFS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IFS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1OUTVALID_DEFAULT (_VDAC_IFS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2OUTVALID (0x1UL << 30) /**< Set OPA2OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IFS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IFS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2OUTVALID_DEFAULT (_VDAC_IFS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFS */ + +/* Bit fields for VDAC IFC */ +#define _VDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFC */ +#define _VDAC_IFC_MASK 0x7077803FUL /**< Mask for VDAC_IFC */ +#define VDAC_IFC_CH0CD (0x1UL << 0) /**< Clear CH0CD Interrupt Flag */ +#define _VDAC_IFC_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IFC_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IFC_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0CD_DEFAULT (_VDAC_IFC_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1CD (0x1UL << 1) /**< Clear CH1CD Interrupt Flag */ +#define _VDAC_IFC_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IFC_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IFC_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1CD_DEFAULT (_VDAC_IFC_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0OF (0x1UL << 2) /**< Clear CH0OF Interrupt Flag */ +#define _VDAC_IFC_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IFC_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IFC_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0OF_DEFAULT (_VDAC_IFC_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1OF (0x1UL << 3) /**< Clear CH1OF Interrupt Flag */ +#define _VDAC_IFC_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IFC_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IFC_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1OF_DEFAULT (_VDAC_IFC_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0UF (0x1UL << 4) /**< Clear CH0UF Interrupt Flag */ +#define _VDAC_IFC_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0UF_DEFAULT (_VDAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1UF (0x1UL << 5) /**< Clear CH1UF Interrupt Flag */ +#define _VDAC_IFC_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1UF_DEFAULT (_VDAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_EM23ERR (0x1UL << 15) /**< Clear EM23ERR Interrupt Flag */ +#define _VDAC_IFC_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IFC_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_EM23ERR_DEFAULT (_VDAC_IFC_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0APORTCONFLICT (0x1UL << 16) /**< Clear OPA0APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFC_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFC_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1APORTCONFLICT (0x1UL << 17) /**< Clear OPA1APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFC_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFC_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2APORTCONFLICT (0x1UL << 18) /**< Clear OPA2APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFC_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFC_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0PRSTIMEDERR (0x1UL << 20) /**< Clear OPA0PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1PRSTIMEDERR (0x1UL << 21) /**< Clear OPA1PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2PRSTIMEDERR (0x1UL << 22) /**< Clear OPA2PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0OUTVALID (0x1UL << 28) /**< Clear OPA0OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IFC_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IFC_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0OUTVALID_DEFAULT (_VDAC_IFC_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1OUTVALID (0x1UL << 29) /**< Clear OPA1OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IFC_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IFC_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1OUTVALID_DEFAULT (_VDAC_IFC_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2OUTVALID (0x1UL << 30) /**< Clear OPA2OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IFC_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IFC_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2OUTVALID_DEFAULT (_VDAC_IFC_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFC */ + +/* Bit fields for VDAC IEN */ +#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ +#define _VDAC_IEN_MASK 0x707780FFUL /**< Mask for VDAC_IEN */ +#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0CD Interrupt Enable */ +#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1CD Interrupt Enable */ +#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF (0x1UL << 2) /**< CH0OF Interrupt Enable */ +#define _VDAC_IEN_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF (0x1UL << 3) /**< CH1OF Interrupt Enable */ +#define _VDAC_IEN_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF (0x1UL << 4) /**< CH0UF Interrupt Enable */ +#define _VDAC_IEN_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF (0x1UL << 5) /**< CH1UF Interrupt Enable */ +#define _VDAC_IEN_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0BL (0x1UL << 6) /**< CH0BL Interrupt Enable */ +#define _VDAC_IEN_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_IEN_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_IEN_CH0BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0BL_DEFAULT (_VDAC_IEN_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1BL (0x1UL << 7) /**< CH1BL Interrupt Enable */ +#define _VDAC_IEN_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_IEN_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_IEN_CH1BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1BL_DEFAULT (_VDAC_IEN_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_EM23ERR (0x1UL << 15) /**< EM23ERR Interrupt Enable */ +#define _VDAC_IEN_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IEN_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_EM23ERR_DEFAULT (_VDAC_IEN_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IEN_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IEN_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IEN_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IEN_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IEN_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IEN_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0OUTVALID (0x1UL << 28) /**< OPA0OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IEN_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IEN_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0OUTVALID_DEFAULT (_VDAC_IEN_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1OUTVALID (0x1UL << 29) /**< OPA1OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IEN_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IEN_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1OUTVALID_DEFAULT (_VDAC_IEN_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2OUTVALID (0x1UL << 30) /**< OPA2OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IEN_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IEN_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2OUTVALID_DEFAULT (_VDAC_IEN_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IEN */ + +/* Bit fields for VDAC CH0DATA */ +#define _VDAC_CH0DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH0DATA */ +#define _VDAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH0DATA */ +#define _VDAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH0DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH0DATA */ +#define VDAC_CH0DATA_DATA_DEFAULT (_VDAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0DATA */ + +/* Bit fields for VDAC CH1DATA */ +#define _VDAC_CH1DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH1DATA */ +#define _VDAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH1DATA */ +#define _VDAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH1DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH1DATA */ +#define VDAC_CH1DATA_DATA_DEFAULT (_VDAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1DATA */ + +/* Bit fields for VDAC COMBDATA */ +#define _VDAC_COMBDATA_RESETVALUE 0x08000800UL /**< Default value for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for VDAC_CH0DATA */ +#define _VDAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for VDAC_CH0DATA */ +#define _VDAC_COMBDATA_CH0DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ +#define VDAC_COMBDATA_CH0DATA_DEFAULT (_VDAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for VDAC_CH1DATA */ +#define _VDAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for VDAC_CH1DATA */ +#define _VDAC_COMBDATA_CH1DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ +#define VDAC_COMBDATA_CH1DATA_DEFAULT (_VDAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ + +/* Bit fields for VDAC CAL */ +#define _VDAC_CAL_RESETVALUE 0x00082004UL /**< Default value for VDAC_CAL */ +#define _VDAC_CAL_MASK 0x000F3F07UL /**< Mask for VDAC_CAL */ +#define _VDAC_CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for VDAC_OFFSETTRIM */ +#define _VDAC_CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for VDAC_OFFSETTRIM */ +#define _VDAC_CAL_OFFSETTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_OFFSETTRIM_DEFAULT (_VDAC_CAL_OFFSETTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CAL */ +#define _VDAC_CAL_GAINERRTRIM_SHIFT 8 /**< Shift value for VDAC_GAINERRTRIM */ +#define _VDAC_CAL_GAINERRTRIM_MASK 0x3F00UL /**< Bit mask for VDAC_GAINERRTRIM */ +#define _VDAC_CAL_GAINERRTRIM_DEFAULT 0x00000020UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_GAINERRTRIM_DEFAULT (_VDAC_CAL_GAINERRTRIM_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CAL */ +#define _VDAC_CAL_GAINERRTRIMCH1_SHIFT 16 /**< Shift value for VDAC_GAINERRTRIMCH1 */ +#define _VDAC_CAL_GAINERRTRIMCH1_MASK 0xF0000UL /**< Bit mask for VDAC_GAINERRTRIMCH1 */ +#define _VDAC_CAL_GAINERRTRIMCH1_DEFAULT 0x00000008UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_GAINERRTRIMCH1_DEFAULT (_VDAC_CAL_GAINERRTRIMCH1_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CAL */ + +/* Bit fields for VDAC OPA_APORTREQ */ +#define _VDAC_OPA_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTREQ */ +#define _VDAC_OPA_APORTREQ_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XREQ */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XREQ */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YREQ */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YREQ */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XREQ */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XREQ */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YREQ */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YREQ */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XREQ */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XREQ */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YREQ */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YREQ */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XREQ */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XREQ */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YREQ */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YREQ */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ + +/* Bit fields for VDAC OPA_APORTCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ + +/* Bit fields for VDAC OPA_CTRL */ +#define _VDAC_OPA_CTRL_RESETVALUE 0x0000000EUL /**< Default value for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_MASK 0x00313F1FUL /**< Mask for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for VDAC_OPADRIVESTRENGTH */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_MASK 0x3UL /**< Bit mask for VDAC_OPADRIVESTRENGTH */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT (_VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_INCBW (0x1UL << 2) /**< OPAx unity gain bandwidth scale. */ +#define _VDAC_OPA_CTRL_INCBW_SHIFT 2 /**< Shift value for VDAC_OPAINCBW */ +#define _VDAC_OPA_CTRL_INCBW_MASK 0x4UL /**< Bit mask for VDAC_OPAINCBW */ +#define _VDAC_OPA_CTRL_INCBW_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_INCBW_DEFAULT (_VDAC_OPA_CTRL_INCBW_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_HCMDIS (0x1UL << 3) /**< High Common Mode Disable. */ +#define _VDAC_OPA_CTRL_HCMDIS_SHIFT 3 /**< Shift value for VDAC_OPAHCMDIS */ +#define _VDAC_OPA_CTRL_HCMDIS_MASK 0x8UL /**< Bit mask for VDAC_OPAHCMDIS */ +#define _VDAC_OPA_CTRL_HCMDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_HCMDIS_DEFAULT (_VDAC_OPA_CTRL_HCMDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE (0x1UL << 4) /**< Scale OPAx output driving strength. */ +#define _VDAC_OPA_CTRL_OUTSCALE_SHIFT 4 /**< Shift value for VDAC_OPAOUTSCALE */ +#define _VDAC_OPA_CTRL_OUTSCALE_MASK 0x10UL /**< Bit mask for VDAC_OPAOUTSCALE */ +#define _VDAC_OPA_CTRL_OUTSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_OUTSCALE_FULL 0x00000000UL /**< Mode FULL for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_OUTSCALE_HALF 0x00000001UL /**< Mode HALF for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_DEFAULT (_VDAC_OPA_CTRL_OUTSCALE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_FULL (_VDAC_OPA_CTRL_OUTSCALE_FULL << 4) /**< Shifted mode FULL for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_HALF (_VDAC_OPA_CTRL_OUTSCALE_HALF << 4) /**< Shifted mode HALF for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSEN (0x1UL << 8) /**< OPAx PRS Trigger Enable */ +#define _VDAC_OPA_CTRL_PRSEN_SHIFT 8 /**< Shift value for VDAC_OPAPRSEN */ +#define _VDAC_OPA_CTRL_PRSEN_MASK 0x100UL /**< Bit mask for VDAC_OPAPRSEN */ +#define _VDAC_OPA_CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSEN_DEFAULT (_VDAC_OPA_CTRL_PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE (0x1UL << 9) /**< OPAx PRS Trigger Mode */ +#define _VDAC_OPA_CTRL_PRSMODE_SHIFT 9 /**< Shift value for VDAC_OPAPRSMODE */ +#define _VDAC_OPA_CTRL_PRSMODE_MASK 0x200UL /**< Bit mask for VDAC_OPAPRSMODE */ +#define _VDAC_OPA_CTRL_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_DEFAULT (_VDAC_OPA_CTRL_PRSMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_PULSED (_VDAC_OPA_CTRL_PRSMODE_PULSED << 9) /**< Shifted mode PULSED for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_TIMED (_VDAC_OPA_CTRL_PRSMODE_TIMED << 9) /**< Shifted mode TIMED for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_SHIFT 10 /**< Shift value for VDAC_OPAPRSSEL */ +#define _VDAC_OPA_CTRL_PRSSEL_MASK 0x3C00UL /**< Bit mask for VDAC_OPAPRSSEL */ +#define _VDAC_OPA_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_DEFAULT (_VDAC_OPA_CTRL_PRSSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH0 (_VDAC_OPA_CTRL_PRSSEL_PRSCH0 << 10) /**< Shifted mode PRSCH0 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH1 (_VDAC_OPA_CTRL_PRSSEL_PRSCH1 << 10) /**< Shifted mode PRSCH1 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH2 (_VDAC_OPA_CTRL_PRSSEL_PRSCH2 << 10) /**< Shifted mode PRSCH2 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH3 (_VDAC_OPA_CTRL_PRSSEL_PRSCH3 << 10) /**< Shifted mode PRSCH3 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH4 (_VDAC_OPA_CTRL_PRSSEL_PRSCH4 << 10) /**< Shifted mode PRSCH4 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH5 (_VDAC_OPA_CTRL_PRSSEL_PRSCH5 << 10) /**< Shifted mode PRSCH5 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH6 (_VDAC_OPA_CTRL_PRSSEL_PRSCH6 << 10) /**< Shifted mode PRSCH6 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH7 (_VDAC_OPA_CTRL_PRSSEL_PRSCH7 << 10) /**< Shifted mode PRSCH7 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH8 (_VDAC_OPA_CTRL_PRSSEL_PRSCH8 << 10) /**< Shifted mode PRSCH8 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH9 (_VDAC_OPA_CTRL_PRSSEL_PRSCH9 << 10) /**< Shifted mode PRSCH9 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH10 (_VDAC_OPA_CTRL_PRSSEL_PRSCH10 << 10) /**< Shifted mode PRSCH10 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH11 (_VDAC_OPA_CTRL_PRSSEL_PRSCH11 << 10) /**< Shifted mode PRSCH11 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE (0x1UL << 16) /**< OPAx PRS Output Select. */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_SHIFT 16 /**< Shift value for VDAC_OPAPRSOUTMODE */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_MASK 0x10000UL /**< Bit mask for VDAC_OPAPRSOUTMODE */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_WARM 0x00000000UL /**< Mode WARM for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID 0x00000001UL /**< Mode OUTVALID for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT (_VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_WARM (_VDAC_OPA_CTRL_PRSOUTMODE_WARM << 16) /**< Shifted mode WARM for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID (_VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID << 16) /**< Shifted mode OUTVALID for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTXMASTERDIS (0x1UL << 20) /**< APORT Bus Master Disable */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_SHIFT 20 /**< Shift value for VDAC_OPAAPORTXMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_MASK 0x100000UL /**< Bit mask for VDAC_OPAAPORTXMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTYMASTERDIS (0x1UL << 21) /**< APORT Bus Master Disable */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_SHIFT 21 /**< Shift value for VDAC_OPAAPORTYMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_MASK 0x200000UL /**< Bit mask for VDAC_OPAAPORTYMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ + +/* Bit fields for VDAC OPA_TIMER */ +#define _VDAC_OPA_TIMER_RESETVALUE 0x00010700UL /**< Default value for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_MASK 0x03FF7F3FUL /**< Mask for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_STARTUPDLY_SHIFT 0 /**< Shift value for VDAC_OPASTARTUPDLY */ +#define _VDAC_OPA_TIMER_STARTUPDLY_MASK 0x3FUL /**< Bit mask for VDAC_OPASTARTUPDLY */ +#define _VDAC_OPA_TIMER_STARTUPDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_STARTUPDLY_DEFAULT (_VDAC_OPA_TIMER_STARTUPDLY_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_WARMUPTIME_SHIFT 8 /**< Shift value for VDAC_OPAWARMUPTIME */ +#define _VDAC_OPA_TIMER_WARMUPTIME_MASK 0x7F00UL /**< Bit mask for VDAC_OPAWARMUPTIME */ +#define _VDAC_OPA_TIMER_WARMUPTIME_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_WARMUPTIME_DEFAULT (_VDAC_OPA_TIMER_WARMUPTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_SETTLETIME_SHIFT 16 /**< Shift value for VDAC_OPASETTLETIME */ +#define _VDAC_OPA_TIMER_SETTLETIME_MASK 0x3FF0000UL /**< Bit mask for VDAC_OPASETTLETIME */ +#define _VDAC_OPA_TIMER_SETTLETIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_SETTLETIME_DEFAULT (_VDAC_OPA_TIMER_SETTLETIME_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ + +/* Bit fields for VDAC OPA_MUX */ +#define _VDAC_OPA_MUX_RESETVALUE 0x0016F2F1UL /**< Default value for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_MASK 0x0717FFFFUL /**< Mask for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_SHIFT 0 /**< Shift value for VDAC_OPAPOSSEL */ +#define _VDAC_OPA_MUX_POSSEL_MASK 0xFFUL /**< Bit mask for VDAC_OPAPOSSEL */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH2 0x00000021UL /**< Mode APORT1XCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH4 0x00000022UL /**< Mode APORT1XCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH6 0x00000023UL /**< Mode APORT1XCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH8 0x00000024UL /**< Mode APORT1XCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH10 0x00000025UL /**< Mode APORT1XCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH12 0x00000026UL /**< Mode APORT1XCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH14 0x00000027UL /**< Mode APORT1XCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH16 0x00000028UL /**< Mode APORT1XCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH18 0x00000029UL /**< Mode APORT1XCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH20 0x0000002AUL /**< Mode APORT1XCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH22 0x0000002BUL /**< Mode APORT1XCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH24 0x0000002CUL /**< Mode APORT1XCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH26 0x0000002DUL /**< Mode APORT1XCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH28 0x0000002EUL /**< Mode APORT1XCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH30 0x0000002FUL /**< Mode APORT1XCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH1 0x00000040UL /**< Mode APORT2XCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH3 0x00000041UL /**< Mode APORT2XCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH5 0x00000042UL /**< Mode APORT2XCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH7 0x00000043UL /**< Mode APORT2XCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH9 0x00000044UL /**< Mode APORT2XCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH11 0x00000045UL /**< Mode APORT2XCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH13 0x00000046UL /**< Mode APORT2XCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH15 0x00000047UL /**< Mode APORT2XCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH17 0x00000048UL /**< Mode APORT2XCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH19 0x00000049UL /**< Mode APORT2XCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH21 0x0000004AUL /**< Mode APORT2XCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH23 0x0000004BUL /**< Mode APORT2XCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH25 0x0000004CUL /**< Mode APORT2XCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH27 0x0000004DUL /**< Mode APORT2XCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH29 0x0000004EUL /**< Mode APORT2XCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH31 0x0000004FUL /**< Mode APORT2XCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH2 0x00000061UL /**< Mode APORT3XCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH4 0x00000062UL /**< Mode APORT3XCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH6 0x00000063UL /**< Mode APORT3XCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH8 0x00000064UL /**< Mode APORT3XCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH10 0x00000065UL /**< Mode APORT3XCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH12 0x00000066UL /**< Mode APORT3XCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH14 0x00000067UL /**< Mode APORT3XCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH16 0x00000068UL /**< Mode APORT3XCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH18 0x00000069UL /**< Mode APORT3XCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH20 0x0000006AUL /**< Mode APORT3XCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH22 0x0000006BUL /**< Mode APORT3XCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH24 0x0000006CUL /**< Mode APORT3XCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH26 0x0000006DUL /**< Mode APORT3XCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH28 0x0000006EUL /**< Mode APORT3XCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH30 0x0000006FUL /**< Mode APORT3XCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH1 0x00000080UL /**< Mode APORT4XCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH3 0x00000081UL /**< Mode APORT4XCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH5 0x00000082UL /**< Mode APORT4XCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH7 0x00000083UL /**< Mode APORT4XCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH9 0x00000084UL /**< Mode APORT4XCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH11 0x00000085UL /**< Mode APORT4XCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH13 0x00000086UL /**< Mode APORT4XCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH15 0x00000087UL /**< Mode APORT4XCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH17 0x00000088UL /**< Mode APORT4XCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH19 0x00000089UL /**< Mode APORT4XCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH21 0x0000008AUL /**< Mode APORT4XCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH23 0x0000008BUL /**< Mode APORT4XCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH25 0x0000008CUL /**< Mode APORT4XCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH27 0x0000008DUL /**< Mode APORT4XCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH29 0x0000008EUL /**< Mode APORT4XCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH31 0x0000008FUL /**< Mode APORT4XCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DEFAULT 0x000000F1UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DAC 0x000000F1UL /**< Mode DAC for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_POSPAD 0x000000F2UL /**< Mode POSPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_OPANEXT 0x000000F3UL /**< Mode OPANEXT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_OPATAP 0x000000F4UL /**< Mode OPATAP for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH0 (_VDAC_OPA_MUX_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH2 (_VDAC_OPA_MUX_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH4 (_VDAC_OPA_MUX_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH6 (_VDAC_OPA_MUX_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH8 (_VDAC_OPA_MUX_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH10 (_VDAC_OPA_MUX_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH12 (_VDAC_OPA_MUX_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH14 (_VDAC_OPA_MUX_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH16 (_VDAC_OPA_MUX_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH18 (_VDAC_OPA_MUX_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH20 (_VDAC_OPA_MUX_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH22 (_VDAC_OPA_MUX_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH24 (_VDAC_OPA_MUX_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH26 (_VDAC_OPA_MUX_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH28 (_VDAC_OPA_MUX_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH30 (_VDAC_OPA_MUX_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH1 (_VDAC_OPA_MUX_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH3 (_VDAC_OPA_MUX_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH5 (_VDAC_OPA_MUX_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH7 (_VDAC_OPA_MUX_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH9 (_VDAC_OPA_MUX_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH11 (_VDAC_OPA_MUX_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH13 (_VDAC_OPA_MUX_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH15 (_VDAC_OPA_MUX_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH17 (_VDAC_OPA_MUX_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH19 (_VDAC_OPA_MUX_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH21 (_VDAC_OPA_MUX_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH23 (_VDAC_OPA_MUX_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH25 (_VDAC_OPA_MUX_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH27 (_VDAC_OPA_MUX_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH29 (_VDAC_OPA_MUX_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH31 (_VDAC_OPA_MUX_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH0 (_VDAC_OPA_MUX_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH2 (_VDAC_OPA_MUX_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH4 (_VDAC_OPA_MUX_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH6 (_VDAC_OPA_MUX_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH8 (_VDAC_OPA_MUX_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH10 (_VDAC_OPA_MUX_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH12 (_VDAC_OPA_MUX_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH14 (_VDAC_OPA_MUX_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH16 (_VDAC_OPA_MUX_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH18 (_VDAC_OPA_MUX_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH20 (_VDAC_OPA_MUX_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH22 (_VDAC_OPA_MUX_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH24 (_VDAC_OPA_MUX_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH26 (_VDAC_OPA_MUX_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH28 (_VDAC_OPA_MUX_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH30 (_VDAC_OPA_MUX_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH1 (_VDAC_OPA_MUX_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH3 (_VDAC_OPA_MUX_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH5 (_VDAC_OPA_MUX_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH7 (_VDAC_OPA_MUX_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH9 (_VDAC_OPA_MUX_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH11 (_VDAC_OPA_MUX_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH13 (_VDAC_OPA_MUX_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH15 (_VDAC_OPA_MUX_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH17 (_VDAC_OPA_MUX_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH19 (_VDAC_OPA_MUX_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH21 (_VDAC_OPA_MUX_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH23 (_VDAC_OPA_MUX_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH25 (_VDAC_OPA_MUX_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH27 (_VDAC_OPA_MUX_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH29 (_VDAC_OPA_MUX_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH31 (_VDAC_OPA_MUX_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DISABLE (_VDAC_OPA_MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DEFAULT (_VDAC_OPA_MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DAC (_VDAC_OPA_MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_POSPAD (_VDAC_OPA_MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_OPANEXT (_VDAC_OPA_MUX_POSSEL_OPANEXT << 0) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_OPATAP (_VDAC_OPA_MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_SHIFT 8 /**< Shift value for VDAC_OPANEGSEL */ +#define _VDAC_OPA_MUX_NEGSEL_MASK 0xFF00UL /**< Bit mask for VDAC_OPANEGSEL */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_UG 0x000000F1UL /**< Mode UG for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_DEFAULT 0x000000F2UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_OPATAP 0x000000F2UL /**< Mode OPATAP for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_NEGPAD 0x000000F3UL /**< Mode NEGPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_DISABLE (_VDAC_OPA_MUX_NEGSEL_DISABLE << 8) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_UG (_VDAC_OPA_MUX_NEGSEL_UG << 8) /**< Shifted mode UG for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_DEFAULT (_VDAC_OPA_MUX_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_OPATAP (_VDAC_OPA_MUX_NEGSEL_OPATAP << 8) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_NEGPAD (_VDAC_OPA_MUX_NEGSEL_NEGPAD << 8) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_SHIFT 16 /**< Shift value for VDAC_OPARESINMUX */ +#define _VDAC_OPA_MUX_RESINMUX_MASK 0x70000UL /**< Bit mask for VDAC_OPARESINMUX */ +#define _VDAC_OPA_MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_OPANEXT 0x00000001UL /**< Mode OPANEXT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_COMPAD 0x00000004UL /**< Mode COMPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_CENTER 0x00000005UL /**< Mode CENTER for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_DEFAULT 0x00000006UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_VSS 0x00000006UL /**< Mode VSS for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_DISABLE (_VDAC_OPA_MUX_RESINMUX_DISABLE << 16) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_OPANEXT (_VDAC_OPA_MUX_RESINMUX_OPANEXT << 16) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_NEGPAD (_VDAC_OPA_MUX_RESINMUX_NEGPAD << 16) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_POSPAD (_VDAC_OPA_MUX_RESINMUX_POSPAD << 16) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_COMPAD (_VDAC_OPA_MUX_RESINMUX_COMPAD << 16) /**< Shifted mode COMPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_CENTER (_VDAC_OPA_MUX_RESINMUX_CENTER << 16) /**< Shifted mode CENTER for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_DEFAULT (_VDAC_OPA_MUX_RESINMUX_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_VSS (_VDAC_OPA_MUX_RESINMUX_VSS << 16) /**< Shifted mode VSS for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_GAIN3X (0x1UL << 20) /**< OPAx Dedicated 3x gain resistor ladder. */ +#define _VDAC_OPA_MUX_GAIN3X_SHIFT 20 /**< Shift value for VDAC_OPAGAIN3X */ +#define _VDAC_OPA_MUX_GAIN3X_MASK 0x100000UL /**< Bit mask for VDAC_OPAGAIN3X */ +#define _VDAC_OPA_MUX_GAIN3X_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_GAIN3X_DEFAULT (_VDAC_OPA_MUX_GAIN3X_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_SHIFT 24 /**< Shift value for VDAC_OPARESSEL */ +#define _VDAC_OPA_MUX_RESSEL_MASK 0x7000000UL /**< Bit mask for VDAC_OPARESSEL */ +#define _VDAC_OPA_MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_DEFAULT (_VDAC_OPA_MUX_RESSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES0 (_VDAC_OPA_MUX_RESSEL_RES0 << 24) /**< Shifted mode RES0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES1 (_VDAC_OPA_MUX_RESSEL_RES1 << 24) /**< Shifted mode RES1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES2 (_VDAC_OPA_MUX_RESSEL_RES2 << 24) /**< Shifted mode RES2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES3 (_VDAC_OPA_MUX_RESSEL_RES3 << 24) /**< Shifted mode RES3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES4 (_VDAC_OPA_MUX_RESSEL_RES4 << 24) /**< Shifted mode RES4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES5 (_VDAC_OPA_MUX_RESSEL_RES5 << 24) /**< Shifted mode RES5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES6 (_VDAC_OPA_MUX_RESSEL_RES6 << 24) /**< Shifted mode RES6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES7 (_VDAC_OPA_MUX_RESSEL_RES7 << 24) /**< Shifted mode RES7 for VDAC_OPA_MUX */ + +/* Bit fields for VDAC OPA_OUT */ +#define _VDAC_OPA_OUT_RESETVALUE 0x00000001UL /**< Default value for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_MASK 0x00FF01FFUL /**< Mask for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_MAINOUTEN (0x1UL << 0) /**< OPAx Main Output Enable */ +#define _VDAC_OPA_OUT_MAINOUTEN_SHIFT 0 /**< Shift value for VDAC_OPAMAINOUTEN */ +#define _VDAC_OPA_OUT_MAINOUTEN_MASK 0x1UL /**< Bit mask for VDAC_OPAMAINOUTEN */ +#define _VDAC_OPA_OUT_MAINOUTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_MAINOUTEN_DEFAULT (_VDAC_OPA_OUT_MAINOUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTEN (0x1UL << 1) /**< OPAx Alternative Output Enable */ +#define _VDAC_OPA_OUT_ALTOUTEN_SHIFT 1 /**< Shift value for VDAC_OPAALTOUTEN */ +#define _VDAC_OPA_OUT_ALTOUTEN_MASK 0x2UL /**< Bit mask for VDAC_OPAALTOUTEN */ +#define _VDAC_OPA_OUT_ALTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTEN (0x1UL << 2) /**< OPAx Aport Output Enable */ +#define _VDAC_OPA_OUT_APORTOUTEN_SHIFT 2 /**< Shift value for VDAC_OPAAPORTOUTEN */ +#define _VDAC_OPA_OUT_APORTOUTEN_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORTOUTEN */ +#define _VDAC_OPA_OUT_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTEN_DEFAULT (_VDAC_OPA_OUT_APORTOUTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_SHORT (0x1UL << 3) /**< OPAx Main and Alternative Output Short */ +#define _VDAC_OPA_OUT_SHORT_SHIFT 3 /**< Shift value for VDAC_OPASHORT */ +#define _VDAC_OPA_OUT_SHORT_MASK 0x8UL /**< Bit mask for VDAC_OPASHORT */ +#define _VDAC_OPA_OUT_SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_SHORT_DEFAULT (_VDAC_OPA_OUT_SHORT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_SHIFT 4 /**< Shift value for VDAC_OPAALTOUTPADEN */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_MASK 0x1F0UL /**< Bit mask for VDAC_OPAALTOUTPADEN */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT0 0x00000001UL /**< Mode OUT0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT1 0x00000002UL /**< Mode OUT1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT2 0x00000004UL /**< Mode OUT2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT3 0x00000008UL /**< Mode OUT3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT4 0x00000010UL /**< Mode OUT4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT0 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT0 << 4) /**< Shifted mode OUT0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT1 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT1 << 4) /**< Shifted mode OUT1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT2 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT2 << 4) /**< Shifted mode OUT2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT3 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT3 << 4) /**< Shifted mode OUT3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT4 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT4 << 4) /**< Shifted mode OUT4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_SHIFT 16 /**< Shift value for VDAC_OPAAPORTOUTSEL */ +#define _VDAC_OPA_OUT_APORTOUTSEL_MASK 0xFF0000UL /**< Bit mask for VDAC_OPAAPORTOUTSEL */ +#define _VDAC_OPA_OUT_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_DEFAULT (_VDAC_OPA_OUT_APORTOUTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for VDAC_OPA_OUT */ + +/* Bit fields for VDAC OPA_CAL */ +#define _VDAC_OPA_CAL_RESETVALUE 0x000080E7UL /**< Default value for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_MASK 0x7DF6EDEFUL /**< Mask for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM1_SHIFT 0 /**< Shift value for VDAC_OPACM1 */ +#define _VDAC_OPA_CAL_CM1_MASK 0xFUL /**< Bit mask for VDAC_OPACM1 */ +#define _VDAC_OPA_CAL_CM1_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM1_DEFAULT (_VDAC_OPA_CAL_CM1_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM2_SHIFT 5 /**< Shift value for VDAC_OPACM2 */ +#define _VDAC_OPA_CAL_CM2_MASK 0x1E0UL /**< Bit mask for VDAC_OPACM2 */ +#define _VDAC_OPA_CAL_CM2_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM2_DEFAULT (_VDAC_OPA_CAL_CM2_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM3_SHIFT 10 /**< Shift value for VDAC_OPACM3 */ +#define _VDAC_OPA_CAL_CM3_MASK 0xC00UL /**< Bit mask for VDAC_OPACM3 */ +#define _VDAC_OPA_CAL_CM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM3_DEFAULT (_VDAC_OPA_CAL_CM3_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_GM_SHIFT 13 /**< Shift value for VDAC_OPAGM */ +#define _VDAC_OPA_CAL_GM_MASK 0xE000UL /**< Bit mask for VDAC_OPAGM */ +#define _VDAC_OPA_CAL_GM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_GM_DEFAULT (_VDAC_OPA_CAL_GM_DEFAULT << 13) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_GM3_SHIFT 17 /**< Shift value for VDAC_OPAGM3 */ +#define _VDAC_OPA_CAL_GM3_MASK 0x60000UL /**< Bit mask for VDAC_OPAGM3 */ +#define _VDAC_OPA_CAL_GM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_GM3_DEFAULT (_VDAC_OPA_CAL_GM3_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_OFFSETP_SHIFT 20 /**< Shift value for VDAC_OPAOFFSETP */ +#define _VDAC_OPA_CAL_OFFSETP_MASK 0x1F00000UL /**< Bit mask for VDAC_OPAOFFSETP */ +#define _VDAC_OPA_CAL_OFFSETP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_OFFSETP_DEFAULT (_VDAC_OPA_CAL_OFFSETP_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_OFFSETN_SHIFT 26 /**< Shift value for VDAC_OPAOFFSETN */ +#define _VDAC_OPA_CAL_OFFSETN_MASK 0x7C000000UL /**< Bit mask for VDAC_OPAOFFSETN */ +#define _VDAC_OPA_CAL_OFFSETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_OFFSETN_DEFAULT (_VDAC_OPA_CAL_OFFSETN_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ + +/** @} End of group EFM32PG12B_VDAC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_vdac_opa.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_vdac_opa.h new file mode 100644 index 00000000000..a082dfbff81 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_vdac_opa.h @@ -0,0 +1,53 @@ +/**************************************************************************//** + * @file efm32pg12b_vdac_opa.h + * @brief EFM32PG12B_VDAC_OPA register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief VDAC_OPA EFM32PG12B VDAC OPA + *****************************************************************************/ +typedef struct +{ + __IM uint32_t APORTREQ; /**< Operational Amplifier APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< Operational Amplifier APORT Conflict Status Register */ + __IOM uint32_t CTRL; /**< Operational Amplifier Control Register */ + __IOM uint32_t TIMER; /**< Operational Amplifier Timer Control Register */ + __IOM uint32_t MUX; /**< Operational Amplifier Mux Configuration Register */ + __IOM uint32_t OUT; /**< Operational Amplifier Output Configuration Register */ + __IOM uint32_t CAL; /**< Operational Amplifier Calibration Register */ + uint32_t RESERVED0[1]; /**< Reserved future */ +} VDAC_OPA_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_wdog.h new file mode 100644 index 00000000000..53114a019b1 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_wdog.h @@ -0,0 +1,335 @@ +/**************************************************************************//** + * @file efm32pg12b_wdog.h + * @brief EFM32PG12B_WDOG register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_WDOG + * @{ + * @brief EFM32PG12B_WDOG Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + WDOG_PCH_TypeDef PCH[2]; /**< PCH */ + + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Watchdog Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} WDOG_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_WDOG_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for WDOG CTRL */ +#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */ +#define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */ +#define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */ +#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */ +#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */ +#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */ +#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */ +#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */ +#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_HFCORECLK 0x00000003UL /**< Mode HFCORECLK for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_HFCORECLK (_WDOG_CTRL_CLKSEL_HFCORECLK << 12) /**< Shifted mode HFCORECLK for WDOG_CTRL */ +#define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */ +#define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */ +#define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */ +#define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */ +#define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/* Bit fields for WDOG PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IFS */ +#define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */ +#define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */ +#define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */ +#define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */ +#define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */ +#define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */ +#define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */ +#define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */ + +/* Bit fields for WDOG IFC */ +#define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */ +#define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */ +#define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */ +#define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */ +#define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */ +#define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */ +#define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */ +#define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/** @} End of group EFM32PG12B_WDOG */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_wdog_pch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_wdog_pch.h new file mode 100644 index 00000000000..6c8b7edadb8 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_wdog_pch.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efm32pg12b_wdog_pch.h + * @brief EFM32PG12B_WDOG_PCH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief WDOG_PCH EFM32PG12B WDOG PCH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t PRSCTRL; /**< PRS Control Register */ +} WDOG_PCH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/em_device.h new file mode 100644 index 00000000000..0b5751daa37 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/em_device.h @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file em_device.h + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + * + * + * @endverbatim + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H + +#if defined(EFM32PG12B500F1024GL125) +#include "efm32pg12b500f1024gl125.h" + +#elif defined(EFM32PG12B500F1024GM48) +#include "efm32pg12b500f1024gm48.h" + +#elif defined(EFM32PG12B500F1024IL125) +#include "efm32pg12b500f1024il125.h" + +#elif defined(EFM32PG12B500F1024IM48) +#include "efm32pg12b500f1024im48.h" + +#elif defined(EFM32PG12B500F512GL125) +#include "efm32pg12b500f512gl125.h" + +#elif defined(EFM32PG12B500F512GM48) +#include "efm32pg12b500f512gm48.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif +#endif /* EM_DEVICE_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/system_efm32pg12b.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/system_efm32pg12b.c new file mode 100644 index 00000000000..25ade0ffc4a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/system_efm32pg12b.c @@ -0,0 +1,384 @@ +/***************************************************************************//** + * @file system_efm32pg12b.c + * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** LFRCO frequency, tuned to below frequency during manufacturing. */ +#define EFM32_LFRCO_FREQ (32768UL) +#define EFM32_ULFRCO_FREQ (1000UL) + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +/* System oscillator frequencies. These frequencies are normally constant */ +/* for a target, but they are made configurable in order to allow run-time */ +/* handling of different boards. The crystal oscillator clocks can be set */ +/* compile time to a non-default value by defining respective EFM_nFXO_FREQ */ +/* values according to board design. By defining the EFM_nFXO_FREQ to 0, */ +/* one indicates that the oscillator is not present, in order to save some */ +/* SW footprint. */ + +#ifndef EFM32_HFRCO_MAX_FREQ +#define EFM32_HFRCO_MAX_FREQ (38000000UL) +#endif + +#ifndef EFM32_HFXO_FREQ +#define EFM32_HFXO_FREQ (40000000UL) +#endif + +#ifndef EFM32_HFRCO_STARTUP_FREQ +#define EFM32_HFRCO_STARTUP_FREQ (19000000UL) +#endif + + +/* Do not define variable if HF crystal oscillator not present */ +#if (EFM32_HFXO_FREQ > 0UL) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System HFXO clock. */ +static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + +#ifndef EFM32_LFXO_FREQ +#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ) +#endif +/* Do not define variable if LF crystal oscillator not present */ +#if (EFM32_LFXO_FREQ > 0UL) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System LFXO clock. */ +static uint32_t SystemLFXOClock = 32768UL; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock; + + +/** + * @brief + * System HFRCO frequency + * + * @note + * This is an EFM32 proprietary variable, not part of the CMSIS definition. + * + * @details + * Frequency of the system HFRCO oscillator + */ +uint32_t SystemHfrcoFreq = EFM32_HFRCO_STARTUP_FREQ; + + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the current core clock frequency. + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemCoreClockGet(void) +{ + uint32_t ret; + uint32_t presc; + + ret = SystemHFClockGet(); + presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >> + _CMU_HFCOREPRESC_PRESC_SHIFT; + ret /= (presc + 1); + + /* Keep CMSIS system clock variable up-to-date */ + SystemCoreClock = ret; + + return ret; +} + + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \ + EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ); +} + + +/***************************************************************************//** + * @brief + * Get the current HFCLK frequency. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current HFCLK frequency in Hz. + ******************************************************************************/ +uint32_t SystemHFClockGet(void) +{ + uint32_t ret; + + switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) + { + case CMU_HFCLKSTATUS_SELECTED_LFXO: +#if (EFM32_LFXO_FREQ > 0) + ret = SystemLFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + case CMU_HFCLKSTATUS_SELECTED_LFRCO: + ret = EFM32_LFRCO_FREQ; + break; + + case CMU_HFCLKSTATUS_SELECTED_HFXO: +#if (EFM32_HFXO_FREQ > 0) + ret = SystemHFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */ + ret = SystemHfrcoFreq; + break; + } + + return ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT)); +} + + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * HFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFM32_HFXO_FREQ > 0) + return SystemHFXOClock; +#else + return 0; +#endif +} + + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFM32_HFXO_FREQ > 0) + SystemHFXOClock = freq; + + /* Update core clock frequency if HFXO is used to clock core */ + if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_HFXO) + { + /* The function will update the global variable */ + SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} + + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Set floating point coprosessor access mode. */ + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif +} + + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + /* Currently we assume that this frequency is properly tuned during */ + /* manufacturing and is not changed after reset. If future requirements */ + /* for re-tuning by user, we can add support for that. */ + return EFM32_LFRCO_FREQ; +} + + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + /* The ULFRCO frequency is not tuned, and can be very inaccurate */ + return EFM32_ULFRCO_FREQ; +} + + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFM32_LFXO_FREQ > 0) + return SystemLFXOClock; +#else + return 0; +#endif +} + + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFM32_LFXO_FREQ > 0) + SystemLFXOClock = freq; + + /* Update core clock frequency if LFXO is used to clock core */ + if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_LFXO) + { + /* The function will update the global variable */ + SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/system_efm32pg12b.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/system_efm32pg12b.h new file mode 100644 index 00000000000..feb8ceef0da --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/system_efm32pg12b.h @@ -0,0 +1,129 @@ +/***************************************************************************//** + * @file system_efm32pg12b.h + * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef SYSTEM_EFM32_H +#define SYSTEM_EFM32_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void EMU_IRQHandler(void); +void WDOG0_IRQHandler(void); +void LDMA_IRQHandler(void); +void GPIO_EVEN_IRQHandler(void); +void TIMER0_IRQHandler(void); +void USART0_RX_IRQHandler(void); +void USART0_TX_IRQHandler(void); +void ACMP0_IRQHandler(void); +void ADC0_IRQHandler(void); +void IDAC0_IRQHandler(void); +void I2C0_IRQHandler(void); +void GPIO_ODD_IRQHandler(void); +void TIMER1_IRQHandler(void); +void USART1_RX_IRQHandler(void); +void USART1_TX_IRQHandler(void); +void LEUART0_IRQHandler(void); +void PCNT0_IRQHandler(void); +void CMU_IRQHandler(void); +void MSC_IRQHandler(void); +void LETIMER0_IRQHandler(void); +void RTCC_IRQHandler(void); +void CRYOTIMER_IRQHandler(void); + +#if (__FPU_PRESENT == 1) +void FPUEH_IRQHandler(void); +#endif + +uint32_t SystemCoreClockGet(void); + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EFM CMU + * API, this variable will be kept updated. This function is only provided + * for CMSIS compliance and if a user modifies the the core clock outside + * the CMU API. + *****************************************************************************/ +static __INLINE void SystemCoreClockUpdate(void) +{ + SystemCoreClockGet(); +} + +uint32_t SystemMaxCoreClockGet(void); + +void SystemInit(void); +uint32_t SystemHFClockGet(void); + +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); + +uint32_t SystemLFRCOClockGet(void); +uint32_t SystemULFRCOClockGet(void); + +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_EFM32_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f128.h index 3f041f77853..09761384098 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f128.h @@ -2,10 +2,10 @@ * @file efm32wg230f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG230F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG230F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f256.h index 264621120cd..5a5fa8c1402 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f256.h @@ -2,10 +2,10 @@ * @file efm32wg230f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG230F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG230F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f64.h index 455ab9e5fa7..4c29b86f6d7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f64.h @@ -2,10 +2,10 @@ * @file efm32wg230f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG230F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG230F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f128.h index e3ed1a79a19..b06d9b5b412 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f128.h @@ -2,10 +2,10 @@ * @file efm32wg232f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG232F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG232F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f256.h index d15eba63f37..1f9b76d10bc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f256.h @@ -2,10 +2,10 @@ * @file efm32wg232f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG232F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG232F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f64.h index 457486acabe..ef1ac42b7f4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f64.h @@ -2,10 +2,10 @@ * @file efm32wg232f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG232F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG232F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f128.h index fbc49446c12..8f3db4efb48 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f128.h @@ -2,10 +2,10 @@ * @file efm32wg280f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG280F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG280F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f256.h index 8441967725f..65740741a59 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f256.h @@ -2,10 +2,10 @@ * @file efm32wg280f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG280F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG280F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f64.h index 632db480dfc..7810f254847 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f64.h @@ -2,10 +2,10 @@ * @file efm32wg280f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG280F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG280F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f128.h index ab5ab78134d..6722cb3c30d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f128.h @@ -2,10 +2,10 @@ * @file efm32wg290f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG290F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG290F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f256.h index cc8f1425a60..1a33b194c88 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f256.h @@ -2,10 +2,10 @@ * @file efm32wg290f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG290F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG290F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f64.h index 6e54e4df6e9..0e79a6b946c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f64.h @@ -2,10 +2,10 @@ * @file efm32wg290f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG290F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG290F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f128.h index 54572f0ebaa..89712b13c9b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f128.h @@ -2,10 +2,10 @@ * @file efm32wg295f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG295F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG295F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f256.h index 2ab20c3cd47..62cbbd9acb3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f256.h @@ -2,10 +2,10 @@ * @file efm32wg295f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG295F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG295F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f64.h index e832031bcc0..54aca949bc9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f64.h @@ -2,10 +2,10 @@ * @file efm32wg295f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG295F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG295F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f128.h index 60748b64fae..8e17d656231 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f128.h @@ -2,10 +2,10 @@ * @file efm32wg330f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG330F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG330F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f256.h index b9326e88153..3091585eaf1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f256.h @@ -2,10 +2,10 @@ * @file efm32wg330f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG330F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG330F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f64.h index d8bbbdb9d71..53ace98297b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f64.h @@ -2,10 +2,10 @@ * @file efm32wg330f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG330F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG330F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f128.h index 36eeddebb62..32973a88e45 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f128.h @@ -2,10 +2,10 @@ * @file efm32wg332f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG332F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG332F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f256.h index f85bfc897ce..14dd40b6b88 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f256.h @@ -2,10 +2,10 @@ * @file efm32wg332f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG332F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG332F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f64.h index 555d720809e..4e30b9a7156 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f64.h @@ -2,10 +2,10 @@ * @file efm32wg332f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG332F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG332F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f128.h index 6e825affcc4..293f6ebceab 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f128.h @@ -2,10 +2,10 @@ * @file efm32wg360f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG360F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG360F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f256.h index b49660b1479..a1b1608908f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f256.h @@ -2,10 +2,10 @@ * @file efm32wg360f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG360F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG360F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f64.h index aeb5aa846e9..654dad97e37 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f64.h @@ -2,10 +2,10 @@ * @file efm32wg360f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG360F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG360F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f128.h index fd80c5e4bcb..acea57d5b5c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f128.h @@ -2,10 +2,10 @@ * @file efm32wg380f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG380F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG380F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f256.h index cd2ad874ddd..d1ce01086ad 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f256.h @@ -2,10 +2,10 @@ * @file efm32wg380f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG380F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG380F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f64.h index 68da0d10030..6efff59de97 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f64.h @@ -2,10 +2,10 @@ * @file efm32wg380f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG380F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG380F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f128.h index d89f2f6ec0b..7ee4456310f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f128.h @@ -2,10 +2,10 @@ * @file efm32wg390f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG390F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG390F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f256.h index 67aad0ff1c4..aa6c7c1e03f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f256.h @@ -2,10 +2,10 @@ * @file efm32wg390f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG390F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG390F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f64.h index f8e7b0fca9d..3989b6f64c9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f64.h @@ -2,10 +2,10 @@ * @file efm32wg390f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG390F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG390F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f128.h index 867e8ae8d3a..20d485d893a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f128.h @@ -2,10 +2,10 @@ * @file efm32wg395f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG395F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG395F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f256.h index 5648a0db21c..b5d1114f429 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f256.h @@ -2,10 +2,10 @@ * @file efm32wg395f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG395F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG395F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f64.h index b8b0abdeb4f..630b51d93c7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f64.h @@ -2,10 +2,10 @@ * @file efm32wg395f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG395F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG395F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f128.h index 019ad140572..cd8e5e496b1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f128.h @@ -2,10 +2,10 @@ * @file efm32wg840f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG840F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG840F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f256.h index 24aed469c94..e4dbf2ce316 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f256.h @@ -2,10 +2,10 @@ * @file efm32wg840f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG840F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG840F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f64.h index 17c22918496..6a81de12ea9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f64.h @@ -2,10 +2,10 @@ * @file efm32wg840f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG840F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG840F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f128.h index b163f7f9d68..87475c53a49 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f128.h @@ -2,10 +2,10 @@ * @file efm32wg842f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG842F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG842F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f256.h index 9d0417627ed..c56e34dd5a2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f256.h @@ -2,10 +2,10 @@ * @file efm32wg842f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG842F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG842F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f64.h index f34de7a25e2..49bdecf5724 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f64.h @@ -2,10 +2,10 @@ * @file efm32wg842f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG842F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG842F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f128.h index 159f19015b9..fdfc8592348 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f128.h @@ -2,10 +2,10 @@ * @file efm32wg880f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG880F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG880F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f256.h index 10ac7b01db4..fc620b6ef97 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f256.h @@ -2,10 +2,10 @@ * @file efm32wg880f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG880F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG880F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f64.h index 8a2878ef6ec..e0ecc5ee217 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f64.h @@ -2,10 +2,10 @@ * @file efm32wg880f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG880F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG880F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f128.h index 06341382398..2d781eec477 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f128.h @@ -2,10 +2,10 @@ * @file efm32wg890f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG890F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG890F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f256.h index e5bc463845d..c65150bff06 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f256.h @@ -2,10 +2,10 @@ * @file efm32wg890f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG890F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG890F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f64.h index f6af8b87557..1c1770ce43a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f64.h @@ -2,10 +2,10 @@ * @file efm32wg890f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG890F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG890F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f128.h index 324ba3e0828..68c961e7356 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f128.h @@ -2,10 +2,10 @@ * @file efm32wg895f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG895F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG895F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f256.h index e91cea86b64..e17248c46d8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f256.h @@ -2,10 +2,10 @@ * @file efm32wg895f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG895F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG895F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f64.h index 020ec7da098..3efb6fd41bf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f64.h @@ -2,10 +2,10 @@ * @file efm32wg895f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG895F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG895F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg900f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg900f256.h index 82b495307c1..340d1fd3773 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg900f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg900f256.h @@ -2,10 +2,10 @@ * @file efm32wg900f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG900F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG900F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f128.h index 3a7b901c44e..36241163237 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f128.h @@ -2,10 +2,10 @@ * @file efm32wg940f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG940F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG940F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f256.h index f9ff3ddf926..951ef33cbef 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f256.h @@ -2,10 +2,10 @@ * @file efm32wg940f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG940F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG940F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f64.h index 4dfff0e49fc..37178548563 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f64.h @@ -2,10 +2,10 @@ * @file efm32wg940f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG940F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG940F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f128.h index 837a50f2c2a..1afa6e13aa7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f128.h @@ -2,10 +2,10 @@ * @file efm32wg942f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG942F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG942F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f256.h index 2b5d1159982..28ed3e2517b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f256.h @@ -2,10 +2,10 @@ * @file efm32wg942f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG942F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG942F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f64.h index 0132cc50b40..f2e13852a12 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f64.h @@ -2,10 +2,10 @@ * @file efm32wg942f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG942F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG942F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f128.h index 6af43c4466c..cea633d452e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f128.h @@ -2,10 +2,10 @@ * @file efm32wg980f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG980F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG980F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f256.h index 4395cd683a1..529f951d8ab 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f256.h @@ -2,10 +2,10 @@ * @file efm32wg980f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG980F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG980F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f64.h index b2c2faa03b3..2608a1acd92 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f64.h @@ -2,10 +2,10 @@ * @file efm32wg980f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG980F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG980F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f128.h index fdbe31b88cc..d60f6b3a891 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f128.h @@ -2,10 +2,10 @@ * @file efm32wg990f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG990F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG990F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f256.h index 354fe249f6a..8a971fb7325 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f256.h @@ -2,10 +2,10 @@ * @file efm32wg990f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG990F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG990F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f64.h index 341601ee6ad..416d4e710e2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f64.h @@ -2,10 +2,10 @@ * @file efm32wg990f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG990F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG990F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f128.h index e7ce6e5dea1..3863fe588e4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f128.h @@ -2,10 +2,10 @@ * @file efm32wg995f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG995F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG995F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f256.h index b192d642f16..e2575f75721 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f256.h @@ -2,10 +2,10 @@ * @file efm32wg995f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG995F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG995F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f64.h index 5d26fd8890c..571bf4327dd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f64.h @@ -2,10 +2,10 @@ * @file efm32wg995f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG995F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG995F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_acmp.h index a3b459a50eb..ae1cc299d78 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_acmp.h * @brief EFM32WG_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_adc.h index 8875dc9cefb..81229269a96 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_adc.h * @brief EFM32WG_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_aes.h index 02cdd806cd9..186552f0443 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_aes.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_aes.h * @brief EFM32WG_AES register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_pins.h index 18a7dd99487..21c06b9d9df 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_af_pins.h * @brief EFM32WG_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_ports.h index dcf8cb68db2..6b02f8bd410 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_af_ports.h * @brief EFM32WG_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc.h index 9f6ca5a7544..2028591cee2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_burtc.h * @brief EFM32WG_BURTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc_ret.h index 82d73dfaff8..d1dc9e7fe1d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc_ret.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc_ret.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_burtc_ret.h * @brief EFM32WG_BURTC_RET register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_calibrate.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_calibrate.h index 2c27f37a79f..5670ec155cb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_calibrate.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_calibrate.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_calibrate.h * @brief EFM32WG_CALIBRATE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_cmu.h index 7af287d0f5a..a03cc49ccb3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_cmu.h * @brief EFM32WG_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dac.h index af7a596bb69..51dce4e00fb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dac.h * @brief EFM32WG_DAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_devinfo.h index 4aecac5ff98..3820271f32e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_devinfo.h * @brief EFM32WG_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma.h index d93e5715a41..e245d788160 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dma.h * @brief EFM32WG_DMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_ch.h index bcbd316108c..a313dd24625 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dma_ch.h * @brief EFM32WG_DMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_descriptor.h index 90ed75eedec..ade4f8ae414 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dma_descriptor.h * @brief EFM32WG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmactrl.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmactrl.h index 195a1791d7e..099729f164c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmactrl.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmactrl.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dmactrl.h * @brief EFM32WG_DMACTRL register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmareq.h index 0edd04116ee..584b133f62b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dmareq.h * @brief EFM32WG_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_ebi.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_ebi.h index 2bf86080c1f..02593572a07 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_ebi.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_ebi.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_ebi.h * @brief EFM32WG_EBI register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_emu.h index a23a23610a6..2050be183e5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_emu.h * @brief EFM32WG_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_etm.h index 8cd95dba3c5..8b89d7edfdf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_etm.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_etm.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_etm.h * @brief EFM32WG_ETM register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_fpueh.h index 5def7890819..38c583aca8f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_fpueh.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_fpueh.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_fpueh.h * @brief EFM32WG_FPUEH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio.h index e0c72b50541..355eb50669e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_gpio.h * @brief EFM32WG_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio_p.h index 8558d7780c1..fd0584c9ff0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_gpio_p.h * @brief EFM32WG_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_i2c.h index b9753c1a77a..f71303db9d6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_i2c.h * @brief EFM32WG_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lcd.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lcd.h index 244bdd75dbd..2dbbc6671a5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lcd.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lcd.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_lcd.h * @brief EFM32WG_LCD register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense.h index 7ae1ee14d4d..52a4d951ed2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_lesense.h * @brief EFM32WG_LESENSE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_buf.h index 7d1a1396b86..7a417b85e29 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_buf.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_buf.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_lesense_buf.h * @brief EFM32WG_LESENSE_BUF register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_ch.h index d40bdcbdace..d4d5fedb299 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_lesense_ch.h * @brief EFM32WG_LESENSE_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_st.h index 49bad15ff9c..1f93581997d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_st.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_st.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_lesense_st.h * @brief EFM32WG_LESENSE_ST register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_letimer.h index 3ee19798b82..f2278f73afc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_letimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_letimer.h * @brief EFM32WG_LETIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_leuart.h index 84a3a427c48..495e526bd70 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_leuart.h * @brief EFM32WG_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_msc.h index 8acd0d12710..88035ccfa29 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_msc.h * @brief EFM32WG_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_pcnt.h index 2223f332205..39ce9aecc55 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_pcnt.h * @brief EFM32WG_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs.h index 8184e1fc049..6f018b1c02c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_prs.h * @brief EFM32WG_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_ch.h index b4859254797..99b29a903a5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_prs_ch.h * @brief EFM32WG_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_signals.h index 3f8ed15eb26..dfb5366f842 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_prs_signals.h * @brief EFM32WG_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rmu.h index e0cebb4c783..66bb4466b31 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_rmu.h * @brief EFM32WG_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_romtable.h index 91abd7da6c0..47fc2933b10 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_romtable.h * @brief EFM32WG_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rtc.h index 2c0191ac6a0..f989024a98d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_rtc.h * @brief EFM32WG_RTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer.h index b357695ff3a..0f0cc4c6610 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_timer.h * @brief EFM32WG_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer_cc.h index 99b285e76c7..8f2168cd213 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_timer_cc.h * @brief EFM32WG_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_uart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_uart.h index 4e894672c3e..815b0cb9a64 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_uart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_uart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_uart.h * @brief EFM32WG_UART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usart.h index 1313c3711c7..5b93bc26730 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_usart.h * @brief EFM32WG_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb.h index 8a14d120681..41480957395 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_usb.h * @brief EFM32WG_USB register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_diep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_diep.h index 12fe6181007..e7f802a776d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_diep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_diep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_usb_diep.h * @brief EFM32WG_USB_DIEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_doep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_doep.h index 68102871d63..0edea23f83e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_doep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_doep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_usb_doep.h * @brief EFM32WG_USB_DOEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_hc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_hc.h index 20e4f4ec3fd..963e508e95b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_hc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_hc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_usb_hc.h * @brief EFM32WG_USB_HC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_vcmp.h index 8bd3b0194b2..d586a3d3756 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_vcmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_vcmp.h * @brief EFM32WG_VCMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_wdog.h index 085565cec78..8a01da8b1ea 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_wdog.h * @brief EFM32WG_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/em_device.h index a184b2646f5..965748a13e2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.c index 4b45b092df6..4627ecbaded 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32wg.c * @brief CMSIS Cortex-M4 System Layer for EFM32WG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.h index 34015257aff..41c8fbbc4f6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32wg.h * @brief CMSIS Cortex-M4 System Layer for EFM32WG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f16.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f16.h index 3829f8d074c..580a81c44eb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f16.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f16.h @@ -2,10 +2,10 @@ * @file efm32zg108f16.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG108F16 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -94,12 +94,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG108F16) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f32.h index 6283ebf2774..dab5568a156 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f32.h @@ -2,10 +2,10 @@ * @file efm32zg108f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG108F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -94,12 +94,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG108F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f4.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f4.h index 2951705ff24..31ab90ca39c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f4.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f4.h @@ -2,10 +2,10 @@ * @file efm32zg108f4.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG108F4 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -94,12 +94,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG108F4) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f8.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f8.h index 84030149a3b..d37603e5c33 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f8.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f8.h @@ -2,10 +2,10 @@ * @file efm32zg108f8.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG108F8 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -94,12 +94,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG108F8) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f16.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f16.h index 38dad00217c..9c87f961e5a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f16.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f16.h @@ -2,10 +2,10 @@ * @file efm32zg110f16.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG110F16 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG110F16) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f32.h index 3736eed7bf0..cd9d660df07 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f32.h @@ -2,10 +2,10 @@ * @file efm32zg110f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG110F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG110F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f4.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f4.h index 476c389596c..d90d7ac3c64 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f4.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f4.h @@ -2,10 +2,10 @@ * @file efm32zg110f4.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG110F4 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG110F4) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f8.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f8.h index 4b3a4cde9f5..492d06c8335 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f8.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f8.h @@ -2,10 +2,10 @@ * @file efm32zg110f8.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG110F8 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG110F8) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f16.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f16.h index 3e0237714b5..822e1ece9f3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f16.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f16.h @@ -2,10 +2,10 @@ * @file efm32zg210f16.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG210F16 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG210F16) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f32.h index 2a420b4e206..68dbb27edac 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f32.h @@ -2,10 +2,10 @@ * @file efm32zg210f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG210F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG210F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f4.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f4.h index 9a506581543..8115f49fdfc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f4.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f4.h @@ -2,10 +2,10 @@ * @file efm32zg210f4.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG210F4 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG210F4) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f8.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f8.h index fef237144d2..9182c1c146d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f8.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f8.h @@ -2,10 +2,10 @@ * @file efm32zg210f8.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG210F8 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG210F8) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f16.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f16.h index 75f522208ea..3c0cc3c1d8c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f16.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f16.h @@ -2,10 +2,10 @@ * @file efm32zg222f16.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG222F16 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG222F16) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f32.h index 4d75f60666d..e6079459881 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f32.h @@ -2,10 +2,10 @@ * @file efm32zg222f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG222F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG222F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f4.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f4.h index be3d9bab0a8..b22d8a9f855 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f4.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f4.h @@ -2,10 +2,10 @@ * @file efm32zg222f4.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG222F4 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG222F4) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f8.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f8.h index d72c224e0ab..4e59bd94300 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f8.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f8.h @@ -2,10 +2,10 @@ * @file efm32zg222f8.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG222F8 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG222F8) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_acmp.h index 73378258647..130c10e18e6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_acmp.h * @brief EFM32ZG_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_adc.h index c2a9c53edf8..2d45bba2768 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_adc.h * @brief EFM32ZG_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_aes.h index cd662796db3..0fc304b7dc7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_aes.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_aes.h * @brief EFM32ZG_AES register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_pins.h index c4571cf5d05..cd7c37faf9f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_af_pins.h * @brief EFM32ZG_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_ports.h index 774f68aa087..2b3e703d00c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_af_ports.h * @brief EFM32ZG_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_calibrate.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_calibrate.h index db294aafaff..c0c5cb6db00 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_calibrate.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_calibrate.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_calibrate.h * @brief EFM32ZG_CALIBRATE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_cmu.h index ab9d92d8bfc..4395a1ee597 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_cmu.h * @brief EFM32ZG_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_devinfo.h index 774a089e026..9b5a9365a6a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_devinfo.h * @brief EFM32ZG_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma.h index ff512918105..5e2b025bafe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_dma.h * @brief EFM32ZG_DMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_ch.h index 1aa6884cad0..abdbe970abe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_dma_ch.h * @brief EFM32ZG_DMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_descriptor.h index 6aa61a9e28a..83df2b3748e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_dma_descriptor.h * @brief EFM32ZG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmactrl.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmactrl.h index 9b7bd096544..b1c665deb6f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmactrl.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmactrl.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_dmactrl.h * @brief EFM32ZG_DMACTRL register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmareq.h index 5944eaedaca..4164c99a80f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_dmareq.h * @brief EFM32ZG_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_emu.h index a27f2d47099..44a06ad8596 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_emu.h * @brief EFM32ZG_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio.h index 2ba1d940a61..40e7cb42626 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_gpio.h * @brief EFM32ZG_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio_p.h index 8614268bbee..939d676c129 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_gpio_p.h * @brief EFM32ZG_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_i2c.h index 6b296faf730..e4e97208152 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_i2c.h * @brief EFM32ZG_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_idac.h index 8b5d1c966a1..3ac8310a3d5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_idac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_idac.h * @brief EFM32ZG_IDAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_leuart.h index e50846090cf..252771833f9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_leuart.h * @brief EFM32ZG_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_msc.h index 98f731b416e..21ec685a7a4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_msc.h * @brief EFM32ZG_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_pcnt.h index d90e4cbfb95..ac9f7cae2a7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_pcnt.h * @brief EFM32ZG_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs.h index bf6ad5681b5..719d1d99192 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_prs.h * @brief EFM32ZG_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_ch.h index 394d6c0e520..d647366514a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_prs_ch.h * @brief EFM32ZG_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_signals.h index 11cf956add6..4da5fb01e4b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_prs_signals.h * @brief EFM32ZG_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rmu.h index 5c5067d9096..ee0b42606f9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_rmu.h * @brief EFM32ZG_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_romtable.h index 3889b89e4d5..a2bd59691c5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_romtable.h * @brief EFM32ZG_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rtc.h index 39891b2828a..b416e788f16 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_rtc.h * @brief EFM32ZG_RTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer.h index abeb4b0d5c6..f8deabf05e8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_timer.h * @brief EFM32ZG_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer_cc.h index 349a3e8f377..fcba4a9e447 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_timer_cc.h * @brief EFM32ZG_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_usart.h index a381d739acc..4822e8ac6d1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_usart.h * @brief EFM32ZG_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_vcmp.h index e6b1024183f..49422aa8935 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_vcmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_vcmp.h * @brief EFM32ZG_VCMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_wdog.h index 2dccc0f0913..64dc1ce2dd8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_wdog.h * @brief EFM32ZG_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/em_device.h index a169e283f19..324adc04d0b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.c index 448c19d31bd..c8f986bbc10 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32zg.c * @brief CMSIS Cortex-M0+ System Layer for EFM32ZG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.h index 113a9d8ff5a..8a04a2638b0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file system_efm32zg.h * @brief CMSIS Cortex-M System Layer for EFM32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h index 93f25106394..13cbb9af1a0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h @@ -44,13 +44,14 @@ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ 0x142, /* Steady-state CTUNE for WSTK boards without load caps */ \ _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ - _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ - 0x7, /* Recommended steady-state XO core bias current */ \ + 0x20, /* Matching errata fix in CHIP_Init() */ \ + 0x7, /* Recommended steady-state osc core bias current */ \ 0x6, /* Recommended peak detection threshold */ \ _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \ 0xA, /* Recommended peak detection timeout */ \ - _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ + 0x4, /* Recommended steady timeout */ \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ } #endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_THUNDERBOARD_SENSE/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_THUNDERBOARD_SENSE/device_peripherals.h index 93f25106394..976dce7abac 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_THUNDERBOARD_SENSE/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_THUNDERBOARD_SENSE/device_peripherals.h @@ -42,7 +42,7 @@ false, /* Disable auto-select on EM0/1 entry */ \ false, /* Disable auto-start and select on RAC wakeup */ \ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ - 0x142, /* Steady-state CTUNE for WSTK boards without load caps */ \ + 0x142, /* Steady-state CTUNE for TBSENSE boards without load caps */ \ _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ 0x7, /* Recommended steady-state XO core bias current */ \ @@ -51,6 +51,7 @@ 0xA, /* Recommended peak detection timeout */ \ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ } #endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p131f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p131f256gm48.h index fbeb567812f..b45160a7a5c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p131f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p131f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p131f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P131F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P131F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gj43.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gj43.h index bb1ebb1e28e..91f10a5241d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gj43.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gj43.h @@ -2,10 +2,10 @@ * @file efr32mg1p132f256gj43.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P132F256GJ43 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P132F256GJ43) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm32.h index a54e8698540..6a70ce06396 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm32.h @@ -2,10 +2,10 @@ * @file efr32mg1p132f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P132F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P132F256GM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm48.h index f555d25c1f9..59ce0ef0860 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p132f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P132F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P132F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256im32.h index 79ef333565e..1198f133fb3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256im32.h @@ -2,10 +2,10 @@ * @file efr32mg1p132f256im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P132F256IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P132F256IM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p133f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p133f256gm48.h index 9dc9e77e70e..db738dc4e5e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p133f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p133f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p133f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P133F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P133F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p231f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p231f256gm48.h index ec17e343693..99508169f81 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p231f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p231f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p231f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P231F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P231F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gj43.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gj43.h index a980bde03cf..2042c752010 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gj43.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gj43.h @@ -2,10 +2,10 @@ * @file efr32mg1p232f256gj43.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P232F256GJ43 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P232F256GJ43) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm32.h index 97ae7baee22..4f1c91ae6c9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm32.h @@ -2,10 +2,10 @@ * @file efr32mg1p232f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P232F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P232F256GM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm48.h index d3d0349f726..84dc7417540 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p232f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P232F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P232F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p233f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p233f256gm48.h index efda4690cd4..ced9ab1ab43 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p233f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p233f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p233f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P233F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P233F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256gm32.h index d7cff49a0f3..d6acd3c29e7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256gm32.h @@ -2,10 +2,10 @@ * @file efr32mg1p632f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P632F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P632F256GM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256im32.h index c15b3a3cb82..0153e592f4f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256im32.h @@ -2,10 +2,10 @@ * @file efr32mg1p632f256im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P632F256IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P632F256IM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256gm32.h index bdb163d8844..3e6d47a1428 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256gm32.h @@ -2,10 +2,10 @@ * @file efr32mg1p732f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P732F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P732F256GM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256im32.h index ae2df0c68ef..088e6e01dc3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256im32.h @@ -2,10 +2,10 @@ * @file efr32mg1p732f256im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P732F256IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P732F256IM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_acmp.h index c0f3cfa4149..140119c6ac4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_acmp.h * @brief EFR32MG1P_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -329,8 +329,6 @@ typedef struct #define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ @@ -497,8 +495,6 @@ typedef struct #define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */ @@ -667,8 +663,6 @@ typedef struct #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ @@ -835,8 +829,6 @@ typedef struct #define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_adc.h index 5bc32c55c31..05a8d4f88f7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_adc.h * @brief EFR32MG1P_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_pins.h index a82b2d4a274..ea097badc0f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_af_pins.h * @brief EFR32MG1P_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_ports.h index c7b3bc3768d..eb85d8e5d56 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_af_ports.h * @brief EFR32MG1P_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cmu.h index 22185e0240c..7f00e1de505 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_cmu.h * @brief EFR32MG1P_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -56,8 +56,9 @@ typedef struct __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */ __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + __IOM uint32_t ULFRCOCTRL; /**< ULFRCO Control Register */ - uint32_t RESERVED3[5]; /**< Reserved for future use **/ + uint32_t RESERVED3[4]; /**< Reserved for future use **/ __IOM uint32_t CALCTRL; /**< Calibration Control Register */ __IOM uint32_t CALCNT; /**< Calibration Counter Register */ uint32_t RESERVED4[2]; /**< Reserved for future use **/ @@ -637,6 +638,30 @@ typedef struct #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ +/* Bit fields for CMU ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_RESETVALUE 0x00020020UL /**< Default value for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MASK 0x00030C3FUL /**< Mask for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_ULFRCOCTRL_TUNING_MASK 0x3FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_ULFRCOCTRL_TUNING_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_TUNING_DEFAULT (_CMU_ULFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_SHIFT 10 /**< Shift value for CMU_MODE */ +#define _CMU_ULFRCOCTRL_MODE_MASK 0xC00UL /**< Bit mask for CMU_MODE */ +#define _CMU_ULFRCOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_1KHZ 0x00000000UL /**< Mode 1KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_2KHZ 0x00000001UL /**< Mode 2KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_4KHZ 0x00000002UL /**< Mode 4KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_32KHZ 0x00000003UL /**< Mode 32KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_DEFAULT (_CMU_ULFRCOCTRL_MODE_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_1KHZ (_CMU_ULFRCOCTRL_MODE_1KHZ << 10) /**< Shifted mode 1KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_2KHZ (_CMU_ULFRCOCTRL_MODE_2KHZ << 10) /**< Shifted mode 2KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_4KHZ (_CMU_ULFRCOCTRL_MODE_4KHZ << 10) /**< Shifted mode 4KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_32KHZ (_CMU_ULFRCOCTRL_MODE_32KHZ << 10) /**< Shifted mode 32KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_RESTRIM_SHIFT 16 /**< Shift value for CMU_RESTRIM */ +#define _CMU_ULFRCOCTRL_RESTRIM_MASK 0x30000UL /**< Bit mask for CMU_RESTRIM */ +#define _CMU_ULFRCOCTRL_RESTRIM_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_RESTRIM_DEFAULT (_CMU_ULFRCOCTRL_RESTRIM_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ + /* Bit fields for CMU CALCTRL */ #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ #define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */ @@ -902,7 +927,7 @@ typedef struct /* Bit fields for CMU STATUS */ #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ -#define _CMU_STATUS_MASK 0x07C103FFUL /**< Mask for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x07E103FFUL /**< Mask for CMU_STATUS */ #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ @@ -958,6 +983,11 @@ typedef struct #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required by Hardware (e.g. RAC) */ +#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cryotimer.h index 9ca92fe4782..2ac2c092541 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cryotimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cryotimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_cryotimer.h * @brief EFR32MG1P_CRYOTIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_crypto.h index 3751bc35a14..f45bca536bd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_crypto.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_crypto.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_crypto.h * @brief EFR32MG1P_CRYPTO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -843,7 +843,7 @@ typedef struct /* Bit fields for CRYPTO IFS */ #define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */ -#define _CRYPTO_IFS_MASK 0x0000000FUL /**< Mask for CRYPTO_IFS */ +#define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */ #define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */ #define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -854,20 +854,10 @@ typedef struct #define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ #define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFOF (0x1UL << 2) /**< Set BUFOF Interrupt Flag */ -#define _CRYPTO_IFS_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IFS_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFOF_DEFAULT (_CRYPTO_IFS_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFUF (0x1UL << 3) /**< Set BUFUF Interrupt Flag */ -#define _CRYPTO_IFS_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IFS_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IFS_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFUF_DEFAULT (_CRYPTO_IFS_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IFS */ /* Bit fields for CRYPTO IFC */ #define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */ -#define _CRYPTO_IFC_MASK 0x0000000FUL /**< Mask for CRYPTO_IFC */ +#define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */ #define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */ #define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -878,20 +868,10 @@ typedef struct #define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ #define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFOF (0x1UL << 2) /**< Clear BUFOF Interrupt Flag */ -#define _CRYPTO_IFC_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IFC_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFOF_DEFAULT (_CRYPTO_IFC_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFUF (0x1UL << 3) /**< Clear BUFUF Interrupt Flag */ -#define _CRYPTO_IFC_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IFC_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IFC_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFUF_DEFAULT (_CRYPTO_IFC_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IFC */ /* Bit fields for CRYPTO IEN */ #define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */ -#define _CRYPTO_IEN_MASK 0x0000000FUL /**< Mask for CRYPTO_IEN */ +#define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */ #define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */ #define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -902,16 +882,6 @@ typedef struct #define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ #define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFOF (0x1UL << 2) /**< BUFOF Interrupt Enable */ -#define _CRYPTO_IEN_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IEN_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFOF_DEFAULT (_CRYPTO_IEN_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFUF (0x1UL << 3) /**< BUFUF Interrupt Enable */ -#define _CRYPTO_IEN_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IEN_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IEN_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFUF_DEFAULT (_CRYPTO_IEN_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IEN */ /* Bit fields for CRYPTO SEQ0 */ #define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_devinfo.h index 228a38ee4f1..2100aa44612 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_devinfo.h * @brief EFR32MG1P_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,8 +118,10 @@ typedef struct #define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */ #define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */ #define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */ #define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dma_descriptor.h index cd1750ba53d..c890c388dcd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_dma_descriptor.h * @brief EFR32MG1P_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dmareq.h index ade9e672811..8cbbfbba45b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_dmareq.h * @brief EFR32MG1P_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_emu.h index c02c75f48df..c6b30b1f5b2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_emu.h * @brief EFR32MG1P_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -63,24 +63,32 @@ typedef struct __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ - - uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ __IOM uint32_t DCDCTIMING; /**< DCDC Controller Timing Value Register */ __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ - uint32_t RESERVED3[1]; /**< Reserved for future use **/ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ - uint32_t RESERVED4[1]; /**< Reserved for future use **/ + uint32_t RESERVED3[1]; /**< Reserved for future use **/ __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ - uint32_t RESERVED5[5]; /**< Reserved for future use **/ + uint32_t RESERVED4[5]; /**< Reserved for future use **/ __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + + uint32_t RESERVED5[49]; /**< Reserved for future use **/ + __IOM uint32_t BIASCONF; /**< Configurations Related to the Bias */ + + uint32_t RESERVED6[10]; /**< Reserved for future use **/ + __IOM uint32_t TESTLOCK; /**< Test Lock Register */ + + uint32_t RESERVED7[2]; /**< Reserved for future use **/ + __IOM uint32_t BIASTESTCTRL; /**< Test Control Register for regulator and BIAS */ } EMU_TypeDef; /** @} */ /**************************************************************************//** @@ -351,7 +359,7 @@ typedef struct /* Bit fields for EMU IFS */ #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ -#define _EMU_IFS_MASK 0xE11FF0FFUL /**< Mask for EMU_IFS */ +#define _EMU_IFS_MASK 0xE11FC0FFUL /**< Mask for EMU_IFS */ #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -392,16 +400,6 @@ typedef struct #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDFALL (0x1UL << 12) /**< Set VMONPAVDDFALL Interrupt Flag */ -#define _EMU_IFS_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IFS_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IFS_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDFALL_DEFAULT (_EMU_IFS_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDRISE (0x1UL << 13) /**< Set VMONPAVDDRISE Interrupt Flag */ -#define _EMU_IFS_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IFS_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IFS_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDRISE_DEFAULT (_EMU_IFS_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -460,7 +458,7 @@ typedef struct /* Bit fields for EMU IFC */ #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ -#define _EMU_IFC_MASK 0xE11FF0FFUL /**< Mask for EMU_IFC */ +#define _EMU_IFC_MASK 0xE11FC0FFUL /**< Mask for EMU_IFC */ #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -501,16 +499,6 @@ typedef struct #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDFALL (0x1UL << 12) /**< Clear VMONPAVDDFALL Interrupt Flag */ -#define _EMU_IFC_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IFC_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IFC_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDFALL_DEFAULT (_EMU_IFC_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDRISE (0x1UL << 13) /**< Clear VMONPAVDDRISE Interrupt Flag */ -#define _EMU_IFC_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IFC_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IFC_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDRISE_DEFAULT (_EMU_IFC_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -569,7 +557,7 @@ typedef struct /* Bit fields for EMU IEN */ #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ -#define _EMU_IEN_MASK 0xE11FF0FFUL /**< Mask for EMU_IEN */ +#define _EMU_IEN_MASK 0xE11FC0FFUL /**< Mask for EMU_IEN */ #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -610,16 +598,6 @@ typedef struct #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDFALL (0x1UL << 12) /**< VMONPAVDDFALL Interrupt Enable */ -#define _EMU_IEN_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IEN_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IEN_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDFALL_DEFAULT (_EMU_IEN_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDRISE (0x1UL << 13) /**< VMONPAVDDRISE Interrupt Enable */ -#define _EMU_IEN_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IEN_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IEN_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDRISE_DEFAULT (_EMU_IEN_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -817,6 +795,34 @@ typedef struct #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + /* Bit fields for EMU DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ @@ -1035,6 +1041,65 @@ typedef struct #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +/* Bit fields for EMU BIASCONF */ +#define _EMU_BIASCONF_RESETVALUE 0x000000F8UL /**< Default value for EMU_BIASCONF */ +#define _EMU_BIASCONF_MASK 0x000000FCUL /**< Mask for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM01 (0x1UL << 2) /**< NA DUTY in EM01 */ +#define _EMU_BIASCONF_NADUTYEM01_SHIFT 2 /**< Shift value for EMU_NADUTYEM01 */ +#define _EMU_BIASCONF_NADUTYEM01_MASK 0x4UL /**< Bit mask for EMU_NADUTYEM01 */ +#define _EMU_BIASCONF_NADUTYEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM01_DEFAULT (_EMU_BIASCONF_NADUTYEM01_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM01 (0x1UL << 3) /**< LP in EM01 */ +#define _EMU_BIASCONF_LPEM01_SHIFT 3 /**< Shift value for EMU_LPEM01 */ +#define _EMU_BIASCONF_LPEM01_MASK 0x8UL /**< Bit mask for EMU_LPEM01 */ +#define _EMU_BIASCONF_LPEM01_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM01_DEFAULT (_EMU_BIASCONF_LPEM01_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_GMCEM23 (0x1UL << 4) /**< GMC in EM234 */ +#define _EMU_BIASCONF_GMCEM23_SHIFT 4 /**< Shift value for EMU_GMCEM23 */ +#define _EMU_BIASCONF_GMCEM23_MASK 0x10UL /**< Bit mask for EMU_GMCEM23 */ +#define _EMU_BIASCONF_GMCEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_GMCEM23_DEFAULT (_EMU_BIASCONF_GMCEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_UADUTYEM23 (0x1UL << 5) /**< UADUTY in EM234 */ +#define _EMU_BIASCONF_UADUTYEM23_SHIFT 5 /**< Shift value for EMU_UADUTYEM23 */ +#define _EMU_BIASCONF_UADUTYEM23_MASK 0x20UL /**< Bit mask for EMU_UADUTYEM23 */ +#define _EMU_BIASCONF_UADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_UADUTYEM23_DEFAULT (_EMU_BIASCONF_UADUTYEM23_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM23 (0x1UL << 6) /**< NA DUTY in EM234 */ +#define _EMU_BIASCONF_NADUTYEM23_SHIFT 6 /**< Shift value for EMU_NADUTYEM23 */ +#define _EMU_BIASCONF_NADUTYEM23_MASK 0x40UL /**< Bit mask for EMU_NADUTYEM23 */ +#define _EMU_BIASCONF_NADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM23_DEFAULT (_EMU_BIASCONF_NADUTYEM23_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM23 (0x1UL << 7) /**< LP in EM234 */ +#define _EMU_BIASCONF_LPEM23_SHIFT 7 /**< Shift value for EMU_LPEM23 */ +#define _EMU_BIASCONF_LPEM23_MASK 0x80UL /**< Bit mask for EMU_LPEM23 */ +#define _EMU_BIASCONF_LPEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM23_DEFAULT (_EMU_BIASCONF_LPEM23_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_BIASCONF */ + +/* Bit fields for EMU TESTLOCK */ +#define _EMU_TESTLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_TESTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_TESTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_DEFAULT (_EMU_TESTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_UNLOCKED (_EMU_TESTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_LOCKED (_EMU_TESTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_UNLOCK (_EMU_TESTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_TESTLOCK */ + +/* Bit fields for EMU BIASTESTCTRL */ +#define _EMU_BIASTESTCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BIASTESTCTRL */ +#define _EMU_BIASTESTCTRL_MASK 0x00000008UL /**< Mask for EMU_BIASTESTCTRL */ +#define EMU_BIASTESTCTRL_BIAS_RIP_RESET (0x1UL << 3) /**< Reset Bias Ripple Counter */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_SHIFT 3 /**< Shift value for EMU_BIAS_RIP_RESET */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_MASK 0x8UL /**< Bit mask for EMU_BIAS_RIP_RESET */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASTESTCTRL */ +#define EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT (_EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASTESTCTRL */ + /** @} End of group EFR32MG1P_EMU */ /** @} End of group Parts */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_fpueh.h index d684c508bc6..ff839cdc747 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_fpueh.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_fpueh.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_fpueh.h * @brief EFR32MG1P_FPUEH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpcrc.h index 0c32728539a..16b567fe477 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpcrc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpcrc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_gpcrc.h * @brief EFR32MG1P_GPCRC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio.h index 883f6473108..8311aa84a96 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_gpio.h * @brief EFR32MG1P_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio_p.h index 37a502a0134..93d08be621c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_gpio_p.h * @brief EFR32MG1P_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_i2c.h index 64544eede8c..b3709a685ec 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_i2c.h * @brief EFR32MG1P_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_idac.h index 9fe0848cef3..8e6e49e99fe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_idac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_idac.h * @brief EFR32MG1P_IDAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -43,7 +43,7 @@ typedef struct __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CURPROG; /**< Current Programming Register */ uint32_t RESERVED0[1]; /**< Reserved for future use **/ - __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configauration Register */ + __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */ uint32_t RESERVED1[2]; /**< Reserved for future use **/ __IM uint32_t STATUS; /**< Status Register */ @@ -259,12 +259,7 @@ typedef struct /* Bit fields for IDAC IFS */ #define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */ -#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */ -#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */ -#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ -#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */ +#define _IDAC_IFS_MASK 0x00000002UL /**< Mask for IDAC_IFS */ #define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */ #define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ @@ -273,12 +268,7 @@ typedef struct /* Bit fields for IDAC IFC */ #define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */ -#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */ -#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */ -#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ -#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */ +#define _IDAC_IFC_MASK 0x00000002UL /**< Mask for IDAC_IFC */ #define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */ #define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ @@ -287,12 +277,7 @@ typedef struct /* Bit fields for IDAC IEN */ #define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */ -#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */ -#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */ -#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ -#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */ +#define _IDAC_IEN_MASK 0x00000002UL /**< Mask for IDAC_IEN */ #define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */ #define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma.h index 053b0627384..8c9a3a21b0e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_ldma.h * @brief EFR32MG1P_LDMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma_ch.h index 607a8e9f7db..1153f0bb660 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_ldma_ch.h * @brief EFR32MG1P_LDMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_letimer.h index 29388ceca7c..a4111225011 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_letimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_letimer.h * @brief EFR32MG1P_LETIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_leuart.h index 8cc320cf8cb..b47c546f1a8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_leuart.h * @brief EFR32MG1P_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_msc.h index 10b477aa7a4..39503771f69 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_msc.h * @brief EFR32MG1P_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_pcnt.h index 738e0943a3f..cb803866c9c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_pcnt.h * @brief EFR32MG1P_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs.h index 89891796ee0..8d338b1b2a7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_prs.h * @brief EFR32MG1P_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -756,6 +756,7 @@ typedef struct #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ @@ -821,6 +822,7 @@ typedef struct #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ @@ -891,6 +893,7 @@ typedef struct #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x00000036UL /**< Mode PCNT0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000003CUL /**< Mode CRYOTIMER for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_CMU 0x0000003DUL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ @@ -908,6 +911,7 @@ typedef struct #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ #define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_ch.h index 3239628cdb3..2916bec5f20 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_prs_ch.h * @brief EFR32MG1P_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_signals.h index ce02dfe5aaa..d9ab908d297 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_prs_signals.h * @brief EFR32MG1P_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -103,6 +103,7 @@ #define PRS_CRYOTIMER_PERIOD ((60 << 8) + 0) /**< PRS CRYOTIMER Output */ #define PRS_CMU_CLKOUT0 ((61 << 8) + 0) /**< PRS Clock Output 0 */ #define PRS_CMU_CLKOUT1 ((61 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ /** @} End of group EFR32MG1P_PRS */ /** @} End of group Parts */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rmu.h index 4392cb0c2e6..2b5189d5cc8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_rmu.h * @brief EFR32MG1P_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_romtable.h index cc6596032c6..41b6623ed5b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_romtable.h * @brief EFR32MG1P_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc.h index 3d6098ac849..f33f3becd62 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_rtcc.h * @brief EFR32MG1P_RTCC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_cc.h index 4f5770110da..b29f210b14e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_rtcc_cc.h * @brief EFR32MG1P_RTCC_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_ret.h index 00e48da5ed2..f91263f96ca 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_ret.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_ret.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_rtcc_ret.h * @brief EFR32MG1P_RTCC_RET register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer.h index b58d22588c6..3711bedaa7b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_timer.h * @brief EFR32MG1P_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -188,7 +188,7 @@ typedef struct #define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ #define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Ouptut initial State */ +#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ #define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ #define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ #define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer_cc.h index 2122f93c21f..5b5b5a1835a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_timer_cc.h * @brief EFR32MG1P_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_usart.h index 60a3511217c..6992e704065 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_usart.h * @brief EFR32MG1P_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog.h index 27200c1f9d5..a1402e7cc9a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_wdog.h * @brief EFR32MG1P_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -215,17 +215,17 @@ typedef struct /* Bit fields for WDOG IF */ #define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ #define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ -#define WDOG_IF_TOUT (0x1UL << 0) /**< Wdog Timeout Interrupt Flag */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ #define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ #define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ #define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN (0x1UL << 1) /**< Wdog Warning Timeout Interrupt Flag */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ #define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ #define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ #define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN (0x1UL << 2) /**< Wdog Window Interrupt Flag */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ #define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ #define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ #define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog_pch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog_pch.h index 31a087d2fc8..5864e5e971e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog_pch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog_pch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_wdog_pch.h * @brief EFR32MG1P_WDOG_PCH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/em_device.h index 99afa55bc4f..2cc49181f7c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.c index ab75a311190..c909a8e8610 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efr32mg1p.c * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.h index 0df2036b78f..a9053e92f99 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efr32mg1p.h * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralNames.h new file mode 100644 index 00000000000..2e5170aef5f --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralNames.h @@ -0,0 +1,69 @@ +/***************************************************************************//** + * @file PeripheralNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "em_adc.h" +#include "em_usart.h" +#include "em_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_0 = ADC0_BASE +} ADCName; + +typedef enum { + I2C_0 = I2C0_BASE, + I2C_1 = I2C1_BASE, +} I2CName; + +typedef enum { + PWM_CH0 = 0, + PWM_CH1 = 1, + PWM_CH2 = 2, + PWM_CH3 = 3 +} PWMName; + +typedef enum { + USART_0 = USART0_BASE, + USART_1 = USART1_BASE, + USART_2 = USART2_BASE, + USART_3 = USART3_BASE, + LEUART_0 = LEUART0_BASE, +} UARTName; + +typedef enum { + SPI_0 = USART0_BASE, + SPI_1 = USART1_BASE, + SPI_2 = USART2_BASE, + SPI_3 = USART3_BASE, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.c new file mode 100644 index 00000000000..95baad0840a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.c @@ -0,0 +1,427 @@ +/***************************************************************************//** + * @file PeripheralPins.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "PeripheralPins.h" + +/************ADC***************/ +/* The third "function" value is used to select the correct ADC channel */ +const PinMap PinMap_ADC[] = { + {PA0, ADC_0, adcPosSelAPORT3XCH8}, + {PA1, ADC_0, adcPosSelAPORT4XCH9}, + {PA2, ADC_0, adcPosSelAPORT3XCH10}, + {PA3, ADC_0, adcPosSelAPORT4XCH11}, + {PA4, ADC_0, adcPosSelAPORT3XCH12}, + {PA5, ADC_0, adcPosSelAPORT4XCH13}, + + {PB11, ADC_0, adcPosSelAPORT4XCH27}, + {PB12, ADC_0, adcPosSelAPORT3XCH28}, + {PB14, ADC_0, adcPosSelAPORT3XCH30}, + {PB15, ADC_0, adcPosSelAPORT4XCH31}, + + {PC6, ADC_0, adcPosSelAPORT1XCH6}, + {PC7, ADC_0, adcPosSelAPORT2XCH7}, + {PC8, ADC_0, adcPosSelAPORT1XCH8}, + {PC9, ADC_0, adcPosSelAPORT2XCH9}, + {PC10, ADC_0, adcPosSelAPORT1XCH10}, + {PC11, ADC_0, adcPosSelAPORT2XCH11}, + + {PD9, ADC_0, adcPosSelAPORT4XCH1}, + {PD10, ADC_0, adcPosSelAPORT3XCH2}, + {PD11, ADC_0, adcPosSelAPORT3YCH3}, + {PD12, ADC_0, adcPosSelAPORT3XCH4}, + {PD13, ADC_0, adcPosSelAPORT3YCH5}, + {PD14, ADC_0, adcPosSelAPORT3XCH6}, + {PD15, ADC_0, adcPosSelAPORT4XCH7}, + + {PF0, ADC_0, adcPosSelAPORT1XCH16}, + {PF1, ADC_0, adcPosSelAPORT2XCH17}, + {PF2, ADC_0, adcPosSelAPORT1XCH18}, + {PF3, ADC_0, adcPosSelAPORT2XCH19}, + {PF4, ADC_0, adcPosSelAPORT1XCH20}, + {PF5, ADC_0, adcPosSelAPORT2XCH21}, + {PF6, ADC_0, adcPosSelAPORT1XCH22}, + {PF7, ADC_0, adcPosSelAPORT2XCH23}, + {NC , NC , NC} +}; + +/************I2C SCL***********/ +const PinMap PinMap_I2C_SCL[] = { + /* I2C0 */ + {PA1, I2C_0, 0}, + {PA2, I2C_0, 1}, + {PA3, I2C_0, 2}, + {PA4, I2C_0, 3}, + {PA5, I2C_0, 4}, + {PB11, I2C_0, 5}, + {PB12, I2C_0, 6}, + {PB13, I2C_0, 7}, + {PB14, I2C_0, 8}, + {PB15, I2C_0, 9}, + {PC6, I2C_0, 10}, + {PC7, I2C_0, 11}, + {PC8, I2C_0, 12}, + {PC9, I2C_0, 13}, + {PC10, I2C_0, 14}, + {PC11, I2C_0, 15}, + {PD9, I2C_0, 16}, + {PD10, I2C_0, 17}, + {PD11, I2C_0, 18}, + {PD12, I2C_0, 19}, + {PD13, I2C_0, 20}, + {PD14, I2C_0, 21}, + {PD15, I2C_0, 22}, + {PF0, I2C_0, 23}, + {PF1, I2C_0, 24}, + {PF2, I2C_0, 25}, + {PF3, I2C_0, 26}, + {PF4, I2C_0, 27}, + {PF5, I2C_0, 28}, + {PF6, I2C_0, 29}, + {PF7, I2C_0, 30}, + {PA0, I2C_0, 31}, + + {NC , NC , NC} +}; + +/************I2C SDA***********/ +const PinMap PinMap_I2C_SDA[] = { + /* I2C0 */ + {PA0, I2C_0, 0}, + {PA1, I2C_0, 1}, + {PA2, I2C_0, 2}, + {PA3, I2C_0, 3}, + {PA4, I2C_0, 4}, + {PA5, I2C_0, 5}, + {PB11, I2C_0, 6}, + {PB12, I2C_0, 7}, + {PB13, I2C_0, 8}, + {PB14, I2C_0, 9}, + {PB15, I2C_0, 10}, + {PC6, I2C_0, 11}, + {PC7, I2C_0, 12}, + {PC8, I2C_0, 13}, + {PC9, I2C_0, 14}, + {PC10, I2C_0, 15}, + {PC11, I2C_0, 16}, + {PD9, I2C_0, 17}, + {PD10, I2C_0, 18}, + {PD11, I2C_0, 19}, + {PD12, I2C_0, 20}, + {PD13, I2C_0, 21}, + {PD14, I2C_0, 22}, + {PD15, I2C_0, 23}, + {PF0, I2C_0, 24}, + {PF1, I2C_0, 25}, + {PF2, I2C_0, 26}, + {PF3, I2C_0, 27}, + {PF4, I2C_0, 28}, + {PF5, I2C_0, 29}, + {PF6, I2C_0, 30}, + {PF7, I2C_0, 31}, + + /* Not connected */ + {NC , NC , NC} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PA0, PWM_CH0, 0}, + {PA1, PWM_CH1, 0}, + {PA2, PWM_CH2, 0}, + {PA3, PWM_CH3, 0}, + {PA4, PWM_CH2, 2}, + {PA5, PWM_CH3, 2}, + {PB11, PWM_CH1, 5}, + {PB12, PWM_CH2, 5}, + {PB13, PWM_CH3, 5}, + {PB14, PWM_CH0, 9}, + {PB15, PWM_CH0, 10}, + {PC6, PWM_CH0, 11}, + {PC7, PWM_CH1, 11}, + {PC8, PWM_CH2, 11}, + {PC9, PWM_CH3, 11}, + {PC10, PWM_CH2, 13}, + {PC11, PWM_CH3, 13}, + {PD9, PWM_CH3, 14}, + {PD10, PWM_CH0, 18}, + {PD11, PWM_CH1, 18}, + {PD12, PWM_CH2, 18}, + {PD13, PWM_CH3, 18}, + {PD14, PWM_CH0, 22}, + {PD15, PWM_CH1, 22}, + {PF0, PWM_CH0, 24}, + {PF1, PWM_CH1, 24}, + {PF2, PWM_CH2, 24}, + {PF3, PWM_CH3, 24}, + {PF4, PWM_CH0, 28}, + {PF5, PWM_CH1, 28}, + {PF6, PWM_CH2, 28}, + {PF7, PWM_CH3, 28}, + + {NC , NC , NC} +}; + +/*************SPI**************/ +const PinMap PinMap_SPI_MOSI[] = { + + /* USART0 */ + {PA0, SPI_0, 0}, + {PA1, SPI_0, 1}, + {PA2, SPI_0, 2}, + {PA3, SPI_0, 3}, + {PA4, SPI_0, 4}, + {PA5, SPI_0, 5}, + {PB11, SPI_0, 6}, + {PB12, SPI_0, 7}, + {PB13, SPI_0, 8}, + {PB14, SPI_0, 9}, + {PB15, SPI_0, 10}, + {PD9, SPI_0, 17}, + {PD10, SPI_0, 18}, + {PD11, SPI_0, 19}, + {PD12, SPI_0, 20}, + {PD13, SPI_0, 21}, + {PD14, SPI_0, 22}, + {PD15, SPI_0, 23}, + + /* USART1 */ + {PC6, SPI_1, 11}, + {PC7, SPI_1, 12}, + {PC8, SPI_1, 13}, + {PC9, SPI_1, 14}, + {PC10, SPI_1, 15}, + {PC11, SPI_1, 16}, + {PF0, SPI_1, 24}, + {PF1, SPI_1, 25}, + {PF2, SPI_1, 26}, + {PF3, SPI_1, 27}, + {PF4, SPI_1, 28}, + {PF5, SPI_1, 29}, + {PF6, SPI_1, 30}, + {PF7, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_MISO[] = { + + /* USART0 */ + {PA0, SPI_0, 31}, + {PA1, SPI_0, 0}, + {PA2, SPI_0, 1}, + {PA3, SPI_0, 2}, + {PA4, SPI_0, 3}, + {PA5, SPI_0, 4}, + {PB11, SPI_0, 5}, + {PB12, SPI_0, 6}, + {PB13, SPI_0, 7}, + {PB14, SPI_0, 8}, + {PB15, SPI_0, 9}, + {PD9, SPI_0, 16}, + {PD10, SPI_0, 17}, + {PD11, SPI_0, 18}, + {PD12, SPI_0, 19}, + {PD13, SPI_0, 20}, + {PD14, SPI_0, 21}, + {PD15, SPI_0, 22}, + + /* USART1 */ + {PC6, SPI_1, 10}, + {PC7, SPI_1, 11}, + {PC8, SPI_1, 12}, + {PC9, SPI_1, 13}, + {PC10, SPI_1, 14}, + {PC11, SPI_1, 15}, + {PF0, SPI_1, 23}, + {PF1, SPI_1, 24}, + {PF2, SPI_1, 25}, + {PF3, SPI_1, 26}, + {PF4, SPI_1, 27}, + {PF5, SPI_1, 28}, + {PF6, SPI_1, 29}, + {PF7, SPI_1, 30}, + {PA0, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_CLK[] = { + + /* USART0 */ + {PA0, SPI_0, 30}, + {PA1, SPI_0, 31}, + {PA2, SPI_0, 0}, + {PA3, SPI_0, 1}, + {PA4, SPI_0, 2}, + {PA5, SPI_0, 3}, + {PB11, SPI_0, 4}, + {PB12, SPI_0, 5}, + {PB13, SPI_0, 6}, + {PB14, SPI_0, 7}, + {PB15, SPI_0, 8}, + {PD9, SPI_0, 15}, + {PD10, SPI_0, 16}, + {PD11, SPI_0, 17}, + {PD12, SPI_0, 18}, + {PD13, SPI_0, 19}, + {PD14, SPI_0, 20}, + {PD15, SPI_0, 21}, + + /* USART1 */ + {PC6, SPI_1, 9}, + {PC7, SPI_1, 10}, + {PC8, SPI_1, 11}, + {PC9, SPI_1, 12}, + {PC10, SPI_1, 13}, + {PC11, SPI_1, 14}, + {PF0, SPI_1, 22}, + {PF1, SPI_1, 23}, + {PF2, SPI_1, 24}, + {PF3, SPI_1, 25}, + {PF4, SPI_1, 26}, + {PF5, SPI_1, 27}, + {PF6, SPI_1, 28}, + {PF7, SPI_1, 29}, + {PA0, SPI_1, 30}, + {PA1, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_CS[] = { + + /* USART0 */ + {PA0, SPI_0, 29}, + {PA1, SPI_0, 30}, + {PA2, SPI_0, 31}, + {PA3, SPI_0, 0}, + {PA4, SPI_0, 1}, + {PA5, SPI_0, 2}, + {PB11, SPI_0, 3}, + {PB12, SPI_0, 4}, + {PB13, SPI_0, 5}, + {PB14, SPI_0, 6}, + {PB15, SPI_0, 7}, + {PD9, SPI_0, 14}, + {PD10, SPI_0, 15}, + {PD11, SPI_0, 16}, + {PD12, SPI_0, 17}, + {PD13, SPI_0, 18}, + {PD14, SPI_0, 19}, + {PD15, SPI_0, 20}, + + /* USART1 */ + {PC6, SPI_1, 8}, + {PC7, SPI_1, 9}, + {PC8, SPI_1, 10}, + {PC9, SPI_1, 11}, + {PC10, SPI_1, 12}, + {PC11, SPI_1, 13}, + {PF0, SPI_1, 21}, + {PF1, SPI_1, 22}, + {PF2, SPI_1, 23}, + {PF3, SPI_1, 24}, + {PF4, SPI_1, 25}, + {PF5, SPI_1, 26}, + {PF6, SPI_1, 27}, + {PF7, SPI_1, 28}, + + {NC , NC , NC} +}; + +/************UART**************/ +const PinMap PinMap_UART_TX[] = { + {PA0, USART_0, 0}, + {PA1, USART_0, 1}, + {PA2, USART_0, 2}, + {PA3, USART_0, 3}, + {PA4, USART_0, 4}, + {PA5, USART_0, 5}, + {PB11, USART_0, 6}, + {PB12, USART_0, 7}, + {PB13, USART_0, 8}, + {PB14, USART_0, 9}, + {PB15, USART_0, 10}, + {PD9, LEUART_0, 17}, + {PD10, LEUART_0, 18}, + {PD11, LEUART_0, 19}, + {PD12, LEUART_0, 20}, + {PD13, LEUART_0, 21}, + {PD14, LEUART_0, 22}, + {PD15, LEUART_0, 23}, + + {PC6, USART_1, 11}, + {PC7, USART_1, 12}, + {PC8, USART_1, 13}, + {PC9, USART_1, 14}, + {PC10, USART_1, 15}, + {PC11, USART_1, 16}, + {PF0, USART_1, 24}, + {PF1, USART_1, 25}, + {PF2, USART_1, 26}, + {PF3, USART_1, 27}, + {PF4, USART_1, 28}, + {PF5, USART_1, 29}, + {PF6, USART_1, 30}, + {PF7, USART_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_UART_RX[] = { + {PA0, USART_0, 31}, + {PA1, USART_0, 0}, + {PA2, USART_0, 1}, + {PA3, USART_0, 2}, + {PA4, USART_0, 3}, + {PA5, USART_0, 4}, + {PB11, USART_0, 5}, + {PB12, USART_0, 6}, + {PB13, USART_0, 7}, + {PB14, USART_0, 8}, + {PB15, USART_0, 9}, + {PD9, LEUART_0, 16}, + {PD10, LEUART_0, 17}, + {PD11, LEUART_0, 18}, + {PD12, LEUART_0, 19}, + {PD13, LEUART_0, 20}, + {PD14, LEUART_0, 21}, + {PD15, LEUART_0, 22}, + + {PC6, USART_1, 10}, + {PC7, USART_1, 11}, + {PC8, USART_1, 12}, + {PC9, USART_1, 13}, + {PC10, USART_1, 14}, + {PC11, USART_1, 15}, + {PF0, USART_1, 23}, + {PF1, USART_1, 24}, + {PF2, USART_1, 25}, + {PF3, USART_1, 26}, + {PF4, USART_1, 27}, + {PF5, USART_1, 28}, + {PF6, USART_1, 29}, + {PF7, USART_1, 30}, + + {NC , NC , NC} +}; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.h new file mode 100644 index 00000000000..79d6072e833 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file PeripheralPins.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************I2C SCL***********/ +extern const PinMap PinMap_I2C_SCL[]; + +/************I2C SDA***********/ +extern const PinMap PinMap_I2C_SDA[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_CLK[]; +extern const PinMap PinMap_SPI_CS[]; + +/************UART**************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +#endif + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/PinNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/PinNames.h new file mode 100644 index 00000000000..a56373d4d9e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/PinNames.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file PinNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "CommonPinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + EFM32_STANDARD_PIN_DEFINITIONS, + + /* Starter Kit says LED0 and LED1, but mbed expects 1 and 2. This way using 1 and 2 or 0 and 1 will work. */ + LED0 = PD8, + LED1 = PD9, + LED2 = LED0, + LED3 = LED0, + LED4 = LED1, + + /* Push Buttons */ + SW0 = PD14, + SW1 = PD15, + BTN0 = SW0, + BTN1 = SW1, + + /* Expansion headers */ + EXP3 = PA8, + EXP4 = PC6, + EXP5 = PA9, + EXP6 = PC7, + EXP7 = PF3, + EXP8 = PC8, + EXP9 = PF4, + EXP10 = PC9, + EXP11 = PF5, + EXP12 = PA6, + EXP13 = PF6, + EXP14 = PA7, + EXP15 = PC11, + EXP16 = PC10, + + /* Serial (just some usable pins) */ + SERIAL_TX = PA6, + SERIAL_RX = PA7, + + /* Board Controller UART (USB)*/ + USBTX = PA0, + USBRX = PA1, + + /* Board Controller */ + STDIO_UART_TX = USBTX, + STDIO_UART_RX = USBRX +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/device_peripherals.h new file mode 100644 index 00000000000..976dce7abac --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/device_peripherals.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file device_peripherals.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_DEVICE_PERIPHERALS_H +#define MBED_DEVICE_PERIPHERALS_H + +/* us ticker */ +#define US_TICKER_TIMER TIMER0 +#define US_TICKER_TIMER_CLOCK cmuClock_TIMER0 +#define US_TICKER_TIMER_IRQ TIMER0_IRQn + +/* PWM */ +#define PWM_TIMER TIMER1 +#define PWM_TIMER_CLOCK cmuClock_TIMER1 +#define PWM_ROUTE TIMER_ROUTE_LOCATION_LOC1 + +/* Crystal calibration */ +#if !defined(CMU_HFXOINIT_WSTK_DEFAULT) +#define CMU_HFXOINIT_WSTK_DEFAULT \ +{ \ + false, /* Low-noise mode for EFR32 */ \ + false, /* Disable auto-start on EM0/1 entry */ \ + false, /* Disable auto-select on EM0/1 entry */ \ + false, /* Disable auto-start and select on RAC wakeup */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + 0x142, /* Steady-state CTUNE for TBSENSE boards without load caps */ \ + _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ + _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ + 0x7, /* Recommended steady-state XO core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \ + 0xA, /* Recommended peak detection timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ +} +#endif +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct new file mode 100644 index 00000000000..19a1e790859 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00100000 { ; load region size_region + ER_IROM1 0x00000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x2000010C 0x0003FEF4 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/startup_efr32mg12p.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/startup_efr32mg12p.S new file mode 100644 index 00000000000..514135d4d6a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/startup_efr32mg12p.S @@ -0,0 +1,320 @@ +;/**************************************************************************//** +; * @file startup_efr32mg1p.s +; * @brief CMSIS Core Device Startup File for +; * Silicon Labs EFR32MG1P Device Series +; * @version 4.3.0 +; * @date 03. February 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00010000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY, ALIGN=8 + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD FRC_IRQHandler ; 4: FRC Interrupt + DCD MODEM_IRQHandler ; 5: MODEM Interrupt + DCD RAC_SEQ_IRQHandler ; 6: RAC_SEQ Interrupt + DCD RAC_RSM_IRQHandler ; 7: RAC_RSM Interrupt + DCD BUFC_IRQHandler ; 8: BUFC Interrupt + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD AGC_IRQHandler ; 28: AGC Interrupt + DCD PROTIMER_IRQHandler ; 29: PROTIMER Interrupt + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD SYNTH_IRQHandler ; 31: SYNTH Interrupt + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD RFSENSE_IRQHandler ; 33: RFSENSE Interrupt + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved + +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT EMU_IRQHandler [WEAK] + EXPORT FRC_PRI_IRQHandler [WEAK] + EXPORT WDOG0_IRQHandler [WEAK] + EXPORT WDOG1_IRQHandler [WEAK] + EXPORT FRC_IRQHandler [WEAK] + EXPORT MODEM_IRQHandler [WEAK] + EXPORT RAC_SEQ_IRQHandler [WEAK] + EXPORT RAC_RSM_IRQHandler [WEAK] + EXPORT BUFC_IRQHandler [WEAK] + EXPORT LDMA_IRQHandler [WEAK] + EXPORT GPIO_EVEN_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT USART0_RX_IRQHandler [WEAK] + EXPORT USART0_TX_IRQHandler [WEAK] + EXPORT ACMP0_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT IDAC0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT GPIO_ODD_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT USART1_RX_IRQHandler [WEAK] + EXPORT USART1_TX_IRQHandler [WEAK] + EXPORT LEUART0_IRQHandler [WEAK] + EXPORT PCNT0_IRQHandler [WEAK] + EXPORT CMU_IRQHandler [WEAK] + EXPORT MSC_IRQHandler [WEAK] + EXPORT CRYPTO0_IRQHandler [WEAK] + EXPORT LETIMER0_IRQHandler [WEAK] + EXPORT AGC_IRQHandler [WEAK] + EXPORT PROTIMER_IRQHandler [WEAK] + EXPORT RTCC_IRQHandler [WEAK] + EXPORT SYNTH_IRQHandler [WEAK] + EXPORT CRYOTIMER_IRQHandler [WEAK] + EXPORT RFSENSE_IRQHandler [WEAK] + EXPORT FPUEH_IRQHandler [WEAK] + EXPORT SMU_IRQHandler [WEAK] + EXPORT WTIMER0_IRQHandler [WEAK] + EXPORT WTIMER1_IRQHandler [WEAK] + EXPORT PCNT1_IRQHandler [WEAK] + EXPORT PCNT2_IRQHandler [WEAK] + EXPORT USART2_RX_IRQHandler [WEAK] + EXPORT USART2_TX_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT USART3_RX_IRQHandler [WEAK] + EXPORT USART3_TX_IRQHandler [WEAK] + EXPORT VDAC0_IRQHandler [WEAK] + EXPORT CSEN_IRQHandler [WEAK] + EXPORT LESENSE_IRQHandler [WEAK] + EXPORT CRYPTO1_IRQHandler [WEAK] + EXPORT TRNG0_IRQHandler [WEAK] + + +EMU_IRQHandler +FRC_PRI_IRQHandler +WDOG0_IRQHandler +WDOG1_IRQHandler +FRC_IRQHandler +MODEM_IRQHandler +RAC_SEQ_IRQHandler +RAC_RSM_IRQHandler +BUFC_IRQHandler +LDMA_IRQHandler +GPIO_EVEN_IRQHandler +TIMER0_IRQHandler +USART0_RX_IRQHandler +USART0_TX_IRQHandler +ACMP0_IRQHandler +ADC0_IRQHandler +IDAC0_IRQHandler +I2C0_IRQHandler +GPIO_ODD_IRQHandler +TIMER1_IRQHandler +USART1_RX_IRQHandler +USART1_TX_IRQHandler +LEUART0_IRQHandler +PCNT0_IRQHandler +CMU_IRQHandler +MSC_IRQHandler +CRYPTO0_IRQHandler +LETIMER0_IRQHandler +AGC_IRQHandler +PROTIMER_IRQHandler +RTCC_IRQHandler +SYNTH_IRQHandler +CRYOTIMER_IRQHandler +RFSENSE_IRQHandler +FPUEH_IRQHandler +SMU_IRQHandler +WTIMER0_IRQHandler +WTIMER1_IRQHandler +PCNT1_IRQHandler +PCNT2_IRQHandler +USART2_RX_IRQHandler +USART2_TX_IRQHandler +I2C1_IRQHandler +USART3_RX_IRQHandler +USART3_TX_IRQHandler +VDAC0_IRQHandler +CSEN_IRQHandler +LESENSE_IRQHandler +CRYPTO1_IRQHandler +TRNG0_IRQHandler + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld new file mode 100644 index 00000000000..cf057464308 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld @@ -0,0 +1,215 @@ +/* Linker script for Silicon Labs EFR32MG1P devices */ +/* */ +/* This file is subject to the license terms as defined in ARM's */ +/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of */ +/* Example Code. */ +/* */ +/* Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com */ +/* */ +/* Version 4.3.0 */ +/* */ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 262144 +} + +/* MBED: mbed needs to be able to dynamically set the interrupt vector table. + * We make room for the table at the very beginning of RAM, i.e. at + * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 bytes for EFM32PG */ +__vector_size = 0x10C; + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + PROVIDE( __start_vector_table__ = .); + . += __vector_size; + PROVIDE( __end_vector_table__ = .); + *(vtable) + *(.data*) + . = ALIGN (4); + *(.ram) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if FLASH usage exceeds FLASH size */ + ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") +} diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/startup_efr32mg12p.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/startup_efr32mg12p.S new file mode 100644 index 00000000000..e0a9c7d7008 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/startup_efr32mg12p.S @@ -0,0 +1,360 @@ +/* @file startup_efr32mg1p.S + * @brief startup file for Silicon Labs EFR32MG1P devices. + * For use with GCC for ARM Embedded Processors + * @version 4.3.0 + * Date: 12 June 2014 + * + */ +/* Copyright (c) 2011 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + .syntax unified + .arch armv7-m + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00004000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00010000 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long Default_Handler /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long EMU_IRQHandler /* 0 - EMU */ + .long FRC_PRI_IRQHandler /* 1 - FRC_PRI */ + .long WDOG0_IRQHandler /* 2 - WDOG0 */ + .long WDOG1_IRQHandler /* 3 - WDOG1 */ + .long FRC_IRQHandler /* 4 - FRC */ + .long MODEM_IRQHandler /* 5 - MODEM */ + .long RAC_SEQ_IRQHandler /* 6 - RAC_SEQ */ + .long RAC_RSM_IRQHandler /* 7 - RAC_RSM */ + .long BUFC_IRQHandler /* 8 - BUFC */ + .long LDMA_IRQHandler /* 9 - LDMA */ + .long GPIO_EVEN_IRQHandler /* 10 - GPIO_EVEN */ + .long TIMER0_IRQHandler /* 11 - TIMER0 */ + .long USART0_RX_IRQHandler /* 12 - USART0_RX */ + .long USART0_TX_IRQHandler /* 13 - USART0_TX */ + .long ACMP0_IRQHandler /* 14 - ACMP0 */ + .long ADC0_IRQHandler /* 15 - ADC0 */ + .long IDAC0_IRQHandler /* 16 - IDAC0 */ + .long I2C0_IRQHandler /* 17 - I2C0 */ + .long GPIO_ODD_IRQHandler /* 18 - GPIO_ODD */ + .long TIMER1_IRQHandler /* 19 - TIMER1 */ + .long USART1_RX_IRQHandler /* 20 - USART1_RX */ + .long USART1_TX_IRQHandler /* 21 - USART1_TX */ + .long LEUART0_IRQHandler /* 22 - LEUART0 */ + .long PCNT0_IRQHandler /* 23 - PCNT0 */ + .long CMU_IRQHandler /* 24 - CMU */ + .long MSC_IRQHandler /* 25 - MSC */ + .long CRYPTO0_IRQHandler /* 26 - CRYPTO0 */ + .long LETIMER0_IRQHandler /* 27 - LETIMER0 */ + .long AGC_IRQHandler /* 28 - AGC */ + .long PROTIMER_IRQHandler /* 29 - PROTIMER */ + .long RTCC_IRQHandler /* 30 - RTCC */ + .long SYNTH_IRQHandler /* 31 - SYNTH */ + .long CRYOTIMER_IRQHandler /* 32 - CRYOTIMER */ + .long RFSENSE_IRQHandler /* 33 - RFSENSE */ + .long FPUEH_IRQHandler /* 34 - FPUEH */ + .long SMU_IRQHandler /* 35 - SMU */ + .long WTIMER0_IRQHandler /* 36 - WTIMER0 */ + .long WTIMER1_IRQHandler /* 37 - WTIMER1 */ + .long PCNT1_IRQHandler /* 38 - PCNT1 */ + .long PCNT2_IRQHandler /* 39 - PCNT2 */ + .long USART2_RX_IRQHandler /* 40 - USART2_RX */ + .long USART2_TX_IRQHandler /* 41 - USART2_TX */ + .long I2C1_IRQHandler /* 42 - I2C1 */ + .long USART3_RX_IRQHandler /* 43 - USART3_RX */ + .long USART3_TX_IRQHandler /* 44 - USART3_TX */ + .long VDAC0_IRQHandler /* 45 - VDAC0 */ + .long CSEN_IRQHandler /* 46 - CSEN */ + .long LESENSE_IRQHandler /* 47 - LESENSE */ + .long CRYPTO1_IRQHandler /* 48 - CRYPTO1 */ + .long TRNG0_IRQHandler /* 49 - TRNG0 */ + .long Default_Handler /* 50 - Reserved */ + + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +#ifndef __NO_SYSTEM_INIT + ldr r0, =SystemInit + blx r0 +#endif + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + + def_irq_handler EMU_IRQHandler + def_irq_handler FRC_PRI_IRQHandler + def_irq_handler WDOG0_IRQHandler + def_irq_handler WDOG1_IRQHandler + def_irq_handler FRC_IRQHandler + def_irq_handler MODEM_IRQHandler + def_irq_handler RAC_SEQ_IRQHandler + def_irq_handler RAC_RSM_IRQHandler + def_irq_handler BUFC_IRQHandler + def_irq_handler LDMA_IRQHandler + def_irq_handler GPIO_EVEN_IRQHandler + def_irq_handler TIMER0_IRQHandler + def_irq_handler USART0_RX_IRQHandler + def_irq_handler USART0_TX_IRQHandler + def_irq_handler ACMP0_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler IDAC0_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler GPIO_ODD_IRQHandler + def_irq_handler TIMER1_IRQHandler + def_irq_handler USART1_RX_IRQHandler + def_irq_handler USART1_TX_IRQHandler + def_irq_handler LEUART0_IRQHandler + def_irq_handler PCNT0_IRQHandler + def_irq_handler CMU_IRQHandler + def_irq_handler MSC_IRQHandler + def_irq_handler CRYPTO0_IRQHandler + def_irq_handler LETIMER0_IRQHandler + def_irq_handler AGC_IRQHandler + def_irq_handler PROTIMER_IRQHandler + def_irq_handler RTCC_IRQHandler + def_irq_handler SYNTH_IRQHandler + def_irq_handler CRYOTIMER_IRQHandler + def_irq_handler RFSENSE_IRQHandler + def_irq_handler FPUEH_IRQHandler + def_irq_handler SMU_IRQHandler + def_irq_handler WTIMER0_IRQHandler + def_irq_handler WTIMER1_IRQHandler + def_irq_handler PCNT1_IRQHandler + def_irq_handler PCNT2_IRQHandler + def_irq_handler USART2_RX_IRQHandler + def_irq_handler USART2_TX_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler USART3_RX_IRQHandler + def_irq_handler USART3_TX_IRQHandler + def_irq_handler VDAC0_IRQHandler + def_irq_handler CSEN_IRQHandler + def_irq_handler LESENSE_IRQHandler + def_irq_handler CRYPTO1_IRQHandler + def_irq_handler TRNG0_IRQHandler + + .end diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf new file mode 100644 index 00000000000..a40090df01c --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x2000010B; +define symbol __ICFEDIT_region_RAM_start__ = 0x2000010C; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +/*-Sizes-*/ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __ICFEDIT_size_cstack__ = 0x4000; +define symbol __ICFEDIT_size_heap__ = 0x10000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; + \ No newline at end of file diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.s new file mode 100644 index 00000000000..2cb725593b6 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.s @@ -0,0 +1,451 @@ +;/**************************************************************************//** +; * @file startup_efr32mg12p.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFR32MG12P Device Series +; * @version 5.1.2 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD FRC_IRQHandler ; 4: FRC Interrupt + DCD MODEM_IRQHandler ; 5: MODEM Interrupt + DCD RAC_SEQ_IRQHandler ; 6: RAC_SEQ Interrupt + DCD RAC_RSM_IRQHandler ; 7: RAC_RSM Interrupt + DCD BUFC_IRQHandler ; 8: BUFC Interrupt + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD AGC_IRQHandler ; 28: AGC Interrupt + DCD PROTIMER_IRQHandler ; 29: PROTIMER Interrupt + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD SYNTH_IRQHandler ; 31: SYNTH Interrupt + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD RFSENSE_IRQHandler ; 33: RFSENSE Interrupt + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved Interrupt + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK FRC_PRI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_PRI_IRQHandler + B FRC_PRI_IRQHandler + + PUBWEAK WDOG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG0_IRQHandler + B WDOG0_IRQHandler + + PUBWEAK WDOG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG1_IRQHandler + B WDOG1_IRQHandler + + PUBWEAK FRC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_IRQHandler + B FRC_IRQHandler + + PUBWEAK MODEM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MODEM_IRQHandler + B MODEM_IRQHandler + + PUBWEAK RAC_SEQ_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_SEQ_IRQHandler + B RAC_SEQ_IRQHandler + + PUBWEAK RAC_RSM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_RSM_IRQHandler + B RAC_RSM_IRQHandler + + PUBWEAK BUFC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BUFC_IRQHandler + B BUFC_IRQHandler + + PUBWEAK LDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LDMA_IRQHandler + B LDMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK IDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IDAC0_IRQHandler + B IDAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK CRYPTO0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO0_IRQHandler + B CRYPTO0_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK AGC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AGC_IRQHandler + B AGC_IRQHandler + + PUBWEAK PROTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PROTIMER_IRQHandler + B PROTIMER_IRQHandler + + PUBWEAK RTCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCC_IRQHandler + B RTCC_IRQHandler + + PUBWEAK SYNTH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SYNTH_IRQHandler + B SYNTH_IRQHandler + + PUBWEAK CRYOTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYOTIMER_IRQHandler + B CRYOTIMER_IRQHandler + + PUBWEAK RFSENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RFSENSE_IRQHandler + B RFSENSE_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + PUBWEAK SMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SMU_IRQHandler + B SMU_IRQHandler + + PUBWEAK WTIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER0_IRQHandler + B WTIMER0_IRQHandler + + PUBWEAK WTIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER1_IRQHandler + B WTIMER1_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK USART3_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_RX_IRQHandler + B USART3_RX_IRQHandler + + PUBWEAK USART3_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_TX_IRQHandler + B USART3_TX_IRQHandler + + PUBWEAK VDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VDAC0_IRQHandler + B VDAC0_IRQHandler + + PUBWEAK CSEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CSEN_IRQHandler + B CSEN_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK CRYPTO1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO1_IRQHandler + B CRYPTO1_IRQHandler + + PUBWEAK TRNG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TRNG0_IRQHandler + B TRNG0_IRQHandler + + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gl125.h new file mode 100644 index 00000000000..5ba18370a80 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gl125.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p132f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P132F1024GL125 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P132F1024GL125_H +#define EFR32MG12P132F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125 EFR32MG12P132F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Core EFR32MG12P132F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P132F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P132F1024GL125_Part EFR32MG12P132F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P132F1024GL125) +#define EFR32MG12P132F1024GL125 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P132F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P132F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P132F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Peripheral_TypeDefs EFR32MG12P132F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P132F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Peripheral_Base EFR32MG12P132F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P132F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Peripheral_Declaration EFR32MG12P132F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P132F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Peripheral_Offsets EFR32MG12P132F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P132F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_BitFields EFR32MG12P132F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_WTIMER_BitFields EFR32MG12P132F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P132F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_SYSTICK_BitFields EFR32MG12P132F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P132F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_UNLOCK EFR32MG12P132F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P132F1024GL125_UNLOCK */ + +/** @} End of group EFR32MG12P132F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Alternate_Function EFR32MG12P132F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P132F1024GL125_Alternate_Function */ + +/** @} End of group EFR32MG12P132F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P132F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gm48.h new file mode 100644 index 00000000000..b012dd912af --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gm48.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p132f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P132F1024GM48 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P132F1024GM48_H +#define EFR32MG12P132F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48 EFR32MG12P132F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Core EFR32MG12P132F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P132F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P132F1024GM48_Part EFR32MG12P132F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P132F1024GM48) +#define EFR32MG12P132F1024GM48 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P132F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P132F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P132F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Peripheral_TypeDefs EFR32MG12P132F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P132F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Peripheral_Base EFR32MG12P132F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P132F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Peripheral_Declaration EFR32MG12P132F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P132F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Peripheral_Offsets EFR32MG12P132F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P132F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_BitFields EFR32MG12P132F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_WTIMER_BitFields EFR32MG12P132F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P132F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_SYSTICK_BitFields EFR32MG12P132F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P132F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_UNLOCK EFR32MG12P132F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P132F1024GM48_UNLOCK */ + +/** @} End of group EFR32MG12P132F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Alternate_Function EFR32MG12P132F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P132F1024GM48_Alternate_Function */ + +/** @} End of group EFR32MG12P132F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P132F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gl125.h new file mode 100644 index 00000000000..bd47f6a40e4 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gl125.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p232f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P232F1024GL125 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P232F1024GL125_H +#define EFR32MG12P232F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125 EFR32MG12P232F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Core EFR32MG12P232F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P232F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P232F1024GL125_Part EFR32MG12P232F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P232F1024GL125) +#define EFR32MG12P232F1024GL125 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P232F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P232F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P232F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Peripheral_TypeDefs EFR32MG12P232F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P232F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Peripheral_Base EFR32MG12P232F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P232F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Peripheral_Declaration EFR32MG12P232F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P232F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Peripheral_Offsets EFR32MG12P232F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P232F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_BitFields EFR32MG12P232F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_WTIMER_BitFields EFR32MG12P232F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P232F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_SYSTICK_BitFields EFR32MG12P232F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P232F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_UNLOCK EFR32MG12P232F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P232F1024GL125_UNLOCK */ + +/** @} End of group EFR32MG12P232F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Alternate_Function EFR32MG12P232F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P232F1024GL125_Alternate_Function */ + +/** @} End of group EFR32MG12P232F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P232F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gm48.h new file mode 100644 index 00000000000..56c7b6ff167 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gm48.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p232f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P232F1024GM48 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P232F1024GM48_H +#define EFR32MG12P232F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48 EFR32MG12P232F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Core EFR32MG12P232F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P232F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P232F1024GM48_Part EFR32MG12P232F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P232F1024GM48) +#define EFR32MG12P232F1024GM48 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P232F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P232F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P232F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Peripheral_TypeDefs EFR32MG12P232F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P232F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Peripheral_Base EFR32MG12P232F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P232F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Peripheral_Declaration EFR32MG12P232F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P232F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Peripheral_Offsets EFR32MG12P232F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P232F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_BitFields EFR32MG12P232F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_WTIMER_BitFields EFR32MG12P232F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P232F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_SYSTICK_BitFields EFR32MG12P232F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P232F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_UNLOCK EFR32MG12P232F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P232F1024GM48_UNLOCK */ + +/** @} End of group EFR32MG12P232F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Alternate_Function EFR32MG12P232F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P232F1024GM48_Alternate_Function */ + +/** @} End of group EFR32MG12P232F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P232F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gl125.h new file mode 100644 index 00000000000..09733a7e745 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gl125.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p332f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P332F1024GL125 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P332F1024GL125_H +#define EFR32MG12P332F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125 EFR32MG12P332F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Core EFR32MG12P332F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P332F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P332F1024GL125_Part EFR32MG12P332F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P332F1024GL125) +#define EFR32MG12P332F1024GL125 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P332F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P332F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P332F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Peripheral_TypeDefs EFR32MG12P332F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P332F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Peripheral_Base EFR32MG12P332F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P332F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Peripheral_Declaration EFR32MG12P332F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P332F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Peripheral_Offsets EFR32MG12P332F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P332F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_BitFields EFR32MG12P332F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_WTIMER_BitFields EFR32MG12P332F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P332F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_SYSTICK_BitFields EFR32MG12P332F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P332F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_UNLOCK EFR32MG12P332F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P332F1024GL125_UNLOCK */ + +/** @} End of group EFR32MG12P332F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Alternate_Function EFR32MG12P332F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P332F1024GL125_Alternate_Function */ + +/** @} End of group EFR32MG12P332F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P332F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gm48.h new file mode 100644 index 00000000000..1ada364f4b3 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gm48.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p332f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P332F1024GM48 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P332F1024GM48_H +#define EFR32MG12P332F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48 EFR32MG12P332F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Core EFR32MG12P332F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P332F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P332F1024GM48_Part EFR32MG12P332F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P332F1024GM48) +#define EFR32MG12P332F1024GM48 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P332F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P332F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P332F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Peripheral_TypeDefs EFR32MG12P332F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P332F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Peripheral_Base EFR32MG12P332F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P332F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Peripheral_Declaration EFR32MG12P332F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P332F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Peripheral_Offsets EFR32MG12P332F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P332F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_BitFields EFR32MG12P332F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_WTIMER_BitFields EFR32MG12P332F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P332F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_SYSTICK_BitFields EFR32MG12P332F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P332F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_UNLOCK EFR32MG12P332F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P332F1024GM48_UNLOCK */ + +/** @} End of group EFR32MG12P332F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Alternate_Function EFR32MG12P332F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P332F1024GM48_Alternate_Function */ + +/** @} End of group EFR32MG12P332F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P332F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gl125.h new file mode 100644 index 00000000000..677bf598f47 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gl125.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p432f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P432F1024GL125 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P432F1024GL125_H +#define EFR32MG12P432F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125 EFR32MG12P432F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Core EFR32MG12P432F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P432F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P432F1024GL125_Part EFR32MG12P432F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P432F1024GL125) +#define EFR32MG12P432F1024GL125 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P432F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P432F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P432F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Peripheral_TypeDefs EFR32MG12P432F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P432F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Peripheral_Base EFR32MG12P432F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P432F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Peripheral_Declaration EFR32MG12P432F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P432F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Peripheral_Offsets EFR32MG12P432F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P432F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_BitFields EFR32MG12P432F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_WTIMER_BitFields EFR32MG12P432F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P432F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_SYSTICK_BitFields EFR32MG12P432F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P432F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_UNLOCK EFR32MG12P432F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P432F1024GL125_UNLOCK */ + +/** @} End of group EFR32MG12P432F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Alternate_Function EFR32MG12P432F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P432F1024GL125_Alternate_Function */ + +/** @} End of group EFR32MG12P432F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P432F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h new file mode 100644 index 00000000000..ea7cd8f7724 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p432f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P432F1024GM48 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P432F1024GM48_H +#define EFR32MG12P432F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48 EFR32MG12P432F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Core EFR32MG12P432F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P432F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P432F1024GM48_Part EFR32MG12P432F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P432F1024GM48) +#define EFR32MG12P432F1024GM48 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P432F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P432F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P432F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Peripheral_TypeDefs EFR32MG12P432F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P432F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Peripheral_Base EFR32MG12P432F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P432F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Peripheral_Declaration EFR32MG12P432F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P432F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Peripheral_Offsets EFR32MG12P432F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P432F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_BitFields EFR32MG12P432F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_WTIMER_BitFields EFR32MG12P432F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P432F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_SYSTICK_BitFields EFR32MG12P432F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P432F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_UNLOCK EFR32MG12P432F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P432F1024GM48_UNLOCK */ + +/** @} End of group EFR32MG12P432F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Alternate_Function EFR32MG12P432F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P432F1024GM48_Alternate_Function */ + +/** @} End of group EFR32MG12P432F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P432F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gl125.h new file mode 100644 index 00000000000..5c27123be59 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gl125.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p433f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P433F1024GL125 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P433F1024GL125_H +#define EFR32MG12P433F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125 EFR32MG12P433F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Core EFR32MG12P433F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P433F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P433F1024GL125_Part EFR32MG12P433F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P433F1024GL125) +#define EFR32MG12P433F1024GL125 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P433F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P433F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P433F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Peripheral_TypeDefs EFR32MG12P433F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P433F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Peripheral_Base EFR32MG12P433F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P433F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Peripheral_Declaration EFR32MG12P433F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P433F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Peripheral_Offsets EFR32MG12P433F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P433F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_BitFields EFR32MG12P433F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_WTIMER_BitFields EFR32MG12P433F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P433F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_SYSTICK_BitFields EFR32MG12P433F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P433F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_UNLOCK EFR32MG12P433F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P433F1024GL125_UNLOCK */ + +/** @} End of group EFR32MG12P433F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Alternate_Function EFR32MG12P433F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P433F1024GL125_Alternate_Function */ + +/** @} End of group EFR32MG12P433F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P433F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gm48.h new file mode 100644 index 00000000000..54efdd7621f --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gm48.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p433f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P433F1024GM48 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P433F1024GM48_H +#define EFR32MG12P433F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48 EFR32MG12P433F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Core EFR32MG12P433F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P433F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P433F1024GM48_Part EFR32MG12P433F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P433F1024GM48) +#define EFR32MG12P433F1024GM48 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P433F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P433F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P433F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Peripheral_TypeDefs EFR32MG12P433F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P433F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Peripheral_Base EFR32MG12P433F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P433F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Peripheral_Declaration EFR32MG12P433F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P433F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Peripheral_Offsets EFR32MG12P433F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P433F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_BitFields EFR32MG12P433F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_WTIMER_BitFields EFR32MG12P433F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P433F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_SYSTICK_BitFields EFR32MG12P433F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P433F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_UNLOCK EFR32MG12P433F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P433F1024GM48_UNLOCK */ + +/** @} End of group EFR32MG12P433F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Alternate_Function EFR32MG12P433F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P433F1024GM48_Alternate_Function */ + +/** @} End of group EFR32MG12P433F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P433F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_acmp.h new file mode 100644 index 00000000000..6bdf56b9f41 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_acmp.h @@ -0,0 +1,1420 @@ +/**************************************************************************//** + * @file efr32mg12p_acmp.h + * @brief EFR32MG12P_ACMP register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_ACMP + * @{ + * @brief EFR32MG12P_ACMP Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTSEL; /**< Input Selection Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ + __IOM uint32_t HYSTERESIS0; /**< Hysteresis 0 Register */ + __IOM uint32_t HYSTERESIS1; /**< Hysteresis 1 Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pine Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t EXTIFCTRL; /**< External override interface control */ +} ACMP_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_ACMP_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x07000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0xBF3CF70DUL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */ +#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */ +#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */ +#define ACMP_CTRL_APORTXMASTERDIS (0x1UL << 8) /**< APORT Bus X Master Disable */ +#define _ACMP_CTRL_APORTXMASTERDIS_SHIFT 8 /**< Shift value for ACMP_APORTXMASTERDIS */ +#define _ACMP_CTRL_APORTXMASTERDIS_MASK 0x100UL /**< Bit mask for ACMP_APORTXMASTERDIS */ +#define _ACMP_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTXMASTERDIS_DEFAULT (_ACMP_CTRL_APORTXMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTYMASTERDIS (0x1UL << 9) /**< APORT Bus Y Master Disable */ +#define _ACMP_CTRL_APORTYMASTERDIS_SHIFT 9 /**< Shift value for ACMP_APORTYMASTERDIS */ +#define _ACMP_CTRL_APORTYMASTERDIS_MASK 0x200UL /**< Bit mask for ACMP_APORTYMASTERDIS */ +#define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTYMASTERDIS_DEFAULT (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus selected by VASEL */ +#define _ACMP_CTRL_APORTVMASTERDIS_SHIFT 10 /**< Shift value for ACMP_APORTVMASTERDIS */ +#define _ACMP_CTRL_APORTVMASTERDIS_MASK 0x400UL /**< Bit mask for ACMP_APORTVMASTERDIS */ +#define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTVMASTERDIS_DEFAULT (_ACMP_CTRL_APORTVMASTERDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_SHIFT 12 /**< Shift value for ACMP_PWRSEL */ +#define _ACMP_CTRL_PWRSEL_MASK 0x7000UL /**< Bit mask for ACMP_PWRSEL */ +#define _ACMP_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_AVDD 0x00000000UL /**< Mode AVDD for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_VREGVDD 0x00000001UL /**< Mode VREGVDD for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_IOVDD0 0x00000002UL /**< Mode IOVDD0 for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_IOVDD1 0x00000004UL /**< Mode IOVDD1 for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_DEFAULT (_ACMP_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_AVDD (_ACMP_CTRL_PWRSEL_AVDD << 12) /**< Shifted mode AVDD for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_VREGVDD (_ACMP_CTRL_PWRSEL_VREGVDD << 12) /**< Shifted mode VREGVDD for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_IOVDD0 (_ACMP_CTRL_PWRSEL_IOVDD0 << 12) /**< Shifted mode IOVDD0 for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_IOVDD1 (_ACMP_CTRL_PWRSEL_IOVDD1 << 12) /**< Shifted mode IOVDD1 for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP accuracy mode */ +#define _ACMP_CTRL_ACCURACY_SHIFT 15 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CTRL_ACCURACY_MASK 0x8000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CTRL_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_DEFAULT (_ACMP_CTRL_ACCURACY_DEFAULT << 15) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_LOW (_ACMP_CTRL_ACCURACY_LOW << 15) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_HIGH (_ACMP_CTRL_ACCURACY_HIGH << 15) /**< Shifted mode HIGH for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_SHIFT 18 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CTRL_INPUTRANGE_MASK 0xC0000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CTRL_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_GTVDDDIV2 0x00000001UL /**< Mode GTVDDDIV2 for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 0x00000002UL /**< Mode LTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_DEFAULT (_ACMP_CTRL_INPUTRANGE_DEFAULT << 18) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_FULL (_ACMP_CTRL_INPUTRANGE_FULL << 18) /**< Shifted mode FULL for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_GTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_GTVDDDIV2 << 18) /**< Shifted mode GTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_LTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_LTVDDDIV2 << 18) /**< Shifted mode LTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_IRISE (0x1UL << 20) /**< Rising Edge Interrupt Sense */ +#define _ACMP_CTRL_IRISE_SHIFT 20 /**< Shift value for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_MASK 0x100000UL /**< Bit mask for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 20) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 20) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 20) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL (0x1UL << 21) /**< Falling Edge Interrupt Sense */ +#define _ACMP_CTRL_IFALL_SHIFT 21 /**< Shift value for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_MASK 0x200000UL /**< Bit mask for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 21) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 21) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 21) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_MASK 0x3F000000UL /**< Bit mask for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */ +#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTSEL */ +#define _ACMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_MASK 0x757FFFFFUL /**< Mask for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH0 (_ACMP_INPUTSEL_POSSEL_APORT0XCH0 << 0) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH1 (_ACMP_INPUTSEL_POSSEL_APORT0XCH1 << 0) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH2 (_ACMP_INPUTSEL_POSSEL_APORT0XCH2 << 0) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH3 (_ACMP_INPUTSEL_POSSEL_APORT0XCH3 << 0) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH4 (_ACMP_INPUTSEL_POSSEL_APORT0XCH4 << 0) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH5 (_ACMP_INPUTSEL_POSSEL_APORT0XCH5 << 0) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH6 (_ACMP_INPUTSEL_POSSEL_APORT0XCH6 << 0) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH7 (_ACMP_INPUTSEL_POSSEL_APORT0XCH7 << 0) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH8 (_ACMP_INPUTSEL_POSSEL_APORT0XCH8 << 0) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH9 (_ACMP_INPUTSEL_POSSEL_APORT0XCH9 << 0) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH10 (_ACMP_INPUTSEL_POSSEL_APORT0XCH10 << 0) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH11 (_ACMP_INPUTSEL_POSSEL_APORT0XCH11 << 0) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH12 (_ACMP_INPUTSEL_POSSEL_APORT0XCH12 << 0) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH13 (_ACMP_INPUTSEL_POSSEL_APORT0XCH13 << 0) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH14 (_ACMP_INPUTSEL_POSSEL_APORT0XCH14 << 0) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH15 (_ACMP_INPUTSEL_POSSEL_APORT0XCH15 << 0) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH0 (_ACMP_INPUTSEL_POSSEL_APORT0YCH0 << 0) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH1 (_ACMP_INPUTSEL_POSSEL_APORT0YCH1 << 0) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH2 (_ACMP_INPUTSEL_POSSEL_APORT0YCH2 << 0) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH3 (_ACMP_INPUTSEL_POSSEL_APORT0YCH3 << 0) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH4 (_ACMP_INPUTSEL_POSSEL_APORT0YCH4 << 0) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH5 (_ACMP_INPUTSEL_POSSEL_APORT0YCH5 << 0) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH6 (_ACMP_INPUTSEL_POSSEL_APORT0YCH6 << 0) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH7 (_ACMP_INPUTSEL_POSSEL_APORT0YCH7 << 0) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH8 (_ACMP_INPUTSEL_POSSEL_APORT0YCH8 << 0) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH9 (_ACMP_INPUTSEL_POSSEL_APORT0YCH9 << 0) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH10 (_ACMP_INPUTSEL_POSSEL_APORT0YCH10 << 0) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH11 (_ACMP_INPUTSEL_POSSEL_APORT0YCH11 << 0) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH12 (_ACMP_INPUTSEL_POSSEL_APORT0YCH12 << 0) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH13 (_ACMP_INPUTSEL_POSSEL_APORT0YCH13 << 0) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH14 (_ACMP_INPUTSEL_POSSEL_APORT0YCH14 << 0) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH15 (_ACMP_INPUTSEL_POSSEL_APORT0YCH15 << 0) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH0 (_ACMP_INPUTSEL_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH1 (_ACMP_INPUTSEL_POSSEL_APORT1YCH1 << 0) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH2 (_ACMP_INPUTSEL_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH3 (_ACMP_INPUTSEL_POSSEL_APORT1YCH3 << 0) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH4 (_ACMP_INPUTSEL_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH5 (_ACMP_INPUTSEL_POSSEL_APORT1YCH5 << 0) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH6 (_ACMP_INPUTSEL_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH7 (_ACMP_INPUTSEL_POSSEL_APORT1YCH7 << 0) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH8 (_ACMP_INPUTSEL_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH9 (_ACMP_INPUTSEL_POSSEL_APORT1YCH9 << 0) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH10 (_ACMP_INPUTSEL_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH11 (_ACMP_INPUTSEL_POSSEL_APORT1YCH11 << 0) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH12 (_ACMP_INPUTSEL_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH13 (_ACMP_INPUTSEL_POSSEL_APORT1YCH13 << 0) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH14 (_ACMP_INPUTSEL_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH15 (_ACMP_INPUTSEL_POSSEL_APORT1YCH15 << 0) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH16 (_ACMP_INPUTSEL_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH17 (_ACMP_INPUTSEL_POSSEL_APORT1YCH17 << 0) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH18 (_ACMP_INPUTSEL_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH19 (_ACMP_INPUTSEL_POSSEL_APORT1YCH19 << 0) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH20 (_ACMP_INPUTSEL_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH21 (_ACMP_INPUTSEL_POSSEL_APORT1YCH21 << 0) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH22 (_ACMP_INPUTSEL_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH23 (_ACMP_INPUTSEL_POSSEL_APORT1YCH23 << 0) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH24 (_ACMP_INPUTSEL_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH25 (_ACMP_INPUTSEL_POSSEL_APORT1YCH25 << 0) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH26 (_ACMP_INPUTSEL_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH27 (_ACMP_INPUTSEL_POSSEL_APORT1YCH27 << 0) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH28 (_ACMP_INPUTSEL_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH29 (_ACMP_INPUTSEL_POSSEL_APORT1YCH29 << 0) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH30 (_ACMP_INPUTSEL_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH31 (_ACMP_INPUTSEL_POSSEL_APORT1YCH31 << 0) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH0 (_ACMP_INPUTSEL_POSSEL_APORT2YCH0 << 0) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH1 (_ACMP_INPUTSEL_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH2 (_ACMP_INPUTSEL_POSSEL_APORT2YCH2 << 0) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH3 (_ACMP_INPUTSEL_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH4 (_ACMP_INPUTSEL_POSSEL_APORT2YCH4 << 0) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH5 (_ACMP_INPUTSEL_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH6 (_ACMP_INPUTSEL_POSSEL_APORT2YCH6 << 0) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH7 (_ACMP_INPUTSEL_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH8 (_ACMP_INPUTSEL_POSSEL_APORT2YCH8 << 0) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH9 (_ACMP_INPUTSEL_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH10 (_ACMP_INPUTSEL_POSSEL_APORT2YCH10 << 0) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH11 (_ACMP_INPUTSEL_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH12 (_ACMP_INPUTSEL_POSSEL_APORT2YCH12 << 0) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH13 (_ACMP_INPUTSEL_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH14 (_ACMP_INPUTSEL_POSSEL_APORT2YCH14 << 0) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH15 (_ACMP_INPUTSEL_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH16 (_ACMP_INPUTSEL_POSSEL_APORT2YCH16 << 0) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH17 (_ACMP_INPUTSEL_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH18 (_ACMP_INPUTSEL_POSSEL_APORT2YCH18 << 0) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH19 (_ACMP_INPUTSEL_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH20 (_ACMP_INPUTSEL_POSSEL_APORT2YCH20 << 0) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH21 (_ACMP_INPUTSEL_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH22 (_ACMP_INPUTSEL_POSSEL_APORT2YCH22 << 0) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH23 (_ACMP_INPUTSEL_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH24 (_ACMP_INPUTSEL_POSSEL_APORT2YCH24 << 0) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH25 (_ACMP_INPUTSEL_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH26 (_ACMP_INPUTSEL_POSSEL_APORT2YCH26 << 0) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH27 (_ACMP_INPUTSEL_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH28 (_ACMP_INPUTSEL_POSSEL_APORT2YCH28 << 0) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH29 (_ACMP_INPUTSEL_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH30 (_ACMP_INPUTSEL_POSSEL_APORT2YCH30 << 0) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH31 (_ACMP_INPUTSEL_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH0 (_ACMP_INPUTSEL_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH1 (_ACMP_INPUTSEL_POSSEL_APORT3YCH1 << 0) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH2 (_ACMP_INPUTSEL_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH3 (_ACMP_INPUTSEL_POSSEL_APORT3YCH3 << 0) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH4 (_ACMP_INPUTSEL_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH5 (_ACMP_INPUTSEL_POSSEL_APORT3YCH5 << 0) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH6 (_ACMP_INPUTSEL_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH7 (_ACMP_INPUTSEL_POSSEL_APORT3YCH7 << 0) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH8 (_ACMP_INPUTSEL_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH9 (_ACMP_INPUTSEL_POSSEL_APORT3YCH9 << 0) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH10 (_ACMP_INPUTSEL_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH11 (_ACMP_INPUTSEL_POSSEL_APORT3YCH11 << 0) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH12 (_ACMP_INPUTSEL_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH13 (_ACMP_INPUTSEL_POSSEL_APORT3YCH13 << 0) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH14 (_ACMP_INPUTSEL_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH15 (_ACMP_INPUTSEL_POSSEL_APORT3YCH15 << 0) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH16 (_ACMP_INPUTSEL_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH17 (_ACMP_INPUTSEL_POSSEL_APORT3YCH17 << 0) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH18 (_ACMP_INPUTSEL_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH19 (_ACMP_INPUTSEL_POSSEL_APORT3YCH19 << 0) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH20 (_ACMP_INPUTSEL_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH21 (_ACMP_INPUTSEL_POSSEL_APORT3YCH21 << 0) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH22 (_ACMP_INPUTSEL_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH23 (_ACMP_INPUTSEL_POSSEL_APORT3YCH23 << 0) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH24 (_ACMP_INPUTSEL_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH25 (_ACMP_INPUTSEL_POSSEL_APORT3YCH25 << 0) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH26 (_ACMP_INPUTSEL_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH27 (_ACMP_INPUTSEL_POSSEL_APORT3YCH27 << 0) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH28 (_ACMP_INPUTSEL_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH29 (_ACMP_INPUTSEL_POSSEL_APORT3YCH29 << 0) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH30 (_ACMP_INPUTSEL_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH31 (_ACMP_INPUTSEL_POSSEL_APORT3YCH31 << 0) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH0 (_ACMP_INPUTSEL_POSSEL_APORT4YCH0 << 0) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH1 (_ACMP_INPUTSEL_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH2 (_ACMP_INPUTSEL_POSSEL_APORT4YCH2 << 0) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH3 (_ACMP_INPUTSEL_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH4 (_ACMP_INPUTSEL_POSSEL_APORT4YCH4 << 0) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH5 (_ACMP_INPUTSEL_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH6 (_ACMP_INPUTSEL_POSSEL_APORT4YCH6 << 0) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH7 (_ACMP_INPUTSEL_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH8 (_ACMP_INPUTSEL_POSSEL_APORT4YCH8 << 0) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH9 (_ACMP_INPUTSEL_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH10 (_ACMP_INPUTSEL_POSSEL_APORT4YCH10 << 0) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH19 (_ACMP_INPUTSEL_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH20 (_ACMP_INPUTSEL_POSSEL_APORT4YCH20 << 0) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH21 (_ACMP_INPUTSEL_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH22 (_ACMP_INPUTSEL_POSSEL_APORT4YCH22 << 0) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH23 (_ACMP_INPUTSEL_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH24 (_ACMP_INPUTSEL_POSSEL_APORT4YCH24 << 0) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH25 (_ACMP_INPUTSEL_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH26 (_ACMP_INPUTSEL_POSSEL_APORT4YCH26 << 0) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH27 (_ACMP_INPUTSEL_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VDD (_ACMP_INPUTSEL_POSSEL_VDD << 0) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VSS (_ACMP_INPUTSEL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 8) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VSS (_ACMP_INPUTSEL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_SHIFT 16 /**< Shift value for ACMP_VASEL */ +#define _ACMP_INPUTSEL_VASEL_MASK 0x3F0000UL /**< Bit mask for ACMP_VASEL */ +#define _ACMP_INPUTSEL_VASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_VDD 0x00000000UL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH0 0x00000001UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH2 0x00000003UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH4 0x00000005UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH6 0x00000007UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH8 0x00000009UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH10 0x0000000BUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH12 0x0000000DUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH14 0x0000000FUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH16 0x00000011UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH18 0x00000013UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH20 0x00000015UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH22 0x00000017UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH24 0x00000019UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH26 0x0000001BUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH28 0x0000001DUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH30 0x0000001FUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_DEFAULT (_ACMP_INPUTSEL_VASEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_VDD (_ACMP_INPUTSEL_VASEL_VDD << 16) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH0 (_ACMP_INPUTSEL_VASEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH2 (_ACMP_INPUTSEL_VASEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH4 (_ACMP_INPUTSEL_VASEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH6 (_ACMP_INPUTSEL_VASEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH8 (_ACMP_INPUTSEL_VASEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH10 (_ACMP_INPUTSEL_VASEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH12 (_ACMP_INPUTSEL_VASEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH14 (_ACMP_INPUTSEL_VASEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH16 (_ACMP_INPUTSEL_VASEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH18 (_ACMP_INPUTSEL_VASEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH20 (_ACMP_INPUTSEL_VASEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH22 (_ACMP_INPUTSEL_VASEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH24 (_ACMP_INPUTSEL_VASEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH26 (_ACMP_INPUTSEL_VASEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH28 (_ACMP_INPUTSEL_VASEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH30 (_ACMP_INPUTSEL_VASEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH0 (_ACMP_INPUTSEL_VASEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH1 (_ACMP_INPUTSEL_VASEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH2 (_ACMP_INPUTSEL_VASEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH3 (_ACMP_INPUTSEL_VASEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH4 (_ACMP_INPUTSEL_VASEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH5 (_ACMP_INPUTSEL_VASEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH6 (_ACMP_INPUTSEL_VASEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH7 (_ACMP_INPUTSEL_VASEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH8 (_ACMP_INPUTSEL_VASEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH9 (_ACMP_INPUTSEL_VASEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH10 (_ACMP_INPUTSEL_VASEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH11 (_ACMP_INPUTSEL_VASEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH12 (_ACMP_INPUTSEL_VASEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH13 (_ACMP_INPUTSEL_VASEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH14 (_ACMP_INPUTSEL_VASEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH15 (_ACMP_INPUTSEL_VASEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH16 (_ACMP_INPUTSEL_VASEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH17 (_ACMP_INPUTSEL_VASEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH18 (_ACMP_INPUTSEL_VASEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH19 (_ACMP_INPUTSEL_VASEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH20 (_ACMP_INPUTSEL_VASEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH21 (_ACMP_INPUTSEL_VASEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH22 (_ACMP_INPUTSEL_VASEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH23 (_ACMP_INPUTSEL_VASEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH24 (_ACMP_INPUTSEL_VASEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH25 (_ACMP_INPUTSEL_VASEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH26 (_ACMP_INPUTSEL_VASEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH27 (_ACMP_INPUTSEL_VASEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH28 (_ACMP_INPUTSEL_VASEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH29 (_ACMP_INPUTSEL_VASEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH30 (_ACMP_INPUTSEL_VASEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH31 (_ACMP_INPUTSEL_VASEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL (0x1UL << 22) /**< VB Selection */ +#define _ACMP_INPUTSEL_VBSEL_SHIFT 22 /**< Shift value for ACMP_VBSEL */ +#define _ACMP_INPUTSEL_VBSEL_MASK 0x400000UL /**< Bit mask for ACMP_VBSEL */ +#define _ACMP_INPUTSEL_VBSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VBSEL_1V25 0x00000000UL /**< Mode 1V25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VBSEL_2V5 0x00000001UL /**< Mode 2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_DEFAULT (_ACMP_INPUTSEL_VBSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_1V25 (_ACMP_INPUTSEL_VBSEL_1V25 << 22) /**< Shifted mode 1V25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_2V5 (_ACMP_INPUTSEL_VBSEL_2V5 << 22) /**< Shifted mode 2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL (0x1UL << 24) /**< Low-Power Sampled Voltage Selection */ +#define _ACMP_INPUTSEL_VLPSEL_SHIFT 24 /**< Shift value for ACMP_VLPSEL */ +#define _ACMP_INPUTSEL_VLPSEL_MASK 0x1000000UL /**< Bit mask for ACMP_VLPSEL */ +#define _ACMP_INPUTSEL_VLPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VLPSEL_VADIV 0x00000000UL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VLPSEL_VBDIV 0x00000001UL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_DEFAULT (_ACMP_INPUTSEL_VLPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_VADIV (_ACMP_INPUTSEL_VLPSEL_VADIV << 24) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_VBDIV (_ACMP_INPUTSEL_VLPSEL_VBDIV << 24) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN (0x1UL << 26) /**< Capacitive Sense Mode Internal Resistor Enable */ +#define _ACMP_INPUTSEL_CSRESEN_SHIFT 26 /**< Shift value for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_MASK 0x4000000UL /**< Bit mask for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 26) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES7 0x00000007UL /**< Mode RES7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES4 (_ACMP_INPUTSEL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES5 (_ACMP_INPUTSEL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES6 (_ACMP_INPUTSEL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES7 (_ACMP_INPUTSEL_CSRESSEL_RES7 << 28) /**< Shifted mode RES7 for ACMP_INPUTSEL */ + +/* Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000000FUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */ +#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Output */ +#define _ACMP_STATUS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_STATUS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_APORTCONFLICT_DEFAULT (_ACMP_STATUS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_EXTIFACT (0x1UL << 3) /**< External override interface active. */ +#define _ACMP_STATUS_EXTIFACT_SHIFT 3 /**< Shift value for ACMP_EXTIFACT */ +#define _ACMP_STATUS_EXTIFACT_MASK 0x8UL /**< Bit mask for ACMP_EXTIFACT */ +#define _ACMP_STATUS_EXTIFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_EXTIFACT_DEFAULT (_ACMP_STATUS_EXTIFACT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x00000007UL /**< Mask for ACMP_IF */ +#define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ +#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */ +#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Interrupt Flag */ +#define _ACMP_IF_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IF_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_APORTCONFLICT_DEFAULT (_ACMP_IF_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IFS */ +#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */ +#define _ACMP_IFS_MASK 0x00000007UL /**< Mask for ACMP_IFS */ +#define ACMP_IFS_EDGE (0x1UL << 0) /**< Set EDGE Interrupt Flag */ +#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP (0x1UL << 1) /**< Set WARMUP Interrupt Flag */ +#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_APORTCONFLICT (0x1UL << 2) /**< Set APORTCONFLICT Interrupt Flag */ +#define _ACMP_IFS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IFS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_APORTCONFLICT_DEFAULT (_ACMP_IFS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFS */ + +/* Bit fields for ACMP IFC */ +#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */ +#define _ACMP_IFC_MASK 0x00000007UL /**< Mask for ACMP_IFC */ +#define ACMP_IFC_EDGE (0x1UL << 0) /**< Clear EDGE Interrupt Flag */ +#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP (0x1UL << 1) /**< Clear WARMUP Interrupt Flag */ +#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_APORTCONFLICT (0x1UL << 2) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _ACMP_IFC_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IFC_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_APORTCONFLICT_DEFAULT (_ACMP_IFC_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFC */ + +/* Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x00000007UL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_EDGE (0x1UL << 0) /**< EDGE Interrupt Enable */ +#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP (0x1UL << 1) /**< WARMUP Interrupt Enable */ +#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_APORTCONFLICT (0x1UL << 2) /**< APORTCONFLICT Interrupt Enable */ +#define _ACMP_IEN_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IEN_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_APORTCONFLICT_DEFAULT (_ACMP_IEN_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP APORTREQ */ +#define _ACMP_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTREQ */ +#define _ACMP_APORTREQ_MASK 0x000003FFUL /**< Mask for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */ +#define _ACMP_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ACMP_APORT0XREQ */ +#define _ACMP_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ACMP_APORT0XREQ */ +#define _ACMP_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0XREQ_DEFAULT (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */ +#define _ACMP_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ACMP_APORT0YREQ */ +#define _ACMP_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ACMP_APORT0YREQ */ +#define _ACMP_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0YREQ_DEFAULT (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _ACMP_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ACMP_APORT1XREQ */ +#define _ACMP_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ACMP_APORT1XREQ */ +#define _ACMP_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1XREQ_DEFAULT (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _ACMP_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ACMP_APORT1YREQ */ +#define _ACMP_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ACMP_APORT1YREQ */ +#define _ACMP_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1YREQ_DEFAULT (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _ACMP_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ACMP_APORT2XREQ */ +#define _ACMP_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ACMP_APORT2XREQ */ +#define _ACMP_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2XREQ_DEFAULT (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _ACMP_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ACMP_APORT2YREQ */ +#define _ACMP_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ACMP_APORT2YREQ */ +#define _ACMP_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2YREQ_DEFAULT (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _ACMP_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ACMP_APORT3XREQ */ +#define _ACMP_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ACMP_APORT3XREQ */ +#define _ACMP_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3XREQ_DEFAULT (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _ACMP_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ACMP_APORT3YREQ */ +#define _ACMP_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ACMP_APORT3YREQ */ +#define _ACMP_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3YREQ_DEFAULT (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _ACMP_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ACMP_APORT4XREQ */ +#define _ACMP_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ACMP_APORT4XREQ */ +#define _ACMP_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4XREQ_DEFAULT (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _ACMP_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ACMP_APORT4YREQ */ +#define _ACMP_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ACMP_APORT4YREQ */ +#define _ACMP_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4YREQ_DEFAULT (_ACMP_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ + +/* Bit fields for ACMP APORTCONFLICT */ +#define _ACMP_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTCONFLICT */ +#define _ACMP_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ACMP_APORT0XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ACMP_APORT0XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ACMP_APORT0YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ACMP_APORT0YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORT1XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORT1XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ACMP_APORT1YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_APORT1YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ACMP_APORT2XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ACMP_APORT2XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ACMP_APORT2YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ACMP_APORT2YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ACMP_APORT3XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ACMP_APORT3XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ACMP_APORT3YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ACMP_APORT3YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ACMP_APORT4XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ACMP_APORT4XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ACMP_APORT4YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ACMP_APORT4YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ + +/* Bit fields for ACMP HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ +#define _ACMP_HYSTERESIS0_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ +#define _ACMP_HYSTERESIS0_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_DEFAULT (_ACMP_HYSTERESIS0_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST0 (_ACMP_HYSTERESIS0_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST1 (_ACMP_HYSTERESIS0_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST2 (_ACMP_HYSTERESIS0_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST3 (_ACMP_HYSTERESIS0_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST4 (_ACMP_HYSTERESIS0_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST5 (_ACMP_HYSTERESIS0_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST6 (_ACMP_HYSTERESIS0_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST7 (_ACMP_HYSTERESIS0_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST8 (_ACMP_HYSTERESIS0_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST9 (_ACMP_HYSTERESIS0_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST10 (_ACMP_HYSTERESIS0_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST11 (_ACMP_HYSTERESIS0_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST12 (_ACMP_HYSTERESIS0_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST13 (_ACMP_HYSTERESIS0_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST14 (_ACMP_HYSTERESIS0_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST15 (_ACMP_HYSTERESIS0_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS0_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS0_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_DIVVA_DEFAULT (_ACMP_HYSTERESIS0_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS0_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS0_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_DIVVB_DEFAULT (_ACMP_HYSTERESIS0_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ + +/* Bit fields for ACMP HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ +#define _ACMP_HYSTERESIS1_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ +#define _ACMP_HYSTERESIS1_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_DEFAULT (_ACMP_HYSTERESIS1_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST0 (_ACMP_HYSTERESIS1_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST1 (_ACMP_HYSTERESIS1_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST2 (_ACMP_HYSTERESIS1_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST3 (_ACMP_HYSTERESIS1_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST4 (_ACMP_HYSTERESIS1_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST5 (_ACMP_HYSTERESIS1_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST6 (_ACMP_HYSTERESIS1_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST7 (_ACMP_HYSTERESIS1_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST8 (_ACMP_HYSTERESIS1_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST9 (_ACMP_HYSTERESIS1_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST10 (_ACMP_HYSTERESIS1_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST11 (_ACMP_HYSTERESIS1_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST12 (_ACMP_HYSTERESIS1_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST13 (_ACMP_HYSTERESIS1_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST14 (_ACMP_HYSTERESIS1_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST15 (_ACMP_HYSTERESIS1_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS1_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS1_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_DIVVA_DEFAULT (_ACMP_HYSTERESIS1_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS1_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS1_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_DIVVB_DEFAULT (_ACMP_HYSTERESIS1_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ + +/* Bit fields for ACMP ROUTEPEN */ +#define _ACMP_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTEPEN */ +#define _ACMP_ROUTEPEN_MASK 0x00000001UL /**< Mask for ACMP_ROUTEPEN */ +#define ACMP_ROUTEPEN_OUTPEN (0x1UL << 0) /**< ACMP Output Pin Enable */ +#define _ACMP_ROUTEPEN_OUTPEN_SHIFT 0 /**< Shift value for ACMP_OUTPEN */ +#define _ACMP_ROUTEPEN_OUTPEN_MASK 0x1UL /**< Bit mask for ACMP_OUTPEN */ +#define _ACMP_ROUTEPEN_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTEPEN */ +#define ACMP_ROUTEPEN_OUTPEN_DEFAULT (_ACMP_ROUTEPEN_OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTEPEN */ + +/* Bit fields for ACMP ROUTELOC0 */ +#define _ACMP_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_MASK 0x0000001FUL /**< Mask for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_SHIFT 0 /**< Shift value for ACMP_OUTLOC */ +#define _ACMP_ROUTELOC0_OUTLOC_MASK 0x1FUL /**< Bit mask for ACMP_OUTLOC */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC4 0x00000004UL /**< Mode LOC4 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC5 0x00000005UL /**< Mode LOC5 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC6 0x00000006UL /**< Mode LOC6 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC7 0x00000007UL /**< Mode LOC7 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC8 0x00000008UL /**< Mode LOC8 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC9 0x00000009UL /**< Mode LOC9 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC10 0x0000000AUL /**< Mode LOC10 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC11 0x0000000BUL /**< Mode LOC11 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC12 0x0000000CUL /**< Mode LOC12 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC13 0x0000000DUL /**< Mode LOC13 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC14 0x0000000EUL /**< Mode LOC14 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC15 0x0000000FUL /**< Mode LOC15 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC16 0x00000010UL /**< Mode LOC16 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC17 0x00000011UL /**< Mode LOC17 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC18 0x00000012UL /**< Mode LOC18 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC19 0x00000013UL /**< Mode LOC19 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC20 0x00000014UL /**< Mode LOC20 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC21 0x00000015UL /**< Mode LOC21 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC22 0x00000016UL /**< Mode LOC22 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC23 0x00000017UL /**< Mode LOC23 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC24 0x00000018UL /**< Mode LOC24 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC25 0x00000019UL /**< Mode LOC25 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC26 0x0000001AUL /**< Mode LOC26 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC27 0x0000001BUL /**< Mode LOC27 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC28 0x0000001CUL /**< Mode LOC28 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC29 0x0000001DUL /**< Mode LOC29 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC30 0x0000001EUL /**< Mode LOC30 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC31 0x0000001FUL /**< Mode LOC31 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC0 (_ACMP_ROUTELOC0_OUTLOC_LOC0 << 0) /**< Shifted mode LOC0 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_DEFAULT (_ACMP_ROUTELOC0_OUTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC1 (_ACMP_ROUTELOC0_OUTLOC_LOC1 << 0) /**< Shifted mode LOC1 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC2 (_ACMP_ROUTELOC0_OUTLOC_LOC2 << 0) /**< Shifted mode LOC2 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC3 (_ACMP_ROUTELOC0_OUTLOC_LOC3 << 0) /**< Shifted mode LOC3 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC4 (_ACMP_ROUTELOC0_OUTLOC_LOC4 << 0) /**< Shifted mode LOC4 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC5 (_ACMP_ROUTELOC0_OUTLOC_LOC5 << 0) /**< Shifted mode LOC5 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC6 (_ACMP_ROUTELOC0_OUTLOC_LOC6 << 0) /**< Shifted mode LOC6 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC7 (_ACMP_ROUTELOC0_OUTLOC_LOC7 << 0) /**< Shifted mode LOC7 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC8 (_ACMP_ROUTELOC0_OUTLOC_LOC8 << 0) /**< Shifted mode LOC8 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC9 (_ACMP_ROUTELOC0_OUTLOC_LOC9 << 0) /**< Shifted mode LOC9 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC10 (_ACMP_ROUTELOC0_OUTLOC_LOC10 << 0) /**< Shifted mode LOC10 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC11 (_ACMP_ROUTELOC0_OUTLOC_LOC11 << 0) /**< Shifted mode LOC11 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC12 (_ACMP_ROUTELOC0_OUTLOC_LOC12 << 0) /**< Shifted mode LOC12 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC13 (_ACMP_ROUTELOC0_OUTLOC_LOC13 << 0) /**< Shifted mode LOC13 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC14 (_ACMP_ROUTELOC0_OUTLOC_LOC14 << 0) /**< Shifted mode LOC14 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC15 (_ACMP_ROUTELOC0_OUTLOC_LOC15 << 0) /**< Shifted mode LOC15 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC16 (_ACMP_ROUTELOC0_OUTLOC_LOC16 << 0) /**< Shifted mode LOC16 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC17 (_ACMP_ROUTELOC0_OUTLOC_LOC17 << 0) /**< Shifted mode LOC17 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC18 (_ACMP_ROUTELOC0_OUTLOC_LOC18 << 0) /**< Shifted mode LOC18 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC19 (_ACMP_ROUTELOC0_OUTLOC_LOC19 << 0) /**< Shifted mode LOC19 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC20 (_ACMP_ROUTELOC0_OUTLOC_LOC20 << 0) /**< Shifted mode LOC20 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC21 (_ACMP_ROUTELOC0_OUTLOC_LOC21 << 0) /**< Shifted mode LOC21 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC22 (_ACMP_ROUTELOC0_OUTLOC_LOC22 << 0) /**< Shifted mode LOC22 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC23 (_ACMP_ROUTELOC0_OUTLOC_LOC23 << 0) /**< Shifted mode LOC23 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC24 (_ACMP_ROUTELOC0_OUTLOC_LOC24 << 0) /**< Shifted mode LOC24 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC25 (_ACMP_ROUTELOC0_OUTLOC_LOC25 << 0) /**< Shifted mode LOC25 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC26 (_ACMP_ROUTELOC0_OUTLOC_LOC26 << 0) /**< Shifted mode LOC26 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC27 (_ACMP_ROUTELOC0_OUTLOC_LOC27 << 0) /**< Shifted mode LOC27 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC28 (_ACMP_ROUTELOC0_OUTLOC_LOC28 << 0) /**< Shifted mode LOC28 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC29 (_ACMP_ROUTELOC0_OUTLOC_LOC29 << 0) /**< Shifted mode LOC29 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC30 (_ACMP_ROUTELOC0_OUTLOC_LOC30 << 0) /**< Shifted mode LOC30 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC31 (_ACMP_ROUTELOC0_OUTLOC_LOC31 << 0) /**< Shifted mode LOC31 for ACMP_ROUTELOC0 */ + +/* Bit fields for ACMP EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_MASK 0x000000F1UL /**< Mask for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_EN (0x1UL << 0) /**< Enable external interface. */ +#define _ACMP_EXTIFCTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EXTIFCTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EXTIFCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_EN_DEFAULT (_ACMP_EXTIFCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_SHIFT 4 /**< Shift value for ACMP_APORTSEL */ +#define _ACMP_EXTIFCTRL_APORTSEL_MASK 0xF0UL /**< Bit mask for ACMP_APORTSEL */ +#define _ACMP_EXTIFCTRL_APORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT0X 0x00000000UL /**< Mode APORT0X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT0Y 0x00000001UL /**< Mode APORT0Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1X 0x00000002UL /**< Mode APORT1X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1Y 0x00000003UL /**< Mode APORT1Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1XY 0x00000004UL /**< Mode APORT1XY for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2X 0x00000005UL /**< Mode APORT2X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2Y 0x00000006UL /**< Mode APORT2Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2YX 0x00000007UL /**< Mode APORT2YX for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3X 0x00000008UL /**< Mode APORT3X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3Y 0x00000009UL /**< Mode APORT3Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3XY 0x0000000AUL /**< Mode APORT3XY for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4X 0x0000000BUL /**< Mode APORT4X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4Y 0x0000000CUL /**< Mode APORT4Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4YX 0x0000000DUL /**< Mode APORT4YX for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_DEFAULT (_ACMP_EXTIFCTRL_APORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT0X (_ACMP_EXTIFCTRL_APORTSEL_APORT0X << 4) /**< Shifted mode APORT0X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT0Y (_ACMP_EXTIFCTRL_APORTSEL_APORT0Y << 4) /**< Shifted mode APORT0Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1X (_ACMP_EXTIFCTRL_APORTSEL_APORT1X << 4) /**< Shifted mode APORT1X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1Y (_ACMP_EXTIFCTRL_APORTSEL_APORT1Y << 4) /**< Shifted mode APORT1Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1XY (_ACMP_EXTIFCTRL_APORTSEL_APORT1XY << 4) /**< Shifted mode APORT1XY for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2X (_ACMP_EXTIFCTRL_APORTSEL_APORT2X << 4) /**< Shifted mode APORT2X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2Y (_ACMP_EXTIFCTRL_APORTSEL_APORT2Y << 4) /**< Shifted mode APORT2Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2YX (_ACMP_EXTIFCTRL_APORTSEL_APORT2YX << 4) /**< Shifted mode APORT2YX for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3X (_ACMP_EXTIFCTRL_APORTSEL_APORT3X << 4) /**< Shifted mode APORT3X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3Y (_ACMP_EXTIFCTRL_APORTSEL_APORT3Y << 4) /**< Shifted mode APORT3Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3XY (_ACMP_EXTIFCTRL_APORTSEL_APORT3XY << 4) /**< Shifted mode APORT3XY for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4X (_ACMP_EXTIFCTRL_APORTSEL_APORT4X << 4) /**< Shifted mode APORT4X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4Y (_ACMP_EXTIFCTRL_APORTSEL_APORT4Y << 4) /**< Shifted mode APORT4Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4YX (_ACMP_EXTIFCTRL_APORTSEL_APORT4YX << 4) /**< Shifted mode APORT4YX for ACMP_EXTIFCTRL */ + +/** @} End of group EFR32MG12P_ACMP */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_adc.h new file mode 100644 index 00000000000..6d485bae4ae --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_adc.h @@ -0,0 +1,2371 @@ +/**************************************************************************//** + * @file efr32mg12p_adc.h + * @brief EFR32MG12P_ADC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_ADC + * @{ + * @brief EFR32MG12P_ADC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t SINGLECTRL; /**< Single Channel Control Register */ + __IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register continued */ + __IOM uint32_t SCANCTRL; /**< Scan Control Register */ + __IOM uint32_t SCANCTRLX; /**< Scan Control Register continued */ + __IOM uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */ + __IOM uint32_t SCANINPUTSEL; /**< Input Selection register for Scan mode */ + __IOM uint32_t SCANNEGSEL; /**< Negative Input select register for Scan */ + __IOM uint32_t CMPTHR; /**< Compare Threshold Register */ + __IOM uint32_t BIASPROG; /**< Bias Programming Register for various analog blocks used in ADC operation. */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */ + __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */ + __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */ + __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */ + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IM uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */ + __IM uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */ + + uint32_t RESERVED2[3]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ + __IM uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */ + __IM uint32_t SCANFIFOCOUNT; /**< Scan FIFO Count Register */ + __IOM uint32_t SINGLEFIFOCLEAR; /**< Single FIFO Clear Register */ + __IOM uint32_t SCANFIFOCLEAR; /**< Scan FIFO Clear Register */ + __IOM uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */ +} ADC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_ADC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ADC CTRL */ +#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */ +#define _ADC_CTRL_MASK 0xFF7F7FDFUL /**< Mask for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC 0x00000002UL /**< Mode KEEPINSLOWACC for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 0) /**< Shifted mode KEEPINSTANDBY for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPINSLOWACC (_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC << 0) /**< Shifted mode KEEPINSLOWACC for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_SINGLEDMAWU (0x1UL << 2) /**< SINGLEFIFO DMA Wakeup */ +#define _ADC_CTRL_SINGLEDMAWU_SHIFT 2 /**< Shift value for ADC_SINGLEDMAWU */ +#define _ADC_CTRL_SINGLEDMAWU_MASK 0x4UL /**< Bit mask for ADC_SINGLEDMAWU */ +#define _ADC_CTRL_SINGLEDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SINGLEDMAWU_DEFAULT (_ADC_CTRL_SINGLEDMAWU_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SCANDMAWU (0x1UL << 3) /**< SCANFIFO DMA Wakeup */ +#define _ADC_CTRL_SCANDMAWU_SHIFT 3 /**< Shift value for ADC_SCANDMAWU */ +#define _ADC_CTRL_SCANDMAWU_MASK 0x8UL /**< Bit mask for ADC_SCANDMAWU */ +#define _ADC_CTRL_SCANDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SCANDMAWU_DEFAULT (_ADC_CTRL_SCANDMAWU_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TAILGATE (0x1UL << 4) /**< Conversion Tailgating */ +#define _ADC_CTRL_TAILGATE_SHIFT 4 /**< Shift value for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK enable mode when ADCCLKMODE=1 */ +#define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */ +#define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */ +#define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_ASYNCCLKEN_ASNEEDED 0x00000000UL /**< Mode ASNEEDED for ADC_CTRL */ +#define _ADC_CTRL_ASYNCCLKEN_ALWAYSON 0x00000001UL /**< Mode ALWAYSON for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_DEFAULT (_ADC_CTRL_ASYNCCLKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_ASNEEDED (_ADC_CTRL_ASYNCCLKEN_ASNEEDED << 6) /**< Shifted mode ASNEEDED for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_ALWAYSON (_ADC_CTRL_ASYNCCLKEN_ALWAYSON << 6) /**< Shifted mode ALWAYSON for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE (0x1UL << 7) /**< ADC Clock Mode */ +#define _ADC_CTRL_ADCCLKMODE_SHIFT 7 /**< Shift value for ADC_ADCCLKMODE */ +#define _ADC_CTRL_ADCCLKMODE_MASK 0x80UL /**< Bit mask for ADC_ADCCLKMODE */ +#define _ADC_CTRL_ADCCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_ADCCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for ADC_CTRL */ +#define _ADC_CTRL_ADCCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_DEFAULT (_ADC_CTRL_ADCCLKMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_SYNC (_ADC_CTRL_ADCCLKMODE_SYNC << 7) /**< Shifted mode SYNC for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_ASYNC (_ADC_CTRL_ADCCLKMODE_ASYNC << 7) /**< Shifted mode ASYNC for ADC_CTRL */ +#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */ +#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */ +#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */ +#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */ +#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */ +#define ADC_CTRL_DBGHALT (0x1UL << 28) /**< Debug Mode Halt Enable */ +#define _ADC_CTRL_DBGHALT_SHIFT 28 /**< Shift value for ADC_DBGHALT */ +#define _ADC_CTRL_DBGHALT_MASK 0x10000000UL /**< Bit mask for ADC_DBGHALT */ +#define _ADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_DBGHALT_DEFAULT (_ADC_CTRL_DBGHALT_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE (0x1UL << 29) /**< Channel Connect */ +#define _ADC_CTRL_CHCONMODE_SHIFT 29 /**< Shift value for ADC_CHCONMODE */ +#define _ADC_CTRL_CHCONMODE_MASK 0x20000000UL /**< Bit mask for ADC_CHCONMODE */ +#define _ADC_CTRL_CHCONMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_CHCONMODE_MAXSETTLE 0x00000000UL /**< Mode MAXSETTLE for ADC_CTRL */ +#define _ADC_CTRL_CHCONMODE_MAXRESP 0x00000001UL /**< Mode MAXRESP for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_DEFAULT (_ADC_CTRL_CHCONMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_MAXSETTLE (_ADC_CTRL_CHCONMODE_MAXSETTLE << 29) /**< Shifted mode MAXSETTLE for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_MAXRESP (_ADC_CTRL_CHCONMODE_MAXRESP << 29) /**< Shifted mode MAXRESP for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_SHIFT 30 /**< Shift value for ADC_CHCONREFWARMIDLE */ +#define _ADC_CTRL_CHCONREFWARMIDLE_MASK 0xC0000000UL /**< Bit mask for ADC_CHCONREFWARMIDLE */ +#define _ADC_CTRL_CHCONREFWARMIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN 0x00000000UL /**< Mode PREFSCAN for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE 0x00000001UL /**< Mode PREFSINGLE for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV 0x00000002UL /**< Mode KEEPPREV for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_DEFAULT (_ADC_CTRL_CHCONREFWARMIDLE_DEFAULT << 30) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN (_ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN << 30) /**< Shifted mode PREFSCAN for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE (_ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE << 30) /**< Shifted mode PREFSINGLE for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV (_ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV << 30) /**< Shifted mode KEEPPREV for ADC_CTRL */ + +/* Bit fields for ADC CMD */ +#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */ +#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */ +#define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Channel Conversion Start */ +#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Channel Conversion Stop */ +#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */ +#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */ +#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */ + +/* Bit fields for ADC STATUS */ +#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */ +#define _ADC_STATUS_MASK 0x00031F07UL /**< Mask for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Channel Conversion Active */ +#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */ +#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANPENDING (0x1UL << 2) /**< Scan Conversion Pending */ +#define _ADC_STATUS_SCANPENDING_SHIFT 2 /**< Shift value for ADC_SCANPENDING */ +#define _ADC_STATUS_SCANPENDING_MASK 0x4UL /**< Bit mask for ADC_SCANPENDING */ +#define _ADC_STATUS_SCANPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANPENDING_DEFAULT (_ADC_STATUS_SCANPENDING_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Channel Reference Warmed Up */ +#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */ +#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_SHIFT 10 /**< Shift value for ADC_PROGERR */ +#define _ADC_STATUS_PROGERR_MASK 0xC00UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_STATUS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_BUSCONF 0x00000001UL /**< Mode BUSCONF for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_NEGSELCONF 0x00000002UL /**< Mode NEGSELCONF for ADC_STATUS */ +#define ADC_STATUS_PROGERR_DEFAULT (_ADC_STATUS_PROGERR_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_PROGERR_BUSCONF (_ADC_STATUS_PROGERR_BUSCONF << 10) /**< Shifted mode BUSCONF for ADC_STATUS */ +#define ADC_STATUS_PROGERR_NEGSELCONF (_ADC_STATUS_PROGERR_NEGSELCONF << 10) /**< Shifted mode NEGSELCONF for ADC_STATUS */ +#define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */ +#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */ +#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */ +#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Channel Data Valid */ +#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */ +#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */ + +/* Bit fields for ADC SINGLECTRL */ +#define _ADC_SINGLECTRL_RESETVALUE 0x00FFFF00UL /**< Default value for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_MASK 0xAFFFFFFFUL /**< Mask for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Channel Repetitive Mode */ +#define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ +#define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ +#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Channel Differential Mode */ +#define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Channel Result Adjustment */ +#define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ +#define _ADC_SINGLECTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ +#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ +#define _ADC_SINGLECTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ +#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_5V (_ADC_SINGLECTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_CONF (_ADC_SINGLECTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SHIFT 8 /**< Shift value for ADC_POSSEL */ +#define _ADC_SINGLECTRL_POSSEL_MASK 0xFF00UL /**< Bit mask for ADC_POSSEL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_BU 0x000000E1UL /**< Mode BU for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_AREG 0x000000E2UL /**< Mode AREG for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VREGOUTPA 0x000000E3UL /**< Mode VREGOUTPA for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_PDBU 0x000000E4UL /**< Mode PDBU for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_IO0 0x000000E5UL /**< Mode IO0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_IO1 0x000000E6UL /**< Mode IO1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_OPA2 0x000000F2UL /**< Mode OPA2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_TESTP 0x000000F5UL /**< Mode TESTP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SUBLSB 0x000000F9UL /**< Mode SUBLSB for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_OPA3 0x000000FAUL /**< Mode OPA3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH0 (_ADC_SINGLECTRL_POSSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH1 (_ADC_SINGLECTRL_POSSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH2 (_ADC_SINGLECTRL_POSSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH3 (_ADC_SINGLECTRL_POSSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH4 (_ADC_SINGLECTRL_POSSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH5 (_ADC_SINGLECTRL_POSSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH6 (_ADC_SINGLECTRL_POSSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH7 (_ADC_SINGLECTRL_POSSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH8 (_ADC_SINGLECTRL_POSSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH9 (_ADC_SINGLECTRL_POSSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH10 (_ADC_SINGLECTRL_POSSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH11 (_ADC_SINGLECTRL_POSSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH12 (_ADC_SINGLECTRL_POSSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH13 (_ADC_SINGLECTRL_POSSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH14 (_ADC_SINGLECTRL_POSSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH15 (_ADC_SINGLECTRL_POSSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH0 (_ADC_SINGLECTRL_POSSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH1 (_ADC_SINGLECTRL_POSSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH2 (_ADC_SINGLECTRL_POSSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH3 (_ADC_SINGLECTRL_POSSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH4 (_ADC_SINGLECTRL_POSSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH5 (_ADC_SINGLECTRL_POSSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH6 (_ADC_SINGLECTRL_POSSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH7 (_ADC_SINGLECTRL_POSSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH8 (_ADC_SINGLECTRL_POSSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH9 (_ADC_SINGLECTRL_POSSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH10 (_ADC_SINGLECTRL_POSSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH11 (_ADC_SINGLECTRL_POSSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH12 (_ADC_SINGLECTRL_POSSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH13 (_ADC_SINGLECTRL_POSSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH14 (_ADC_SINGLECTRL_POSSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH15 (_ADC_SINGLECTRL_POSSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH0 (_ADC_SINGLECTRL_POSSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH1 (_ADC_SINGLECTRL_POSSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH2 (_ADC_SINGLECTRL_POSSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH3 (_ADC_SINGLECTRL_POSSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH4 (_ADC_SINGLECTRL_POSSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH5 (_ADC_SINGLECTRL_POSSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH6 (_ADC_SINGLECTRL_POSSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH7 (_ADC_SINGLECTRL_POSSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH8 (_ADC_SINGLECTRL_POSSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH9 (_ADC_SINGLECTRL_POSSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH10 (_ADC_SINGLECTRL_POSSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH11 (_ADC_SINGLECTRL_POSSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH12 (_ADC_SINGLECTRL_POSSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH13 (_ADC_SINGLECTRL_POSSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH14 (_ADC_SINGLECTRL_POSSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH15 (_ADC_SINGLECTRL_POSSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH16 (_ADC_SINGLECTRL_POSSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH17 (_ADC_SINGLECTRL_POSSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH18 (_ADC_SINGLECTRL_POSSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH19 (_ADC_SINGLECTRL_POSSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH20 (_ADC_SINGLECTRL_POSSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH21 (_ADC_SINGLECTRL_POSSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH22 (_ADC_SINGLECTRL_POSSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH23 (_ADC_SINGLECTRL_POSSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH24 (_ADC_SINGLECTRL_POSSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH25 (_ADC_SINGLECTRL_POSSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH26 (_ADC_SINGLECTRL_POSSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH27 (_ADC_SINGLECTRL_POSSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH28 (_ADC_SINGLECTRL_POSSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH29 (_ADC_SINGLECTRL_POSSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH30 (_ADC_SINGLECTRL_POSSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH31 (_ADC_SINGLECTRL_POSSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH0 (_ADC_SINGLECTRL_POSSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH1 (_ADC_SINGLECTRL_POSSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH2 (_ADC_SINGLECTRL_POSSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH3 (_ADC_SINGLECTRL_POSSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH4 (_ADC_SINGLECTRL_POSSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH5 (_ADC_SINGLECTRL_POSSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH6 (_ADC_SINGLECTRL_POSSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH7 (_ADC_SINGLECTRL_POSSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH8 (_ADC_SINGLECTRL_POSSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH9 (_ADC_SINGLECTRL_POSSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH10 (_ADC_SINGLECTRL_POSSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH11 (_ADC_SINGLECTRL_POSSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH12 (_ADC_SINGLECTRL_POSSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH13 (_ADC_SINGLECTRL_POSSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH14 (_ADC_SINGLECTRL_POSSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH15 (_ADC_SINGLECTRL_POSSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH16 (_ADC_SINGLECTRL_POSSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH17 (_ADC_SINGLECTRL_POSSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH18 (_ADC_SINGLECTRL_POSSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH19 (_ADC_SINGLECTRL_POSSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH20 (_ADC_SINGLECTRL_POSSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH21 (_ADC_SINGLECTRL_POSSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH22 (_ADC_SINGLECTRL_POSSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH23 (_ADC_SINGLECTRL_POSSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH24 (_ADC_SINGLECTRL_POSSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH25 (_ADC_SINGLECTRL_POSSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH26 (_ADC_SINGLECTRL_POSSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH27 (_ADC_SINGLECTRL_POSSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH28 (_ADC_SINGLECTRL_POSSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH29 (_ADC_SINGLECTRL_POSSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH30 (_ADC_SINGLECTRL_POSSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH31 (_ADC_SINGLECTRL_POSSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH0 (_ADC_SINGLECTRL_POSSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH1 (_ADC_SINGLECTRL_POSSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH2 (_ADC_SINGLECTRL_POSSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH3 (_ADC_SINGLECTRL_POSSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH4 (_ADC_SINGLECTRL_POSSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH5 (_ADC_SINGLECTRL_POSSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH6 (_ADC_SINGLECTRL_POSSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH7 (_ADC_SINGLECTRL_POSSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH8 (_ADC_SINGLECTRL_POSSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH9 (_ADC_SINGLECTRL_POSSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH10 (_ADC_SINGLECTRL_POSSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH11 (_ADC_SINGLECTRL_POSSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH12 (_ADC_SINGLECTRL_POSSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH13 (_ADC_SINGLECTRL_POSSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH14 (_ADC_SINGLECTRL_POSSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH15 (_ADC_SINGLECTRL_POSSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH16 (_ADC_SINGLECTRL_POSSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH17 (_ADC_SINGLECTRL_POSSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH18 (_ADC_SINGLECTRL_POSSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH19 (_ADC_SINGLECTRL_POSSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH20 (_ADC_SINGLECTRL_POSSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH21 (_ADC_SINGLECTRL_POSSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH22 (_ADC_SINGLECTRL_POSSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH23 (_ADC_SINGLECTRL_POSSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH24 (_ADC_SINGLECTRL_POSSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH25 (_ADC_SINGLECTRL_POSSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH26 (_ADC_SINGLECTRL_POSSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH27 (_ADC_SINGLECTRL_POSSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH28 (_ADC_SINGLECTRL_POSSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH29 (_ADC_SINGLECTRL_POSSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH30 (_ADC_SINGLECTRL_POSSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH31 (_ADC_SINGLECTRL_POSSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH0 (_ADC_SINGLECTRL_POSSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH1 (_ADC_SINGLECTRL_POSSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH2 (_ADC_SINGLECTRL_POSSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH3 (_ADC_SINGLECTRL_POSSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH4 (_ADC_SINGLECTRL_POSSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH5 (_ADC_SINGLECTRL_POSSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH6 (_ADC_SINGLECTRL_POSSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH7 (_ADC_SINGLECTRL_POSSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH8 (_ADC_SINGLECTRL_POSSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH9 (_ADC_SINGLECTRL_POSSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH10 (_ADC_SINGLECTRL_POSSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH11 (_ADC_SINGLECTRL_POSSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH12 (_ADC_SINGLECTRL_POSSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH13 (_ADC_SINGLECTRL_POSSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH14 (_ADC_SINGLECTRL_POSSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH15 (_ADC_SINGLECTRL_POSSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH16 (_ADC_SINGLECTRL_POSSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH17 (_ADC_SINGLECTRL_POSSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH18 (_ADC_SINGLECTRL_POSSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH19 (_ADC_SINGLECTRL_POSSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH20 (_ADC_SINGLECTRL_POSSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH21 (_ADC_SINGLECTRL_POSSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH22 (_ADC_SINGLECTRL_POSSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH23 (_ADC_SINGLECTRL_POSSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH24 (_ADC_SINGLECTRL_POSSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH25 (_ADC_SINGLECTRL_POSSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH26 (_ADC_SINGLECTRL_POSSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH27 (_ADC_SINGLECTRL_POSSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH28 (_ADC_SINGLECTRL_POSSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH29 (_ADC_SINGLECTRL_POSSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_BU (_ADC_SINGLECTRL_POSSEL_BU << 8) /**< Shifted mode BU for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_AREG (_ADC_SINGLECTRL_POSSEL_AREG << 8) /**< Shifted mode AREG for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VREGOUTPA (_ADC_SINGLECTRL_POSSEL_VREGOUTPA << 8) /**< Shifted mode VREGOUTPA for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_PDBU (_ADC_SINGLECTRL_POSSEL_PDBU << 8) /**< Shifted mode PDBU for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_IO0 (_ADC_SINGLECTRL_POSSEL_IO0 << 8) /**< Shifted mode IO0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_IO1 (_ADC_SINGLECTRL_POSSEL_IO1 << 8) /**< Shifted mode IO1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_OPA2 (_ADC_SINGLECTRL_POSSEL_OPA2 << 8) /**< Shifted mode OPA2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_TESTP (_ADC_SINGLECTRL_POSSEL_TESTP << 8) /**< Shifted mode TESTP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SUBLSB (_ADC_SINGLECTRL_POSSEL_SUBLSB << 8) /**< Shifted mode SUBLSB for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_OPA3 (_ADC_SINGLECTRL_POSSEL_OPA3 << 8) /**< Shifted mode OPA3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DEFAULT (_ADC_SINGLECTRL_POSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VSS (_ADC_SINGLECTRL_POSSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_SHIFT 16 /**< Shift value for ADC_NEGSEL */ +#define _ADC_SINGLECTRL_NEGSEL_MASK 0xFF0000UL /**< Bit mask for ADC_NEGSEL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_TESTN 0x000000F5UL /**< Mode TESTN for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH0 << 16) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH1 << 16) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH2 << 16) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH3 << 16) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH4 << 16) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH5 << 16) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH6 << 16) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH7 << 16) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH8 << 16) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH9 << 16) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH10 << 16) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH11 << 16) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH12 << 16) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH13 << 16) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH14 << 16) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH15 << 16) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH0 << 16) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH1 << 16) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH2 << 16) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH3 << 16) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH4 << 16) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH5 << 16) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH6 << 16) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH7 << 16) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH8 << 16) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH9 << 16) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH10 << 16) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH11 << 16) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH12 << 16) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH13 << 16) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH14 << 16) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH15 << 16) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH1 << 16) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH3 << 16) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH5 << 16) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH7 << 16) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH9 << 16) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH11 << 16) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH13 << 16) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH15 << 16) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH17 << 16) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH19 << 16) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH21 << 16) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH23 << 16) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH25 << 16) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH27 << 16) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH29 << 16) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH31 << 16) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH0 << 16) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH2 << 16) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH4 << 16) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH6 << 16) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH8 << 16) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH10 << 16) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH12 << 16) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH14 << 16) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH16 << 16) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH18 << 16) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH20 << 16) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH22 << 16) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH24 << 16) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH26 << 16) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH28 << 16) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH30 << 16) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH1 << 16) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH3 << 16) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH5 << 16) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH7 << 16) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH9 << 16) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH11 << 16) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH13 << 16) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH15 << 16) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH17 << 16) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH19 << 16) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH21 << 16) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH23 << 16) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH25 << 16) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH27 << 16) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH29 << 16) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH31 << 16) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_TESTN (_ADC_SINGLECTRL_NEGSEL_TESTN << 16) /**< Shifted mode TESTN for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_DEFAULT (_ADC_SINGLECTRL_NEGSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_VSS (_ADC_SINGLECTRL_NEGSEL_VSS << 16) /**< Shifted mode VSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ +#define _ADC_SINGLECTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ +#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_3CYCLES (_ADC_SINGLECTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN (0x1UL << 29) /**< Single Channel PRS Trigger Enable */ +#define _ADC_SINGLECTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Single Channel */ +#define _ADC_SINGLECTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ +#define _ADC_SINGLECTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ +#define _ADC_SINGLECTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_CMPEN_DEFAULT (_ADC_SINGLECTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ + +/* Bit fields for ADC SINGLECTRLX */ +#define _ADC_SINGLECTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ +#define _ADC_SINGLECTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ +#define _ADC_SINGLECTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_DEFAULT (_ADC_SINGLECTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VBGR (_ADC_SINGLECTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VDDXWATT (_ADC_SINGLECTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFP (_ADC_SINGLECTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VENTROPY (_ADC_SINGLECTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */ +#define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ +#define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ +#define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATTFIX_DEFAULT (_ADC_SINGLECTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ +#define _ADC_SINGLECTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ +#define _ADC_SINGLECTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATT_DEFAULT (_ADC_SINGLECTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ +#define _ADC_SINGLECTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ +#define _ADC_SINGLECTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VINATT_DEFAULT (_ADC_SINGLECTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ +#define _ADC_SINGLECTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ +#define _ADC_SINGLECTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_DVL_DEFAULT (_ADC_SINGLECTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT (0x1UL << 14) /**< Single Channel FIFO Overflow Action */ +#define _ADC_SINGLECTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ +#define _ADC_SINGLECTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ +#define _ADC_SINGLECTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_DEFAULT (_ADC_SINGLECTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_DISCARD (_ADC_SINGLECTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE (_ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE (0x1UL << 16) /**< Single Channel PRS Trigger Mode */ +#define _ADC_SINGLECTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ +#define _ADC_SINGLECTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ +#define _ADC_SINGLECTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_DEFAULT (_ADC_SINGLECTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_PULSED (_ADC_SINGLECTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_TIMED (_ADC_SINGLECTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ +#define _ADC_SINGLECTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */ +#define _ADC_SINGLECTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_DEFAULT (_ADC_SINGLECTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH0 (_ADC_SINGLECTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH1 (_ADC_SINGLECTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH2 (_ADC_SINGLECTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH3 (_ADC_SINGLECTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH4 (_ADC_SINGLECTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH5 (_ADC_SINGLECTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH6 (_ADC_SINGLECTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH7 (_ADC_SINGLECTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH8 (_ADC_SINGLECTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH9 (_ADC_SINGLECTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH10 (_ADC_SINGLECTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH11 (_ADC_SINGLECTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ +#define _ADC_SINGLECTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ +#define _ADC_SINGLECTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_DEFAULT (_ADC_SINGLECTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_NODELAY (_ADC_SINGLECTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_4CYCLES (_ADC_SINGLECTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_8CYCLES (_ADC_SINGLECTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_16CYCLES (_ADC_SINGLECTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_32CYCLES (_ADC_SINGLECTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_64CYCLES (_ADC_SINGLECTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_128CYCLES (_ADC_SINGLECTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_256CYCLES (_ADC_SINGLECTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SINGLECTRLX */ + +/* Bit fields for ADC SCANCTRL */ +#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_MASK 0xAF0000FFUL /**< Mask for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */ +#define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ +#define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ +#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */ +#define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */ +#define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ +#define _ADC_SCANCTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ +#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ +#define _ADC_SCANCTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ +#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_5V (_ADC_SCANCTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_CONF (_ADC_SCANCTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ +#define _ADC_SCANCTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ +#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_3CYCLES (_ADC_SCANCTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN (0x1UL << 29) /**< Scan Sequence PRS Trigger Enable */ +#define _ADC_SCANCTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Scan */ +#define _ADC_SCANCTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ +#define _ADC_SCANCTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ +#define _ADC_SCANCTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_CMPEN_DEFAULT (_ADC_SCANCTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ + +/* Bit fields for ADC SCANCTRLX */ +#define _ADC_SCANCTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ +#define _ADC_SCANCTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ +#define _ADC_SCANCTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_DEFAULT (_ADC_SCANCTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VBGR (_ADC_SCANCTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VDDXWATT (_ADC_SCANCTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPWATT (_ADC_SCANCTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFP (_ADC_SCANCTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */ +#define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ +#define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ +#define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATTFIX_DEFAULT (_ADC_SCANCTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ +#define _ADC_SCANCTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ +#define _ADC_SCANCTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATT_DEFAULT (_ADC_SCANCTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ +#define _ADC_SCANCTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ +#define _ADC_SCANCTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VINATT_DEFAULT (_ADC_SCANCTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ +#define _ADC_SCANCTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ +#define _ADC_SCANCTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_DVL_DEFAULT (_ADC_SCANCTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT (0x1UL << 14) /**< Scan FIFO Overflow Action */ +#define _ADC_SCANCTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ +#define _ADC_SCANCTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ +#define _ADC_SCANCTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_DEFAULT (_ADC_SCANCTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_DISCARD (_ADC_SCANCTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_OVERWRITE (_ADC_SCANCTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE (0x1UL << 16) /**< Scan PRS Trigger Mode */ +#define _ADC_SCANCTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ +#define _ADC_SCANCTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ +#define _ADC_SCANCTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_DEFAULT (_ADC_SCANCTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_PULSED (_ADC_SCANCTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_TIMED (_ADC_SCANCTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ +#define _ADC_SCANCTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */ +#define _ADC_SCANCTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_DEFAULT (_ADC_SCANCTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH0 (_ADC_SCANCTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH1 (_ADC_SCANCTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH2 (_ADC_SCANCTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH3 (_ADC_SCANCTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH4 (_ADC_SCANCTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH5 (_ADC_SCANCTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH6 (_ADC_SCANCTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH7 (_ADC_SCANCTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH8 (_ADC_SCANCTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH9 (_ADC_SCANCTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH10 (_ADC_SCANCTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH11 (_ADC_SCANCTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ +#define _ADC_SCANCTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ +#define _ADC_SCANCTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_DEFAULT (_ADC_SCANCTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_NODELAY (_ADC_SCANCTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_4CYCLES (_ADC_SCANCTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_8CYCLES (_ADC_SCANCTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_16CYCLES (_ADC_SCANCTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_32CYCLES (_ADC_SCANCTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_64CYCLES (_ADC_SCANCTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_128CYCLES (_ADC_SCANCTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_256CYCLES (_ADC_SCANCTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SCANCTRLX */ + +/* Bit fields for ADC SCANMASK */ +#define _ADC_SCANMASK_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANMASK */ +#define _ADC_SCANMASK_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */ +#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */ +#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */ + +/* Bit fields for ADC SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_MASK 0x1F1F1F1FUL /**< Mask for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT 0 /**< Shift value for ADC_INPUT0TO7SEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_MASK 0x1FUL /**< Bit mask for ADC_INPUT0TO7SEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 << 0) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 << 0) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 << 0) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 << 0) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 << 0) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 << 0) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 << 0) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 << 0) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 << 0) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 << 0) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT 8 /**< Shift value for ADC_INPUT8TO15SEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_MASK 0x1F00UL /**< Bit mask for ADC_INPUT8TO15SEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 << 8) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 << 8) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 << 8) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 << 8) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 << 8) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 << 8) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 << 8) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 << 8) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 << 8) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 << 8) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT 16 /**< Shift value for ADC_INPUT16TO23SEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_MASK 0x1F0000UL /**< Bit mask for ADC_INPUT16TO23SEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 << 16) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 << 16) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 << 16) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 << 16) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 << 16) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 << 16) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 << 16) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 << 16) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 << 16) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 << 16) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT 24 /**< Shift value for ADC_INPUT24TO31SEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_MASK 0x1F000000UL /**< Bit mask for ADC_INPUT24TO31SEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 << 24) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 << 24) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 << 24) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 << 24) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 << 24) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 << 24) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 << 24) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 << 24) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 << 24) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 << 24) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ + +/* Bit fields for ADC SCANNEGSEL */ +#define _ADC_SCANNEGSEL_RESETVALUE 0x000039E4UL /**< Default value for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_MASK 0x0000FFFFUL /**< Mask for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT 0 /**< Shift value for ADC_INPUT0NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK 0x3UL /**< Bit mask for ADC_INPUT0NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT 2 /**< Shift value for ADC_INPUT2NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK 0xCUL /**< Bit mask for ADC_INPUT2NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 << 2) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 << 2) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 << 2) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 << 2) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT 4 /**< Shift value for ADC_INPUT4NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK 0x30UL /**< Bit mask for ADC_INPUT4NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 << 4) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 << 4) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 << 4) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 << 4) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT 6 /**< Shift value for ADC_INPUT6NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK 0xC0UL /**< Bit mask for ADC_INPUT6NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 << 6) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 << 6) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 << 6) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 << 6) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT 8 /**< Shift value for ADC_INPUT9NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK 0x300UL /**< Bit mask for ADC_INPUT9NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 << 8) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 << 8) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 << 8) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 << 8) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT 10 /**< Shift value for ADC_INPUT11NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK 0xC00UL /**< Bit mask for ADC_INPUT11NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 << 10) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 << 10) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 << 10) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 << 10) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT 12 /**< Shift value for ADC_INPUT13NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK 0x3000UL /**< Bit mask for ADC_INPUT13NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 << 12) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 << 12) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 << 12) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 << 12) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT 14 /**< Shift value for ADC_INPUT15NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK 0xC000UL /**< Bit mask for ADC_INPUT15NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 << 14) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 << 14) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 << 14) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 << 14) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ + +/* Bit fields for ADC CMPTHR */ +#define _ADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for ADC_CMPTHR */ +#define _ADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for ADC_CMPTHR */ +#define _ADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for ADC_ADLT */ +#define _ADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for ADC_ADLT */ +#define _ADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ +#define ADC_CMPTHR_ADLT_DEFAULT (_ADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMPTHR */ +#define _ADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for ADC_ADGT */ +#define _ADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for ADC_ADGT */ +#define _ADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ +#define ADC_CMPTHR_ADGT_DEFAULT (_ADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CMPTHR */ + +/* Bit fields for ADC BIASPROG */ +#define _ADC_BIASPROG_RESETVALUE 0x00000000UL /**< Default value for ADC_BIASPROG */ +#define _ADC_BIASPROG_MASK 0x0001100FUL /**< Mask for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SHIFT 0 /**< Shift value for ADC_ADCBIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_MASK 0xFUL /**< Bit mask for ADC_ADCBIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE2 0x00000004UL /**< Mode SCALE2 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE4 0x00000008UL /**< Mode SCALE4 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE8 0x0000000CUL /**< Mode SCALE8 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE16 0x0000000EUL /**< Mode SCALE16 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE32 0x0000000FUL /**< Mode SCALE32 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_DEFAULT (_ADC_BIASPROG_ADCBIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_NORMAL (_ADC_BIASPROG_ADCBIASPROG_NORMAL << 0) /**< Shifted mode NORMAL for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE2 (_ADC_BIASPROG_ADCBIASPROG_SCALE2 << 0) /**< Shifted mode SCALE2 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE4 (_ADC_BIASPROG_ADCBIASPROG_SCALE4 << 0) /**< Shifted mode SCALE4 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */ +#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF flag */ +#define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */ +#define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */ +#define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy setting for the system bias during ADC operation */ +#define _ADC_BIASPROG_GPBIASACC_SHIFT 16 /**< Shift value for ADC_GPBIASACC */ +#define _ADC_BIASPROG_GPBIASACC_MASK 0x10000UL /**< Bit mask for ADC_GPBIASACC */ +#define _ADC_BIASPROG_GPBIASACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_GPBIASACC_HIGHACC 0x00000000UL /**< Mode HIGHACC for ADC_BIASPROG */ +#define _ADC_BIASPROG_GPBIASACC_LOWACC 0x00000001UL /**< Mode LOWACC for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_DEFAULT (_ADC_BIASPROG_GPBIASACC_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_HIGHACC (_ADC_BIASPROG_GPBIASACC_HIGHACC << 16) /**< Shifted mode HIGHACC for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_LOWACC (_ADC_BIASPROG_GPBIASACC_LOWACC << 16) /**< Shifted mode LOWACC for ADC_BIASPROG */ + +/* Bit fields for ADC CAL */ +#define _ADC_CAL_RESETVALUE 0x40784078UL /**< Default value for ADC_CAL */ +#define _ADC_CAL_MASK 0xFFFFFFFFUL /**< Mask for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_MASK 0xFUL /**< Bit mask for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSETINV_SHIFT 4 /**< Shift value for ADC_SINGLEOFFSETINV */ +#define _ADC_CAL_SINGLEOFFSETINV_MASK 0xF0UL /**< Bit mask for ADC_SINGLEOFFSETINV */ +#define _ADC_CAL_SINGLEOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEOFFSETINV_DEFAULT (_ADC_CAL_SINGLEOFFSETINV_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */ +#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative single-ended offset calibration is enabled */ +#define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */ +#define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */ +#define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_OFFSETINVMODE_DEFAULT (_ADC_CAL_OFFSETINVMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_MASK 0xF0000UL /**< Bit mask for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSETINV_SHIFT 20 /**< Shift value for ADC_SCANOFFSETINV */ +#define _ADC_CAL_SCANOFFSETINV_MASK 0xF00000UL /**< Bit mask for ADC_SCANOFFSETINV */ +#define _ADC_CAL_SCANOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANOFFSETINV_DEFAULT (_ADC_CAL_SCANOFFSETINV_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */ +#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration mode is enabled */ +#define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */ +#define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */ +#define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_CALEN_DEFAULT (_ADC_CAL_CALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_CAL */ + +/* Bit fields for ADC IF */ +#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */ +#define _ADC_IF_MASK 0x3F030F03UL /**< Mask for ADC_IF */ +#define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */ +#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */ +#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single FIFO Overflow Interrupt Flag */ +#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF (0x1UL << 9) /**< Scan FIFO Overflow Interrupt Flag */ +#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEUF (0x1UL << 10) /**< Single FIFO Underflow Interrupt Flag */ +#define _ADC_IF_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IF_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IF_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEUF_DEFAULT (_ADC_IF_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANUF (0x1UL << 11) /**< Scan FIFO Underflow Interrupt Flag */ +#define _ADC_IF_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IF_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IF_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANUF_DEFAULT (_ADC_IF_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLECMP (0x1UL << 16) /**< Single Result Compare Match Interrupt Flag */ +#define _ADC_IF_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IF_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLECMP_DEFAULT (_ADC_IF_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANCMP (0x1UL << 17) /**< Scan Result Compare Match Interrupt Flag */ +#define _ADC_IF_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IF_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANCMP_DEFAULT (_ADC_IF_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_VREFOV (0x1UL << 24) /**< VREF Over Voltage Interrupt Flag */ +#define _ADC_IF_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IF_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IF_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_VREFOV_DEFAULT (_ADC_IF_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_PROGERR (0x1UL << 25) /**< Programming Error Interrupt Flag */ +#define _ADC_IF_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IF_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IF_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_PROGERR_DEFAULT (_ADC_IF_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANEXTPEND (0x1UL << 26) /**< External Scan Trigger Pending Flag */ +#define _ADC_IF_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IF_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IF_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANEXTPEND_DEFAULT (_ADC_IF_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANPEND (0x1UL << 27) /**< Scan Trigger Pending Flag */ +#define _ADC_IF_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IF_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IF_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANPEND_DEFAULT (_ADC_IF_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_PRSTIMEDERR (0x1UL << 28) /**< PRS Timed Mode Error Flag */ +#define _ADC_IF_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IF_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IF_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_PRSTIMEDERR_DEFAULT (_ADC_IF_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_EM23ERR (0x1UL << 29) /**< EM23 Entry Error Flag */ +#define _ADC_IF_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IF_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_EM23ERR_DEFAULT (_ADC_IF_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IF */ + +/* Bit fields for ADC IFS */ +#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */ +#define _ADC_IFS_MASK 0x3F030F00UL /**< Mask for ADC_IFS */ +#define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Set SINGLEOF Interrupt Flag */ +#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF (0x1UL << 9) /**< Set SCANOF Interrupt Flag */ +#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEUF (0x1UL << 10) /**< Set SINGLEUF Interrupt Flag */ +#define _ADC_IFS_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IFS_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IFS_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEUF_DEFAULT (_ADC_IFS_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANUF (0x1UL << 11) /**< Set SCANUF Interrupt Flag */ +#define _ADC_IFS_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IFS_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IFS_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANUF_DEFAULT (_ADC_IFS_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLECMP (0x1UL << 16) /**< Set SINGLECMP Interrupt Flag */ +#define _ADC_IFS_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IFS_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IFS_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLECMP_DEFAULT (_ADC_IFS_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANCMP (0x1UL << 17) /**< Set SCANCMP Interrupt Flag */ +#define _ADC_IFS_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IFS_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IFS_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANCMP_DEFAULT (_ADC_IFS_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_VREFOV (0x1UL << 24) /**< Set VREFOV Interrupt Flag */ +#define _ADC_IFS_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IFS_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IFS_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_VREFOV_DEFAULT (_ADC_IFS_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PROGERR (0x1UL << 25) /**< Set PROGERR Interrupt Flag */ +#define _ADC_IFS_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IFS_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IFS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PROGERR_DEFAULT (_ADC_IFS_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANEXTPEND (0x1UL << 26) /**< Set SCANEXTPEND Interrupt Flag */ +#define _ADC_IFS_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IFS_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IFS_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANEXTPEND_DEFAULT (_ADC_IFS_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANPEND (0x1UL << 27) /**< Set SCANPEND Interrupt Flag */ +#define _ADC_IFS_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IFS_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IFS_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANPEND_DEFAULT (_ADC_IFS_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PRSTIMEDERR (0x1UL << 28) /**< Set PRSTIMEDERR Interrupt Flag */ +#define _ADC_IFS_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IFS_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IFS_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PRSTIMEDERR_DEFAULT (_ADC_IFS_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_EM23ERR (0x1UL << 29) /**< Set EM23ERR Interrupt Flag */ +#define _ADC_IFS_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IFS_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_EM23ERR_DEFAULT (_ADC_IFS_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFS */ + +/* Bit fields for ADC IFC */ +#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */ +#define _ADC_IFC_MASK 0x3F030F00UL /**< Mask for ADC_IFC */ +#define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Clear SINGLEOF Interrupt Flag */ +#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF (0x1UL << 9) /**< Clear SCANOF Interrupt Flag */ +#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEUF (0x1UL << 10) /**< Clear SINGLEUF Interrupt Flag */ +#define _ADC_IFC_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IFC_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IFC_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEUF_DEFAULT (_ADC_IFC_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANUF (0x1UL << 11) /**< Clear SCANUF Interrupt Flag */ +#define _ADC_IFC_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IFC_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IFC_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANUF_DEFAULT (_ADC_IFC_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLECMP (0x1UL << 16) /**< Clear SINGLECMP Interrupt Flag */ +#define _ADC_IFC_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IFC_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IFC_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLECMP_DEFAULT (_ADC_IFC_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANCMP (0x1UL << 17) /**< Clear SCANCMP Interrupt Flag */ +#define _ADC_IFC_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IFC_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IFC_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANCMP_DEFAULT (_ADC_IFC_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_VREFOV (0x1UL << 24) /**< Clear VREFOV Interrupt Flag */ +#define _ADC_IFC_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IFC_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IFC_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_VREFOV_DEFAULT (_ADC_IFC_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PROGERR (0x1UL << 25) /**< Clear PROGERR Interrupt Flag */ +#define _ADC_IFC_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IFC_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IFC_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PROGERR_DEFAULT (_ADC_IFC_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANEXTPEND (0x1UL << 26) /**< Clear SCANEXTPEND Interrupt Flag */ +#define _ADC_IFC_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IFC_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IFC_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANEXTPEND_DEFAULT (_ADC_IFC_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANPEND (0x1UL << 27) /**< Clear SCANPEND Interrupt Flag */ +#define _ADC_IFC_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IFC_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IFC_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANPEND_DEFAULT (_ADC_IFC_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PRSTIMEDERR (0x1UL << 28) /**< Clear PRSTIMEDERR Interrupt Flag */ +#define _ADC_IFC_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IFC_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IFC_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PRSTIMEDERR_DEFAULT (_ADC_IFC_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_EM23ERR (0x1UL << 29) /**< Clear EM23ERR Interrupt Flag */ +#define _ADC_IFC_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IFC_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_EM23ERR_DEFAULT (_ADC_IFC_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFC */ + +/* Bit fields for ADC IEN */ +#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */ +#define _ADC_IEN_MASK 0x3F030F03UL /**< Mask for ADC_IEN */ +#define ADC_IEN_SINGLE (0x1UL << 0) /**< SINGLE Interrupt Enable */ +#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN (0x1UL << 1) /**< SCAN Interrupt Enable */ +#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF (0x1UL << 8) /**< SINGLEOF Interrupt Enable */ +#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF (0x1UL << 9) /**< SCANOF Interrupt Enable */ +#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEUF (0x1UL << 10) /**< SINGLEUF Interrupt Enable */ +#define _ADC_IEN_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IEN_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IEN_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEUF_DEFAULT (_ADC_IEN_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANUF (0x1UL << 11) /**< SCANUF Interrupt Enable */ +#define _ADC_IEN_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IEN_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IEN_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANUF_DEFAULT (_ADC_IEN_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLECMP (0x1UL << 16) /**< SINGLECMP Interrupt Enable */ +#define _ADC_IEN_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IEN_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLECMP_DEFAULT (_ADC_IEN_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANCMP (0x1UL << 17) /**< SCANCMP Interrupt Enable */ +#define _ADC_IEN_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IEN_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANCMP_DEFAULT (_ADC_IEN_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_VREFOV (0x1UL << 24) /**< VREFOV Interrupt Enable */ +#define _ADC_IEN_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IEN_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IEN_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_VREFOV_DEFAULT (_ADC_IEN_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PROGERR (0x1UL << 25) /**< PROGERR Interrupt Enable */ +#define _ADC_IEN_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IEN_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IEN_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PROGERR_DEFAULT (_ADC_IEN_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANEXTPEND (0x1UL << 26) /**< SCANEXTPEND Interrupt Enable */ +#define _ADC_IEN_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IEN_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IEN_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANEXTPEND_DEFAULT (_ADC_IEN_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANPEND (0x1UL << 27) /**< SCANPEND Interrupt Enable */ +#define _ADC_IEN_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IEN_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IEN_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANPEND_DEFAULT (_ADC_IEN_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PRSTIMEDERR (0x1UL << 28) /**< PRSTIMEDERR Interrupt Enable */ +#define _ADC_IEN_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IEN_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IEN_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PRSTIMEDERR_DEFAULT (_ADC_IEN_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_EM23ERR (0x1UL << 29) /**< EM23ERR Interrupt Enable */ +#define _ADC_IEN_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IEN_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_EM23ERR_DEFAULT (_ADC_IEN_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IEN */ + +/* Bit fields for ADC SINGLEDATA */ +#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */ +#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */ + +/* Bit fields for ADC SCANDATA */ +#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */ +#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */ +#define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */ +#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */ + +/* Bit fields for ADC SINGLEDATAP */ +#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */ +#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */ + +/* Bit fields for ADC SCANDATAP */ +#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */ +#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */ + +/* Bit fields for ADC SCANDATAX */ +#define _ADC_SCANDATAX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SCANDATAX_DATA_MASK 0xFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SCANDATAX_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ +#define ADC_SCANDATAX_DATA_DEFAULT (_ADC_SCANDATAX_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_SCANINPUTID_SHIFT 16 /**< Shift value for ADC_SCANINPUTID */ +#define _ADC_SCANDATAX_SCANINPUTID_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTID */ +#define _ADC_SCANDATAX_SCANINPUTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ +#define ADC_SCANDATAX_SCANINPUTID_DEFAULT (_ADC_SCANDATAX_SCANINPUTID_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ + +/* Bit fields for ADC SCANDATAXP */ +#define _ADC_SCANDATAXP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SCANDATAXP_DATAP_MASK 0xFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SCANDATAXP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ +#define ADC_SCANDATAXP_DATAP_DEFAULT (_ADC_SCANDATAXP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_SHIFT 16 /**< Shift value for ADC_SCANINPUTIDPEEK */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTIDPEEK */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ +#define ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT (_ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ + +/* Bit fields for ADC APORTREQ */ +#define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */ +#define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */ +#define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */ +#define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */ +#define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */ +#define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */ +#define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */ +#define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT1X is requested */ +#define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */ +#define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */ +#define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */ +#define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */ +#define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */ +#define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */ +#define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */ +#define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */ +#define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */ +#define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */ +#define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */ +#define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */ +#define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */ +#define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */ +#define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */ +#define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */ +#define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */ +#define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4YREQ_DEFAULT (_ADC_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTREQ */ + +/* Bit fields for ADC APORTCONFLICT */ +#define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */ +#define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ + +/* Bit fields for ADC SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_SHIFT 0 /**< Shift value for ADC_SINGLEDC */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_MASK 0x7UL /**< Bit mask for ADC_SINGLEDC */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCOUNT */ +#define ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT (_ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCOUNT */ + +/* Bit fields for ADC SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_SCANDC_SHIFT 0 /**< Shift value for ADC_SCANDC */ +#define _ADC_SCANFIFOCOUNT_SCANDC_MASK 0x7UL /**< Bit mask for ADC_SCANDC */ +#define _ADC_SCANFIFOCOUNT_SCANDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCOUNT */ +#define ADC_SCANFIFOCOUNT_SCANDC_DEFAULT (_ADC_SCANFIFOCOUNT_SCANDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCOUNT */ + +/* Bit fields for ADC SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */ +#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO content */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */ +#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT (_ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCLEAR */ + +/* Bit fields for ADC SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */ +#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO content */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */ +#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT (_ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCLEAR */ + +/* Bit fields for ADC APORTMASTERDIS */ +#define _ADC_APORTMASTERDIS_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTMASTERDIS */ +#define _ADC_APORTMASTERDIS_MASK 0x000003FCUL /**< Mask for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1XMASTERDIS (0x1UL << 2) /**< APORT1X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_SHIFT 2 /**< Shift value for ADC_APORT1XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_MASK 0x4UL /**< Bit mask for ADC_APORT1XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1YMASTERDIS (0x1UL << 3) /**< APORT1Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_SHIFT 3 /**< Shift value for ADC_APORT1YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_MASK 0x8UL /**< Bit mask for ADC_APORT1YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2XMASTERDIS (0x1UL << 4) /**< APORT2X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_SHIFT 4 /**< Shift value for ADC_APORT2XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_MASK 0x10UL /**< Bit mask for ADC_APORT2XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2YMASTERDIS (0x1UL << 5) /**< APORT2Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_SHIFT 5 /**< Shift value for ADC_APORT2YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_MASK 0x20UL /**< Bit mask for ADC_APORT2YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3XMASTERDIS (0x1UL << 6) /**< APORT3X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_SHIFT 6 /**< Shift value for ADC_APORT3XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_MASK 0x40UL /**< Bit mask for ADC_APORT3XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3YMASTERDIS (0x1UL << 7) /**< APORT3Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_SHIFT 7 /**< Shift value for ADC_APORT3YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_MASK 0x80UL /**< Bit mask for ADC_APORT3YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4XMASTERDIS (0x1UL << 8) /**< APORT4X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_SHIFT 8 /**< Shift value for ADC_APORT4XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_MASK 0x100UL /**< Bit mask for ADC_APORT4XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4YMASTERDIS (0x1UL << 9) /**< APORT4Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_SHIFT 9 /**< Shift value for ADC_APORT4YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_MASK 0x200UL /**< Bit mask for ADC_APORT4YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ + +/** @} End of group EFR32MG12P_ADC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_pins.h new file mode 100644 index 00000000000..0524a8562a4 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_pins.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efr32mg12p_af_pins.h + * @brief EFR32MG12P_AF_PINS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_AF_Pins + * @{ + *****************************************************************************/ + +/** AF pin number for location number i */ +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1) +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : -1) +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1) +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1) +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1) +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1) +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1) +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1) +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1) +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1) +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1) +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1) +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_TIMER0_CC3_PIN(i) (-1) +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_TIMER0_CDTI3_PIN(i) (-1) +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_TIMER1_CDTI0_PIN(i) (-1) +#define AF_TIMER1_CDTI1_PIN(i) (-1) +#define AF_TIMER1_CDTI2_PIN(i) (-1) +#define AF_TIMER1_CDTI3_PIN(i) (-1) +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 12 : (i) == 13 ? 13 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 6 : (i) == 23 ? 7 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER0_CC3_PIN(i) (-1) +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 11 : (i) == 8 ? 12 : (i) == 9 ? 13 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 12 : (i) == 29 ? 13 : (i) == 30 ? 14 : (i) == 31 ? 15 : -1) +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 8 : (i) == 23 ? 9 : (i) == 24 ? 10 : (i) == 25 ? 11 : (i) == 26 ? 12 : (i) == 27 ? 13 : (i) == 28 ? 14 : (i) == 29 ? 15 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CDTI3_PIN(i) (-1) +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 4 : (i) == 9 ? 5 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 5 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 8 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 11 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 12 : (i) == 31 ? 13 : -1) +#define AF_WTIMER1_CDTI0_PIN(i) (-1) +#define AF_WTIMER1_CDTI1_PIN(i) (-1) +#define AF_WTIMER1_CDTI2_PIN(i) (-1) +#define AF_WTIMER1_CDTI3_PIN(i) (-1) +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 9 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 5 : -1) +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 3 : (i) == 15 ? 4 : (i) == 16 ? 5 : (i) == 17 ? 6 : (i) == 18 ? 7 : (i) == 19 ? 8 : (i) == 20 ? 9 : (i) == 21 ? 10 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 5 : (i) == 31 ? 6 : -1) +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 0 : (i) == 12 ? 1 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 3 : (i) == 13 ? 4 : (i) == 14 ? 5 : (i) == 15 ? 6 : (i) == 16 ? 7 : (i) == 17 ? 8 : (i) == 18 ? 9 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 8 : -1) +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 2 : (i) == 9 ? 3 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 14 : (i) == 16 ? 15 : (i) == 17 ? 0 : (i) == 18 ? 1 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 4 : (i) == 22 ? 5 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 8 : -1) +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 13 : (i) == 3 ? 14 : (i) == 4 ? 15 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 14 : (i) == 14 ? 15 : (i) == 15 ? 0 : (i) == 16 ? 1 : (i) == 17 ? 2 : (i) == 18 ? 3 : (i) == 19 ? 4 : (i) == 20 ? 5 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 8 : (i) == 30 ? 9 : (i) == 31 ? 10 : -1) +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 14 : (i) == 13 ? 15 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 4 : (i) == 19 ? 5 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 8 : (i) == 28 ? 9 : (i) == 29 ? 10 : (i) == 30 ? 11 : (i) == 31 ? 12 : -1) +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 10 : -1) +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 11 : -1) +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 12 : -1) +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 13 : -1) +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 14 : -1) +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 15 : -1) +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 4 : -1) +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 5 : -1) +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 6 : -1) +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 7 : -1) +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 14 : -1) +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 15 : -1) +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1) +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 6 : -1) +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 7 : -1) +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 8 : -1) +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 9 : -1) +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 8 : (i) == 3 ? 10 : -1) + +/** @} End of group EFR32MG12P_AF_Pins */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_ports.h new file mode 100644 index 00000000000..2e02e70c11a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_ports.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efr32mg12p_af_ports.h + * @brief EFR32MG12P_AF_PORTS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_AF_Ports + * @{ + *****************************************************************************/ + +/** AF port number for location number i */ +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 0 : -1) +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1) +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1) +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1) +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1) +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC3_PORT(i) (-1) +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI3_PORT(i) (-1) +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CDTI0_PORT(i) (-1) +#define AF_TIMER1_CDTI1_PORT(i) (-1) +#define AF_TIMER1_CDTI2_PORT(i) (-1) +#define AF_TIMER1_CDTI3_PORT(i) (-1) +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 1 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 2 : (i) == 31 ? 2 : -1) +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CC3_PORT(i) (-1) +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER0_CDTI3_PORT(i) (-1) +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CDTI0_PORT(i) (-1) +#define AF_WTIMER1_CDTI1_PORT(i) (-1) +#define AF_WTIMER1_CDTI2_PORT(i) (-1) +#define AF_WTIMER1_CDTI3_PORT(i) (-1) +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 8 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 5 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : (i) == 8 ? 8 : (i) == 9 ? 8 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 9 : (i) == 17 ? 9 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 9 : (i) == 16 ? 9 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 3 : -1) +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 9 : (i) == 15 ? 9 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 9 : (i) == 14 ? 9 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 9 : (i) == 13 ? 9 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1) +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) + +/** @} End of group EFR32MG12P_AF_Ports */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cmu.h new file mode 100644 index 00000000000..a36cbb697a6 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cmu.h @@ -0,0 +1,2032 @@ +/**************************************************************************//** + * @file efr32mg12p_cmu.h + * @brief EFR32MG12P_CMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_CMU + * @{ + * @brief EFR32MG12P_CMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CMU Control Register */ + + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + + uint32_t RESERVED9[1]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED10[1]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED11[3]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + + uint32_t RESERVED12[7]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[1]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + + uint32_t RESERVED14[1]; /**< Reserved for future use **/ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED15[3]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + + uint32_t RESERVED16[1]; /**< Reserved for future use **/ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED17[1]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + + uint32_t RESERVED18[2]; /**< Reserved for future use **/ + __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED19[1]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED20[1]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect */ + + uint32_t RESERVED21[3]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED22[2]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED23[2]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED24[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED25[1]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_CMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x001101EFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x1E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable duty cycling of vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable comparator chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable dynamic element matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x37000731UL /**< Mask for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE (0x1UL << 0) /**< HFXO Mode */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low power mode control. PSR performance is reduced to enable low current consumption. */ +#define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */ +#define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */ +#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N pin to ground when HFXO oscillator is off. */ +#define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */ +#define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */ +#define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P pin to ground when HFXO oscillator is off. */ +#define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */ +#define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */ +#define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00050020UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FF87FUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30B4507UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000168UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24 /**< Shift value for CMU_REGSELILOW */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables oscillator peak detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28 /**< Shift value for CMU_REGISHUPPER */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHUPPER */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0002A067UL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FF0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16 /**< Shift value for CMU_SHUNTOPTTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL /**< Bit mask for CMU_SHUNTOPTTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000001FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< automatic recovery ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0x70UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x000033FFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000033UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5) /**< HFXO Shunt Current Optimization Start */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5 /**< Shift value for CMU_HFXOSHUNTOPTSTART */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL /**< Bit mask for CMU_HFXOSHUNTOPTSTART */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000001UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x1UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x07E133FFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required by Hardware (e.g. RAC) */ +#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization ready */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO oscillation amplitude is too high */ +#define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */ +#define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */ +#define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO amplitude tuning value too low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO regulator shunt current too low */ +#define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */ +#define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */ +#define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ +#define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ +#define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x8003FF7FUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETERR (0x1UL << 10) /**< HFXO Automatic Peak Detection Error Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */ +#define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0x8003FF7FUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10) /**< Set HFXOPEAKDETERR Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Set HFXOSHUNTOPTRDY Interrupt Flag */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0x8003FF7FUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10) /**< Clear HFXOPEAKDETERR Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x8003FF7FUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10) /**< HFXOPEAKDETERR Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXOSHUNTOPTRDY Interrupt Enable */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x0000007FUL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 0) /**< Advanced Encryption Standard Accelerator 0 Clock Enable */ +#define CMU_HFBUSCLKEN0_CRYPTO CMU_HFBUSCLKEN0_CRYPTO0 /**< Alias for CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 0 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x1UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT /**< Alias for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_MASK _CMU_HFBUSCLKEN0_CRYPTO0_MASK /**< Alias for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT*/ +#define CMU_HFBUSCLKEN0_CRYPTO1 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator 1 Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT 1 /**< Shift value for CMU_CRYPTO1 */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_MASK 0x2UL /**< Bit mask for CMU_CRYPTO1 */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 3) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 3 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x8UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 4) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 4 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x10UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 5) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 5 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x20UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 6) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 6 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x40UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER0 (0x1UL << 2) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_WTIMER0_SHIFT 2 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN0_WTIMER0_MASK 0x4UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN0_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER0_DEFAULT (_CMU_HFPERCLKEN0_WTIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER1 (0x1UL << 3) /**< Wide Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_WTIMER1_SHIFT 3 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN0_WTIMER1_MASK 0x8UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN0_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER1_DEFAULT (_CMU_HFPERCLKEN0_WTIMER1_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 4 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x10UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 5) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 5 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x20UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 6) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 6 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x40UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 7 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x80UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 8) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 8 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x100UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 9) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 9 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x200UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 10) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 10 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x400UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 11) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 11 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x800UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 12) /**< CryoTimer Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 12 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x1000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 13) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 13 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x2000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 14) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 14 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x4000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_VDAC0 (0x1UL << 15) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_VDAC0_SHIFT 15 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN0_VDAC0_MASK 0x8000UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_VDAC0_DEFAULT (_CMU_HFPERCLKEN0_VDAC0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CSEN (0x1UL << 16) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN0_CSEN_SHIFT 16 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN0_CSEN_MASK 0x10000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CSEN_DEFAULT (_CMU_HFPERCLKEN0_CSEN_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 17) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 17 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x20000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 1) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 1 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x2UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 0) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x1UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 1) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 1 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x2UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 2) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 2 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x4UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x01001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x0000003FUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 4 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x30UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x0000033FUL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xFUL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 4 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x30UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 8 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x300UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x3F050055UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x00000130UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert clock selected by ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000003UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00000707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} End of group EFR32MG12P_CMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cryotimer.h new file mode 100644 index 00000000000..0688cd00eea --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cryotimer.h @@ -0,0 +1,167 @@ +/**************************************************************************//** + * @file efr32mg12p_cryotimer.h + * @brief EFR32MG12P_CRYOTIMER register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_CRYOTIMER + * @{ + * @brief EFR32MG12P_CRYOTIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t PERIODSEL; /**< Interrupt Duration */ + __IM uint32_t CNT; /**< Counter Value */ + __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} CRYOTIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_CRYOTIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CRYOTIMER CTRL */ +#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_MASK 0x000000EFUL /**< Mask for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */ +#define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */ +#define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */ +#define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */ +#define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */ +#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */ +#define _CRYOTIMER_CTRL_OSCSEL_MASK 0xCUL /**< Bit mask for CRYOTIMER_OSCSEL */ +#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000002UL /**< Mode LFXO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_DISABLED (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2) /**< Shifted mode DISABLED for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */ +#define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */ +#define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */ + +/* Bit fields for CRYOTIMER PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */ +#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */ + +/* Bit fields for CRYOTIMER CNT */ +#define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */ +#define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */ + +/* Bit fields for CRYOTIMER EM4WUEN */ +#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */ +#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */ +#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */ +#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */ +#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */ +#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */ +#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */ + +/* Bit fields for CRYOTIMER IF */ +#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */ +#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */ +#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup event/Interrupt */ +#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */ +#define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */ + +/* Bit fields for CRYOTIMER IFS */ +#define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */ +#define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */ +#define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */ +#define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */ +#define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */ + +/* Bit fields for CRYOTIMER IFC */ +#define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */ +#define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */ +#define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */ +#define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */ +#define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */ + +/* Bit fields for CRYOTIMER IEN */ +#define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */ +#define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */ +#define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */ +#define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */ +#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */ + +/** @} End of group EFR32MG12P_CRYOTIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_crypto.h new file mode 100644 index 00000000000..3fd64d66e2a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_crypto.h @@ -0,0 +1,1216 @@ +/**************************************************************************//** + * @file efr32mg12p_crypto.h + * @brief EFR32MG12P_CRYPTO register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_CRYPTO + * @{ + * @brief EFR32MG12P_CRYPTO Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t WAC; /**< Wide Arithmetic Configuration */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t DSTATUS; /**< Data Status Register */ + __IM uint32_t CSTATUS; /**< Control Status Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t KEY; /**< KEY Register Access */ + __IOM uint32_t KEYBUF; /**< KEY Buffer Register Access */ + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IOM uint32_t SEQCTRL; /**< Sequence Control */ + __IOM uint32_t SEQCTRLB; /**< Sequence Control B */ + uint32_t RESERVED3[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< AES Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t SEQ0; /**< Sequence register 0 */ + __IOM uint32_t SEQ1; /**< Sequence Register 1 */ + __IOM uint32_t SEQ2; /**< Sequence Register 2 */ + __IOM uint32_t SEQ3; /**< Sequence Register 3 */ + __IOM uint32_t SEQ4; /**< Sequence Register 4 */ + uint32_t RESERVED4[7]; /**< Reserved for future use **/ + __IOM uint32_t DATA0; /**< DATA0 Register Access */ + __IOM uint32_t DATA1; /**< DATA1 Register Access */ + __IOM uint32_t DATA2; /**< DATA2 Register Access */ + __IOM uint32_t DATA3; /**< DATA3 Register Access */ + uint32_t RESERVED5[4]; /**< Reserved for future use **/ + __IOM uint32_t DATA0XOR; /**< DATA0XOR Register Access */ + uint32_t RESERVED6[3]; /**< Reserved for future use **/ + __IOM uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */ + __IOM uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IOM uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */ + __IOM uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */ + __IOM uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */ + __IOM uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */ + __IOM uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */ + uint32_t RESERVED8[12]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0; /**< DDATA0 Register Access */ + __IOM uint32_t DDATA1; /**< DDATA1 Register Access */ + __IOM uint32_t DDATA2; /**< DDATA2 Register Access */ + __IOM uint32_t DDATA3; /**< DDATA3 Register Access */ + __IOM uint32_t DDATA4; /**< DDATA4 Register Access */ + uint32_t RESERVED9[7]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */ + uint32_t RESERVED10[3]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */ + __IOM uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */ + __IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 access. */ + uint32_t RESERVED11[13]; /**< Reserved for future use **/ + __IOM uint32_t QDATA0; /**< QDATA0 Register Access */ + __IOM uint32_t QDATA1; /**< QDATA1 Register Access */ + uint32_t RESERVED12[7]; /**< Reserved for future use **/ + __IOM uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */ + uint32_t RESERVED13[6]; /**< Reserved for future use **/ + __IOM uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */ + __IOM uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */ +} CRYPTO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_CRYPTO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CRYPTO CTRL */ +#define _CRYPTO_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_MASK 0xB333C407UL /**< Mask for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES (0x1UL << 0) /**< AES Mode */ +#define _CRYPTO_CTRL_AES_SHIFT 0 /**< Shift value for CRYPTO_AES */ +#define _CRYPTO_CTRL_AES_MASK 0x1UL /**< Bit mask for CRYPTO_AES */ +#define _CRYPTO_CTRL_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_AES_AES128 0x00000000UL /**< Mode AES128 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_AES_AES256 0x00000001UL /**< Mode AES256 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_DEFAULT (_CRYPTO_CTRL_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_AES128 (_CRYPTO_CTRL_AES_AES128 << 0) /**< Shifted mode AES128 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_AES256 (_CRYPTO_CTRL_AES_AES256 << 0) /**< Shifted mode AES256 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_KEYBUFDIS (0x1UL << 1) /**< Key Buffer Disable */ +#define _CRYPTO_CTRL_KEYBUFDIS_SHIFT 1 /**< Shift value for CRYPTO_KEYBUFDIS */ +#define _CRYPTO_CTRL_KEYBUFDIS_MASK 0x2UL /**< Bit mask for CRYPTO_KEYBUFDIS */ +#define _CRYPTO_CTRL_KEYBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_KEYBUFDIS_DEFAULT (_CRYPTO_CTRL_KEYBUFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA (0x1UL << 2) /**< SHA Mode */ +#define _CRYPTO_CTRL_SHA_SHIFT 2 /**< Shift value for CRYPTO_SHA */ +#define _CRYPTO_CTRL_SHA_MASK 0x4UL /**< Bit mask for CRYPTO_SHA */ +#define _CRYPTO_CTRL_SHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_SHA_SHA1 0x00000000UL /**< Mode SHA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_SHA_SHA2 0x00000001UL /**< Mode SHA2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_DEFAULT (_CRYPTO_CTRL_SHA_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_SHA1 (_CRYPTO_CTRL_SHA_SHA1 << 2) /**< Shifted mode SHA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_SHA2 (_CRYPTO_CTRL_SHA_SHA2 << 2) /**< Shifted mode SHA2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_NOBUSYSTALL (0x1UL << 10) /**< No Stalling of Bus When Busy */ +#define _CRYPTO_CTRL_NOBUSYSTALL_SHIFT 10 /**< Shift value for CRYPTO_NOBUSYSTALL */ +#define _CRYPTO_CTRL_NOBUSYSTALL_MASK 0x400UL /**< Bit mask for CRYPTO_NOBUSYSTALL */ +#define _CRYPTO_CTRL_NOBUSYSTALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_NOBUSYSTALL_DEFAULT (_CRYPTO_CTRL_NOBUSYSTALL_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_SHIFT 14 /**< Shift value for CRYPTO_INCWIDTH */ +#define _CRYPTO_CTRL_INCWIDTH_MASK 0xC000UL /**< Bit mask for CRYPTO_INCWIDTH */ +#define _CRYPTO_CTRL_INCWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH1 0x00000000UL /**< Mode INCWIDTH1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH2 0x00000001UL /**< Mode INCWIDTH2 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH3 0x00000002UL /**< Mode INCWIDTH3 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH4 0x00000003UL /**< Mode INCWIDTH4 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_DEFAULT (_CRYPTO_CTRL_INCWIDTH_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH1 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH1 << 14) /**< Shifted mode INCWIDTH1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH2 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH2 << 14) /**< Shifted mode INCWIDTH2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH3 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH3 << 14) /**< Shifted mode INCWIDTH3 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH4 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH4 << 14) /**< Shifted mode INCWIDTH4 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_SHIFT 16 /**< Shift value for CRYPTO_DMA0MODE */ +#define _CRYPTO_CTRL_DMA0MODE_MASK 0x30000UL /**< Bit mask for CRYPTO_DMA0MODE */ +#define _CRYPTO_CTRL_DMA0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_DEFAULT (_CRYPTO_CTRL_DMA0MODE_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_FULL (_CRYPTO_CTRL_DMA0MODE_FULL << 16) /**< Shifted mode FULL for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_LENLIMIT (_CRYPTO_CTRL_DMA0MODE_LENLIMIT << 16) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_FULLBYTE (_CRYPTO_CTRL_DMA0MODE_FULLBYTE << 16) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE << 16) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_SHIFT 20 /**< Shift value for CRYPTO_DMA0RSEL */ +#define _CRYPTO_CTRL_DMA0RSEL_MASK 0x300000UL /**< Bit mask for CRYPTO_DMA0RSEL */ +#define _CRYPTO_CTRL_DMA0RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DATA0 0x00000000UL /**< Mode DATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DDATA0 0x00000001UL /**< Mode DDATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DDATA0BIG 0x00000002UL /**< Mode DDATA0BIG for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_QDATA0 0x00000003UL /**< Mode QDATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DEFAULT (_CRYPTO_CTRL_DMA0RSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DATA0 (_CRYPTO_CTRL_DMA0RSEL_DATA0 << 20) /**< Shifted mode DATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DDATA0 (_CRYPTO_CTRL_DMA0RSEL_DDATA0 << 20) /**< Shifted mode DDATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DDATA0BIG (_CRYPTO_CTRL_DMA0RSEL_DDATA0BIG << 20) /**< Shifted mode DDATA0BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_QDATA0 (_CRYPTO_CTRL_DMA0RSEL_QDATA0 << 20) /**< Shifted mode QDATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_SHIFT 24 /**< Shift value for CRYPTO_DMA1MODE */ +#define _CRYPTO_CTRL_DMA1MODE_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA1MODE */ +#define _CRYPTO_CTRL_DMA1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_DEFAULT (_CRYPTO_CTRL_DMA1MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_FULL (_CRYPTO_CTRL_DMA1MODE_FULL << 24) /**< Shifted mode FULL for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_LENLIMIT (_CRYPTO_CTRL_DMA1MODE_LENLIMIT << 24) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_FULLBYTE (_CRYPTO_CTRL_DMA1MODE_FULLBYTE << 24) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE << 24) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_SHIFT 28 /**< Shift value for CRYPTO_DMA1RSEL */ +#define _CRYPTO_CTRL_DMA1RSEL_MASK 0x30000000UL /**< Bit mask for CRYPTO_DMA1RSEL */ +#define _CRYPTO_CTRL_DMA1RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_DATA1 0x00000000UL /**< Mode DATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_QDATA1 0x00000002UL /**< Mode QDATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_QDATA1BIG 0x00000003UL /**< Mode QDATA1BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DEFAULT (_CRYPTO_CTRL_DMA1RSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DATA1 (_CRYPTO_CTRL_DMA1RSEL_DATA1 << 28) /**< Shifted mode DATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DDATA1 (_CRYPTO_CTRL_DMA1RSEL_DDATA1 << 28) /**< Shifted mode DDATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_QDATA1 (_CRYPTO_CTRL_DMA1RSEL_QDATA1 << 28) /**< Shifted mode QDATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_QDATA1BIG (_CRYPTO_CTRL_DMA1RSEL_QDATA1BIG << 28) /**< Shifted mode QDATA1BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_COMBDMA0WEREQ (0x1UL << 31) /**< Combined Data0 Write DMA Request */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_SHIFT 31 /**< Shift value for CRYPTO_COMBDMA0WEREQ */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_MASK 0x80000000UL /**< Bit mask for CRYPTO_COMBDMA0WEREQ */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT (_CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ + +/* Bit fields for CRYPTO WAC */ +#define _CRYPTO_WAC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_WAC */ +#define _CRYPTO_WAC_MASK 0x00000F1FUL /**< Mask for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_SHIFT 0 /**< Shift value for CRYPTO_MODULUS */ +#define _CRYPTO_WAC_MODULUS_MASK 0xFUL /**< Bit mask for CRYPTO_MODULUS */ +#define _CRYPTO_WAC_MODULUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_BIN256 0x00000000UL /**< Mode BIN256 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_BIN128 0x00000001UL /**< Mode BIN128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233P 0x00000002UL /**< Mode ECCBIN233P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163P 0x00000003UL /**< Mode ECCBIN163P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_GCMBIN128 0x00000004UL /**< Mode GCMBIN128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME256P 0x00000005UL /**< Mode ECCPRIME256P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME224P 0x00000006UL /**< Mode ECCPRIME224P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME192P 0x00000007UL /**< Mode ECCPRIME192P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233N 0x00000008UL /**< Mode ECCBIN233N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233KN 0x00000009UL /**< Mode ECCBIN233KN for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163N 0x0000000AUL /**< Mode ECCBIN163N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163KN 0x0000000BUL /**< Mode ECCBIN163KN for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME256N 0x0000000CUL /**< Mode ECCPRIME256N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME224N 0x0000000DUL /**< Mode ECCPRIME224N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME192N 0x0000000EUL /**< Mode ECCPRIME192N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_DEFAULT (_CRYPTO_WAC_MODULUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_BIN256 (_CRYPTO_WAC_MODULUS_BIN256 << 0) /**< Shifted mode BIN256 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_BIN128 (_CRYPTO_WAC_MODULUS_BIN128 << 0) /**< Shifted mode BIN128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233P (_CRYPTO_WAC_MODULUS_ECCBIN233P << 0) /**< Shifted mode ECCBIN233P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163P (_CRYPTO_WAC_MODULUS_ECCBIN163P << 0) /**< Shifted mode ECCBIN163P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_GCMBIN128 (_CRYPTO_WAC_MODULUS_GCMBIN128 << 0) /**< Shifted mode GCMBIN128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME256P (_CRYPTO_WAC_MODULUS_ECCPRIME256P << 0) /**< Shifted mode ECCPRIME256P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME224P (_CRYPTO_WAC_MODULUS_ECCPRIME224P << 0) /**< Shifted mode ECCPRIME224P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME192P (_CRYPTO_WAC_MODULUS_ECCPRIME192P << 0) /**< Shifted mode ECCPRIME192P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233N (_CRYPTO_WAC_MODULUS_ECCBIN233N << 0) /**< Shifted mode ECCBIN233N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233KN (_CRYPTO_WAC_MODULUS_ECCBIN233KN << 0) /**< Shifted mode ECCBIN233KN for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163N (_CRYPTO_WAC_MODULUS_ECCBIN163N << 0) /**< Shifted mode ECCBIN163N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163KN (_CRYPTO_WAC_MODULUS_ECCBIN163KN << 0) /**< Shifted mode ECCBIN163KN for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME256N (_CRYPTO_WAC_MODULUS_ECCPRIME256N << 0) /**< Shifted mode ECCPRIME256N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME224N (_CRYPTO_WAC_MODULUS_ECCPRIME224N << 0) /**< Shifted mode ECCPRIME224N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME192N (_CRYPTO_WAC_MODULUS_ECCPRIME192N << 0) /**< Shifted mode ECCPRIME192N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP (0x1UL << 4) /**< Modular Operation Field Type */ +#define _CRYPTO_WAC_MODOP_SHIFT 4 /**< Shift value for CRYPTO_MODOP */ +#define _CRYPTO_WAC_MODOP_MASK 0x10UL /**< Bit mask for CRYPTO_MODOP */ +#define _CRYPTO_WAC_MODOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODOP_BINARY 0x00000000UL /**< Mode BINARY for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODOP_REGULAR 0x00000001UL /**< Mode REGULAR for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_DEFAULT (_CRYPTO_WAC_MODOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_BINARY (_CRYPTO_WAC_MODOP_BINARY << 4) /**< Shifted mode BINARY for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_REGULAR (_CRYPTO_WAC_MODOP_REGULAR << 4) /**< Shifted mode REGULAR for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_SHIFT 8 /**< Shift value for CRYPTO_MULWIDTH */ +#define _CRYPTO_WAC_MULWIDTH_MASK 0x300UL /**< Bit mask for CRYPTO_MULWIDTH */ +#define _CRYPTO_WAC_MULWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MUL256 0x00000000UL /**< Mode MUL256 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MUL128 0x00000001UL /**< Mode MUL128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MULMOD 0x00000002UL /**< Mode MULMOD for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_DEFAULT (_CRYPTO_WAC_MULWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MUL256 (_CRYPTO_WAC_MULWIDTH_MUL256 << 8) /**< Shifted mode MUL256 for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MUL128 (_CRYPTO_WAC_MULWIDTH_MUL128 << 8) /**< Shifted mode MUL128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MULMOD (_CRYPTO_WAC_MULWIDTH_MULMOD << 8) /**< Shifted mode MULMOD for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_SHIFT 10 /**< Shift value for CRYPTO_RESULTWIDTH */ +#define _CRYPTO_WAC_RESULTWIDTH_MASK 0xC00UL /**< Bit mask for CRYPTO_RESULTWIDTH */ +#define _CRYPTO_WAC_RESULTWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_256BIT 0x00000000UL /**< Mode 256BIT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_128BIT 0x00000001UL /**< Mode 128BIT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_260BIT 0x00000002UL /**< Mode 260BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_DEFAULT (_CRYPTO_WAC_RESULTWIDTH_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_256BIT (_CRYPTO_WAC_RESULTWIDTH_256BIT << 10) /**< Shifted mode 256BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_128BIT (_CRYPTO_WAC_RESULTWIDTH_128BIT << 10) /**< Shifted mode 128BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_260BIT (_CRYPTO_WAC_RESULTWIDTH_260BIT << 10) /**< Shifted mode 260BIT for CRYPTO_WAC */ + +/* Bit fields for CRYPTO CMD */ +#define _CRYPTO_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CMD */ +#define _CRYPTO_CMD_MASK 0x00000EFFUL /**< Mask for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHIFT 0 /**< Shift value for CRYPTO_INSTR */ +#define _CRYPTO_CMD_INSTR_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR */ +#define _CRYPTO_CMD_INSTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_END 0x00000000UL /**< Mode END for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXEC 0x00000001UL /**< Mode EXEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1INC 0x00000003UL /**< Mode DATA1INC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1INCCLR 0x00000004UL /**< Mode DATA1INCCLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_AESENC 0x00000005UL /**< Mode AESENC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_AESDEC 0x00000006UL /**< Mode AESDEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHA 0x00000007UL /**< Mode SHA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADD 0x00000008UL /**< Mode ADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDC 0x00000009UL /**< Mode ADDC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADD 0x0000000AUL /**< Mode LADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDC 0x0000000BUL /**< Mode LADDC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MADD 0x0000000CUL /**< Mode MADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MADD32 0x0000000DUL /**< Mode MADD32 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SUB 0x00000010UL /**< Mode SUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SUBC 0x00000011UL /**< Mode SUBC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LSUB 0x00000012UL /**< Mode LSUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LSUBC 0x00000013UL /**< Mode LSUBC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MSUB 0x00000014UL /**< Mode MSUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MUL 0x00000018UL /**< Mode MUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MULC 0x00000019UL /**< Mode MULC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LMUL 0x0000001AUL /**< Mode LMUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MMUL 0x0000001CUL /**< Mode MMUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MULO 0x0000001DUL /**< Mode MULO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LMULO 0x0000001FUL /**< Mode LMULO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHL 0x00000020UL /**< Mode SHL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHLC 0x00000021UL /**< Mode SHLC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHLB 0x00000022UL /**< Mode SHLB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHL1 0x00000023UL /**< Mode SHL1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHR 0x00000024UL /**< Mode SHR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRC 0x00000025UL /**< Mode SHRC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRB 0x00000026UL /**< Mode SHRB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHR1 0x00000027UL /**< Mode SHR1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDO 0x00000028UL /**< Mode ADDO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDIC 0x00000029UL /**< Mode ADDIC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDO 0x0000002AUL /**< Mode LADDO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDIC 0x0000002BUL /**< Mode LADDIC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CLR 0x00000030UL /**< Mode CLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_XOR 0x00000031UL /**< Mode XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_INV 0x00000032UL /**< Mode INV for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CSET 0x00000034UL /**< Mode CSET for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CCLR 0x00000035UL /**< Mode CCLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BBSWAP128 0x00000036UL /**< Mode BBSWAP128 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_INC 0x00000038UL /**< Mode INC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DEC 0x00000039UL /**< Mode DEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LINC 0x0000003AUL /**< Mode LINC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LDEC 0x0000003BUL /**< Mode LDEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRA 0x0000003EUL /**< Mode SHRA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0 0x00000040UL /**< Mode DATA0TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0XOR 0x00000041UL /**< Mode DATA0TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN 0x00000042UL /**< Mode DATA0TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA1 0x00000044UL /**< Mode DATA0TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA2 0x00000045UL /**< Mode DATA0TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA3 0x00000046UL /**< Mode DATA0TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0 0x00000048UL /**< Mode DATA1TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0XOR 0x00000049UL /**< Mode DATA1TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN 0x0000004AUL /**< Mode DATA1TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA2 0x0000004DUL /**< Mode DATA1TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA3 0x0000004EUL /**< Mode DATA1TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0 0x00000050UL /**< Mode DATA2TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0XOR 0x00000051UL /**< Mode DATA2TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN 0x00000052UL /**< Mode DATA2TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA1 0x00000054UL /**< Mode DATA2TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA3 0x00000056UL /**< Mode DATA2TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0 0x00000058UL /**< Mode DATA3TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0XOR 0x00000059UL /**< Mode DATA3TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN 0x0000005AUL /**< Mode DATA3TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA1 0x0000005CUL /**< Mode DATA3TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA2 0x0000005DUL /**< Mode DATA3TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATATODMA0 0x00000063UL /**< Mode DATATODMA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TOBUF 0x00000064UL /**< Mode DATA0TOBUF for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TOBUFXOR 0x00000065UL /**< Mode DATA0TOBUFXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATATODMA1 0x0000006BUL /**< Mode DATATODMA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TOBUF 0x0000006CUL /**< Mode DATA1TOBUF for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TOBUFXOR 0x0000006DUL /**< Mode DATA1TOBUFXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA0TODATA 0x00000070UL /**< Mode DMA0TODATA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA0TODATAXOR 0x00000071UL /**< Mode DMA0TODATAXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA1TODATA 0x00000072UL /**< Mode DMA1TODATA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA0 0x00000078UL /**< Mode BUFTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA0XOR 0x00000079UL /**< Mode BUFTODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA1 0x0000007AUL /**< Mode BUFTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA1 0x00000081UL /**< Mode DDATA0TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA2 0x00000082UL /**< Mode DDATA0TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA3 0x00000083UL /**< Mode DDATA0TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA4 0x00000084UL /**< Mode DDATA0TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0LTODATA0 0x00000085UL /**< Mode DDATA0LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0HTODATA1 0x00000086UL /**< Mode DDATA0HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0LTODATA2 0x00000087UL /**< Mode DDATA0LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA0 0x00000088UL /**< Mode DDATA1TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA2 0x0000008AUL /**< Mode DDATA1TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA3 0x0000008BUL /**< Mode DDATA1TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA4 0x0000008CUL /**< Mode DDATA1TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1LTODATA0 0x0000008DUL /**< Mode DDATA1LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1HTODATA1 0x0000008EUL /**< Mode DDATA1HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1LTODATA2 0x0000008FUL /**< Mode DDATA1LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA0 0x00000090UL /**< Mode DDATA2TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA1 0x00000091UL /**< Mode DDATA2TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA3 0x00000093UL /**< Mode DDATA2TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA4 0x00000094UL /**< Mode DDATA2TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2LTODATA2 0x00000097UL /**< Mode DDATA2LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA0 0x00000098UL /**< Mode DDATA3TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA1 0x00000099UL /**< Mode DDATA3TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA2 0x0000009AUL /**< Mode DDATA3TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA4 0x0000009CUL /**< Mode DDATA3TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3LTODATA0 0x0000009DUL /**< Mode DDATA3LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3HTODATA1 0x0000009EUL /**< Mode DDATA3HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA0 0x000000A0UL /**< Mode DDATA4TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA1 0x000000A1UL /**< Mode DDATA4TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA2 0x000000A2UL /**< Mode DDATA4TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA3 0x000000A3UL /**< Mode DDATA4TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4LTODATA0 0x000000A5UL /**< Mode DDATA4LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4HTODATA1 0x000000A6UL /**< Mode DDATA4HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4LTODATA2 0x000000A7UL /**< Mode DDATA4LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODDATA0 0x000000A8UL /**< Mode DATA0TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODDATA1 0x000000A9UL /**< Mode DATA0TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODDATA0 0x000000B0UL /**< Mode DATA1TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODDATA1 0x000000B1UL /**< Mode DATA1TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA0 0x000000B8UL /**< Mode DATA2TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA1 0x000000B9UL /**< Mode DATA2TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA2 0x000000BAUL /**< Mode DATA2TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA0 0x000000C0UL /**< Mode SELDDATA0DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA0 0x000000C1UL /**< Mode SELDDATA1DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA0 0x000000C2UL /**< Mode SELDDATA2DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA0 0x000000C3UL /**< Mode SELDDATA3DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA0 0x000000C4UL /**< Mode SELDDATA4DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA0 0x000000C5UL /**< Mode SELDATA0DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA0 0x000000C6UL /**< Mode SELDATA1DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA0 0x000000C7UL /**< Mode SELDATA2DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA1 0x000000C8UL /**< Mode SELDDATA0DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA1 0x000000C9UL /**< Mode SELDDATA1DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA1 0x000000CAUL /**< Mode SELDDATA2DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA1 0x000000CBUL /**< Mode SELDDATA3DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA1 0x000000CCUL /**< Mode SELDDATA4DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA1 0x000000CDUL /**< Mode SELDATA0DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA1 0x000000CEUL /**< Mode SELDATA1DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA1 0x000000CFUL /**< Mode SELDATA2DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA2 0x000000D0UL /**< Mode SELDDATA0DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA2 0x000000D1UL /**< Mode SELDDATA1DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA2 0x000000D2UL /**< Mode SELDDATA2DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA2 0x000000D3UL /**< Mode SELDDATA3DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA2 0x000000D4UL /**< Mode SELDDATA4DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA2 0x000000D5UL /**< Mode SELDATA0DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA2 0x000000D6UL /**< Mode SELDATA1DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA2 0x000000D7UL /**< Mode SELDATA2DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA3 0x000000D8UL /**< Mode SELDDATA0DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA3 0x000000D9UL /**< Mode SELDDATA1DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA3 0x000000DAUL /**< Mode SELDDATA2DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA3 0x000000DBUL /**< Mode SELDDATA3DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA3 0x000000DCUL /**< Mode SELDDATA4DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA3 0x000000DDUL /**< Mode SELDATA0DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA3 0x000000DEUL /**< Mode SELDATA1DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA3 0x000000DFUL /**< Mode SELDATA2DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA4 0x000000E0UL /**< Mode SELDDATA0DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA4 0x000000E1UL /**< Mode SELDDATA1DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA4 0x000000E2UL /**< Mode SELDDATA2DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA4 0x000000E3UL /**< Mode SELDDATA3DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA4 0x000000E4UL /**< Mode SELDDATA4DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA4 0x000000E5UL /**< Mode SELDATA0DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA4 0x000000E6UL /**< Mode SELDATA1DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA4 0x000000E7UL /**< Mode SELDATA2DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DATA0 0x000000E8UL /**< Mode SELDDATA0DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DATA0 0x000000E9UL /**< Mode SELDDATA1DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DATA0 0x000000EAUL /**< Mode SELDDATA2DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DATA0 0x000000EBUL /**< Mode SELDDATA3DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DATA0 0x000000ECUL /**< Mode SELDDATA4DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DATA0 0x000000EDUL /**< Mode SELDATA0DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DATA0 0x000000EEUL /**< Mode SELDATA1DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DATA0 0x000000EFUL /**< Mode SELDATA2DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DATA1 0x000000F0UL /**< Mode SELDDATA0DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DATA1 0x000000F1UL /**< Mode SELDDATA1DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DATA1 0x000000F2UL /**< Mode SELDDATA2DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DATA1 0x000000F3UL /**< Mode SELDDATA3DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DATA1 0x000000F4UL /**< Mode SELDDATA4DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DATA1 0x000000F5UL /**< Mode SELDATA0DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DATA1 0x000000F6UL /**< Mode SELDATA1DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DATA1 0x000000F7UL /**< Mode SELDATA2DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFA 0x000000F8UL /**< Mode EXECIFA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFB 0x000000F9UL /**< Mode EXECIFB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFNLAST 0x000000FAUL /**< Mode EXECIFNLAST for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFLAST 0x000000FBUL /**< Mode EXECIFLAST for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFCARRY 0x000000FCUL /**< Mode EXECIFCARRY for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFNCARRY 0x000000FDUL /**< Mode EXECIFNCARRY for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECALWAYS 0x000000FEUL /**< Mode EXECALWAYS for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DEFAULT (_CRYPTO_CMD_INSTR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_END (_CRYPTO_CMD_INSTR_END << 0) /**< Shifted mode END for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXEC (_CRYPTO_CMD_INSTR_EXEC << 0) /**< Shifted mode EXEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1INC (_CRYPTO_CMD_INSTR_DATA1INC << 0) /**< Shifted mode DATA1INC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1INCCLR (_CRYPTO_CMD_INSTR_DATA1INCCLR << 0) /**< Shifted mode DATA1INCCLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_AESENC (_CRYPTO_CMD_INSTR_AESENC << 0) /**< Shifted mode AESENC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_AESDEC (_CRYPTO_CMD_INSTR_AESDEC << 0) /**< Shifted mode AESDEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHA (_CRYPTO_CMD_INSTR_SHA << 0) /**< Shifted mode SHA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADD (_CRYPTO_CMD_INSTR_ADD << 0) /**< Shifted mode ADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDC (_CRYPTO_CMD_INSTR_ADDC << 0) /**< Shifted mode ADDC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADD (_CRYPTO_CMD_INSTR_LADD << 0) /**< Shifted mode LADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDC (_CRYPTO_CMD_INSTR_LADDC << 0) /**< Shifted mode LADDC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MADD (_CRYPTO_CMD_INSTR_MADD << 0) /**< Shifted mode MADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MADD32 (_CRYPTO_CMD_INSTR_MADD32 << 0) /**< Shifted mode MADD32 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SUB (_CRYPTO_CMD_INSTR_SUB << 0) /**< Shifted mode SUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SUBC (_CRYPTO_CMD_INSTR_SUBC << 0) /**< Shifted mode SUBC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LSUB (_CRYPTO_CMD_INSTR_LSUB << 0) /**< Shifted mode LSUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LSUBC (_CRYPTO_CMD_INSTR_LSUBC << 0) /**< Shifted mode LSUBC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MSUB (_CRYPTO_CMD_INSTR_MSUB << 0) /**< Shifted mode MSUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MUL (_CRYPTO_CMD_INSTR_MUL << 0) /**< Shifted mode MUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MULC (_CRYPTO_CMD_INSTR_MULC << 0) /**< Shifted mode MULC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LMUL (_CRYPTO_CMD_INSTR_LMUL << 0) /**< Shifted mode LMUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MMUL (_CRYPTO_CMD_INSTR_MMUL << 0) /**< Shifted mode MMUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MULO (_CRYPTO_CMD_INSTR_MULO << 0) /**< Shifted mode MULO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LMULO (_CRYPTO_CMD_INSTR_LMULO << 0) /**< Shifted mode LMULO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHL (_CRYPTO_CMD_INSTR_SHL << 0) /**< Shifted mode SHL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHLC (_CRYPTO_CMD_INSTR_SHLC << 0) /**< Shifted mode SHLC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHLB (_CRYPTO_CMD_INSTR_SHLB << 0) /**< Shifted mode SHLB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHL1 (_CRYPTO_CMD_INSTR_SHL1 << 0) /**< Shifted mode SHL1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHR (_CRYPTO_CMD_INSTR_SHR << 0) /**< Shifted mode SHR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRC (_CRYPTO_CMD_INSTR_SHRC << 0) /**< Shifted mode SHRC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRB (_CRYPTO_CMD_INSTR_SHRB << 0) /**< Shifted mode SHRB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHR1 (_CRYPTO_CMD_INSTR_SHR1 << 0) /**< Shifted mode SHR1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDO (_CRYPTO_CMD_INSTR_ADDO << 0) /**< Shifted mode ADDO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDIC (_CRYPTO_CMD_INSTR_ADDIC << 0) /**< Shifted mode ADDIC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDO (_CRYPTO_CMD_INSTR_LADDO << 0) /**< Shifted mode LADDO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDIC (_CRYPTO_CMD_INSTR_LADDIC << 0) /**< Shifted mode LADDIC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CLR (_CRYPTO_CMD_INSTR_CLR << 0) /**< Shifted mode CLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_XOR (_CRYPTO_CMD_INSTR_XOR << 0) /**< Shifted mode XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_INV (_CRYPTO_CMD_INSTR_INV << 0) /**< Shifted mode INV for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CSET (_CRYPTO_CMD_INSTR_CSET << 0) /**< Shifted mode CSET for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CCLR (_CRYPTO_CMD_INSTR_CCLR << 0) /**< Shifted mode CCLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BBSWAP128 (_CRYPTO_CMD_INSTR_BBSWAP128 << 0) /**< Shifted mode BBSWAP128 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_INC (_CRYPTO_CMD_INSTR_INC << 0) /**< Shifted mode INC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DEC (_CRYPTO_CMD_INSTR_DEC << 0) /**< Shifted mode DEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LINC (_CRYPTO_CMD_INSTR_LINC << 0) /**< Shifted mode LINC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LDEC (_CRYPTO_CMD_INSTR_LDEC << 0) /**< Shifted mode LDEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRA (_CRYPTO_CMD_INSTR_SHRA << 0) /**< Shifted mode SHRA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0 (_CRYPTO_CMD_INSTR_DATA0TODATA0 << 0) /**< Shifted mode DATA0TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0XOR (_CRYPTO_CMD_INSTR_DATA0TODATA0XOR << 0) /**< Shifted mode DATA0TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN << 0) /**< Shifted mode DATA0TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA1 (_CRYPTO_CMD_INSTR_DATA0TODATA1 << 0) /**< Shifted mode DATA0TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA2 (_CRYPTO_CMD_INSTR_DATA0TODATA2 << 0) /**< Shifted mode DATA0TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA3 (_CRYPTO_CMD_INSTR_DATA0TODATA3 << 0) /**< Shifted mode DATA0TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0 (_CRYPTO_CMD_INSTR_DATA1TODATA0 << 0) /**< Shifted mode DATA1TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0XOR (_CRYPTO_CMD_INSTR_DATA1TODATA0XOR << 0) /**< Shifted mode DATA1TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN << 0) /**< Shifted mode DATA1TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA2 (_CRYPTO_CMD_INSTR_DATA1TODATA2 << 0) /**< Shifted mode DATA1TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA3 (_CRYPTO_CMD_INSTR_DATA1TODATA3 << 0) /**< Shifted mode DATA1TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0 (_CRYPTO_CMD_INSTR_DATA2TODATA0 << 0) /**< Shifted mode DATA2TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0XOR (_CRYPTO_CMD_INSTR_DATA2TODATA0XOR << 0) /**< Shifted mode DATA2TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN << 0) /**< Shifted mode DATA2TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA1 (_CRYPTO_CMD_INSTR_DATA2TODATA1 << 0) /**< Shifted mode DATA2TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA3 (_CRYPTO_CMD_INSTR_DATA2TODATA3 << 0) /**< Shifted mode DATA2TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0 (_CRYPTO_CMD_INSTR_DATA3TODATA0 << 0) /**< Shifted mode DATA3TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0XOR (_CRYPTO_CMD_INSTR_DATA3TODATA0XOR << 0) /**< Shifted mode DATA3TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN << 0) /**< Shifted mode DATA3TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA1 (_CRYPTO_CMD_INSTR_DATA3TODATA1 << 0) /**< Shifted mode DATA3TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA2 (_CRYPTO_CMD_INSTR_DATA3TODATA2 << 0) /**< Shifted mode DATA3TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATATODMA0 (_CRYPTO_CMD_INSTR_DATATODMA0 << 0) /**< Shifted mode DATATODMA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TOBUF (_CRYPTO_CMD_INSTR_DATA0TOBUF << 0) /**< Shifted mode DATA0TOBUF for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TOBUFXOR (_CRYPTO_CMD_INSTR_DATA0TOBUFXOR << 0) /**< Shifted mode DATA0TOBUFXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATATODMA1 (_CRYPTO_CMD_INSTR_DATATODMA1 << 0) /**< Shifted mode DATATODMA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TOBUF (_CRYPTO_CMD_INSTR_DATA1TOBUF << 0) /**< Shifted mode DATA1TOBUF for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TOBUFXOR (_CRYPTO_CMD_INSTR_DATA1TOBUFXOR << 0) /**< Shifted mode DATA1TOBUFXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA0TODATA (_CRYPTO_CMD_INSTR_DMA0TODATA << 0) /**< Shifted mode DMA0TODATA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA0TODATAXOR (_CRYPTO_CMD_INSTR_DMA0TODATAXOR << 0) /**< Shifted mode DMA0TODATAXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA1TODATA (_CRYPTO_CMD_INSTR_DMA1TODATA << 0) /**< Shifted mode DMA1TODATA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA0 (_CRYPTO_CMD_INSTR_BUFTODATA0 << 0) /**< Shifted mode BUFTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA0XOR (_CRYPTO_CMD_INSTR_BUFTODATA0XOR << 0) /**< Shifted mode BUFTODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA1 (_CRYPTO_CMD_INSTR_BUFTODATA1 << 0) /**< Shifted mode BUFTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA1 (_CRYPTO_CMD_INSTR_DDATA0TODDATA1 << 0) /**< Shifted mode DDATA0TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA2 (_CRYPTO_CMD_INSTR_DDATA0TODDATA2 << 0) /**< Shifted mode DDATA0TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA3 (_CRYPTO_CMD_INSTR_DDATA0TODDATA3 << 0) /**< Shifted mode DDATA0TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA4 (_CRYPTO_CMD_INSTR_DDATA0TODDATA4 << 0) /**< Shifted mode DDATA0TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0LTODATA0 (_CRYPTO_CMD_INSTR_DDATA0LTODATA0 << 0) /**< Shifted mode DDATA0LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0HTODATA1 (_CRYPTO_CMD_INSTR_DDATA0HTODATA1 << 0) /**< Shifted mode DDATA0HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0LTODATA2 (_CRYPTO_CMD_INSTR_DDATA0LTODATA2 << 0) /**< Shifted mode DDATA0LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA0 (_CRYPTO_CMD_INSTR_DDATA1TODDATA0 << 0) /**< Shifted mode DDATA1TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA2 (_CRYPTO_CMD_INSTR_DDATA1TODDATA2 << 0) /**< Shifted mode DDATA1TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA3 (_CRYPTO_CMD_INSTR_DDATA1TODDATA3 << 0) /**< Shifted mode DDATA1TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA4 (_CRYPTO_CMD_INSTR_DDATA1TODDATA4 << 0) /**< Shifted mode DDATA1TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1LTODATA0 (_CRYPTO_CMD_INSTR_DDATA1LTODATA0 << 0) /**< Shifted mode DDATA1LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1HTODATA1 (_CRYPTO_CMD_INSTR_DDATA1HTODATA1 << 0) /**< Shifted mode DDATA1HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1LTODATA2 (_CRYPTO_CMD_INSTR_DDATA1LTODATA2 << 0) /**< Shifted mode DDATA1LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA0 (_CRYPTO_CMD_INSTR_DDATA2TODDATA0 << 0) /**< Shifted mode DDATA2TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA1 (_CRYPTO_CMD_INSTR_DDATA2TODDATA1 << 0) /**< Shifted mode DDATA2TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA3 (_CRYPTO_CMD_INSTR_DDATA2TODDATA3 << 0) /**< Shifted mode DDATA2TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA4 (_CRYPTO_CMD_INSTR_DDATA2TODDATA4 << 0) /**< Shifted mode DDATA2TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2LTODATA2 (_CRYPTO_CMD_INSTR_DDATA2LTODATA2 << 0) /**< Shifted mode DDATA2LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA0 (_CRYPTO_CMD_INSTR_DDATA3TODDATA0 << 0) /**< Shifted mode DDATA3TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA1 (_CRYPTO_CMD_INSTR_DDATA3TODDATA1 << 0) /**< Shifted mode DDATA3TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA2 (_CRYPTO_CMD_INSTR_DDATA3TODDATA2 << 0) /**< Shifted mode DDATA3TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA4 (_CRYPTO_CMD_INSTR_DDATA3TODDATA4 << 0) /**< Shifted mode DDATA3TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3LTODATA0 (_CRYPTO_CMD_INSTR_DDATA3LTODATA0 << 0) /**< Shifted mode DDATA3LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3HTODATA1 (_CRYPTO_CMD_INSTR_DDATA3HTODATA1 << 0) /**< Shifted mode DDATA3HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA0 (_CRYPTO_CMD_INSTR_DDATA4TODDATA0 << 0) /**< Shifted mode DDATA4TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA1 (_CRYPTO_CMD_INSTR_DDATA4TODDATA1 << 0) /**< Shifted mode DDATA4TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA2 (_CRYPTO_CMD_INSTR_DDATA4TODDATA2 << 0) /**< Shifted mode DDATA4TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA3 (_CRYPTO_CMD_INSTR_DDATA4TODDATA3 << 0) /**< Shifted mode DDATA4TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4LTODATA0 (_CRYPTO_CMD_INSTR_DDATA4LTODATA0 << 0) /**< Shifted mode DDATA4LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4HTODATA1 (_CRYPTO_CMD_INSTR_DDATA4HTODATA1 << 0) /**< Shifted mode DDATA4HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4LTODATA2 (_CRYPTO_CMD_INSTR_DDATA4LTODATA2 << 0) /**< Shifted mode DDATA4LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODDATA0 (_CRYPTO_CMD_INSTR_DATA0TODDATA0 << 0) /**< Shifted mode DATA0TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODDATA1 (_CRYPTO_CMD_INSTR_DATA0TODDATA1 << 0) /**< Shifted mode DATA0TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODDATA0 (_CRYPTO_CMD_INSTR_DATA1TODDATA0 << 0) /**< Shifted mode DATA1TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODDATA1 (_CRYPTO_CMD_INSTR_DATA1TODDATA1 << 0) /**< Shifted mode DATA1TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA0 (_CRYPTO_CMD_INSTR_DATA2TODDATA0 << 0) /**< Shifted mode DATA2TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA1 (_CRYPTO_CMD_INSTR_DATA2TODDATA1 << 0) /**< Shifted mode DATA2TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA2 (_CRYPTO_CMD_INSTR_DATA2TODDATA2 << 0) /**< Shifted mode DATA2TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA0 << 0) /**< Shifted mode SELDDATA0DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA0 << 0) /**< Shifted mode SELDDATA1DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA0 << 0) /**< Shifted mode SELDDATA2DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA0 << 0) /**< Shifted mode SELDDATA3DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA0 << 0) /**< Shifted mode SELDDATA4DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDATA0DDATA0 << 0) /**< Shifted mode SELDATA0DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDATA1DDATA0 << 0) /**< Shifted mode SELDATA1DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDATA2DDATA0 << 0) /**< Shifted mode SELDATA2DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA1 << 0) /**< Shifted mode SELDDATA0DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA1 << 0) /**< Shifted mode SELDDATA1DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA1 << 0) /**< Shifted mode SELDDATA2DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA1 << 0) /**< Shifted mode SELDDATA3DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA1 << 0) /**< Shifted mode SELDDATA4DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDATA0DDATA1 << 0) /**< Shifted mode SELDATA0DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDATA1DDATA1 << 0) /**< Shifted mode SELDATA1DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDATA2DDATA1 << 0) /**< Shifted mode SELDATA2DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA2 << 0) /**< Shifted mode SELDDATA0DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA2 << 0) /**< Shifted mode SELDDATA1DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA2 << 0) /**< Shifted mode SELDDATA2DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA2 << 0) /**< Shifted mode SELDDATA3DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA2 << 0) /**< Shifted mode SELDDATA4DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDATA0DDATA2 << 0) /**< Shifted mode SELDATA0DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDATA1DDATA2 << 0) /**< Shifted mode SELDATA1DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDATA2DDATA2 << 0) /**< Shifted mode SELDATA2DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA3 << 0) /**< Shifted mode SELDDATA0DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA3 << 0) /**< Shifted mode SELDDATA1DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA3 << 0) /**< Shifted mode SELDDATA2DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA3 << 0) /**< Shifted mode SELDDATA3DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA3 << 0) /**< Shifted mode SELDDATA4DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDATA0DDATA3 << 0) /**< Shifted mode SELDATA0DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDATA1DDATA3 << 0) /**< Shifted mode SELDATA1DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDATA2DDATA3 << 0) /**< Shifted mode SELDATA2DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA4 << 0) /**< Shifted mode SELDDATA0DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA4 << 0) /**< Shifted mode SELDDATA1DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA4 << 0) /**< Shifted mode SELDDATA2DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA4 << 0) /**< Shifted mode SELDDATA3DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA4 << 0) /**< Shifted mode SELDDATA4DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDATA0DDATA4 << 0) /**< Shifted mode SELDATA0DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDATA1DDATA4 << 0) /**< Shifted mode SELDATA1DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDATA2DDATA4 << 0) /**< Shifted mode SELDATA2DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DATA0 << 0) /**< Shifted mode SELDDATA0DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DATA0 << 0) /**< Shifted mode SELDDATA1DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DATA0 << 0) /**< Shifted mode SELDDATA2DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DATA0 << 0) /**< Shifted mode SELDDATA3DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DATA0 << 0) /**< Shifted mode SELDDATA4DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDATA0DATA0 << 0) /**< Shifted mode SELDATA0DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDATA1DATA0 << 0) /**< Shifted mode SELDATA1DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDATA2DATA0 << 0) /**< Shifted mode SELDATA2DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DATA1 << 0) /**< Shifted mode SELDDATA0DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DATA1 << 0) /**< Shifted mode SELDDATA1DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DATA1 << 0) /**< Shifted mode SELDDATA2DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DATA1 << 0) /**< Shifted mode SELDDATA3DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DATA1 << 0) /**< Shifted mode SELDDATA4DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDATA0DATA1 << 0) /**< Shifted mode SELDATA0DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDATA1DATA1 << 0) /**< Shifted mode SELDATA1DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDATA2DATA1 << 0) /**< Shifted mode SELDATA2DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFA (_CRYPTO_CMD_INSTR_EXECIFA << 0) /**< Shifted mode EXECIFA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFB (_CRYPTO_CMD_INSTR_EXECIFB << 0) /**< Shifted mode EXECIFB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFNLAST (_CRYPTO_CMD_INSTR_EXECIFNLAST << 0) /**< Shifted mode EXECIFNLAST for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFLAST (_CRYPTO_CMD_INSTR_EXECIFLAST << 0) /**< Shifted mode EXECIFLAST for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFCARRY (_CRYPTO_CMD_INSTR_EXECIFCARRY << 0) /**< Shifted mode EXECIFCARRY for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFNCARRY (_CRYPTO_CMD_INSTR_EXECIFNCARRY << 0) /**< Shifted mode EXECIFNCARRY for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECALWAYS (_CRYPTO_CMD_INSTR_EXECALWAYS << 0) /**< Shifted mode EXECALWAYS for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTART (0x1UL << 9) /**< Encryption/Decryption SEQUENCE Start */ +#define _CRYPTO_CMD_SEQSTART_SHIFT 9 /**< Shift value for CRYPTO_SEQSTART */ +#define _CRYPTO_CMD_SEQSTART_MASK 0x200UL /**< Bit mask for CRYPTO_SEQSTART */ +#define _CRYPTO_CMD_SEQSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTART_DEFAULT (_CRYPTO_CMD_SEQSTART_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTOP (0x1UL << 10) /**< Sequence Stop */ +#define _CRYPTO_CMD_SEQSTOP_SHIFT 10 /**< Shift value for CRYPTO_SEQSTOP */ +#define _CRYPTO_CMD_SEQSTOP_MASK 0x400UL /**< Bit mask for CRYPTO_SEQSTOP */ +#define _CRYPTO_CMD_SEQSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTOP_DEFAULT (_CRYPTO_CMD_SEQSTOP_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTEP (0x1UL << 11) /**< Sequence Step */ +#define _CRYPTO_CMD_SEQSTEP_SHIFT 11 /**< Shift value for CRYPTO_SEQSTEP */ +#define _CRYPTO_CMD_SEQSTEP_MASK 0x800UL /**< Bit mask for CRYPTO_SEQSTEP */ +#define _CRYPTO_CMD_SEQSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTEP_DEFAULT (_CRYPTO_CMD_SEQSTEP_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTO_CMD */ + +/* Bit fields for CRYPTO STATUS */ +#define _CRYPTO_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_STATUS */ +#define _CRYPTO_STATUS_MASK 0x00000007UL /**< Mask for CRYPTO_STATUS */ +#define CRYPTO_STATUS_SEQRUNNING (0x1UL << 0) /**< AES SEQUENCE Running */ +#define _CRYPTO_STATUS_SEQRUNNING_SHIFT 0 /**< Shift value for CRYPTO_SEQRUNNING */ +#define _CRYPTO_STATUS_SEQRUNNING_MASK 0x1UL /**< Bit mask for CRYPTO_SEQRUNNING */ +#define _CRYPTO_STATUS_SEQRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_SEQRUNNING_DEFAULT (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is active */ +#define _CRYPTO_STATUS_INSTRRUNNING_SHIFT 1 /**< Shift value for CRYPTO_INSTRRUNNING */ +#define _CRYPTO_STATUS_INSTRRUNNING_MASK 0x2UL /**< Bit mask for CRYPTO_INSTRRUNNING */ +#define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_INSTRRUNNING_DEFAULT (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is active */ +#define _CRYPTO_STATUS_DMAACTIVE_SHIFT 2 /**< Shift value for CRYPTO_DMAACTIVE */ +#define _CRYPTO_STATUS_DMAACTIVE_MASK 0x4UL /**< Bit mask for CRYPTO_DMAACTIVE */ +#define _CRYPTO_STATUS_DMAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_DMAACTIVE_DEFAULT (_CRYPTO_STATUS_DMAACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ + +/* Bit fields for CRYPTO DSTATUS */ +#define _CRYPTO_DSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_MASK 0x011F0F0FUL /**< Mask for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_SHIFT 0 /**< Shift value for CRYPTO_DATA0ZERO */ +#define _CRYPTO_DSTATUS_DATA0ZERO_MASK 0xFUL /**< Bit mask for CRYPTO_DATA0ZERO */ +#define _CRYPTO_DSTATUS_DATA0ZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 0x00000001UL /**< Mode ZERO0TO31 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 0x00000002UL /**< Mode ZERO32TO63 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 0x00000004UL /**< Mode ZERO64TO95 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 0x00000008UL /**< Mode ZERO96TO127 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_DEFAULT (_CRYPTO_DSTATUS_DATA0ZERO_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 << 0) /**< Shifted mode ZERO0TO31 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 << 0) /**< Shifted mode ZERO32TO63 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 << 0) /**< Shifted mode ZERO64TO95 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 << 0) /**< Shifted mode ZERO96TO127 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT 8 /**< Shift value for CRYPTO_DDATA0LSBS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_MASK 0xF00UL /**< Bit mask for CRYPTO_DDATA0LSBS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT 16 /**< Shift value for CRYPTO_DDATA0MSBS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_MASK 0xF0000UL /**< Bit mask for CRYPTO_DDATA0MSBS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA1MSB (0x1UL << 20) /**< MSB in DDATA1 */ +#define _CRYPTO_DSTATUS_DDATA1MSB_SHIFT 20 /**< Shift value for CRYPTO_DDATA1MSB */ +#define _CRYPTO_DSTATUS_DDATA1MSB_MASK 0x100000UL /**< Bit mask for CRYPTO_DDATA1MSB */ +#define _CRYPTO_DSTATUS_DDATA1MSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA1MSB_DEFAULT (_CRYPTO_DSTATUS_DDATA1MSB_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_CARRY (0x1UL << 24) /**< Carry From Arithmetic Operation */ +#define _CRYPTO_DSTATUS_CARRY_SHIFT 24 /**< Shift value for CRYPTO_CARRY */ +#define _CRYPTO_DSTATUS_CARRY_MASK 0x1000000UL /**< Bit mask for CRYPTO_CARRY */ +#define _CRYPTO_DSTATUS_CARRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_CARRY_DEFAULT (_CRYPTO_DSTATUS_CARRY_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ + +/* Bit fields for CRYPTO CSTATUS */ +#define _CRYPTO_CSTATUS_RESETVALUE 0x00000201UL /**< Default value for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_MASK 0x01F30707UL /**< Mask for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_SHIFT 0 /**< Shift value for CRYPTO_V0 */ +#define _CRYPTO_CSTATUS_V0_MASK 0x7UL /**< Bit mask for CRYPTO_V0 */ +#define _CRYPTO_CSTATUS_V0_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA0 (_CRYPTO_CSTATUS_V0_DDATA0 << 0) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DEFAULT (_CRYPTO_CSTATUS_V0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA1 (_CRYPTO_CSTATUS_V0_DDATA1 << 0) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA2 (_CRYPTO_CSTATUS_V0_DDATA2 << 0) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA3 (_CRYPTO_CSTATUS_V0_DDATA3 << 0) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA4 (_CRYPTO_CSTATUS_V0_DDATA4 << 0) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA0 (_CRYPTO_CSTATUS_V0_DATA0 << 0) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA1 (_CRYPTO_CSTATUS_V0_DATA1 << 0) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA2 (_CRYPTO_CSTATUS_V0_DATA2 << 0) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_SHIFT 8 /**< Shift value for CRYPTO_V1 */ +#define _CRYPTO_CSTATUS_V1_MASK 0x700UL /**< Bit mask for CRYPTO_V1 */ +#define _CRYPTO_CSTATUS_V1_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DEFAULT 0x00000002UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA0 (_CRYPTO_CSTATUS_V1_DDATA0 << 8) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA1 (_CRYPTO_CSTATUS_V1_DDATA1 << 8) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DEFAULT (_CRYPTO_CSTATUS_V1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA2 (_CRYPTO_CSTATUS_V1_DDATA2 << 8) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA3 (_CRYPTO_CSTATUS_V1_DDATA3 << 8) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA4 (_CRYPTO_CSTATUS_V1_DDATA4 << 8) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA0 (_CRYPTO_CSTATUS_V1_DATA0 << 8) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA1 (_CRYPTO_CSTATUS_V1_DATA1 << 8) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA2 (_CRYPTO_CSTATUS_V1_DATA2 << 8) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART (0x1UL << 16) /**< Sequence Part */ +#define _CRYPTO_CSTATUS_SEQPART_SHIFT 16 /**< Shift value for CRYPTO_SEQPART */ +#define _CRYPTO_CSTATUS_SEQPART_MASK 0x10000UL /**< Bit mask for CRYPTO_SEQPART */ +#define _CRYPTO_CSTATUS_SEQPART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQPART_SEQA 0x00000000UL /**< Mode SEQA for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQPART_SEQB 0x00000001UL /**< Mode SEQB for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_DEFAULT (_CRYPTO_CSTATUS_SEQPART_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_SEQA (_CRYPTO_CSTATUS_SEQPART_SEQA << 16) /**< Shifted mode SEQA for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_SEQB (_CRYPTO_CSTATUS_SEQPART_SEQB << 16) /**< Shifted mode SEQB for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQSKIP (0x1UL << 17) /**< Sequence Skip Next Instruction */ +#define _CRYPTO_CSTATUS_SEQSKIP_SHIFT 17 /**< Shift value for CRYPTO_SEQSKIP */ +#define _CRYPTO_CSTATUS_SEQSKIP_MASK 0x20000UL /**< Bit mask for CRYPTO_SEQSKIP */ +#define _CRYPTO_CSTATUS_SEQSKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQSKIP_DEFAULT (_CRYPTO_CSTATUS_SEQSKIP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQIP_SHIFT 20 /**< Shift value for CRYPTO_SEQIP */ +#define _CRYPTO_CSTATUS_SEQIP_MASK 0x1F00000UL /**< Bit mask for CRYPTO_SEQIP */ +#define _CRYPTO_CSTATUS_SEQIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQIP_DEFAULT (_CRYPTO_CSTATUS_SEQIP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ + +/* Bit fields for CRYPTO KEY */ +#define _CRYPTO_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEY */ +#define _CRYPTO_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEY */ +#define CRYPTO_KEY_KEY_DEFAULT (_CRYPTO_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEY */ + +/* Bit fields for CRYPTO KEYBUF */ +#define _CRYPTO_KEYBUF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_SHIFT 0 /**< Shift value for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEYBUF */ +#define CRYPTO_KEYBUF_KEYBUF_DEFAULT (_CRYPTO_KEYBUF_KEYBUF_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEYBUF */ + +/* Bit fields for CRYPTO SEQCTRL */ +#define _CRYPTO_SEQCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_MASK 0xBF303FFFUL /**< Mask for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_LENGTHA_SHIFT 0 /**< Shift value for CRYPTO_LENGTHA */ +#define _CRYPTO_SEQCTRL_LENGTHA_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHA */ +#define _CRYPTO_SEQCTRL_LENGTHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_LENGTHA_DEFAULT (_CRYPTO_SEQCTRL_LENGTHA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_SHIFT 20 /**< Shift value for CRYPTO_BLOCKSIZE */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_MASK 0x300000UL /**< Bit mask for CRYPTO_BLOCKSIZE */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES 0x00000000UL /**< Mode 16BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES 0x00000001UL /**< Mode 32BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES 0x00000002UL /**< Mode 64BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT (_CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES << 20) /**< Shifted mode 16BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES << 20) /**< Shifted mode 32BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES << 20) /**< Shifted mode 64BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_SHIFT 24 /**< Shift value for CRYPTO_DMA0SKIP */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA0SKIP */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_SHIFT 26 /**< Shift value for CRYPTO_DMA1SKIP */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_MASK 0xC000000UL /**< Bit mask for CRYPTO_DMA1SKIP */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve A */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESA */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESA */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve A */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESA */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESA */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_HALT (0x1UL << 31) /**< Halt Sequence */ +#define _CRYPTO_SEQCTRL_HALT_SHIFT 31 /**< Shift value for CRYPTO_HALT */ +#define _CRYPTO_SEQCTRL_HALT_MASK 0x80000000UL /**< Bit mask for CRYPTO_HALT */ +#define _CRYPTO_SEQCTRL_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_HALT_DEFAULT (_CRYPTO_SEQCTRL_HALT_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ + +/* Bit fields for CRYPTO SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_MASK 0x30003FFFUL /**< Mask for CRYPTO_SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_SHIFT 0 /**< Shift value for CRYPTO_LENGTHB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_LENGTHB_DEFAULT (_CRYPTO_SEQCTRLB_LENGTHB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA0PRESB (0x1UL << 28) /**< DMA0 Preserve B */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESB */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESB */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA1PRESB (0x1UL << 29) /**< DMA1 Preserve B */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESB */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESB */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ + +/* Bit fields for CRYPTO IF */ +#define _CRYPTO_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IF */ +#define _CRYPTO_IF_MASK 0x00000003UL /**< Mask for CRYPTO_IF */ +#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction done */ +#define _CRYPTO_IF_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IF_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IF_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_INSTRDONE_DEFAULT (_CRYPTO_IF_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_SEQDONE (0x1UL << 1) /**< Sequence Done */ +#define _CRYPTO_IF_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IF_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IF_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_SEQDONE_DEFAULT (_CRYPTO_IF_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IF */ + +/* Bit fields for CRYPTO IFS */ +#define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */ +#define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */ +#define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */ +#define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFS_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_INSTRDONE_DEFAULT (_CRYPTO_IFS_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_SEQDONE (0x1UL << 1) /**< Set SEQDONE Interrupt Flag */ +#define _CRYPTO_IFS_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */ + +/* Bit fields for CRYPTO IFC */ +#define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */ +#define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */ +#define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */ +#define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFC_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_INSTRDONE_DEFAULT (_CRYPTO_IFC_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_SEQDONE (0x1UL << 1) /**< Clear SEQDONE Interrupt Flag */ +#define _CRYPTO_IFC_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */ + +/* Bit fields for CRYPTO IEN */ +#define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */ +#define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */ +#define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */ +#define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IEN_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_INSTRDONE_DEFAULT (_CRYPTO_IEN_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_SEQDONE (0x1UL << 1) /**< SEQDONE Interrupt Enable */ +#define _CRYPTO_IEN_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */ + +/* Bit fields for CRYPTO SEQ0 */ +#define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR0_SHIFT 0 /**< Shift value for CRYPTO_INSTR0 */ +#define _CRYPTO_SEQ0_INSTR0_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR0 */ +#define _CRYPTO_SEQ0_INSTR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR0_DEFAULT (_CRYPTO_SEQ0_INSTR0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR1_SHIFT 8 /**< Shift value for CRYPTO_INSTR1 */ +#define _CRYPTO_SEQ0_INSTR1_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR1 */ +#define _CRYPTO_SEQ0_INSTR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR1_DEFAULT (_CRYPTO_SEQ0_INSTR1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR2_SHIFT 16 /**< Shift value for CRYPTO_INSTR2 */ +#define _CRYPTO_SEQ0_INSTR2_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR2 */ +#define _CRYPTO_SEQ0_INSTR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR2_DEFAULT (_CRYPTO_SEQ0_INSTR2_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR3_SHIFT 24 /**< Shift value for CRYPTO_INSTR3 */ +#define _CRYPTO_SEQ0_INSTR3_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR3 */ +#define _CRYPTO_SEQ0_INSTR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR3_DEFAULT (_CRYPTO_SEQ0_INSTR3_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ + +/* Bit fields for CRYPTO SEQ1 */ +#define _CRYPTO_SEQ1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR4_SHIFT 0 /**< Shift value for CRYPTO_INSTR4 */ +#define _CRYPTO_SEQ1_INSTR4_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR4 */ +#define _CRYPTO_SEQ1_INSTR4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR4_DEFAULT (_CRYPTO_SEQ1_INSTR4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR5_SHIFT 8 /**< Shift value for CRYPTO_INSTR5 */ +#define _CRYPTO_SEQ1_INSTR5_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR5 */ +#define _CRYPTO_SEQ1_INSTR5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR5_DEFAULT (_CRYPTO_SEQ1_INSTR5_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR6_SHIFT 16 /**< Shift value for CRYPTO_INSTR6 */ +#define _CRYPTO_SEQ1_INSTR6_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR6 */ +#define _CRYPTO_SEQ1_INSTR6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR6_DEFAULT (_CRYPTO_SEQ1_INSTR6_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR7_SHIFT 24 /**< Shift value for CRYPTO_INSTR7 */ +#define _CRYPTO_SEQ1_INSTR7_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR7 */ +#define _CRYPTO_SEQ1_INSTR7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR7_DEFAULT (_CRYPTO_SEQ1_INSTR7_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ + +/* Bit fields for CRYPTO SEQ2 */ +#define _CRYPTO_SEQ2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR8_SHIFT 0 /**< Shift value for CRYPTO_INSTR8 */ +#define _CRYPTO_SEQ2_INSTR8_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR8 */ +#define _CRYPTO_SEQ2_INSTR8_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR8_DEFAULT (_CRYPTO_SEQ2_INSTR8_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR9_SHIFT 8 /**< Shift value for CRYPTO_INSTR9 */ +#define _CRYPTO_SEQ2_INSTR9_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR9 */ +#define _CRYPTO_SEQ2_INSTR9_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR9_DEFAULT (_CRYPTO_SEQ2_INSTR9_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR10_SHIFT 16 /**< Shift value for CRYPTO_INSTR10 */ +#define _CRYPTO_SEQ2_INSTR10_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR10 */ +#define _CRYPTO_SEQ2_INSTR10_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR10_DEFAULT (_CRYPTO_SEQ2_INSTR10_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR11_SHIFT 24 /**< Shift value for CRYPTO_INSTR11 */ +#define _CRYPTO_SEQ2_INSTR11_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR11 */ +#define _CRYPTO_SEQ2_INSTR11_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR11_DEFAULT (_CRYPTO_SEQ2_INSTR11_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ + +/* Bit fields for CRYPTO SEQ3 */ +#define _CRYPTO_SEQ3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR12_SHIFT 0 /**< Shift value for CRYPTO_INSTR12 */ +#define _CRYPTO_SEQ3_INSTR12_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR12 */ +#define _CRYPTO_SEQ3_INSTR12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR12_DEFAULT (_CRYPTO_SEQ3_INSTR12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR13_SHIFT 8 /**< Shift value for CRYPTO_INSTR13 */ +#define _CRYPTO_SEQ3_INSTR13_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR13 */ +#define _CRYPTO_SEQ3_INSTR13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR13_DEFAULT (_CRYPTO_SEQ3_INSTR13_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR14_SHIFT 16 /**< Shift value for CRYPTO_INSTR14 */ +#define _CRYPTO_SEQ3_INSTR14_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR14 */ +#define _CRYPTO_SEQ3_INSTR14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR14_DEFAULT (_CRYPTO_SEQ3_INSTR14_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR15_SHIFT 24 /**< Shift value for CRYPTO_INSTR15 */ +#define _CRYPTO_SEQ3_INSTR15_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR15 */ +#define _CRYPTO_SEQ3_INSTR15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR15_DEFAULT (_CRYPTO_SEQ3_INSTR15_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ + +/* Bit fields for CRYPTO SEQ4 */ +#define _CRYPTO_SEQ4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR16_SHIFT 0 /**< Shift value for CRYPTO_INSTR16 */ +#define _CRYPTO_SEQ4_INSTR16_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR16 */ +#define _CRYPTO_SEQ4_INSTR16_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR16_DEFAULT (_CRYPTO_SEQ4_INSTR16_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR17_SHIFT 8 /**< Shift value for CRYPTO_INSTR17 */ +#define _CRYPTO_SEQ4_INSTR17_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR17 */ +#define _CRYPTO_SEQ4_INSTR17_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR17_DEFAULT (_CRYPTO_SEQ4_INSTR17_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR18_SHIFT 16 /**< Shift value for CRYPTO_INSTR18 */ +#define _CRYPTO_SEQ4_INSTR18_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR18 */ +#define _CRYPTO_SEQ4_INSTR18_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR18_DEFAULT (_CRYPTO_SEQ4_INSTR18_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR19_SHIFT 24 /**< Shift value for CRYPTO_INSTR19 */ +#define _CRYPTO_SEQ4_INSTR19_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR19 */ +#define _CRYPTO_SEQ4_INSTR19_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR19_DEFAULT (_CRYPTO_SEQ4_INSTR19_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ + +/* Bit fields for CRYPTO DATA0 */ +#define _CRYPTO_DATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_SHIFT 0 /**< Shift value for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0 */ +#define CRYPTO_DATA0_DATA0_DEFAULT (_CRYPTO_DATA0_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0 */ + +/* Bit fields for CRYPTO DATA1 */ +#define _CRYPTO_DATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_SHIFT 0 /**< Shift value for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1 */ +#define CRYPTO_DATA1_DATA1_DEFAULT (_CRYPTO_DATA1_DATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1 */ + +/* Bit fields for CRYPTO DATA2 */ +#define _CRYPTO_DATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_SHIFT 0 /**< Shift value for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA2 */ +#define CRYPTO_DATA2_DATA2_DEFAULT (_CRYPTO_DATA2_DATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA2 */ + +/* Bit fields for CRYPTO DATA3 */ +#define _CRYPTO_DATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_SHIFT 0 /**< Shift value for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA3 */ +#define CRYPTO_DATA3_DATA3_DEFAULT (_CRYPTO_DATA3_DATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA3 */ + +/* Bit fields for CRYPTO DATA0XOR */ +#define _CRYPTO_DATA0XOR_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_SHIFT 0 /**< Shift value for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XOR */ +#define CRYPTO_DATA0XOR_DATA0XOR_DEFAULT (_CRYPTO_DATA0XOR_DATA0XOR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XOR */ + +/* Bit fields for CRYPTO DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE */ +#define CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT (_CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE */ + +/* Bit fields for CRYPTO DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1BYTE */ +#define CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT (_CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1BYTE */ + +/* Bit fields for CRYPTO DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XORBYTE */ +#define CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT (_CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XORBYTE */ + +/* Bit fields for CRYPTO DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE12 */ +#define CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT (_CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE12 */ + +/* Bit fields for CRYPTO DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE13 */ +#define CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT (_CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE13 */ + +/* Bit fields for CRYPTO DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE14 */ +#define CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT (_CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE14 */ + +/* Bit fields for CRYPTO DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE15 */ +#define CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT (_CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE15 */ + +/* Bit fields for CRYPTO DDATA0 */ +#define _CRYPTO_DDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_SHIFT 0 /**< Shift value for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0 */ +#define CRYPTO_DDATA0_DDATA0_DEFAULT (_CRYPTO_DDATA0_DDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0 */ + +/* Bit fields for CRYPTO DDATA1 */ +#define _CRYPTO_DDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_SHIFT 0 /**< Shift value for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1 */ +#define CRYPTO_DDATA1_DDATA1_DEFAULT (_CRYPTO_DDATA1_DDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1 */ + +/* Bit fields for CRYPTO DDATA2 */ +#define _CRYPTO_DDATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_SHIFT 0 /**< Shift value for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA2 */ +#define CRYPTO_DDATA2_DDATA2_DEFAULT (_CRYPTO_DDATA2_DDATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA2 */ + +/* Bit fields for CRYPTO DDATA3 */ +#define _CRYPTO_DDATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_SHIFT 0 /**< Shift value for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA3 */ +#define CRYPTO_DDATA3_DDATA3_DEFAULT (_CRYPTO_DDATA3_DDATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA3 */ + +/* Bit fields for CRYPTO DDATA4 */ +#define _CRYPTO_DDATA4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_SHIFT 0 /**< Shift value for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA4 */ +#define CRYPTO_DDATA4_DDATA4_DEFAULT (_CRYPTO_DDATA4_DDATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA4 */ + +/* Bit fields for CRYPTO DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BIG */ +#define CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT (_CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BIG */ + +/* Bit fields for CRYPTO DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE */ +#define CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT (_CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE */ + +/* Bit fields for CRYPTO DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1BYTE */ +#define CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT (_CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1BYTE */ + +/* Bit fields for CRYPTO DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_MASK 0x0000000FUL /**< Mask for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK 0xFUL /**< Bit mask for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE32 */ +#define CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT (_CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE32 */ + +/* Bit fields for CRYPTO QDATA0 */ +#define _CRYPTO_QDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_SHIFT 0 /**< Shift value for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0 */ +#define CRYPTO_QDATA0_QDATA0_DEFAULT (_CRYPTO_QDATA0_QDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0 */ + +/* Bit fields for CRYPTO QDATA1 */ +#define _CRYPTO_QDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_SHIFT 0 /**< Shift value for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1 */ +#define CRYPTO_QDATA1_QDATA1_DEFAULT (_CRYPTO_QDATA1_QDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1 */ + +/* Bit fields for CRYPTO QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BIG */ +#define CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT (_CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BIG */ + +/* Bit fields for CRYPTO QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0BYTE */ +#define CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT (_CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0BYTE */ + +/* Bit fields for CRYPTO QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */ +#define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */ + +/** @} End of group EFR32MG12P_CRYPTO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h new file mode 100644 index 00000000000..c7d480da7f9 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h @@ -0,0 +1,1003 @@ +/**************************************************************************//** + * @file efr32mg12p_csen.h + * @brief EFR32MG12P_CSEN register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_CSEN + * @{ + * @brief EFR32MG12P_CSEN Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t TIMCTRL; /**< Timing Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t PRSSEL; /**< Control Register */ + __IOM uint32_t DATA; /**< Control Register */ + __IOM uint32_t SCANMASK0; /**< CSEN Channel Scan Mask */ + __IOM uint32_t SCANINPUTSEL0; /**< Input Channel Configuration register for Scan mode */ + __IOM uint32_t SCANMASK1; /**< CSEN Channel Scan Mask */ + __IOM uint32_t SCANINPUTSEL1; /**< Input Channel Configuration register for Scan mode */ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ + __IOM uint32_t CMPTHR; /**< CSEN Comparator Threshold */ + __IOM uint32_t EMA; /**< Exponential Moving Average */ + __IOM uint32_t EMACTRL; /**< Exponential Moving Average */ + __IOM uint32_t SINGLECTRL; /**< CSEN Single Conversion Control Register */ + __IOM uint32_t DMBASELINE; /**< Control Register */ + __IOM uint32_t DMCFG; /**< Control Register */ + __IOM uint32_t ANACTRL; /**< Analog Control Register */ + + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} CSEN_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_CSEN_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CSEN CTRL */ +#define _CSEN_CTRL_RESETVALUE 0x00030000UL /**< Default value for CSEN_CTRL */ +#define _CSEN_CTRL_MASK 0x1FFFF336UL /**< Mask for CSEN_CTRL */ +#define CSEN_CTRL_EN (0x1UL << 1) /**< CSEN Enable */ +#define _CSEN_CTRL_EN_SHIFT 1 /**< Shift value for CSEN_EN */ +#define _CSEN_CTRL_EN_MASK 0x2UL /**< Bit mask for CSEN_EN */ +#define _CSEN_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_EN_DEFAULT (_CSEN_CTRL_EN_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_EN_DISABLE (_CSEN_CTRL_EN_DISABLE << 1) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_EN_ENABLE (_CSEN_CTRL_EN_ENABLE << 1) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL (0x1UL << 2) /**< CSEN Digital Comparator Polarity Select */ +#define _CSEN_CTRL_CMPPOL_SHIFT 2 /**< Shift value for CSEN_CMPPOL */ +#define _CSEN_CTRL_CMPPOL_MASK 0x4UL /**< Bit mask for CSEN_CMPPOL */ +#define _CSEN_CTRL_CMPPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPPOL_GT 0x00000000UL /**< Mode GT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPPOL_LTE 0x00000001UL /**< Mode LTE for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_DEFAULT (_CSEN_CTRL_CMPPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_GT (_CSEN_CTRL_CMPPOL_GT << 2) /**< Shifted mode GT for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_LTE (_CSEN_CTRL_CMPPOL_LTE << 2) /**< Shifted mode LTE for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SHIFT 4 /**< Shift value for CSEN_CM */ +#define _CSEN_CTRL_CM_MASK 0x30UL /**< Bit mask for CSEN_CM */ +#define _CSEN_CTRL_CM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SGL 0x00000000UL /**< Mode SGL for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SCAN 0x00000001UL /**< Mode SCAN for CSEN_CTRL */ +#define _CSEN_CTRL_CM_CONTSGL 0x00000002UL /**< Mode CONTSGL for CSEN_CTRL */ +#define _CSEN_CTRL_CM_CONTSCAN 0x00000003UL /**< Mode CONTSCAN for CSEN_CTRL */ +#define CSEN_CTRL_CM_DEFAULT (_CSEN_CTRL_CM_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CM_SGL (_CSEN_CTRL_CM_SGL << 4) /**< Shifted mode SGL for CSEN_CTRL */ +#define CSEN_CTRL_CM_SCAN (_CSEN_CTRL_CM_SCAN << 4) /**< Shifted mode SCAN for CSEN_CTRL */ +#define CSEN_CTRL_CM_CONTSGL (_CSEN_CTRL_CM_CONTSGL << 4) /**< Shifted mode CONTSGL for CSEN_CTRL */ +#define CSEN_CTRL_CM_CONTSCAN (_CSEN_CTRL_CM_CONTSCAN << 4) /**< Shifted mode CONTSCAN for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_SHIFT 8 /**< Shift value for CSEN_SARCR */ +#define _CSEN_CTRL_SARCR_MASK 0x300UL /**< Bit mask for CSEN_SARCR */ +#define _CSEN_CTRL_SARCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK10 0x00000000UL /**< Mode CLK10 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK12 0x00000001UL /**< Mode CLK12 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK14 0x00000002UL /**< Mode CLK14 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK16 0x00000003UL /**< Mode CLK16 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_DEFAULT (_CSEN_CTRL_SARCR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK10 (_CSEN_CTRL_SARCR_CLK10 << 8) /**< Shifted mode CLK10 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK12 (_CSEN_CTRL_SARCR_CLK12 << 8) /**< Shifted mode CLK12 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK14 (_CSEN_CTRL_SARCR_CLK14 << 8) /**< Shifted mode CLK14 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK16 (_CSEN_CTRL_SARCR_CLK16 << 8) /**< Shifted mode CLK16 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_SHIFT 12 /**< Shift value for CSEN_ACU */ +#define _CSEN_CTRL_ACU_MASK 0x7000UL /**< Bit mask for CSEN_ACU */ +#define _CSEN_CTRL_ACU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC1 0x00000000UL /**< Mode ACC1 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC2 0x00000001UL /**< Mode ACC2 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC4 0x00000002UL /**< Mode ACC4 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC8 0x00000003UL /**< Mode ACC8 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC16 0x00000004UL /**< Mode ACC16 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC32 0x00000005UL /**< Mode ACC32 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC64 0x00000006UL /**< Mode ACC64 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_DEFAULT (_CSEN_CTRL_ACU_DEFAULT << 12) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC1 (_CSEN_CTRL_ACU_ACC1 << 12) /**< Shifted mode ACC1 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC2 (_CSEN_CTRL_ACU_ACC2 << 12) /**< Shifted mode ACC2 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC4 (_CSEN_CTRL_ACU_ACC4 << 12) /**< Shifted mode ACC4 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC8 (_CSEN_CTRL_ACU_ACC8 << 12) /**< Shifted mode ACC8 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC16 (_CSEN_CTRL_ACU_ACC16 << 12) /**< Shifted mode ACC16 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC32 (_CSEN_CTRL_ACU_ACC32 << 12) /**< Shifted mode ACC32 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC64 (_CSEN_CTRL_ACU_ACC64 << 12) /**< Shifted mode ACC64 for CSEN_CTRL */ +#define CSEN_CTRL_MCEN (0x1UL << 15) /**< CSEN Multiple Channel Enable. */ +#define _CSEN_CTRL_MCEN_SHIFT 15 /**< Shift value for CSEN_MCEN */ +#define _CSEN_CTRL_MCEN_MASK 0x8000UL /**< Bit mask for CSEN_MCEN */ +#define _CSEN_CTRL_MCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_MCEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_MCEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_DEFAULT (_CSEN_CTRL_MCEN_DEFAULT << 15) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_DISABLE (_CSEN_CTRL_MCEN_DISABLE << 15) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_ENABLE (_CSEN_CTRL_MCEN_ENABLE << 15) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define _CSEN_CTRL_STM_SHIFT 16 /**< Shift value for CSEN_STM */ +#define _CSEN_CTRL_STM_MASK 0x30000UL /**< Bit mask for CSEN_STM */ +#define _CSEN_CTRL_STM_PRS 0x00000000UL /**< Mode PRS for CSEN_CTRL */ +#define _CSEN_CTRL_STM_TIMER 0x00000001UL /**< Mode TIMER for CSEN_CTRL */ +#define _CSEN_CTRL_STM_START 0x00000002UL /**< Mode START for CSEN_CTRL */ +#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_STM_PRS (_CSEN_CTRL_STM_PRS << 16) /**< Shifted mode PRS for CSEN_CTRL */ +#define CSEN_CTRL_STM_TIMER (_CSEN_CTRL_STM_TIMER << 16) /**< Shifted mode TIMER for CSEN_CTRL */ +#define CSEN_CTRL_STM_START (_CSEN_CTRL_STM_START << 16) /**< Shifted mode START for CSEN_CTRL */ +#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN (0x1UL << 18) /**< CSEN Digital Comparator Enable Bit. */ +#define _CSEN_CTRL_CMPEN_SHIFT 18 /**< Shift value for CSEN_CMPEN */ +#define _CSEN_CTRL_CMPEN_MASK 0x40000UL /**< Bit mask for CSEN_CMPEN */ +#define _CSEN_CTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_CMPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_DEFAULT (_CSEN_CTRL_CMPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_DISABLE (_CSEN_CTRL_CMPEN_DISABLE << 18) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_ENABLE (_CSEN_CTRL_CMPEN_ENABLE << 18) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF (0x1UL << 19) /**< CSEN Disable Right-Shift. */ +#define _CSEN_CTRL_DRSF_SHIFT 19 /**< Shift value for CSEN_DRSF */ +#define _CSEN_CTRL_DRSF_MASK 0x80000UL /**< Bit mask for CSEN_DRSF */ +#define _CSEN_CTRL_DRSF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_DRSF_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_DRSF_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_DEFAULT (_CSEN_CTRL_DRSF_DEFAULT << 19) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_DISABLE (_CSEN_CTRL_DRSF_DISABLE << 19) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_ENABLE (_CSEN_CTRL_DRSF_ENABLE << 19) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN (0x1UL << 20) /**< CSEN DMA Enable Bit. */ +#define _CSEN_CTRL_DMAEN_SHIFT 20 /**< Shift value for CSEN_DMAEN */ +#define _CSEN_CTRL_DMAEN_MASK 0x100000UL /**< Bit mask for CSEN_DMAEN */ +#define _CSEN_CTRL_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_DEFAULT (_CSEN_CTRL_DMAEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_DISABLE (_CSEN_CTRL_DMAEN_DISABLE << 20) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_ENABLE (_CSEN_CTRL_DMAEN_ENABLE << 20) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL (0x1UL << 21) /**< CSEN Converter Select */ +#define _CSEN_CTRL_CONVSEL_SHIFT 21 /**< Shift value for CSEN_CONVSEL */ +#define _CSEN_CTRL_CONVSEL_MASK 0x200000UL /**< Bit mask for CSEN_CONVSEL */ +#define _CSEN_CTRL_CONVSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CONVSEL_SAR 0x00000000UL /**< Mode SAR for CSEN_CTRL */ +#define _CSEN_CTRL_CONVSEL_DM 0x00000001UL /**< Mode DM for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_DEFAULT (_CSEN_CTRL_CONVSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_SAR (_CSEN_CTRL_CONVSEL_SAR << 21) /**< Shifted mode SAR for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_DM (_CSEN_CTRL_CONVSEL_DM << 21) /**< Shifted mode DM for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN (0x1UL << 22) /**< CSEN Chop Enable */ +#define _CSEN_CTRL_CHOPEN_SHIFT 22 /**< Shift value for CSEN_CHOPEN */ +#define _CSEN_CTRL_CHOPEN_MASK 0x400000UL /**< Bit mask for CSEN_CHOPEN */ +#define _CSEN_CTRL_CHOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CHOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_CHOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_DEFAULT (_CSEN_CTRL_CHOPEN_DEFAULT << 22) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_DISABLE (_CSEN_CTRL_CHOPEN_DISABLE << 22) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_ENABLE (_CSEN_CTRL_CHOPEN_ENABLE << 22) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND (0x1UL << 23) /**< CSEN auto ground enable */ +#define _CSEN_CTRL_AUTOGND_SHIFT 23 /**< Shift value for CSEN_AUTOGND */ +#define _CSEN_CTRL_AUTOGND_MASK 0x800000UL /**< Bit mask for CSEN_AUTOGND */ +#define _CSEN_CTRL_AUTOGND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_AUTOGND_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_AUTOGND_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_DEFAULT (_CSEN_CTRL_AUTOGND_DEFAULT << 23) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_DISABLE (_CSEN_CTRL_AUTOGND_DISABLE << 23) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_ENABLE (_CSEN_CTRL_AUTOGND_ENABLE << 23) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_MXUC (0x1UL << 24) /**< CSEN Mux Disconnect. */ +#define _CSEN_CTRL_MXUC_SHIFT 24 /**< Shift value for CSEN_MXUC */ +#define _CSEN_CTRL_MXUC_MASK 0x1000000UL /**< Bit mask for CSEN_MXUC */ +#define _CSEN_CTRL_MXUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_MXUC_CONN 0x00000000UL /**< Mode CONN for CSEN_CTRL */ +#define _CSEN_CTRL_MXUC_UNC 0x00000001UL /**< Mode UNC for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_DEFAULT (_CSEN_CTRL_MXUC_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_CONN (_CSEN_CTRL_MXUC_CONN << 24) /**< Shifted mode CONN for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_UNC (_CSEN_CTRL_MXUC_UNC << 24) /**< Shifted mode UNC for CSEN_CTRL */ +#define CSEN_CTRL_EMACMPEN (0x1UL << 25) /**< Greater and less than comparison using the exponential moving average (EMA) is enabled. */ +#define _CSEN_CTRL_EMACMPEN_SHIFT 25 /**< Shift value for CSEN_EMACMPEN */ +#define _CSEN_CTRL_EMACMPEN_MASK 0x2000000UL /**< Bit mask for CSEN_EMACMPEN */ +#define _CSEN_CTRL_EMACMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_EMACMPEN_DEFAULT (_CSEN_CTRL_EMACMPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE (0x1UL << 26) /**< Select Warmup mode for CSEN */ +#define _CSEN_CTRL_WARMUPMODE_SHIFT 26 /**< Shift value for CSEN_WARMUPMODE */ +#define _CSEN_CTRL_WARMUPMODE_MASK 0x4000000UL /**< Bit mask for CSEN_WARMUPMODE */ +#define _CSEN_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for CSEN_CTRL */ +#define _CSEN_CTRL_WARMUPMODE_KEEPCSENWARM 0x00000001UL /**< Mode KEEPCSENWARM for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_DEFAULT (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_NORMAL (_CSEN_CTRL_WARMUPMODE_NORMAL << 26) /**< Shifted mode NORMAL for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */ +#define CSEN_CTRL_LOCALSENS (0x1UL << 27) /**< Sense local cap connection instead of the external kelvin connection. */ +#define _CSEN_CTRL_LOCALSENS_SHIFT 27 /**< Shift value for CSEN_LOCALSENS */ +#define _CSEN_CTRL_LOCALSENS_MASK 0x8000000UL /**< Bit mask for CSEN_LOCALSENS */ +#define _CSEN_CTRL_LOCALSENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_LOCALSENS_DEFAULT (_CSEN_CTRL_LOCALSENS_DEFAULT << 27) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY (0x1UL << 28) /**< Sets the accuracy of the charge pump. */ +#define _CSEN_CTRL_CPACCURACY_SHIFT 28 /**< Shift value for CSEN_CPACCURACY */ +#define _CSEN_CTRL_CPACCURACY_MASK 0x10000000UL /**< Bit mask for CSEN_CPACCURACY */ +#define _CSEN_CTRL_CPACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CPACCURACY_LO 0x00000000UL /**< Mode LO for CSEN_CTRL */ +#define _CSEN_CTRL_CPACCURACY_HI 0x00000001UL /**< Mode HI for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_DEFAULT (_CSEN_CTRL_CPACCURACY_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_LO (_CSEN_CTRL_CPACCURACY_LO << 28) /**< Shifted mode LO for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_HI (_CSEN_CTRL_CPACCURACY_HI << 28) /**< Shifted mode HI for CSEN_CTRL */ + +/* Bit fields for CSEN TIMCTRL */ +#define _CSEN_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_MASK 0x0003FF07UL /**< Mask for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_SHIFT 0 /**< Shift value for CSEN_PCPRESC */ +#define _CSEN_TIMCTRL_PCPRESC_MASK 0x7UL /**< Bit mask for CSEN_PCPRESC */ +#define _CSEN_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DEFAULT (_CSEN_TIMCTRL_PCPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV1 (_CSEN_TIMCTRL_PCPRESC_DIV1 << 0) /**< Shifted mode DIV1 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV2 (_CSEN_TIMCTRL_PCPRESC_DIV2 << 0) /**< Shifted mode DIV2 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV4 (_CSEN_TIMCTRL_PCPRESC_DIV4 << 0) /**< Shifted mode DIV4 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV8 (_CSEN_TIMCTRL_PCPRESC_DIV8 << 0) /**< Shifted mode DIV8 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV16 (_CSEN_TIMCTRL_PCPRESC_DIV16 << 0) /**< Shifted mode DIV16 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV32 (_CSEN_TIMCTRL_PCPRESC_DIV32 << 0) /**< Shifted mode DIV32 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) /**< Shifted mode DIV64 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV128 (_CSEN_TIMCTRL_PCPRESC_DIV128 << 0) /**< Shifted mode DIV128 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCTOP_SHIFT 8 /**< Shift value for CSEN_PCTOP */ +#define _CSEN_TIMCTRL_PCTOP_MASK 0xFF00UL /**< Bit mask for CSEN_PCTOP */ +#define _CSEN_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCTOP_DEFAULT (_CSEN_TIMCTRL_PCTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_WARMUPCNT_SHIFT 16 /**< Shift value for CSEN_WARMUPCNT */ +#define _CSEN_TIMCTRL_WARMUPCNT_MASK 0x30000UL /**< Bit mask for CSEN_WARMUPCNT */ +#define _CSEN_TIMCTRL_WARMUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_WARMUPCNT_DEFAULT (_CSEN_TIMCTRL_WARMUPCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ + +/* Bit fields for CSEN CMD */ +#define _CSEN_CMD_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMD */ +#define _CSEN_CMD_MASK 0x00000001UL /**< Mask for CSEN_CMD */ +#define CSEN_CMD_START (0x1UL << 0) /**< Start a CSEN conversion. */ +#define _CSEN_CMD_START_SHIFT 0 /**< Shift value for CSEN_START */ +#define _CSEN_CMD_START_MASK 0x1UL /**< Bit mask for CSEN_START */ +#define _CSEN_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMD */ +#define CSEN_CMD_START_DEFAULT (_CSEN_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMD */ + +/* Bit fields for CSEN STATUS */ +#define _CSEN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CSEN_STATUS */ +#define _CSEN_STATUS_MASK 0x00000001UL /**< Mask for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY (0x1UL << 0) /**< CSEN Busy */ +#define _CSEN_STATUS_CSENBUSY_SHIFT 0 /**< Shift value for CSEN_CSENBUSY */ +#define _CSEN_STATUS_CSENBUSY_MASK 0x1UL /**< Bit mask for CSEN_CSENBUSY */ +#define _CSEN_STATUS_CSENBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_STATUS */ +#define _CSEN_STATUS_CSENBUSY_IDLE 0x00000000UL /**< Mode IDLE for CSEN_STATUS */ +#define _CSEN_STATUS_CSENBUSY_BUSY 0x00000001UL /**< Mode BUSY for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_DEFAULT (_CSEN_STATUS_CSENBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_IDLE (_CSEN_STATUS_CSENBUSY_IDLE << 0) /**< Shifted mode IDLE for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_BUSY (_CSEN_STATUS_CSENBUSY_BUSY << 0) /**< Shifted mode BUSY for CSEN_STATUS */ + +/* Bit fields for CSEN PRSSEL */ +#define _CSEN_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_MASK 0x0000000FUL /**< Mask for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_SHIFT 0 /**< Shift value for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_MASK 0xFUL /**< Bit mask for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_DEFAULT (_CSEN_PRSSEL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH0 (_CSEN_PRSSEL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH1 (_CSEN_PRSSEL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH2 (_CSEN_PRSSEL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH3 (_CSEN_PRSSEL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH4 (_CSEN_PRSSEL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH5 (_CSEN_PRSSEL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH6 (_CSEN_PRSSEL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH7 (_CSEN_PRSSEL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH8 (_CSEN_PRSSEL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH9 (_CSEN_PRSSEL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH10 (_CSEN_PRSSEL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH11 (_CSEN_PRSSEL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for CSEN_PRSSEL */ + +/* Bit fields for CSEN DATA */ +#define _CSEN_DATA_RESETVALUE 0x00000000UL /**< Default value for CSEN_DATA */ +#define _CSEN_DATA_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DATA */ +#define _CSEN_DATA_DATA_SHIFT 0 /**< Shift value for CSEN_DATA */ +#define _CSEN_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_DATA */ +#define _CSEN_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DATA */ +#define CSEN_DATA_DATA_DEFAULT (_CSEN_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DATA */ + +/* Bit fields for CSEN SCANMASK0 */ +#define _CSEN_SCANMASK0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK0 */ +#define _CSEN_SCANMASK0_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK0 */ +#define _CSEN_SCANMASK0_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK0_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK0_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK0 */ +#define CSEN_SCANMASK0_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK0_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK0 */ + +/* Bit fields for CSEN SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT 0 /**< Shift value for CSEN_INPUT0TO7SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT0TO7SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT 8 /**< Shift value for CSEN_INPUT8TO15SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT8TO15SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT 16 /**< Shift value for CSEN_INPUT16TO23SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT16TO23SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT 24 /**< Shift value for CSEN_INPUT24TO31SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT24TO31SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ + +/* Bit fields for CSEN SCANMASK1 */ +#define _CSEN_SCANMASK1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK1 */ +#define _CSEN_SCANMASK1_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK1 */ +#define _CSEN_SCANMASK1_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK1_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK1_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK1 */ +#define CSEN_SCANMASK1_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK1_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK1 */ + +/* Bit fields for CSEN SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT 0 /**< Shift value for CSEN_INPUT32TO39SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT32TO39SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT 8 /**< Shift value for CSEN_INPUT40TO47SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT40TO47SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT 16 /**< Shift value for CSEN_INPUT48TO55SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT48TO55SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT 24 /**< Shift value for CSEN_INPUT56TO63SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT56TO63SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ + +/* Bit fields for CSEN APORTREQ */ +#define _CSEN_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTREQ */ +#define _CSEN_APORTREQ_MASK 0x000003FCUL /**< Mask for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _CSEN_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for CSEN_APORT1XREQ */ +#define _CSEN_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for CSEN_APORT1XREQ */ +#define _CSEN_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1XREQ_DEFAULT (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _CSEN_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for CSEN_APORT1YREQ */ +#define _CSEN_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for CSEN_APORT1YREQ */ +#define _CSEN_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1YREQ_DEFAULT (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _CSEN_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for CSEN_APORT2XREQ */ +#define _CSEN_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for CSEN_APORT2XREQ */ +#define _CSEN_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2XREQ_DEFAULT (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _CSEN_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for CSEN_APORT2YREQ */ +#define _CSEN_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for CSEN_APORT2YREQ */ +#define _CSEN_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2YREQ_DEFAULT (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _CSEN_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for CSEN_APORT3XREQ */ +#define _CSEN_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for CSEN_APORT3XREQ */ +#define _CSEN_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3XREQ_DEFAULT (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _CSEN_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for CSEN_APORT3YREQ */ +#define _CSEN_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for CSEN_APORT3YREQ */ +#define _CSEN_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3YREQ_DEFAULT (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _CSEN_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for CSEN_APORT4XREQ */ +#define _CSEN_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for CSEN_APORT4XREQ */ +#define _CSEN_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4XREQ_DEFAULT (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _CSEN_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for CSEN_APORT4YREQ */ +#define _CSEN_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for CSEN_APORT4YREQ */ +#define _CSEN_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4YREQ_DEFAULT (_CSEN_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ + +/* Bit fields for CSEN APORTCONFLICT */ +#define _CSEN_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTCONFLICT */ +#define _CSEN_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for CSEN_APORT1XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for CSEN_APORT1XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for CSEN_APORT1YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for CSEN_APORT1YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORT2XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORT2XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for CSEN_APORT2YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for CSEN_APORT2YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for CSEN_APORT3XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for CSEN_APORT3XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for CSEN_APORT3YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for CSEN_APORT3YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for CSEN_APORT4XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for CSEN_APORT4XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for CSEN_APORT4YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for CSEN_APORT4YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ + +/* Bit fields for CSEN CMPTHR */ +#define _CSEN_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_MASK 0x0000FFFFUL /**< Mask for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_SHIFT 0 /**< Shift value for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_MASK 0xFFFFUL /**< Bit mask for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMPTHR */ +#define CSEN_CMPTHR_CMPTHR_DEFAULT (_CSEN_CMPTHR_CMPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMPTHR */ + +/* Bit fields for CSEN EMA */ +#define _CSEN_EMA_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMA */ +#define _CSEN_EMA_MASK 0x003FFFFFUL /**< Mask for CSEN_EMA */ +#define _CSEN_EMA_EMA_SHIFT 0 /**< Shift value for CSEN_EMA */ +#define _CSEN_EMA_EMA_MASK 0x3FFFFFUL /**< Bit mask for CSEN_EMA */ +#define _CSEN_EMA_EMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMA */ +#define CSEN_EMA_EMA_DEFAULT (_CSEN_EMA_EMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMA */ + +/* Bit fields for CSEN EMACTRL */ +#define _CSEN_EMACTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_MASK 0x00000007UL /**< Mask for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_SHIFT 0 /**< Shift value for CSEN_EMASAMPLE */ +#define _CSEN_EMACTRL_EMASAMPLE_MASK 0x7UL /**< Bit mask for CSEN_EMASAMPLE */ +#define _CSEN_EMACTRL_EMASAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W1 0x00000000UL /**< Mode W1 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W2 0x00000001UL /**< Mode W2 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W4 0x00000002UL /**< Mode W4 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W8 0x00000003UL /**< Mode W8 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W16 0x00000004UL /**< Mode W16 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W32 0x00000005UL /**< Mode W32 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W64 0x00000006UL /**< Mode W64 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_DEFAULT (_CSEN_EMACTRL_EMASAMPLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W1 (_CSEN_EMACTRL_EMASAMPLE_W1 << 0) /**< Shifted mode W1 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W2 (_CSEN_EMACTRL_EMASAMPLE_W2 << 0) /**< Shifted mode W2 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W4 (_CSEN_EMACTRL_EMASAMPLE_W4 << 0) /**< Shifted mode W4 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W8 (_CSEN_EMACTRL_EMASAMPLE_W8 << 0) /**< Shifted mode W8 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W16 (_CSEN_EMACTRL_EMASAMPLE_W16 << 0) /**< Shifted mode W16 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W32 (_CSEN_EMACTRL_EMASAMPLE_W32 << 0) /**< Shifted mode W32 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W64 (_CSEN_EMACTRL_EMASAMPLE_W64 << 0) /**< Shifted mode W64 for CSEN_EMACTRL */ + +/* Bit fields for CSEN SINGLECTRL */ +#define _CSEN_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_MASK 0x000007F0UL /**< Mask for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_SHIFT 4 /**< Shift value for CSEN_SINGLESEL */ +#define _CSEN_SINGLECTRL_SINGLESEL_MASK 0x7F0UL /**< Bit mask for CSEN_SINGLESEL */ +#define _CSEN_SINGLECTRL_SINGLESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_DEFAULT (_CSEN_SINGLECTRL_SINGLESEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 << 4) /**< Shifted mode APORT3XCH0 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 << 4) /**< Shifted mode APORT3YCH1 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 << 4) /**< Shifted mode APORT3XCH2 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 << 4) /**< Shifted mode APORT3YCH3 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 << 4) /**< Shifted mode APORT3XCH4 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 << 4) /**< Shifted mode APORT3YCH5 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 << 4) /**< Shifted mode APORT3XCH6 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 << 4) /**< Shifted mode APORT3YCH7 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 << 4) /**< Shifted mode APORT3XCH8 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 << 4) /**< Shifted mode APORT3YCH9 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 << 4) /**< Shifted mode APORT3XCH10 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 << 4) /**< Shifted mode APORT3YCH11 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 << 4) /**< Shifted mode APORT3XCH12 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 << 4) /**< Shifted mode APORT3YCH13 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 << 4) /**< Shifted mode APORT3XCH14 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 << 4) /**< Shifted mode APORT3YCH15 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 << 4) /**< Shifted mode APORT3XCH16 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 << 4) /**< Shifted mode APORT3YCH17 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 << 4) /**< Shifted mode APORT3XCH18 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 << 4) /**< Shifted mode APORT3YCH19 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 << 4) /**< Shifted mode APORT3XCH20 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 << 4) /**< Shifted mode APORT3YCH21 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 << 4) /**< Shifted mode APORT3XCH22 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 << 4) /**< Shifted mode APORT3YCH23 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 << 4) /**< Shifted mode APORT3XCH24 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 << 4) /**< Shifted mode APORT3YCH25 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 << 4) /**< Shifted mode APORT3XCH26 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 << 4) /**< Shifted mode APORT3YCH27 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 << 4) /**< Shifted mode APORT3XCH28 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 << 4) /**< Shifted mode APORT3YCH29 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 << 4) /**< Shifted mode APORT3XCH30 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 << 4) /**< Shifted mode APORT3YCH31 for CSEN_SINGLECTRL */ + +/* Bit fields for CSEN DMBASELINE */ +#define _CSEN_DMBASELINE_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_BASELINEUP_SHIFT 0 /**< Shift value for CSEN_BASELINEUP */ +#define _CSEN_DMBASELINE_BASELINEUP_MASK 0xFFFFUL /**< Bit mask for CSEN_BASELINEUP */ +#define _CSEN_DMBASELINE_BASELINEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ +#define CSEN_DMBASELINE_BASELINEUP_DEFAULT (_CSEN_DMBASELINE_BASELINEUP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_BASELINEDN_SHIFT 16 /**< Shift value for CSEN_BASELINEDN */ +#define _CSEN_DMBASELINE_BASELINEDN_MASK 0xFFFF0000UL /**< Bit mask for CSEN_BASELINEDN */ +#define _CSEN_DMBASELINE_BASELINEDN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ +#define CSEN_DMBASELINE_BASELINEDN_DEFAULT (_CSEN_DMBASELINE_BASELINEDN_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ + +/* Bit fields for CSEN DMCFG */ +#define _CSEN_DMCFG_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMCFG */ +#define _CSEN_DMCFG_MASK 0x103F0FFFUL /**< Mask for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMG_SHIFT 0 /**< Shift value for CSEN_DMG */ +#define _CSEN_DMCFG_DMG_MASK 0xFFUL /**< Bit mask for CSEN_DMG */ +#define _CSEN_DMCFG_DMG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMG_DEFAULT (_CSEN_DMCFG_DMG_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMR_SHIFT 8 /**< Shift value for CSEN_DMR */ +#define _CSEN_DMCFG_DMR_MASK 0xF00UL /**< Bit mask for CSEN_DMR */ +#define _CSEN_DMCFG_DMR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMR_DEFAULT (_CSEN_DMCFG_DMR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMCR_SHIFT 16 /**< Shift value for CSEN_DMCR */ +#define _CSEN_DMCFG_DMCR_MASK 0xF0000UL /**< Bit mask for CSEN_DMCR */ +#define _CSEN_DMCFG_DMCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMCR_DEFAULT (_CSEN_DMCFG_DMCR_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_SHIFT 20 /**< Shift value for CSEN_CRMODE */ +#define _CSEN_DMCFG_CRMODE_MASK 0x300000UL /**< Bit mask for CSEN_CRMODE */ +#define _CSEN_DMCFG_CRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM10 0x00000000UL /**< Mode DM10 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM12 0x00000001UL /**< Mode DM12 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM14 0x00000002UL /**< Mode DM14 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM16 0x00000003UL /**< Mode DM16 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DEFAULT (_CSEN_DMCFG_CRMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM10 (_CSEN_DMCFG_CRMODE_DM10 << 20) /**< Shifted mode DM10 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM12 (_CSEN_DMCFG_CRMODE_DM12 << 20) /**< Shifted mode DM12 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM14 (_CSEN_DMCFG_CRMODE_DM14 << 20) /**< Shifted mode DM14 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM16 (_CSEN_DMCFG_CRMODE_DM16 << 20) /**< Shifted mode DM16 for CSEN_DMCFG */ +#define CSEN_DMCFG_DMGRDIS (0x1UL << 28) /**< Disable delta modulator gain reduction. */ +#define _CSEN_DMCFG_DMGRDIS_SHIFT 28 /**< Shift value for CSEN_DMGRDIS */ +#define _CSEN_DMCFG_DMGRDIS_MASK 0x10000000UL /**< Bit mask for CSEN_DMGRDIS */ +#define _CSEN_DMCFG_DMGRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMGRDIS_DEFAULT (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */ + +/* Bit fields for CSEN ANACTRL */ +#define _CSEN_ANACTRL_RESETVALUE 0x00000070UL /**< Default value for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_MASK 0x03730771UL /**< Mask for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF (0x1UL << 0) /**< Reference capacitor divide by half. */ +#define _CSEN_ANACTRL_CREFHALF_SHIFT 0 /**< Shift value for CSEN_CREFHALF */ +#define _CSEN_ANACTRL_CREFHALF_MASK 0x1UL /**< Bit mask for CSEN_CREFHALF */ +#define _CSEN_ANACTRL_CREFHALF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_CREFHALF_FULL 0x00000000UL /**< Mode FULL for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_CREFHALF_HALF 0x00000001UL /**< Mode HALF for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_DEFAULT (_CSEN_ANACTRL_CREFHALF_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_FULL (_CSEN_ANACTRL_CREFHALF_FULL << 0) /**< Shifted mode FULL for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_HALF (_CSEN_ANACTRL_CREFHALF_HALF << 0) /**< Shifted mode HALF for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_IREFPROG_SHIFT 4 /**< Shift value for CSEN_IREFPROG */ +#define _CSEN_ANACTRL_IREFPROG_MASK 0x70UL /**< Bit mask for CSEN_IREFPROG */ +#define _CSEN_ANACTRL_IREFPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_IREFPROG_DEFAULT (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_IDACIREFS_SHIFT 8 /**< Shift value for CSEN_IDACIREFS */ +#define _CSEN_ANACTRL_IDACIREFS_MASK 0x700UL /**< Bit mask for CSEN_IDACIREFS */ +#define _CSEN_ANACTRL_IDACIREFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_IDACIREFS_DEFAULT (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_SHIFT 16 /**< Shift value for CSEN_DUTYSCALE */ +#define _CSEN_ANACTRL_DUTYSCALE_MASK 0x30000UL /**< Bit mask for CSEN_DUTYSCALE */ +#define _CSEN_ANACTRL_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DEFAULT (_CSEN_ANACTRL_DUTYSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV1 (_CSEN_ANACTRL_DUTYSCALE_DIV1 << 16) /**< Shifted mode DIV1 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV2 (_CSEN_ANACTRL_DUTYSCALE_DIV2 << 16) /**< Shifted mode DIV2 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV4 (_CSEN_ANACTRL_DUTYSCALE_DIV4 << 16) /**< Shifted mode DIV4 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV8 (_CSEN_ANACTRL_DUTYSCALE_DIV8 << 16) /**< Shifted mode DIV8 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_TRSTPROG_SHIFT 20 /**< Shift value for CSEN_TRSTPROG */ +#define _CSEN_ANACTRL_TRSTPROG_MASK 0x700000UL /**< Bit mask for CSEN_TRSTPROG */ +#define _CSEN_ANACTRL_TRSTPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_TRSTPROG_DEFAULT (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_SHIFT 24 /**< Shift value for CSEN_BIASPROG */ +#define _CSEN_ANACTRL_BIASPROG_MASK 0x3000000UL /**< Bit mask for CSEN_BIASPROG */ +#define _CSEN_ANACTRL_BIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_ONEX 0x00000000UL /**< Mode ONEX for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_TWOX 0x00000001UL /**< Mode TWOX for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_ONETENTH 0x00000002UL /**< Mode ONETENTH for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_HALF 0x00000003UL /**< Mode HALF for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_DEFAULT (_CSEN_ANACTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_ONEX (_CSEN_ANACTRL_BIASPROG_ONEX << 24) /**< Shifted mode ONEX for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_TWOX (_CSEN_ANACTRL_BIASPROG_TWOX << 24) /**< Shifted mode TWOX for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_ONETENTH (_CSEN_ANACTRL_BIASPROG_ONETENTH << 24) /**< Shifted mode ONETENTH for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_HALF (_CSEN_ANACTRL_BIASPROG_HALF << 24) /**< Shifted mode HALF for CSEN_ANACTRL */ + +/* Bit fields for CSEN IF */ +#define _CSEN_IF_RESETVALUE 0x00000000UL /**< Default value for CSEN_IF */ +#define _CSEN_IF_MASK 0x0000001FUL /**< Mask for CSEN_IF */ +#define CSEN_IF_CMP (0x1UL << 0) /**< CSEN Digital Comparator Interrupt Flag */ +#define _CSEN_IF_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IF_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IF_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CMP_DEFAULT (_CSEN_IF_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CONV (0x1UL << 1) /**< CSEN Conversion Done Interrupt Flag */ +#define _CSEN_IF_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IF_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IF_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CONV_DEFAULT (_CSEN_IF_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_EOS (0x1UL << 2) /**< CSEN End of Scan Interrupt Flag. */ +#define _CSEN_IF_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IF_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IF_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_EOS_DEFAULT (_CSEN_IF_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_DMAOF (0x1UL << 3) /**< CSEN DMA Overflow Interrupt Flag. */ +#define _CSEN_IF_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IF_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IF_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_DMAOF_DEFAULT (_CSEN_IF_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_APORTCONFLICT (0x1UL << 4) /**< APORT Conflict Interrupt Flag */ +#define _CSEN_IF_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IF_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_APORTCONFLICT_DEFAULT (_CSEN_IF_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IF */ + +/* Bit fields for CSEN IFS */ +#define _CSEN_IFS_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFS */ +#define _CSEN_IFS_MASK 0x0000001FUL /**< Mask for CSEN_IFS */ +#define CSEN_IFS_CMP (0x1UL << 0) /**< Set CMP Interrupt Flag */ +#define _CSEN_IFS_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IFS_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IFS_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CMP_DEFAULT (_CSEN_IFS_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CONV (0x1UL << 1) /**< Set CONV Interrupt Flag */ +#define _CSEN_IFS_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IFS_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IFS_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CONV_DEFAULT (_CSEN_IFS_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_EOS (0x1UL << 2) /**< Set EOS Interrupt Flag */ +#define _CSEN_IFS_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IFS_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IFS_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_EOS_DEFAULT (_CSEN_IFS_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_DMAOF (0x1UL << 3) /**< Set DMAOF Interrupt Flag */ +#define _CSEN_IFS_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IFS_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IFS_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_DMAOF_DEFAULT (_CSEN_IFS_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_APORTCONFLICT (0x1UL << 4) /**< Set APORTCONFLICT Interrupt Flag */ +#define _CSEN_IFS_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IFS_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_APORTCONFLICT_DEFAULT (_CSEN_IFS_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFS */ + +/* Bit fields for CSEN IFC */ +#define _CSEN_IFC_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFC */ +#define _CSEN_IFC_MASK 0x0000001FUL /**< Mask for CSEN_IFC */ +#define CSEN_IFC_CMP (0x1UL << 0) /**< Clear CMP Interrupt Flag */ +#define _CSEN_IFC_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IFC_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IFC_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CMP_DEFAULT (_CSEN_IFC_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CONV (0x1UL << 1) /**< Clear CONV Interrupt Flag */ +#define _CSEN_IFC_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IFC_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IFC_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CONV_DEFAULT (_CSEN_IFC_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_EOS (0x1UL << 2) /**< Clear EOS Interrupt Flag */ +#define _CSEN_IFC_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IFC_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IFC_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_EOS_DEFAULT (_CSEN_IFC_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_DMAOF (0x1UL << 3) /**< Clear DMAOF Interrupt Flag */ +#define _CSEN_IFC_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IFC_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IFC_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_DMAOF_DEFAULT (_CSEN_IFC_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_APORTCONFLICT (0x1UL << 4) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _CSEN_IFC_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IFC_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_APORTCONFLICT_DEFAULT (_CSEN_IFC_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFC */ + +/* Bit fields for CSEN IEN */ +#define _CSEN_IEN_RESETVALUE 0x00000000UL /**< Default value for CSEN_IEN */ +#define _CSEN_IEN_MASK 0x0000001FUL /**< Mask for CSEN_IEN */ +#define CSEN_IEN_CMP (0x1UL << 0) /**< CMP Interrupt Enable */ +#define _CSEN_IEN_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IEN_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IEN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CMP_DEFAULT (_CSEN_IEN_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CONV (0x1UL << 1) /**< CONV Interrupt Enable */ +#define _CSEN_IEN_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IEN_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IEN_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CONV_DEFAULT (_CSEN_IEN_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_EOS (0x1UL << 2) /**< EOS Interrupt Enable */ +#define _CSEN_IEN_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IEN_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IEN_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_EOS_DEFAULT (_CSEN_IEN_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_DMAOF (0x1UL << 3) /**< DMAOF Interrupt Enable */ +#define _CSEN_IEN_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IEN_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IEN_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_DMAOF_DEFAULT (_CSEN_IEN_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_APORTCONFLICT (0x1UL << 4) /**< APORTCONFLICT Interrupt Enable */ +#define _CSEN_IEN_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IEN_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_APORTCONFLICT_DEFAULT (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */ + +/** @} End of group EFR32MG12P_CSEN */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_devinfo.h new file mode 100644 index 00000000000..dd7222602f1 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_devinfo.h @@ -0,0 +1,1298 @@ +/**************************************************************************//** + * @file efr32mg12p_devinfo.h + * @brief EFR32MG12P_DEVINFO register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_DEVINFO + * @{ + *****************************************************************************/ + +typedef struct +{ + __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */ + uint32_t RESERVED0[7]; /**< Reserved for future use **/ + __IM uint32_t EXTINFO; /**< External Component description */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */ + __IM uint32_t EUI48H; /**< OUI */ + __IM uint32_t CUSTOMINFO; /**< Custom information */ + __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */ + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */ + __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */ + __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */ + __IM uint32_t PART; /**< Part description */ + __IM uint32_t DEVINFOREV; /**< Device information page revision */ + __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */ + uint32_t RESERVED3[2]; /**< Reserved for future use **/ + __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */ + __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */ + __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */ + __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */ + uint32_t RESERVED4[4]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */ + uint32_t RESERVED5[2]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */ + uint32_t RESERVED6[2]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */ + __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */ + __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */ + __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */ + __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */ + uint32_t RESERVED8[11]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */ + uint32_t RESERVED9[2]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */ + uint32_t RESERVED10[2]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */ + __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */ + __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */ + uint32_t RESERVED11[1]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */ + __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */ + __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */ + uint32_t RESERVED12[11]; /**< Reserved for future use **/ + __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */ + __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */ + __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */ + uint32_t RESERVED13[3]; /**< Reserved for future use **/ + __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */ + __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */ + uint32_t RESERVED14[2]; /**< Reserved for future use **/ + __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */ + __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */ + __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */ + __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */ + __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */ + __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */ + __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */ + __IM uint32_t VDAC0MAINCAL; /**< VDAC0 Cals for Main Path */ + __IM uint32_t VDAC0ALTCAL; /**< VDAC0 Cals for Alternate Path */ + __IM uint32_t VDAC0CH1CAL; /**< VDAC0 CH1 Error Cal */ + __IM uint32_t OPA0CAL0; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA0CAL1; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA0CAL2; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA0CAL3; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA1CAL0; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA1CAL1; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA1CAL2; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA1CAL3; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA2CAL0; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA2CAL1; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA2CAL2; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA2CAL3; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t CSENGAINCAL; /**< Cap Sense Gain Adjustment */ + uint32_t RESERVED15[3]; /**< Reserved for future use **/ + __IM uint32_t OPA0CAL4; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA0CAL5; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA0CAL6; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA0CAL7; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t OPA1CAL4; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA1CAL5; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA1CAL6; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA1CAL7; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t OPA2CAL4; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA2CAL5; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA2CAL6; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA2CAL7; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ +} DEVINFO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_DEVINFO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for DEVINFO CAL */ +#define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */ +#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */ +#define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */ +#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */ +#define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */ +#define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */ +#define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */ +#define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */ +#define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */ +#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_BGA (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */ +#define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */ +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */ +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */ + +/* Bit fields for DEVINFO UNIQUEL */ +#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */ +#define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */ + +/* Bit fields for DEVINFO UNIQUEH */ +#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */ +#define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */ +#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */ +#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */ +#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL /**< Mode EFR32MG2P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16) /**< Shifted mode EFR32MG2P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */ +#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */ +#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */ + +/* Bit fields for DEVINFO DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */ + +/* Bit fields for DEVINFO ADC0CAL0 */ +#define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */ +#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */ +#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */ +#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */ +#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */ + +/* Bit fields for DEVINFO ADC0CAL1 */ +#define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */ +#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */ +#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */ +#define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */ +#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */ +#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */ + +/* Bit fields for DEVINFO ADC0CAL2 */ +#define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */ +#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */ + +/* Bit fields for DEVINFO ADC0CAL3 */ +#define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */ +#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */ +#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */ + +/* Bit fields for DEVINFO HFRCOCAL0 */ +#define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */ +#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL3 */ +#define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */ +#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL6 */ +#define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */ +#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL7 */ +#define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */ +#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL8 */ +#define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */ +#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL10 */ +#define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */ +#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL11 */ +#define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */ +#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL12 */ +#define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */ +#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL0 */ +#define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */ +#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL3 */ +#define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */ +#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL6 */ +#define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */ +#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL7 */ +#define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */ +#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL8 */ +#define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */ +#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL10 */ +#define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */ +#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL11 */ +#define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */ +#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL12 */ +#define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */ +#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO VMONCAL0 */ +#define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */ + +/* Bit fields for DEVINFO VMONCAL1 */ +#define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */ + +/* Bit fields for DEVINFO VMONCAL2 */ +#define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */ + +/* Bit fields for DEVINFO IDAC0CAL0 */ +#define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */ + +/* Bit fields for DEVINFO IDAC0CAL1 */ +#define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */ + +/* Bit fields for DEVINFO DCDCLNVCTRL0 */ +#define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL0 */ +#define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL1 */ +#define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL2 */ +#define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL3 */ +#define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */ + +/* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */ + +/* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */ + +/* Bit fields for DEVINFO VDAC0MAINCAL */ +#define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0MAINCAL */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12 /**< Shift value for GAINERRTRIM1V25 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18 /**< Shift value for GAINERRTRIM2V5 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPIN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPIN */ + +/* Bit fields for DEVINFO VDAC0ALTCAL */ +#define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0ALTCAL */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12 /**< Shift value for GAINERRTRIM1V25ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18 /**< Shift value for GAINERRTRIM2V5ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPINALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPINALT */ + +/* Bit fields for DEVINFO VDAC0CH1CAL */ +#define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL /**< Mask for DEVINFO_VDAC0CH1CAL */ +#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for OFFSETTRIM */ +#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for OFFSETTRIM */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4 /**< Shift value for GAINERRTRIMCH1A */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL /**< Bit mask for GAINERRTRIMCH1A */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8 /**< Shift value for GAINERRTRIMCH1B */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL /**< Bit mask for GAINERRTRIMCH1B */ + +/* Bit fields for DEVINFO OPA0CAL0 */ +#define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL0 */ +#define _DEVINFO_OPA0CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL1 */ +#define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL1 */ +#define _DEVINFO_OPA0CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL2 */ +#define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL2 */ +#define _DEVINFO_OPA0CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL3 */ +#define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL3 */ +#define _DEVINFO_OPA0CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL0 */ +#define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL0 */ +#define _DEVINFO_OPA1CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL1 */ +#define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL1 */ +#define _DEVINFO_OPA1CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL2 */ +#define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL2 */ +#define _DEVINFO_OPA1CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL3 */ +#define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL3 */ +#define _DEVINFO_OPA1CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL0 */ +#define _DEVINFO_OPA2CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL0 */ +#define _DEVINFO_OPA2CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL1 */ +#define _DEVINFO_OPA2CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL1 */ +#define _DEVINFO_OPA2CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL2 */ +#define _DEVINFO_OPA2CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL2 */ +#define _DEVINFO_OPA2CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL3 */ +#define _DEVINFO_OPA2CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL3 */ +#define _DEVINFO_OPA2CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO CSENGAINCAL */ +#define _DEVINFO_CSENGAINCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_CSENGAINCAL */ +#define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT 0 /**< Shift value for GAINCAL */ +#define _DEVINFO_CSENGAINCAL_GAINCAL_MASK 0xFFUL /**< Bit mask for GAINCAL */ + +/* Bit fields for DEVINFO OPA0CAL4 */ +#define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL4 */ +#define _DEVINFO_OPA0CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL5 */ +#define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL5 */ +#define _DEVINFO_OPA0CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL6 */ +#define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL6 */ +#define _DEVINFO_OPA0CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL7 */ +#define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL7 */ +#define _DEVINFO_OPA0CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL4 */ +#define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL4 */ +#define _DEVINFO_OPA1CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL5 */ +#define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL5 */ +#define _DEVINFO_OPA1CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL6 */ +#define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL6 */ +#define _DEVINFO_OPA1CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL7 */ +#define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL7 */ +#define _DEVINFO_OPA1CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL4 */ +#define _DEVINFO_OPA2CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL4 */ +#define _DEVINFO_OPA2CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL5 */ +#define _DEVINFO_OPA2CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL5 */ +#define _DEVINFO_OPA2CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL6 */ +#define _DEVINFO_OPA2CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL6 */ +#define _DEVINFO_OPA2CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL7 */ +#define _DEVINFO_OPA2CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL7 */ +#define _DEVINFO_OPA2CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/** @} End of group EFR32MG12P_DEVINFO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dma_descriptor.h new file mode 100644 index 00000000000..753467817f5 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dma_descriptor.h @@ -0,0 +1,52 @@ +/**************************************************************************//** + * @file efr32mg12p_dma_descriptor.h + * @brief EFR32MG12P_DMA_DESCRIPTOR register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_DMA_DESCRIPTOR + * @{ + *****************************************************************************/ +typedef struct +{ + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dmareq.h new file mode 100644 index 00000000000..aaab226a7f2 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dmareq.h @@ -0,0 +1,110 @@ +/**************************************************************************//** + * @file efr32mg12p_dmareq.h + * @brief EFR32MG12P_DMAREQ register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P_DMAREQ_BitFields + * @{ + *****************************************************************************/ +#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */ +#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */ +#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */ +#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */ +#define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */ +#define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */ +#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */ +#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */ +#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */ +#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */ +#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */ +#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */ +#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */ +#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */ +#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */ +#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */ +#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */ +#define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */ +#define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */ +#define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */ +#define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */ +#define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */ +#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */ +#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */ +#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */ +#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */ +#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */ +#define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */ +#define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */ +#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */ +#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */ +#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */ +#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */ +#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */ +#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */ +#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */ +#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */ +#define DMAREQ_TIMER1_CC3 ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */ +#define DMAREQ_WTIMER0_UFOF ((26 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */ +#define DMAREQ_WTIMER0_CC0 ((26 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */ +#define DMAREQ_WTIMER0_CC1 ((26 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */ +#define DMAREQ_WTIMER0_CC2 ((26 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */ +#define DMAREQ_WTIMER1_UFOF ((27 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */ +#define DMAREQ_WTIMER1_CC0 ((27 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */ +#define DMAREQ_WTIMER1_CC1 ((27 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */ +#define DMAREQ_WTIMER1_CC2 ((27 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */ +#define DMAREQ_WTIMER1_CC3 ((27 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */ +#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */ +#define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */ +#define DMAREQ_CRYPTO_DATA0WR DMAREQ_CRYPTO0_DATA0WR /**< Alias for DMAREQ_CRYPTO0_DATA0WR */ +#define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */ +#define DMAREQ_CRYPTO_DATA0XWR DMAREQ_CRYPTO0_DATA0XWR /**< Alias for DMAREQ_CRYPTO0_DATA0XWR */ +#define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */ +#define DMAREQ_CRYPTO_DATA0RD DMAREQ_CRYPTO0_DATA0RD /**< Alias for DMAREQ_CRYPTO0_DATA0RD */ +#define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */ +#define DMAREQ_CRYPTO_DATA1WR DMAREQ_CRYPTO0_DATA1WR /**< Alias for DMAREQ_CRYPTO0_DATA1WR */ +#define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */ +#define DMAREQ_CRYPTO_DATA1RD DMAREQ_CRYPTO0_DATA1RD /**< Alias for DMAREQ_CRYPTO0_DATA1RD */ +#define DMAREQ_CSEN_DATA ((50 << 16) + 0) /**< DMA channel select for CSEN_DATA */ +#define DMAREQ_CSEN_BSLN ((50 << 16) + 1) /**< DMA channel select for CSEN_BSLN */ +#define DMAREQ_LESENSE_BUFDATAV ((51 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */ +#define DMAREQ_CRYPTO1_DATA0WR ((52 << 16) + 0) /**< DMA channel select for CRYPTO1_DATA0WR */ +#define DMAREQ_CRYPTO1_DATA0XWR ((52 << 16) + 1) /**< DMA channel select for CRYPTO1_DATA0XWR */ +#define DMAREQ_CRYPTO1_DATA0RD ((52 << 16) + 2) /**< DMA channel select for CRYPTO1_DATA0RD */ +#define DMAREQ_CRYPTO1_DATA1WR ((52 << 16) + 3) /**< DMA channel select for CRYPTO1_DATA1WR */ +#define DMAREQ_CRYPTO1_DATA1RD ((52 << 16) + 4) /**< DMA channel select for CRYPTO1_DATA1RD */ + +/** @} End of group EFR32MG12P_DMAREQ */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_emu.h new file mode 100644 index 00000000000..5762f8777c2 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_emu.h @@ -0,0 +1,1437 @@ +/**************************************************************************//** + * @file efr32mg12p_emu.h + * @brief EFR32MG12P_EMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_EMU + * @{ + * @brief EFR32MG12P_EMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */ + __IM uint32_t TEMP; /**< Value of last temperature measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + __IOM uint32_t PWRCFG; /**< Power Configuration Register */ + __IOM uint32_t PWRCTRL; /**< Power Control Register. */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED4[1]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED5[5]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + + uint32_t RESERVED6[5]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + + uint32_t RESERVED7[12]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration bits for low power mode to be applied during EM01, this field is only relevant if LP mode is used in EM01. */ + + uint32_t RESERVED8[4]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears corresponding bits in EM23PERNORETAINSTATUS unlocking access to peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status indicating if peripherals were powered down in EM23, subsequently locking access to it. */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When set corresponding peripherals may get powered down in EM23 */ +} EMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_EMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically configures Flash, Ram and Frequency to wakeup from EM2 or EM3 at low voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x0417011FUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */ +#define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */ +#define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */ +#define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE31FC0FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */ +#define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */ +#define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE31FC0FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE31FC0FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE31FC0FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCFG */ +#define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */ +#define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_UNCONFIGURED 0x00000000UL /**< Mode UNCONFIGURED for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_UNCONFIGURED (_EMU_PWRCFG_PWRCFG_UNCONFIGURED << 0) /**< Shifted mode UNCONFIGURED for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00001420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This field selects the input for the regulator. */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_DVDDBODDIS (0x1UL << 12) /**< DVDD BOD Disable */ +#define _EMU_PWRCTRL_DVDDBODDIS_SHIFT 12 /**< Shift value for EMU_DVDDBODDIS */ +#define _EMU_PWRCTRL_DVDDBODDIS_MASK 0x1000UL /**< Bit mask for EMU_DVDDBODDIS */ +#define _EMU_PWRCTRL_DVDDBODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_DVDDBODDIS_DEFAULT (_EMU_PWRCTRL_DVDDBODDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP mode hysteresis in the state machine control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator threshold on the high side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC into CCM mode immediately, based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP mode duty cycling enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x00000003UL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0x3UL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 0x00000002UL /**< Mode BLK1 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 0x00000003UL /**< Mode BLK0TO1 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 << 0) /**< Shifted mode BLK1 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 << 0) /**< Shifted mode BLK0TO1 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x00000001UL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0x1UL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK 0x00000001UL /**< Mode BLK for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK << 0) /**< Shifted mode BLK for EMU_RAM2CTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears status bit of ACMP0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears status bit of ACMP1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears status bit of PCNT0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears status bit of PCNT1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears status bit of PCNT2 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears status bit of I2C0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears status bit of I2C1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears status bit of DAC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears status bit of IDAC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears status bit of ADC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears status bit of LETIMER0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears status bit of WDOG0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears status bit of WDOG1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears status bit of LESENSE0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears status bit of CSEN and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears status bit of LEUART0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates if ACMP0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates if ACMP1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates if PCNT0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates if PCNT1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates if PCNT2 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates if I2C0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates if I2C1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates if DAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates if IDAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates if ADC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates if LETIMER0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates if WDOG0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates if WDOG1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates if LESENSE0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates if CSEN powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates if LEUART0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow power down of ACMP0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow power down of ACMP1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow power down of PCNT0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow power down of PCNT1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow power down of PCNT2 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow power down of I2C0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow power down of I2C1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_DAC0DIS (0x1UL << 7) /**< Allow power down of DAC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT 7 /**< Shift value for EMU_DAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK 0x80UL /**< Bit mask for EMU_DAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow power down of IDAC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow power down of ADC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow power down of LETIMER0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow power down of WDOG0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow power down of WDOG1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow power down of LESENSE0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow power down of CSEN during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow power down of LEUART0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} End of group EFR32MG12P_EMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_etm.h new file mode 100644 index 00000000000..0f4b66e07bb --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_etm.h @@ -0,0 +1,781 @@ +/**************************************************************************//** + * @file efr32mg12p_etm.h + * @brief EFR32MG12P_ETM register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_ETM + * @{ + * @brief EFR32MG12P_ETM Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t ETMCR; /**< Main Control Register */ + __IM uint32_t ETMCCR; /**< Configuration Code Register */ + __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMSR; /**< ETM Status Register */ + __IM uint32_t ETMSCR; /**< ETM System Configuration Register */ + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */ + __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */ + uint32_t RESERVED3[68]; /**< Reserved for future use **/ + __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */ + uint32_t RESERVED4[39]; /**< Reserved for future use **/ + __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */ + __IM uint32_t ETMIDR; /**< ID Register */ + __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */ + uint32_t RESERVED5[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */ + uint32_t RESERVED6[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */ + uint32_t RESERVED8[1]; /**< Reserved for future use **/ + __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */ + uint32_t RESERVED9[66]; /**< Reserved for future use **/ + __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */ + uint32_t RESERVED10[754]; /**< Reserved for future use **/ + __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */ + uint32_t RESERVED11[1]; /**< Reserved for future use **/ + __IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */ + uint32_t RESERVED12[1]; /**< Reserved for future use **/ + __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */ + uint32_t RESERVED13[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */ + uint32_t RESERVED14[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */ + uint32_t RESERVED15[39]; /**< Reserved for future use **/ + __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */ + __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */ + uint32_t RESERVED16[2]; /**< Reserved for future use **/ + __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */ + __IM uint32_t ETMLSR; /**< Lock Status Register */ + __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */ + uint32_t RESERVED17[4]; /**< Reserved for future use **/ + __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */ + __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */ + __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */ + __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */ + __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */ + __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */ + __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */ + __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */ + __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */ + __IM uint32_t ETMCIDR0; /**< Component ID0 Register */ + __IM uint32_t ETMCIDR1; /**< Component ID1 Register */ + __IM uint32_t ETMCIDR2; /**< Component ID2 Register */ + __IM uint32_t ETMCIDR3; /**< Component ID3 Register */ +} ETM_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_ETM_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ETM ETMCR */ +#define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */ +#define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */ +#define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */ +#define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */ +#define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */ +#define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */ +#define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */ +#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */ +#define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */ +#define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */ +#define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */ +#define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */ +#define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */ + +/* Bit fields for ETM ETMCCR */ +#define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */ +#define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */ +#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */ +#define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */ +#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */ +#define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */ +#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */ +#define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */ + +/* Bit fields for ETM ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ + +/* Bit fields for ETM ETMSR */ +#define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */ +#define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */ +#define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */ +#define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */ +#define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */ +#define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */ +#define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */ + +/* Bit fields for ETM ETMSCR */ +#define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */ +#define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */ +#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */ +#define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */ +#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */ +#define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */ +#define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */ +#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */ + +/* Bit fields for ETM ETMTEEVR */ +#define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ + +/* Bit fields for ETM ETMTECR1 */ +#define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */ +#define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */ +#define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */ + +/* Bit fields for ETM ETMFFLR */ +#define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */ +#define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */ +#define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */ +#define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */ + +/* Bit fields for ETM ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */ +#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */ + +/* Bit fields for ETM ETMSYNCFR */ +#define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */ +#define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */ +#define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */ +#define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */ + +/* Bit fields for ETM ETMIDR */ +#define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */ +#define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */ +#define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */ +#define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */ +#define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */ +#define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */ +#define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */ +#define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */ +#define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */ + +/* Bit fields for ETM ETMCCER */ +#define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */ +#define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */ +#define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */ +#define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */ +#define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */ +#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */ +#define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */ +#define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */ +#define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */ +#define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */ +#define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */ +#define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */ +#define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */ + +/* Bit fields for ETM ETMTESSEICR */ +#define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ + +/* Bit fields for ETM ETMTSEVR */ +#define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ + +/* Bit fields for ETM ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */ +#define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */ + +/* Bit fields for ETM ETMIDR2 */ +#define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */ +#define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */ +#define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */ + +/* Bit fields for ETM ETMPDSR */ +#define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */ +#define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */ +#define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */ +#define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */ +#define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */ + +/* Bit fields for ETM ETMISCIN */ +#define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */ +#define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */ +#define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */ +#define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ + +/* Bit fields for ETM ITTRIGOUT */ +#define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */ +#define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */ +#define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */ +#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */ + +/* Bit fields for ETM ETMITATBCTR2 */ +#define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */ +#define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */ +#define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */ +#define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */ +#define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */ + +/* Bit fields for ETM ETMITATBCTR0 */ +#define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */ +#define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */ +#define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */ +#define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */ +#define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */ + +/* Bit fields for ETM ETMITCTRL */ +#define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */ +#define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */ +#define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */ +#define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */ +#define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */ + +/* Bit fields for ETM ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */ +#define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */ + +/* Bit fields for ETM ETMCLAIMCLR */ +#define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */ +#define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */ +#define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */ +#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */ +#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */ + +/* Bit fields for ETM ETMLAR */ +#define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */ +#define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */ +#define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */ +#define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */ +#define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */ +#define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */ +#define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */ + +/* Bit fields for ETM ETMLSR */ +#define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */ +#define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */ +#define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */ +#define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */ + +/* Bit fields for ETM ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ + +/* Bit fields for ETM ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ + +/* Bit fields for ETM ETMPIDR4 */ +#define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ + +/* Bit fields for ETM ETMPIDR5 */ +#define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */ +#define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */ + +/* Bit fields for ETM ETMPIDR6 */ +#define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */ +#define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */ + +/* Bit fields for ETM ETMPIDR7 */ +#define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */ +#define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */ + +/* Bit fields for ETM ETMPIDR0 */ +#define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */ +#define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */ +#define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */ +#define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */ + +/* Bit fields for ETM ETMPIDR1 */ +#define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ + +/* Bit fields for ETM ETMPIDR2 */ +#define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */ +#define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */ +#define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */ +#define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ + +/* Bit fields for ETM ETMPIDR3 */ +#define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ + +/* Bit fields for ETM ETMCIDR0 */ +#define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */ +#define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */ +#define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */ +#define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */ + +/* Bit fields for ETM ETMCIDR1 */ +#define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */ +#define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */ +#define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */ +#define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */ + +/* Bit fields for ETM ETMCIDR2 */ +#define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */ +#define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */ +#define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */ +#define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */ + +/* Bit fields for ETM ETMCIDR3 */ +#define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */ +#define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */ +#define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */ +#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */ + +/** @} End of group EFR32MG12P_ETM */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_fpueh.h new file mode 100644 index 00000000000..0ac910613a7 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_fpueh.h @@ -0,0 +1,192 @@ +/**************************************************************************//** + * @file efr32mg12p_fpueh.h + * @brief EFR32MG12P_FPUEH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_FPUEH + * @{ + * @brief EFR32MG12P_FPUEH Register Declaration + *****************************************************************************/ +typedef struct +{ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} FPUEH_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_FPUEH_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for FPUEH IF */ +#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */ +#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */ +#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */ +#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */ +#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */ +#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */ +#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */ +#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */ +#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */ + +/* Bit fields for FPUEH IFS */ +#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */ +#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */ +#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */ +#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */ +#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */ +#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */ +#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */ +#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */ +#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */ + +/* Bit fields for FPUEH IFC */ +#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */ +#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */ +#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */ +#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */ +#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */ +#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */ +#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */ +#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */ +#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */ + +/* Bit fields for FPUEH IEN */ +#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */ +#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */ +#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */ +#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */ +#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */ +#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */ +#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */ +#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */ +#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */ + +/** @} End of group EFR32MG12P_FPUEH */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpcrc.h new file mode 100644 index 00000000000..19a26bc3069 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpcrc.h @@ -0,0 +1,185 @@ +/**************************************************************************//** + * @file efr32mg12p_gpcrc.h + * @brief EFR32MG12P_GPCRC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_GPCRC + * @{ + * @brief EFR32MG12P_GPCRC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_GPCRC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */ +#define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */ +#define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} End of group EFR32MG12P_GPCRC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio.h new file mode 100644 index 00000000000..fcc15c2c68a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio.h @@ -0,0 +1,1538 @@ +/**************************************************************************//** + * @file efr32mg12p_gpio.h + * @brief EFR32MG12P_GPIO register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_GPIO + * @{ + * @brief EFR32MG12P_GPIO Register Declaration + *****************************************************************************/ +typedef struct +{ + GPIO_P_TypeDef P[12]; /**< Port configuration bits */ + + uint32_t RESERVED0[112]; /**< Reserved for future use **/ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */ + __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High Register */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */ + __IOM uint32_t EXTILEVEL; /**< External Interrupt Level Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wake up Enable Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register 1 */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t INSENSE; /**< Input Sense Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ +} GPIO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_GPIO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for GPIO P_CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00500050UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10711071UL /**< Mask for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive strength for port */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for GPIO_DRIVESTRENGTH */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_MASK 0x1UL /**< Bit mask for GPIO_DRIVESTRENGTH */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_STRONG (_GPIO_P_CTRL_DRIVESTRENGTH_STRONG << 0) /**< Shifted mode STRONG for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_WEAK (_GPIO_P_CTRL_DRIVESTRENGTH_WEAK << 0) /**< Shifted mode WEAK for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate drive strength for port */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT 16 /**< Shift value for GPIO_DRIVESTRENGTHALT */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK 0x10000UL /**< Bit mask for GPIO_DRIVESTRENGTHALT */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG (_GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG << 16) /**< Shifted mode STRONG for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK (_GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK << 16) /**< Shifted mode WEAK for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data In Disable */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO P_MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ + +/* Bit fields for GPIO P_MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */ +#define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */ +#define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULLALT (_GPIO_P_MODEH_MODE8_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALT (_GPIO_P_MODEH_MODE8_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */ +#define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */ +#define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULLALT (_GPIO_P_MODEH_MODE9_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALT (_GPIO_P_MODEH_MODE9_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */ +#define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */ +#define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULLALT (_GPIO_P_MODEH_MODE10_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALT (_GPIO_P_MODEH_MODE10_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */ +#define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */ +#define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULLALT (_GPIO_P_MODEH_MODE11_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALT (_GPIO_P_MODEH_MODE11_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */ +#define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */ +#define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULLALT (_GPIO_P_MODEH_MODE12_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALT (_GPIO_P_MODEH_MODE12_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */ +#define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */ +#define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULLALT (_GPIO_P_MODEH_MODE13_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALT (_GPIO_P_MODEH_MODE13_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */ +#define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */ +#define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULLALT (_GPIO_P_MODEH_MODE14_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALT (_GPIO_P_MODEH_MODE14_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */ +#define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */ +#define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULLALT (_GPIO_P_MODEH_MODE15_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALT (_GPIO_P_MODEH_MODE15_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ + +/* Bit fields for GPIO P_DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */ +#define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */ + +/* Bit fields for GPIO P_DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ + +/* Bit fields for GPIO P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */ +#define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */ + +/* Bit fields for GPIO P_OVTDIS */ +#define _GPIO_P_OVTDIS_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_OVTDIS */ +#define _GPIO_P_OVTDIS_MASK 0x0000FFFFUL /**< Mask for GPIO_P_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_SHIFT 0 /**< Shift value for GPIO_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_MASK 0xFFFFUL /**< Bit mask for GPIO_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_OVTDIS */ +#define GPIO_P_OVTDIS_OVTDIS_DEFAULT (_GPIO_P_OVTDIS_OVTDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_OVTDIS */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTI (_GPIO_EXTIPSELL_EXTIPSEL0_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL0_PORTJ << 0) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTK (_GPIO_EXTIPSELL_EXTIPSEL0_PORTK << 0) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTI (_GPIO_EXTIPSELL_EXTIPSEL1_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL1_PORTJ << 4) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTK (_GPIO_EXTIPSELL_EXTIPSEL1_PORTK << 4) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTI (_GPIO_EXTIPSELL_EXTIPSEL2_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL2_PORTJ << 8) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTK (_GPIO_EXTIPSELL_EXTIPSEL2_PORTK << 8) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTI (_GPIO_EXTIPSELL_EXTIPSEL3_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL3_PORTJ << 12) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTK (_GPIO_EXTIPSELL_EXTIPSEL3_PORTK << 12) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTI (_GPIO_EXTIPSELL_EXTIPSEL4_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL4_PORTJ << 16) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTK (_GPIO_EXTIPSELL_EXTIPSEL4_PORTK << 16) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTI (_GPIO_EXTIPSELL_EXTIPSEL5_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL5_PORTJ << 20) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTK (_GPIO_EXTIPSELL_EXTIPSEL5_PORTK << 20) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTI (_GPIO_EXTIPSELL_EXTIPSEL6_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL6_PORTJ << 24) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTK (_GPIO_EXTIPSELL_EXTIPSEL6_PORTK << 24) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTI (_GPIO_EXTIPSELL_EXTIPSEL7_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL7_PORTJ << 28) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTK (_GPIO_EXTIPSELL_EXTIPSEL7_PORTK << 28) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL8 */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTI (_GPIO_EXTIPSELH_EXTIPSEL8_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL8_PORTJ << 0) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTK (_GPIO_EXTIPSELH_EXTIPSEL8_PORTK << 0) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL9 */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTI (_GPIO_EXTIPSELH_EXTIPSEL9_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL9_PORTJ << 4) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTK (_GPIO_EXTIPSELH_EXTIPSEL9_PORTK << 4) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL10 */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTI (_GPIO_EXTIPSELH_EXTIPSEL10_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL10_PORTJ << 8) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTK (_GPIO_EXTIPSELH_EXTIPSEL10_PORTK << 8) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL11 */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTI (_GPIO_EXTIPSELH_EXTIPSEL11_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL11_PORTJ << 12) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTK (_GPIO_EXTIPSELH_EXTIPSEL11_PORTK << 12) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL12 */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTI (_GPIO_EXTIPSELH_EXTIPSEL12_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL12_PORTJ << 16) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTK (_GPIO_EXTIPSELH_EXTIPSEL12_PORTK << 16) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL13 */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTI (_GPIO_EXTIPSELH_EXTIPSEL13_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL13_PORTJ << 20) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTK (_GPIO_EXTIPSELH_EXTIPSEL13_PORTK << 20) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL14 */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTI (_GPIO_EXTIPSELH_EXTIPSEL14_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL14_PORTJ << 24) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTK (_GPIO_EXTIPSELH_EXTIPSEL14_PORTK << 24) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL15 */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL15 */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTI (_GPIO_EXTIPSELH_EXTIPSEL15_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL15_PORTJ << 28) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTK (_GPIO_EXTIPSELH_EXTIPSEL15_PORTK << 28) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 << 16) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 << 16) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 << 16) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 << 16) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 << 20) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 << 20) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 << 20) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 << 20) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 << 24) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 << 24) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 << 24) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 << 24) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 << 28) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 << 28) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 << 28) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 << 28) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL8 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL8 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL9 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL9 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL10 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL10 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL11 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL11 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL12 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL12 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 << 16) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 << 16) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 << 16) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 << 16) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL13 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL13 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 << 20) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 << 20) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 << 20) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 << 20) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL14 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL14 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 << 24) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 << 24) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 << 24) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 << 24) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL15 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL15 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 << 28) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 << 28) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 << 28) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 << 28) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO EXTILEVEL */ +#define _GPIO_EXTILEVEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTILEVEL */ +#define _GPIO_EXTILEVEL_MASK 0x13130000UL /**< Mask for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU0 (0x1UL << 16) /**< EM4 Wake Up Level for EM4WU0 Pin */ +#define _GPIO_EXTILEVEL_EM4WU0_SHIFT 16 /**< Shift value for GPIO_EM4WU0 */ +#define _GPIO_EXTILEVEL_EM4WU0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WU0 */ +#define _GPIO_EXTILEVEL_EM4WU0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU0_DEFAULT (_GPIO_EXTILEVEL_EM4WU0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU1 (0x1UL << 17) /**< EM4 Wake Up Level for EM4WU1 Pin */ +#define _GPIO_EXTILEVEL_EM4WU1_SHIFT 17 /**< Shift value for GPIO_EM4WU1 */ +#define _GPIO_EXTILEVEL_EM4WU1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WU1 */ +#define _GPIO_EXTILEVEL_EM4WU1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU1_DEFAULT (_GPIO_EXTILEVEL_EM4WU1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU4 (0x1UL << 20) /**< EM4 Wake Up Level for EM4WU4 Pin */ +#define _GPIO_EXTILEVEL_EM4WU4_SHIFT 20 /**< Shift value for GPIO_EM4WU4 */ +#define _GPIO_EXTILEVEL_EM4WU4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WU4 */ +#define _GPIO_EXTILEVEL_EM4WU4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU4_DEFAULT (_GPIO_EXTILEVEL_EM4WU4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU8 (0x1UL << 24) /**< EM4 Wake Up Level for EM4WU8 Pin */ +#define _GPIO_EXTILEVEL_EM4WU8_SHIFT 24 /**< Shift value for GPIO_EM4WU8 */ +#define _GPIO_EXTILEVEL_EM4WU8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WU8 */ +#define _GPIO_EXTILEVEL_EM4WU8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU8_DEFAULT (_GPIO_EXTILEVEL_EM4WU8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU9 (0x1UL << 25) /**< EM4 Wake Up Level for EM4WU9 Pin */ +#define _GPIO_EXTILEVEL_EM4WU9_SHIFT 25 /**< Shift value for GPIO_EM4WU9 */ +#define _GPIO_EXTILEVEL_EM4WU9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WU9 */ +#define _GPIO_EXTILEVEL_EM4WU9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU9_DEFAULT (_GPIO_EXTILEVEL_EM4WU9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU12 (0x1UL << 28) /**< EM4 Wake Up Level for EM4WU12 Pin */ +#define _GPIO_EXTILEVEL_EM4WU12_SHIFT 28 /**< Shift value for GPIO_EM4WU12 */ +#define _GPIO_EXTILEVEL_EM4WU12_MASK 0x10000000UL /**< Bit mask for GPIO_EM4WU12 */ +#define _GPIO_EXTILEVEL_EM4WU12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU12_DEFAULT (_GPIO_EXTILEVEL_EM4WU12_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IF */ +#define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IFS */ +#define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */ +#define _GPIO_IFS_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFS */ +#define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ +#define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFS */ +#define _GPIO_IFS_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IFS_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IFS_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ +#define GPIO_IFS_EM4WU_DEFAULT (_GPIO_IFS_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFS */ + +/* Bit fields for GPIO IFC */ +#define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */ +#define _GPIO_IFC_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFC */ +#define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ +#define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFC */ +#define _GPIO_IFC_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IFC_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IFC_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ +#define GPIO_IFC_EM4WU_DEFAULT (_GPIO_IFC_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFC */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IEN */ +#define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define _GPIO_IEN_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IEN_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WU_DEFAULT (_GPIO_IEN_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0xFFFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO ROUTEPEN */ +#define _GPIO_ROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_ROUTEPEN */ +#define _GPIO_ROUTEPEN_MASK 0x001F001FUL /**< Mask for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Serial Wire Clock and JTAG Test Clock Pin Enable */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Serial Wire Data and JTAG Test Mode Select Pin Enable */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_ROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_ROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_ROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDOPEN_DEFAULT (_GPIO_ROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_ROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_ROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_ROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDIPEN_DEFAULT (_GPIO_ROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWVPEN (0x1UL << 4) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_ROUTEPEN_SWVPEN_SHIFT 4 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_ROUTEPEN_SWVPEN_MASK 0x10UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_ROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWVPEN_DEFAULT (_GPIO_ROUTEPEN_SWVPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTCLKPEN (0x1UL << 16) /**< ETM Trace Clock Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_SHIFT 16 /**< Shift value for GPIO_ETMTCLKPEN */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_MASK 0x10000UL /**< Bit mask for GPIO_ETMTCLKPEN */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT (_GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD0PEN (0x1UL << 17) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_SHIFT 17 /**< Shift value for GPIO_ETMTD0PEN */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_MASK 0x20000UL /**< Bit mask for GPIO_ETMTD0PEN */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD1PEN (0x1UL << 18) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_SHIFT 18 /**< Shift value for GPIO_ETMTD1PEN */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_MASK 0x40000UL /**< Bit mask for GPIO_ETMTD1PEN */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD2PEN (0x1UL << 19) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_SHIFT 19 /**< Shift value for GPIO_ETMTD2PEN */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_MASK 0x80000UL /**< Bit mask for GPIO_ETMTD2PEN */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD3PEN (0x1UL << 20) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_SHIFT 20 /**< Shift value for GPIO_ETMTD3PEN */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_MASK 0x100000UL /**< Bit mask for GPIO_ETMTD3PEN */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ + +/* Bit fields for GPIO ROUTELOC0 */ +#define _GPIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_MASK 0x00000003UL /**< Mask for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_SHIFT 0 /**< Shift value for GPIO_SWVLOC */ +#define _GPIO_ROUTELOC0_SWVLOC_MASK 0x3UL /**< Bit mask for GPIO_SWVLOC */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC0 (_GPIO_ROUTELOC0_SWVLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_DEFAULT (_GPIO_ROUTELOC0_SWVLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC1 (_GPIO_ROUTELOC0_SWVLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC2 (_GPIO_ROUTELOC0_SWVLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC3 (_GPIO_ROUTELOC0_SWVLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC0 */ + +/* Bit fields for GPIO ROUTELOC1 */ +#define _GPIO_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_MASK 0x0C30C303UL /**< Mask for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_SHIFT 0 /**< Shift value for GPIO_ETMTCLKLOC */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_MASK 0x3UL /**< Bit mask for GPIO_ETMTCLKLOC */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT (_GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_SHIFT 8 /**< Shift value for GPIO_ETMTD0LOC */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_MASK 0x300UL /**< Bit mask for GPIO_ETMTD0LOC */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC0 << 8) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC1 << 8) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC2 << 8) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC3 << 8) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_SHIFT 14 /**< Shift value for GPIO_ETMTD1LOC */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_MASK 0xC000UL /**< Bit mask for GPIO_ETMTD1LOC */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC0 << 14) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC1 << 14) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC2 << 14) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC3 << 14) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_SHIFT 20 /**< Shift value for GPIO_ETMTD2LOC */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_MASK 0x300000UL /**< Bit mask for GPIO_ETMTD2LOC */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC0 << 20) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC1 << 20) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC2 << 20) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC3 << 20) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_SHIFT 26 /**< Shift value for GPIO_ETMTD3LOC */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_MASK 0xC000000UL /**< Bit mask for GPIO_ETMTD3LOC */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC0 << 26) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC1 << 26) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC2 << 26) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC3 << 26) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ + +/* Bit fields for GPIO INSENSE */ +#define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */ +#define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */ +#define GPIO_INSENSE_INT (0x1UL << 0) /**< Interrupt Sense Enable */ +#define _GPIO_INSENSE_INT_SHIFT 0 /**< Shift value for GPIO_INT */ +#define _GPIO_INSENSE_INT_MASK 0x1UL /**< Bit mask for GPIO_INT */ +#define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_EM4WU (0x1UL << 1) /**< EM4WU Interrupt Sense Enable */ +#define _GPIO_INSENSE_EM4WU_SHIFT 1 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_INSENSE_EM4WU_MASK 0x2UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_INSENSE_EM4WU_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_EM4WU_DEFAULT (_GPIO_INSENSE_EM4WU_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/** @} End of group EFR32MG12P_GPIO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio_p.h new file mode 100644 index 00000000000..cd06090dee4 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio_p.h @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file efr32mg12p_gpio_p.h + * @brief EFR32MG12P_GPIO_P register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief GPIO_P EFR32MG12P GPIO P + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Port Control Register */ + __IOM uint32_t MODEL; /**< Port Pin Mode Low Register */ + __IOM uint32_t MODEH; /**< Port Pin Mode High Register */ + __IOM uint32_t DOUT; /**< Port Data Out Register */ + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */ + __IM uint32_t DIN; /**< Port Data In Register */ + __IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t OVTDIS; /**< Over Voltage Disable for all modes */ + uint32_t RESERVED2[1]; /**< Reserved future */ +} GPIO_P_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_i2c.h new file mode 100644 index 00000000000..e333039b866 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_i2c.h @@ -0,0 +1,921 @@ +/**************************************************************************//** + * @file efr32mg12p_i2c.h + * @brief EFR32MG12P_I2C register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_I2C + * @{ + * @brief EFR32MG12P_I2C Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Slave Address Register */ + __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ +} I2C_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_I2C_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */ +#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IFS */ +#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */ +#define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */ +#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */ +#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */ +#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */ +#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */ +#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */ +#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */ +#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */ +#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */ +#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */ +#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */ +#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */ +#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */ +#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */ +#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */ +#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */ +#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */ +#define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */ +#define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */ + +/* Bit fields for I2C IFC */ +#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */ +#define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */ +#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */ +#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */ +#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */ +#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */ +#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */ +#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */ +#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */ +#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */ +#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */ +#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */ +#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */ +#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */ +#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */ +#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */ +#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */ +#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */ +#define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */ +#define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ + +/* Bit fields for I2C ROUTEPEN */ +#define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */ +#define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */ +#define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */ +#define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */ +#define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */ +#define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */ +#define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */ +#define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ + +/* Bit fields for I2C ROUTELOC0 */ +#define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */ +#define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */ +#define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */ +#define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */ +#define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ + +/** @} End of group EFR32MG12P_I2C */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_idac.h new file mode 100644 index 00000000000..981d726d987 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_idac.h @@ -0,0 +1,352 @@ +/**************************************************************************//** + * @file efr32mg12p_idac.h + * @brief EFR32MG12P_IDAC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_IDAC + * @{ + * @brief EFR32MG12P_IDAC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CURPROG; /**< Current Programming Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ +} IDAC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_IDAC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for IDAC CTRL */ +#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */ +#define _IDAC_CTRL_MASK 0x00FD7FFFUL /**< Mask for IDAC_CTRL */ +#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */ +#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */ +#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */ +#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */ +#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */ +#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */ +#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */ +#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */ +#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */ +#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */ +#define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */ +#define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */ +#define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */ +#define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */ +#define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */ +#define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */ +#define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */ +#define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */ +#define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */ +#define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */ +#define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */ +#define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */ +#define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */ +#define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */ +#define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */ +#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */ +#define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */ +#define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */ +#define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTEN (0x1UL << 18) /**< Output Enable */ +#define _IDAC_CTRL_MAINOUTEN_SHIFT 18 /**< Shift value for IDAC_MAINOUTEN */ +#define _IDAC_CTRL_MAINOUTEN_MASK 0x40000UL /**< Bit mask for IDAC_MAINOUTEN */ +#define _IDAC_CTRL_MAINOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTEN_DEFAULT (_IDAC_CTRL_MAINOUTEN_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTENPRS (0x1UL << 19) /**< PRS Controlled Main Pad Output Enable */ +#define _IDAC_CTRL_MAINOUTENPRS_SHIFT 19 /**< Shift value for IDAC_MAINOUTENPRS */ +#define _IDAC_CTRL_MAINOUTENPRS_MASK 0x80000UL /**< Bit mask for IDAC_MAINOUTENPRS */ +#define _IDAC_CTRL_MAINOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTENPRS_DEFAULT (_IDAC_CTRL_MAINOUTENPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */ +#define _IDAC_CTRL_PRSSEL_MASK 0xF00000UL /**< Bit mask for IDAC_PRSSEL */ +#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */ + +/* Bit fields for IDAC CURPROG */ +#define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */ +#define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */ +#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */ +#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */ +#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */ +#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */ +#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */ +#define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */ +#define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */ +#define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */ + +/* Bit fields for IDAC DUTYCONFIG */ +#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */ +#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */ +#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable. */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */ +#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */ + +/* Bit fields for IDAC STATUS */ +#define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */ +#define _IDAC_STATUS_MASK 0x00000003UL /**< Mask for IDAC_STATUS */ +#define IDAC_STATUS_CURSTABLE (0x1UL << 0) /**< IDAC Output Current Stable */ +#define _IDAC_STATUS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_STATUS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_STATUS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_CURSTABLE_DEFAULT (_IDAC_STATUS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */ +#define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */ + +/* Bit fields for IDAC IF */ +#define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */ +#define _IDAC_IF_MASK 0x00000003UL /**< Mask for IDAC_IF */ +#define IDAC_IF_CURSTABLE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ +#define _IDAC_IF_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IF_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IF_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ +#define IDAC_IF_CURSTABLE_DEFAULT (_IDAC_IF_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IF */ +#define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */ +#define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ +#define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */ + +/* Bit fields for IDAC IFS */ +#define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */ +#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */ +#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */ +#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */ +#define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */ + +/* Bit fields for IDAC IFC */ +#define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */ +#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */ +#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */ +#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */ + +/* Bit fields for IDAC IEN */ +#define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */ +#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */ +#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */ +#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */ +#define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */ + +/* Bit fields for IDAC APORTREQ */ +#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */ +#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the APORT bus connected to APORT1X is requested */ +#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */ +#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */ +#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */ +#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */ +#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */ +#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ + +/* Bit fields for IDAC APORTCONFLICT */ +#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */ +#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ + +/** @} End of group EFR32MG12P_IDAC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma.h new file mode 100644 index 00000000000..d8b0944cb28 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma.h @@ -0,0 +1,643 @@ +/**************************************************************************//** + * @file efr32mg12p_ldma.h + * @brief EFR32MG12P_LDMA register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_LDMA + * @{ + * @brief EFR32MG12P_LDMA Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */ + uint32_t RESERVED0[5]; /**< Reserved for future use **/ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + uint32_t RESERVED1[7]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable register */ + + uint32_t RESERVED2[4]; /**< Reserved registers */ + LDMA_CH_TypeDef CH[8]; /**< DMA Channel Registers */ +} LDMA_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_LDMA_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x0700FFFFUL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */ +#define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */ +#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */ +#define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */ +#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F073BUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0x38UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x700UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNC */ +#define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */ +#define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */ +#define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */ +#define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ +#define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IF_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IFS */ +#define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */ +#define _LDMA_IFS_MASK 0x800000FFUL /**< Mask for LDMA_IFS */ +#define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */ +#define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */ + +/* Bit fields for LDMA IFC */ +#define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */ +#define _LDMA_IFC_MASK 0x800000FFUL /**< Mask for LDMA_IFC */ +#define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */ +#define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_REQSEL */ +#define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV 0x00000000UL /**< Mode USART3RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF 0x00000000UL /**< Mode WTIMER1UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR /**< Alias for mode CRYPTO0DATA0WR */ +#define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR 0x00000000UL /**< Mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBL 0x00000001UL /**< Mode USART3TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 0x00000001UL /**< Mode WTIMER1CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR /**< Alias for mode CRYPTO0DATA0XWR */ +#define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR 0x00000001UL /**< Mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY 0x00000002UL /**< Mode USART3TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 0x00000002UL /**< Mode WTIMER1CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD /**< Alias for mode CRYPTO0DATA0RD */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD 0x00000002UL /**< Mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT 0x00000003UL /**< Mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 0x00000003UL /**< Mode WTIMER1CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR /**< Alias for mode CRYPTO0DATA1WR */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR 0x00000003UL /**< Mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT 0x00000004UL /**< Mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 0x00000004UL /**< Mode WTIMER1CC3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD /**< Alias for mode CRYPTO0DATA1RD */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD 0x00000004UL /**< Mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF << 0) /**< Shifted mode WTIMER1UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR << 0) /**< Shifted mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXBL (_LDMA_CH_REQSEL_SIGSEL_USART3TXBL << 0) /**< Shifted mode USART3TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR << 0) /**< Shifted mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY << 0) /**< Shifted mode USART3TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD << 0) /**< Shifted mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT << 0) /**< Shifted mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR << 0) /**< Shifted mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT << 0) /**< Shifted mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD << 0) /**< Shifted mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART3 0x0000000FUL /**< Mode USART3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x0000001AUL /**< Mode WTIMER0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER1 0x0000001BUL /**< Mode WTIMER1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 /**< Alias for mode CRYPTO0 */ +#define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x00000032UL /**< Mode CSEN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x00000033UL /**< Mode LESENSE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 0x00000034UL /**< Mode CRYPTO1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART3 (_LDMA_CH_REQSEL_SOURCESEL_USART3 << 16) /**< Shifted mode USART3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER1 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER1 << 16) /**< Shifted mode WTIMER1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 << 16) /**< Shifted mode CRYPTO1 for LDMA_CH_REQSEL */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */ +#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */ +#define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */ +#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} End of group EFR32MG12P_LDMA */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma_ch.h new file mode 100644 index 00000000000..11b358ecc07 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma_ch.h @@ -0,0 +1,53 @@ +/**************************************************************************//** + * @file efr32mg12p_ldma_ch.h + * @brief EFR32MG12P_LDMA_CH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LDMA_CH EFR32MG12P LDMA CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */ + uint32_t RESERVED0[5]; /**< Reserved future */ +} LDMA_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense.h new file mode 100644 index 00000000000..e2c1b2c8f16 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense.h @@ -0,0 +1,1867 @@ +/**************************************************************************//** + * @file efr32mg12p_lesense.h + * @brief EFR32MG12P_LESENSE register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_LESENSE + * @{ + * @brief EFR32MG12P_LESENSE Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t TIMCTRL; /**< Timing Control Register */ + __IOM uint32_t PERCTRL; /**< Peripheral Control Register */ + __IOM uint32_t DECCTRL; /**< Decoder control Register */ + __IOM uint32_t BIASCTRL; /**< Bias Control Register */ + __IOM uint32_t EVALCTRL; /**< LESENSE evaluation control */ + __IOM uint32_t PRSCTRL; /**< PRS control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t CHEN; /**< Channel enable Register */ + __IOM uint32_t SCANRES; /**< Scan result register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t PTR; /**< Result buffer pointers */ + __IM uint32_t BUFDATA; /**< Result buffer data register */ + __IM uint32_t CURCH; /**< Current channel index */ + __IOM uint32_t DECSTATE; /**< Current decoder state */ + __IOM uint32_t SENSORSTATE; /**< Decoder input register */ + __IOM uint32_t IDLECONF; /**< GPIO Idle phase configuration */ + __IOM uint32_t ALTEXCONF; /**< Alternative excite pin configuration */ + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Register */ + + uint32_t RESERVED1[38]; /**< Reserved registers */ + LESENSE_ST_TypeDef ST[32]; /**< Decoding states */ + + LESENSE_BUF_TypeDef BUF[16]; /**< Scanresult */ + + LESENSE_CH_TypeDef CH[16]; /**< Scanconfig */ +} LESENSE_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_LESENSE_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LESENSE CTRL */ +#define _LESENSE_CTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CTRL */ +#define _LESENSE_CTRL_MASK 0x007B29BFUL /**< Mask for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_DEFAULT (_LESENSE_CTRL_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PERIODIC (_LESENSE_CTRL_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_ONESHOT (_LESENSE_CTRL_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PRS (_LESENSE_CTRL_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_SHIFT 2 /**< Shift value for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_MASK 0x3CUL /**< Bit mask for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_DEFAULT (_LESENSE_CTRL_PRSSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH0 (_LESENSE_CTRL_PRSSEL_PRSCH0 << 2) /**< Shifted mode PRSCH0 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH1 (_LESENSE_CTRL_PRSSEL_PRSCH1 << 2) /**< Shifted mode PRSCH1 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH2 (_LESENSE_CTRL_PRSSEL_PRSCH2 << 2) /**< Shifted mode PRSCH2 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH3 (_LESENSE_CTRL_PRSSEL_PRSCH3 << 2) /**< Shifted mode PRSCH3 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH4 (_LESENSE_CTRL_PRSSEL_PRSCH4 << 2) /**< Shifted mode PRSCH4 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH5 (_LESENSE_CTRL_PRSSEL_PRSCH5 << 2) /**< Shifted mode PRSCH5 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH6 (_LESENSE_CTRL_PRSSEL_PRSCH6 << 2) /**< Shifted mode PRSCH6 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH7 (_LESENSE_CTRL_PRSSEL_PRSCH7 << 2) /**< Shifted mode PRSCH7 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH8 (_LESENSE_CTRL_PRSSEL_PRSCH8 << 2) /**< Shifted mode PRSCH8 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH9 (_LESENSE_CTRL_PRSSEL_PRSCH9 << 2) /**< Shifted mode PRSCH9 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH10 (_LESENSE_CTRL_PRSSEL_PRSCH10 << 2) /**< Shifted mode PRSCH10 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH11 (_LESENSE_CTRL_PRSSEL_PRSCH11 << 2) /**< Shifted mode PRSCH11 for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_SHIFT 7 /**< Shift value for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_MASK 0x180UL /**< Bit mask for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DEFAULT (_LESENSE_CTRL_SCANCONF_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DIRMAP (_LESENSE_CTRL_SCANCONF_DIRMAP << 7) /**< Shifted mode DIRMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_INVMAP (_LESENSE_CTRL_SCANCONF_INVMAP << 7) /**< Shifted mode INVMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_TOGGLE (_LESENSE_CTRL_SCANCONF_TOGGLE << 7) /**< Shifted mode TOGGLE for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DECDEF (_LESENSE_CTRL_SCANCONF_DECDEF << 7) /**< Shifted mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP (0x1UL << 11) /**< Alternative excitation map */ +#define _LESENSE_CTRL_ALTEXMAP_SHIFT 11 /**< Shift value for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_MASK 0x800UL /**< Bit mask for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_ALTEX 0x00000000UL /**< Mode ALTEX for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_CH 0x00000001UL /**< Mode CH for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_DEFAULT (_LESENSE_CTRL_ALTEXMAP_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_ALTEX (_LESENSE_CTRL_ALTEXMAP_ALTEX << 11) /**< Shifted mode ALTEX for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_CH (_LESENSE_CTRL_ALTEXMAP_CH << 11) /**< Shifted mode CH for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE (0x1UL << 13) /**< Enable dual sample mode */ +#define _LESENSE_CTRL_DUALSAMPLE_SHIFT 13 /**< Shift value for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_MASK 0x2000UL /**< Bit mask for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE_DEFAULT (_LESENSE_CTRL_DUALSAMPLE_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW (0x1UL << 16) /**< Result buffer overwrite */ +#define _LESENSE_CTRL_BUFOW_SHIFT 16 /**< Shift value for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_MASK 0x10000UL /**< Bit mask for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW_DEFAULT (_LESENSE_CTRL_BUFOW_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES (0x1UL << 17) /**< Enable storing of SCANRES */ +#define _LESENSE_CTRL_STRSCANRES_SHIFT 17 /**< Shift value for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_MASK 0x20000UL /**< Bit mask for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES_DEFAULT (_LESENSE_CTRL_STRSCANRES_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL (0x1UL << 19) /**< Result buffer interrupt and DMA trigger level */ +#define _LESENSE_CTRL_BUFIDL_SHIFT 19 /**< Shift value for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_MASK 0x80000UL /**< Bit mask for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_HALFFULL 0x00000000UL /**< Mode HALFFULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_FULL 0x00000001UL /**< Mode FULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_DEFAULT (_LESENSE_CTRL_BUFIDL_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_HALFFULL (_LESENSE_CTRL_BUFIDL_HALFFULL << 19) /**< Shifted mode HALFFULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_FULL (_LESENSE_CTRL_BUFIDL_FULL << 19) /**< Shifted mode FULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_SHIFT 20 /**< Shift value for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_MASK 0x300000UL /**< Bit mask for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFDATAV 0x00000001UL /**< Mode BUFDATAV for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFLEVEL 0x00000002UL /**< Mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DEFAULT (_LESENSE_CTRL_DMAWU_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DISABLE (_LESENSE_CTRL_DMAWU_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFDATAV (_LESENSE_CTRL_DMAWU_BUFDATAV << 20) /**< Shifted mode BUFDATAV for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFLEVEL (_LESENSE_CTRL_DMAWU_BUFLEVEL << 20) /**< Shifted mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN (0x1UL << 22) /**< Debug Mode Run Enable */ +#define _LESENSE_CTRL_DEBUGRUN_SHIFT 22 /**< Shift value for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_MASK 0x400000UL /**< Bit mask for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN_DEFAULT (_LESENSE_CTRL_DEBUGRUN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_CTRL */ + +/* Bit fields for LESENSE TIMCTRL */ +#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUXHFRCO startup configuration */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */ + +/* Bit fields for LESENSE PERCTRL */ +#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_MASK 0x3FF0014FUL /**< Mask for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0EN (0x1UL << 0) /**< VDAC CH0 enable. */ +#define _LESENSE_PERCTRL_DACCH0EN_SHIFT 0 /**< Shift value for LESENSE_DACCH0EN */ +#define _LESENSE_PERCTRL_DACCH0EN_MASK 0x1UL /**< Bit mask for LESENSE_DACCH0EN */ +#define _LESENSE_PERCTRL_DACCH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0EN_DEFAULT (_LESENSE_PERCTRL_DACCH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1EN (0x1UL << 1) /**< VDAC CH1 enable. */ +#define _LESENSE_PERCTRL_DACCH1EN_SHIFT 1 /**< Shift value for LESENSE_DACCH1EN */ +#define _LESENSE_PERCTRL_DACCH1EN_MASK 0x2UL /**< Bit mask for LESENSE_DACCH1EN */ +#define _LESENSE_PERCTRL_DACCH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1EN_DEFAULT (_LESENSE_PERCTRL_DACCH1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< VDAC CH0 data selection. */ +#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA (0x1UL << 3) /**< VDAC CH1 data selection. */ +#define _LESENSE_PERCTRL_DACCH1DATA_SHIFT 3 /**< Shift value for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_MASK 0x8UL /**< Bit mask for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DEFAULT (_LESENSE_PERCTRL_DACCH1DATA_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DACDATA (_LESENSE_PERCTRL_DACCH1DATA_DACDATA << 3) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_THRES (_LESENSE_PERCTRL_DACCH1DATA_THRES << 3) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< VDAC startup configuration */ +#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< VDAC conversion trigger configuration */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x300000UL /**< Bit mask for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DISABLE (_LESENSE_PERCTRL_ACMP0MODE_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0xC00000UL /**< Bit mask for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DISABLE (_LESENSE_PERCTRL_ACMP1MODE_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert analog comparator 0 output */ +#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert analog comparator 1 output */ +#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0HYSTEN (0x1UL << 26) /**< ACMP0 hysteresis enable */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_SHIFT 26 /**< Shift value for LESENSE_ACMP0HYSTEN */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_MASK 0x4000000UL /**< Bit mask for LESENSE_ACMP0HYSTEN */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1HYSTEN (0x1UL << 27) /**< ACMP1 hysteresis enable */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_SHIFT 27 /**< Shift value for LESENSE_ACMP1HYSTEN */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_MASK 0x8000000UL /**< Bit mask for LESENSE_ACMP1HYSTEN */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT << 27) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_SHIFT 28 /**< Shift value for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_MASK 0x30000000UL /**< Bit mask for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM 0x00000001UL /**< Mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM 0x00000002UL /**< Mode KEEPDACWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM 0x00000003UL /**< Mode KEEPACMPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_DEFAULT (_LESENSE_PERCTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_NORMAL (_LESENSE_PERCTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM << 28) /**< Shifted mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM << 28) /**< Shifted mode KEEPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM << 28) /**< Shifted mode KEEPACMPDACWARM for LESENSE_PERCTRL */ + +/* Bit fields for LESENSE DECCTRL */ +#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_MASK 0x1EF7BDFFUL /**< Mask for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DISABLE (0x1UL << 0) /**< Disable the decoder */ +#define _LESENSE_DECCTRL_DISABLE_SHIFT 0 /**< Shift value for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_MASK 0x1UL /**< Bit mask for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DISABLE_DEFAULT (_LESENSE_DECCTRL_DISABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK (0x1UL << 1) /**< Enable check of current state */ +#define _LESENSE_DECCTRL_ERRCHK_SHIFT 1 /**< Shift value for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_MASK 0x2UL /**< Bit mask for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK_DEFAULT (_LESENSE_DECCTRL_ERRCHK_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable decoder to channel interrupt mapping */ +#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable decoder hysteresis on PRS0 output */ +#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable decoder hysteresis on PRS1 output */ +#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable decoder hysteresis on PRS2 output */ +#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable decoder hysteresis on interrupt requests */ +#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable count mode on decoder PRS channels 0 and 1 */ +#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT (0x1UL << 8) /**< LESENSE decoder input configuration */ +#define _LESENSE_DECCTRL_INPUT_SHIFT 8 /**< Shift value for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_MASK 0x100UL /**< Bit mask for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_SENSORSTATE 0x00000000UL /**< Mode SENSORSTATE for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_PRS 0x00000001UL /**< Mode PRS for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_DEFAULT (_LESENSE_DECCTRL_INPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_SENSORSTATE (_LESENSE_DECCTRL_INPUT_SENSORSTATE << 8) /**< Shifted mode SENSORSTATE for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_PRS (_LESENSE_DECCTRL_INPUT_PRS << 8) /**< Shifted mode PRS for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_SHIFT 10 /**< Shift value for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_MASK 0x3C00UL /**< Bit mask for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_DEFAULT (_LESENSE_DECCTRL_PRSSEL0_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH0 (_LESENSE_DECCTRL_PRSSEL0_PRSCH0 << 10) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH1 (_LESENSE_DECCTRL_PRSSEL0_PRSCH1 << 10) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH2 (_LESENSE_DECCTRL_PRSSEL0_PRSCH2 << 10) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH3 (_LESENSE_DECCTRL_PRSSEL0_PRSCH3 << 10) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH4 (_LESENSE_DECCTRL_PRSSEL0_PRSCH4 << 10) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH5 (_LESENSE_DECCTRL_PRSSEL0_PRSCH5 << 10) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH6 (_LESENSE_DECCTRL_PRSSEL0_PRSCH6 << 10) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH7 (_LESENSE_DECCTRL_PRSSEL0_PRSCH7 << 10) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH8 (_LESENSE_DECCTRL_PRSSEL0_PRSCH8 << 10) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH9 (_LESENSE_DECCTRL_PRSSEL0_PRSCH9 << 10) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH10 (_LESENSE_DECCTRL_PRSSEL0_PRSCH10 << 10) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH11 (_LESENSE_DECCTRL_PRSSEL0_PRSCH11 << 10) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_SHIFT 15 /**< Shift value for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_MASK 0x78000UL /**< Bit mask for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_DEFAULT (_LESENSE_DECCTRL_PRSSEL1_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH0 (_LESENSE_DECCTRL_PRSSEL1_PRSCH0 << 15) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH1 (_LESENSE_DECCTRL_PRSSEL1_PRSCH1 << 15) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH2 (_LESENSE_DECCTRL_PRSSEL1_PRSCH2 << 15) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH3 (_LESENSE_DECCTRL_PRSSEL1_PRSCH3 << 15) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH4 (_LESENSE_DECCTRL_PRSSEL1_PRSCH4 << 15) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH5 (_LESENSE_DECCTRL_PRSSEL1_PRSCH5 << 15) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH6 (_LESENSE_DECCTRL_PRSSEL1_PRSCH6 << 15) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH7 (_LESENSE_DECCTRL_PRSSEL1_PRSCH7 << 15) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH8 (_LESENSE_DECCTRL_PRSSEL1_PRSCH8 << 15) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH9 (_LESENSE_DECCTRL_PRSSEL1_PRSCH9 << 15) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH10 (_LESENSE_DECCTRL_PRSSEL1_PRSCH10 << 15) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH11 (_LESENSE_DECCTRL_PRSSEL1_PRSCH11 << 15) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_SHIFT 20 /**< Shift value for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_MASK 0xF00000UL /**< Bit mask for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_DEFAULT (_LESENSE_DECCTRL_PRSSEL2_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH0 (_LESENSE_DECCTRL_PRSSEL2_PRSCH0 << 20) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH1 (_LESENSE_DECCTRL_PRSSEL2_PRSCH1 << 20) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH2 (_LESENSE_DECCTRL_PRSSEL2_PRSCH2 << 20) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH3 (_LESENSE_DECCTRL_PRSSEL2_PRSCH3 << 20) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH4 (_LESENSE_DECCTRL_PRSSEL2_PRSCH4 << 20) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH5 (_LESENSE_DECCTRL_PRSSEL2_PRSCH5 << 20) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH6 (_LESENSE_DECCTRL_PRSSEL2_PRSCH6 << 20) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH7 (_LESENSE_DECCTRL_PRSSEL2_PRSCH7 << 20) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH8 (_LESENSE_DECCTRL_PRSSEL2_PRSCH8 << 20) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH9 (_LESENSE_DECCTRL_PRSSEL2_PRSCH9 << 20) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH10 (_LESENSE_DECCTRL_PRSSEL2_PRSCH10 << 20) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH11 (_LESENSE_DECCTRL_PRSSEL2_PRSCH11 << 20) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_SHIFT 25 /**< Shift value for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_MASK 0x1E000000UL /**< Bit mask for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_DEFAULT (_LESENSE_DECCTRL_PRSSEL3_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH0 (_LESENSE_DECCTRL_PRSSEL3_PRSCH0 << 25) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH1 (_LESENSE_DECCTRL_PRSSEL3_PRSCH1 << 25) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH2 (_LESENSE_DECCTRL_PRSSEL3_PRSCH2 << 25) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH3 (_LESENSE_DECCTRL_PRSSEL3_PRSCH3 << 25) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH4 (_LESENSE_DECCTRL_PRSSEL3_PRSCH4 << 25) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH5 (_LESENSE_DECCTRL_PRSSEL3_PRSCH5 << 25) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH6 (_LESENSE_DECCTRL_PRSSEL3_PRSCH6 << 25) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH7 (_LESENSE_DECCTRL_PRSSEL3_PRSCH7 << 25) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH8 (_LESENSE_DECCTRL_PRSSEL3_PRSCH8 << 25) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH9 (_LESENSE_DECCTRL_PRSSEL3_PRSCH9 << 25) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH10 (_LESENSE_DECCTRL_PRSSEL3_PRSCH10 << 25) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH11 (_LESENSE_DECCTRL_PRSSEL3_PRSCH11 << 25) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ + +/* Bit fields for LESENSE BIASCTRL */ +#define _LESENSE_BIASCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_MASK 0x00000003UL /**< Mask for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_SHIFT 0 /**< Shift value for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_MASK 0x3UL /**< Bit mask for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DONTTOUCH 0x00000000UL /**< Mode DONTTOUCH for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE 0x00000001UL /**< Mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_HIGHACC 0x00000002UL /**< Mode HIGHACC for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DEFAULT (_LESENSE_BIASCTRL_BIASMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DONTTOUCH (_LESENSE_BIASCTRL_BIASMODE_DONTTOUCH << 0) /**< Shifted mode DONTTOUCH for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE (_LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE << 0) /**< Shifted mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_HIGHACC (_LESENSE_BIASCTRL_BIASMODE_HIGHACC << 0) /**< Shifted mode HIGHACC for LESENSE_BIASCTRL */ + +/* Bit fields for LESENSE EVALCTRL */ +#define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */ +#define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */ + +/* Bit fields for LESENSE PRSCTRL */ +#define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS output DECCMP */ +#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ + +/* Bit fields for LESENSE CMD */ +#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */ +#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */ +#define LESENSE_CMD_START (0x1UL << 0) /**< Start scanning of sensors. */ +#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */ +#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */ +#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop scanning of sensors */ +#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start decoder */ +#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear result buffer */ +#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */ + +/* Bit fields for LESENSE CHEN */ +#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */ +#define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */ +#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */ + +/* Bit fields for LESENSE SCANRES */ +#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ + +/* Bit fields for LESENSE STATUS */ +#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */ +#define _LESENSE_STATUS_MASK 0x0000003FUL /**< Mask for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFDATAV (0x1UL << 0) /**< Result data valid */ +#define _LESENSE_STATUS_BUFDATAV_SHIFT 0 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_MASK 0x1UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFDATAV_DEFAULT (_LESENSE_STATUS_BUFDATAV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL (0x1UL << 1) /**< Result buffer half full */ +#define _LESENSE_STATUS_BUFHALFFULL_SHIFT 1 /**< Shift value for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_MASK 0x2UL /**< Bit mask for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL_DEFAULT (_LESENSE_STATUS_BUFHALFFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL (0x1UL << 2) /**< Result buffer full */ +#define _LESENSE_STATUS_BUFFULL_SHIFT 2 /**< Shift value for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_MASK 0x4UL /**< Bit mask for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL_DEFAULT (_LESENSE_STATUS_BUFFULL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING (0x1UL << 3) /**< LESENSE periodic counter running */ +#define _LESENSE_STATUS_RUNNING_SHIFT 3 /**< Shift value for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_MASK 0x8UL /**< Bit mask for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE (0x1UL << 4) /**< LESENSE scan active */ +#define _LESENSE_STATUS_SCANACTIVE_SHIFT 4 /**< Shift value for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_MASK 0x10UL /**< Bit mask for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE (0x1UL << 5) /**< LESENSE VDAC interface is active */ +#define _LESENSE_STATUS_DACACTIVE_SHIFT 5 /**< Shift value for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_MASK 0x20UL /**< Bit mask for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE_DEFAULT (_LESENSE_STATUS_DACACTIVE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */ + +/* Bit fields for LESENSE PTR */ +#define _LESENSE_PTR_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PTR */ +#define _LESENSE_PTR_MASK 0x000000FFUL /**< Mask for LESENSE_PTR */ +#define _LESENSE_PTR_RD_SHIFT 0 /**< Shift value for LESENSE_RD */ +#define _LESENSE_PTR_RD_MASK 0xFUL /**< Bit mask for LESENSE_RD */ +#define _LESENSE_PTR_RD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_RD_DEFAULT (_LESENSE_PTR_RD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PTR */ +#define _LESENSE_PTR_WR_SHIFT 4 /**< Shift value for LESENSE_WR */ +#define _LESENSE_PTR_WR_MASK 0xF0UL /**< Bit mask for LESENSE_WR */ +#define _LESENSE_PTR_WR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_WR_DEFAULT (_LESENSE_PTR_WR_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_PTR */ + +/* Bit fields for LESENSE BUFDATA */ +#define _LESENSE_BUFDATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_SHIFT 0 /**< Shift value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ +#define LESENSE_BUFDATA_BUFDATA_DEFAULT (_LESENSE_BUFDATA_BUFDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATASRC_SHIFT 16 /**< Shift value for LESENSE_BUFDATASRC */ +#define _LESENSE_BUFDATA_BUFDATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_BUFDATASRC */ +#define _LESENSE_BUFDATA_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ +#define LESENSE_BUFDATA_BUFDATASRC_DEFAULT (_LESENSE_BUFDATA_BUFDATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ + +/* Bit fields for LESENSE CURCH */ +#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */ +#define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */ +#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */ + +/* Bit fields for LESENSE DECSTATE */ +#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */ +#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */ + +/* Bit fields for LESENSE SENSORSTATE */ +#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */ +#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE */ + +/* Bit fields for LESENSE IDLECONF */ +#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_MASK 0x3UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DEFAULT (_LESENSE_IDLECONF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DISABLE (_LESENSE_IDLECONF_CH0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_HIGH (_LESENSE_IDLECONF_CH0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_LOW (_LESENSE_IDLECONF_CH0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DAC (_LESENSE_IDLECONF_CH0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_SHIFT 2 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_MASK 0xCUL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DEFAULT (_LESENSE_IDLECONF_CH1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DISABLE (_LESENSE_IDLECONF_CH1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_HIGH (_LESENSE_IDLECONF_CH1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_LOW (_LESENSE_IDLECONF_CH1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DAC (_LESENSE_IDLECONF_CH1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_SHIFT 4 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_MASK 0x30UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DEFAULT (_LESENSE_IDLECONF_CH2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DISABLE (_LESENSE_IDLECONF_CH2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_HIGH (_LESENSE_IDLECONF_CH2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_LOW (_LESENSE_IDLECONF_CH2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DAC (_LESENSE_IDLECONF_CH2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_SHIFT 6 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_MASK 0xC0UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DEFAULT (_LESENSE_IDLECONF_CH3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DISABLE (_LESENSE_IDLECONF_CH3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_HIGH (_LESENSE_IDLECONF_CH3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_LOW (_LESENSE_IDLECONF_CH3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DAC (_LESENSE_IDLECONF_CH3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_SHIFT 8 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_MASK 0x300UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DEFAULT (_LESENSE_IDLECONF_CH4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DISABLE (_LESENSE_IDLECONF_CH4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_HIGH (_LESENSE_IDLECONF_CH4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_LOW (_LESENSE_IDLECONF_CH4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DAC (_LESENSE_IDLECONF_CH4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_SHIFT 10 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_MASK 0xC00UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DEFAULT (_LESENSE_IDLECONF_CH5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DISABLE (_LESENSE_IDLECONF_CH5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_HIGH (_LESENSE_IDLECONF_CH5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_LOW (_LESENSE_IDLECONF_CH5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DAC (_LESENSE_IDLECONF_CH5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_SHIFT 12 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_MASK 0x3000UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DEFAULT (_LESENSE_IDLECONF_CH6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DISABLE (_LESENSE_IDLECONF_CH6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_HIGH (_LESENSE_IDLECONF_CH6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_LOW (_LESENSE_IDLECONF_CH6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DAC (_LESENSE_IDLECONF_CH6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_SHIFT 14 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_MASK 0xC000UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DEFAULT (_LESENSE_IDLECONF_CH7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DISABLE (_LESENSE_IDLECONF_CH7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_HIGH (_LESENSE_IDLECONF_CH7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_LOW (_LESENSE_IDLECONF_CH7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DAC (_LESENSE_IDLECONF_CH7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_SHIFT 16 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_MASK 0x30000UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DEFAULT (_LESENSE_IDLECONF_CH8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DISABLE (_LESENSE_IDLECONF_CH8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_HIGH (_LESENSE_IDLECONF_CH8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_LOW (_LESENSE_IDLECONF_CH8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DAC (_LESENSE_IDLECONF_CH8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_SHIFT 18 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_MASK 0xC0000UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DEFAULT (_LESENSE_IDLECONF_CH9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DISABLE (_LESENSE_IDLECONF_CH9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_HIGH (_LESENSE_IDLECONF_CH9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_LOW (_LESENSE_IDLECONF_CH9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DAC (_LESENSE_IDLECONF_CH9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_SHIFT 20 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_MASK 0x300000UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DEFAULT (_LESENSE_IDLECONF_CH10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DISABLE (_LESENSE_IDLECONF_CH10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_HIGH (_LESENSE_IDLECONF_CH10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_LOW (_LESENSE_IDLECONF_CH10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DAC (_LESENSE_IDLECONF_CH10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_SHIFT 22 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_MASK 0xC00000UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DEFAULT (_LESENSE_IDLECONF_CH11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DISABLE (_LESENSE_IDLECONF_CH11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_HIGH (_LESENSE_IDLECONF_CH11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_LOW (_LESENSE_IDLECONF_CH11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DAC (_LESENSE_IDLECONF_CH11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_SHIFT 24 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_MASK 0x3000000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DEFAULT (_LESENSE_IDLECONF_CH12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DISABLE (_LESENSE_IDLECONF_CH12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_HIGH (_LESENSE_IDLECONF_CH12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_LOW (_LESENSE_IDLECONF_CH12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DAC (_LESENSE_IDLECONF_CH12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_SHIFT 26 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_MASK 0xC000000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DEFAULT (_LESENSE_IDLECONF_CH13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DISABLE (_LESENSE_IDLECONF_CH13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_HIGH (_LESENSE_IDLECONF_CH13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_LOW (_LESENSE_IDLECONF_CH13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DAC (_LESENSE_IDLECONF_CH13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_SHIFT 28 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_MASK 0x30000000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DEFAULT (_LESENSE_IDLECONF_CH14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DISABLE (_LESENSE_IDLECONF_CH14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_HIGH (_LESENSE_IDLECONF_CH14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_LOW (_LESENSE_IDLECONF_CH14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DAC (_LESENSE_IDLECONF_CH14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_SHIFT 30 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DEFAULT (_LESENSE_IDLECONF_CH15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DISABLE (_LESENSE_IDLECONF_CH15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_HIGH (_LESENSE_IDLECONF_CH15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_LOW (_LESENSE_IDLECONF_CH15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DAC (_LESENSE_IDLECONF_CH15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */ + +/* Bit fields for LESENSE ALTEXCONF */ +#define _LESENSE_ALTEXCONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_SHIFT 0 /**< Shift value for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_MASK 0x3UL /**< Bit mask for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DISABLE (_LESENSE_ALTEXCONF_IDLECONF0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_HIGH (_LESENSE_ALTEXCONF_IDLECONF0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_LOW (_LESENSE_ALTEXCONF_IDLECONF0_LOW << 0) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_SHIFT 2 /**< Shift value for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_MASK 0xCUL /**< Bit mask for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DISABLE (_LESENSE_ALTEXCONF_IDLECONF1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_HIGH (_LESENSE_ALTEXCONF_IDLECONF1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_LOW (_LESENSE_ALTEXCONF_IDLECONF1_LOW << 2) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_SHIFT 4 /**< Shift value for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_MASK 0x30UL /**< Bit mask for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DISABLE (_LESENSE_ALTEXCONF_IDLECONF2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_HIGH (_LESENSE_ALTEXCONF_IDLECONF2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_LOW (_LESENSE_ALTEXCONF_IDLECONF2_LOW << 4) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_SHIFT 6 /**< Shift value for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_MASK 0xC0UL /**< Bit mask for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DISABLE (_LESENSE_ALTEXCONF_IDLECONF3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_HIGH (_LESENSE_ALTEXCONF_IDLECONF3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_LOW (_LESENSE_ALTEXCONF_IDLECONF3_LOW << 6) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_SHIFT 8 /**< Shift value for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_MASK 0x300UL /**< Bit mask for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DISABLE (_LESENSE_ALTEXCONF_IDLECONF4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_HIGH (_LESENSE_ALTEXCONF_IDLECONF4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_LOW (_LESENSE_ALTEXCONF_IDLECONF4_LOW << 8) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_SHIFT 10 /**< Shift value for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_MASK 0xC00UL /**< Bit mask for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DISABLE (_LESENSE_ALTEXCONF_IDLECONF5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_HIGH (_LESENSE_ALTEXCONF_IDLECONF5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_LOW (_LESENSE_ALTEXCONF_IDLECONF5_LOW << 10) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_SHIFT 12 /**< Shift value for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_MASK 0x3000UL /**< Bit mask for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DISABLE (_LESENSE_ALTEXCONF_IDLECONF6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_HIGH (_LESENSE_ALTEXCONF_IDLECONF6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_LOW (_LESENSE_ALTEXCONF_IDLECONF6_LOW << 12) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_SHIFT 14 /**< Shift value for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_MASK 0xC000UL /**< Bit mask for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DISABLE (_LESENSE_ALTEXCONF_IDLECONF7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_HIGH (_LESENSE_ALTEXCONF_IDLECONF7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_LOW (_LESENSE_ALTEXCONF_IDLECONF7_LOW << 14) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0 (0x1UL << 16) /**< ALTEX0 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX0_SHIFT 16 /**< Shift value for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_MASK 0x10000UL /**< Bit mask for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0_DEFAULT (_LESENSE_ALTEXCONF_AEX0_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1 (0x1UL << 17) /**< ALTEX1 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX1_SHIFT 17 /**< Shift value for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_MASK 0x20000UL /**< Bit mask for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1_DEFAULT (_LESENSE_ALTEXCONF_AEX1_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2 (0x1UL << 18) /**< ALTEX2 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX2_SHIFT 18 /**< Shift value for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_MASK 0x40000UL /**< Bit mask for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2_DEFAULT (_LESENSE_ALTEXCONF_AEX2_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3 (0x1UL << 19) /**< ALTEX3 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX3_SHIFT 19 /**< Shift value for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_MASK 0x80000UL /**< Bit mask for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3_DEFAULT (_LESENSE_ALTEXCONF_AEX3_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4 (0x1UL << 20) /**< ALTEX4 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX4_SHIFT 20 /**< Shift value for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_MASK 0x100000UL /**< Bit mask for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4_DEFAULT (_LESENSE_ALTEXCONF_AEX4_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5 (0x1UL << 21) /**< ALTEX5 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX5_SHIFT 21 /**< Shift value for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_MASK 0x200000UL /**< Bit mask for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5_DEFAULT (_LESENSE_ALTEXCONF_AEX5_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6 (0x1UL << 22) /**< ALTEX6 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX6_SHIFT 22 /**< Shift value for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_MASK 0x400000UL /**< Bit mask for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6_DEFAULT (_LESENSE_ALTEXCONF_AEX6_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7 (0x1UL << 23) /**< ALTEX7 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX7_SHIFT 23 /**< Shift value for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_MASK 0x800000UL /**< Bit mask for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7_DEFAULT (_LESENSE_ALTEXCONF_AEX7_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ + +/* Bit fields for LESENSE IF */ +#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */ +#define _LESENSE_IF_MASK 0x007FFFFFUL /**< Mask for LESENSE_IF */ +#define LESENSE_IF_CH0 (0x1UL << 0) /**< CH0 interrupt flag */ +#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1 (0x1UL << 1) /**< CH1 interrupt flag */ +#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2 (0x1UL << 2) /**< CH2 interrupt flag */ +#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3 (0x1UL << 3) /**< CH3 interrupt flag */ +#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4 (0x1UL << 4) /**< CH4 interrupt flag */ +#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5 (0x1UL << 5) /**< CH5 interrupt flag */ +#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6 (0x1UL << 6) /**< CH6 interrupt flag */ +#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7 (0x1UL << 7) /**< CH7 interrupt flag */ +#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8 (0x1UL << 8) /**< CH8 interrupt flag */ +#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9 (0x1UL << 9) /**< CH9 interrupt flag */ +#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10 (0x1UL << 10) /**< CH10 interrupt flag */ +#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11 (0x1UL << 11) /**< CH11 interrupt flag */ +#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12 (0x1UL << 12) /**< CH12 interrupt flag */ +#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13 (0x1UL << 13) /**< CH13 interrupt flag */ +#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14 (0x1UL << 14) /**< CH14 interrupt flag */ +#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15 (0x1UL << 15) /**< CH15 interrupt flag */ +#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE interrupt flag */ +#define _LESENSE_IF_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE_DEFAULT (_LESENSE_IF_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC (0x1UL << 17) /**< DEC interrupt flag */ +#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR (0x1UL << 18) /**< DECERR interrupt flag */ +#define _LESENSE_IF_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR_DEFAULT (_LESENSE_IF_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV (0x1UL << 19) /**< BUFDATAV interrupt flag */ +#define _LESENSE_IF_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV_DEFAULT (_LESENSE_IF_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL interrupt flag */ +#define _LESENSE_IF_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL_DEFAULT (_LESENSE_IF_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF (0x1UL << 21) /**< BUFOF interrupt flag */ +#define _LESENSE_IF_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF_DEFAULT (_LESENSE_IF_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF (0x1UL << 22) /**< CNTOF interrupt flag */ +#define _LESENSE_IF_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IF */ + +/* Bit fields for LESENSE IFS */ +#define _LESENSE_IFS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFS */ +#define _LESENSE_IFS_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFS */ +#define LESENSE_IFS_CH0 (0x1UL << 0) /**< Set CH0 Interrupt Flag */ +#define _LESENSE_IFS_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH0_DEFAULT (_LESENSE_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1 (0x1UL << 1) /**< Set CH1 Interrupt Flag */ +#define _LESENSE_IFS_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1_DEFAULT (_LESENSE_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2 (0x1UL << 2) /**< Set CH2 Interrupt Flag */ +#define _LESENSE_IFS_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2_DEFAULT (_LESENSE_IFS_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3 (0x1UL << 3) /**< Set CH3 Interrupt Flag */ +#define _LESENSE_IFS_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3_DEFAULT (_LESENSE_IFS_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4 (0x1UL << 4) /**< Set CH4 Interrupt Flag */ +#define _LESENSE_IFS_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4_DEFAULT (_LESENSE_IFS_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5 (0x1UL << 5) /**< Set CH5 Interrupt Flag */ +#define _LESENSE_IFS_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5_DEFAULT (_LESENSE_IFS_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6 (0x1UL << 6) /**< Set CH6 Interrupt Flag */ +#define _LESENSE_IFS_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6_DEFAULT (_LESENSE_IFS_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7 (0x1UL << 7) /**< Set CH7 Interrupt Flag */ +#define _LESENSE_IFS_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7_DEFAULT (_LESENSE_IFS_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8 (0x1UL << 8) /**< Set CH8 Interrupt Flag */ +#define _LESENSE_IFS_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8_DEFAULT (_LESENSE_IFS_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9 (0x1UL << 9) /**< Set CH9 Interrupt Flag */ +#define _LESENSE_IFS_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9_DEFAULT (_LESENSE_IFS_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10 (0x1UL << 10) /**< Set CH10 Interrupt Flag */ +#define _LESENSE_IFS_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10_DEFAULT (_LESENSE_IFS_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11 (0x1UL << 11) /**< Set CH11 Interrupt Flag */ +#define _LESENSE_IFS_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11_DEFAULT (_LESENSE_IFS_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12 (0x1UL << 12) /**< Set CH12 Interrupt Flag */ +#define _LESENSE_IFS_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12_DEFAULT (_LESENSE_IFS_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13 (0x1UL << 13) /**< Set CH13 Interrupt Flag */ +#define _LESENSE_IFS_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13_DEFAULT (_LESENSE_IFS_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14 (0x1UL << 14) /**< Set CH14 Interrupt Flag */ +#define _LESENSE_IFS_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14_DEFAULT (_LESENSE_IFS_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15 (0x1UL << 15) /**< Set CH15 Interrupt Flag */ +#define _LESENSE_IFS_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15_DEFAULT (_LESENSE_IFS_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE (0x1UL << 16) /**< Set SCANCOMPLETE Interrupt Flag */ +#define _LESENSE_IFS_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE_DEFAULT (_LESENSE_IFS_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC (0x1UL << 17) /**< Set DEC Interrupt Flag */ +#define _LESENSE_IFS_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC_DEFAULT (_LESENSE_IFS_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR (0x1UL << 18) /**< Set DECERR Interrupt Flag */ +#define _LESENSE_IFS_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR_DEFAULT (_LESENSE_IFS_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV (0x1UL << 19) /**< Set BUFDATAV Interrupt Flag */ +#define _LESENSE_IFS_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV_DEFAULT (_LESENSE_IFS_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL (0x1UL << 20) /**< Set BUFLEVEL Interrupt Flag */ +#define _LESENSE_IFS_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL_DEFAULT (_LESENSE_IFS_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF (0x1UL << 21) /**< Set BUFOF Interrupt Flag */ +#define _LESENSE_IFS_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF_DEFAULT (_LESENSE_IFS_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF (0x1UL << 22) /**< Set CNTOF Interrupt Flag */ +#define _LESENSE_IFS_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF_DEFAULT (_LESENSE_IFS_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFS */ + +/* Bit fields for LESENSE IFC */ +#define _LESENSE_IFC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFC */ +#define _LESENSE_IFC_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFC */ +#define LESENSE_IFC_CH0 (0x1UL << 0) /**< Clear CH0 Interrupt Flag */ +#define _LESENSE_IFC_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH0_DEFAULT (_LESENSE_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1 (0x1UL << 1) /**< Clear CH1 Interrupt Flag */ +#define _LESENSE_IFC_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1_DEFAULT (_LESENSE_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2 (0x1UL << 2) /**< Clear CH2 Interrupt Flag */ +#define _LESENSE_IFC_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2_DEFAULT (_LESENSE_IFC_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3 (0x1UL << 3) /**< Clear CH3 Interrupt Flag */ +#define _LESENSE_IFC_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3_DEFAULT (_LESENSE_IFC_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4 (0x1UL << 4) /**< Clear CH4 Interrupt Flag */ +#define _LESENSE_IFC_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4_DEFAULT (_LESENSE_IFC_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5 (0x1UL << 5) /**< Clear CH5 Interrupt Flag */ +#define _LESENSE_IFC_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5_DEFAULT (_LESENSE_IFC_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6 (0x1UL << 6) /**< Clear CH6 Interrupt Flag */ +#define _LESENSE_IFC_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6_DEFAULT (_LESENSE_IFC_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7 (0x1UL << 7) /**< Clear CH7 Interrupt Flag */ +#define _LESENSE_IFC_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7_DEFAULT (_LESENSE_IFC_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8 (0x1UL << 8) /**< Clear CH8 Interrupt Flag */ +#define _LESENSE_IFC_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8_DEFAULT (_LESENSE_IFC_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9 (0x1UL << 9) /**< Clear CH9 Interrupt Flag */ +#define _LESENSE_IFC_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9_DEFAULT (_LESENSE_IFC_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10 (0x1UL << 10) /**< Clear CH10 Interrupt Flag */ +#define _LESENSE_IFC_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10_DEFAULT (_LESENSE_IFC_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11 (0x1UL << 11) /**< Clear CH11 Interrupt Flag */ +#define _LESENSE_IFC_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11_DEFAULT (_LESENSE_IFC_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12 (0x1UL << 12) /**< Clear CH12 Interrupt Flag */ +#define _LESENSE_IFC_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12_DEFAULT (_LESENSE_IFC_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13 (0x1UL << 13) /**< Clear CH13 Interrupt Flag */ +#define _LESENSE_IFC_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13_DEFAULT (_LESENSE_IFC_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14 (0x1UL << 14) /**< Clear CH14 Interrupt Flag */ +#define _LESENSE_IFC_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14_DEFAULT (_LESENSE_IFC_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15 (0x1UL << 15) /**< Clear CH15 Interrupt Flag */ +#define _LESENSE_IFC_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15_DEFAULT (_LESENSE_IFC_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE (0x1UL << 16) /**< Clear SCANCOMPLETE Interrupt Flag */ +#define _LESENSE_IFC_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE_DEFAULT (_LESENSE_IFC_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC (0x1UL << 17) /**< Clear DEC Interrupt Flag */ +#define _LESENSE_IFC_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC_DEFAULT (_LESENSE_IFC_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR (0x1UL << 18) /**< Clear DECERR Interrupt Flag */ +#define _LESENSE_IFC_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR_DEFAULT (_LESENSE_IFC_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV (0x1UL << 19) /**< Clear BUFDATAV Interrupt Flag */ +#define _LESENSE_IFC_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV_DEFAULT (_LESENSE_IFC_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL (0x1UL << 20) /**< Clear BUFLEVEL Interrupt Flag */ +#define _LESENSE_IFC_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL_DEFAULT (_LESENSE_IFC_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF (0x1UL << 21) /**< Clear BUFOF Interrupt Flag */ +#define _LESENSE_IFC_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF_DEFAULT (_LESENSE_IFC_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF (0x1UL << 22) /**< Clear CNTOF Interrupt Flag */ +#define _LESENSE_IFC_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF_DEFAULT (_LESENSE_IFC_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFC */ + +/* Bit fields for LESENSE IEN */ +#define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */ +#define _LESENSE_IEN_MASK 0x007FFFFFUL /**< Mask for LESENSE_IEN */ +#define LESENSE_IEN_CH0 (0x1UL << 0) /**< CH0 Interrupt Enable */ +#define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1 (0x1UL << 1) /**< CH1 Interrupt Enable */ +#define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2 (0x1UL << 2) /**< CH2 Interrupt Enable */ +#define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3 (0x1UL << 3) /**< CH3 Interrupt Enable */ +#define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4 (0x1UL << 4) /**< CH4 Interrupt Enable */ +#define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5 (0x1UL << 5) /**< CH5 Interrupt Enable */ +#define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6 (0x1UL << 6) /**< CH6 Interrupt Enable */ +#define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7 (0x1UL << 7) /**< CH7 Interrupt Enable */ +#define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8 (0x1UL << 8) /**< CH8 Interrupt Enable */ +#define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9 (0x1UL << 9) /**< CH9 Interrupt Enable */ +#define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10 (0x1UL << 10) /**< CH10 Interrupt Enable */ +#define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11 (0x1UL << 11) /**< CH11 Interrupt Enable */ +#define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12 (0x1UL << 12) /**< CH12 Interrupt Enable */ +#define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13 (0x1UL << 13) /**< CH13 Interrupt Enable */ +#define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14 (0x1UL << 14) /**< CH14 Interrupt Enable */ +#define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15 (0x1UL << 15) /**< CH15 Interrupt Enable */ +#define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE Interrupt Enable */ +#define _LESENSE_IEN_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE_DEFAULT (_LESENSE_IEN_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC (0x1UL << 17) /**< DEC Interrupt Enable */ +#define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR (0x1UL << 18) /**< DECERR Interrupt Enable */ +#define _LESENSE_IEN_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR_DEFAULT (_LESENSE_IEN_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV (0x1UL << 19) /**< BUFDATAV Interrupt Enable */ +#define _LESENSE_IEN_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV_DEFAULT (_LESENSE_IEN_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL Interrupt Enable */ +#define _LESENSE_IEN_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL_DEFAULT (_LESENSE_IEN_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF (0x1UL << 21) /**< BUFOF Interrupt Enable */ +#define _LESENSE_IEN_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF_DEFAULT (_LESENSE_IEN_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF (0x1UL << 22) /**< CNTOF Interrupt Enable */ +#define _LESENSE_IEN_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IEN */ + +/* Bit fields for LESENSE SYNCBUSY */ +#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */ +#define _LESENSE_SYNCBUSY_MASK 0x00000080UL /**< Mask for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD (0x1UL << 7) /**< CMD Register Busy */ +#define _LESENSE_SYNCBUSY_CMD_SHIFT 7 /**< Shift value for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_MASK 0x80UL /**< Bit mask for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */ + +/* Bit fields for LESENSE ROUTEPEN */ +#define _LESENSE_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ROUTEPEN */ +#define _LESENSE_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for LESENSE_CH0PEN */ +#define _LESENSE_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for LESENSE_CH0PEN */ +#define _LESENSE_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH0PEN_DEFAULT (_LESENSE_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH0 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for LESENSE_CH1PEN */ +#define _LESENSE_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for LESENSE_CH1PEN */ +#define _LESENSE_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH1PEN_DEFAULT (_LESENSE_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for LESENSE_CH2PEN */ +#define _LESENSE_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for LESENSE_CH2PEN */ +#define _LESENSE_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH2PEN_DEFAULT (_LESENSE_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for LESENSE_CH3PEN */ +#define _LESENSE_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for LESENSE_CH3PEN */ +#define _LESENSE_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH3PEN_DEFAULT (_LESENSE_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for LESENSE_CH4PEN */ +#define _LESENSE_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for LESENSE_CH4PEN */ +#define _LESENSE_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH4PEN_DEFAULT (_LESENSE_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for LESENSE_CH5PEN */ +#define _LESENSE_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for LESENSE_CH5PEN */ +#define _LESENSE_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH5PEN_DEFAULT (_LESENSE_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for LESENSE_CH6PEN */ +#define _LESENSE_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for LESENSE_CH6PEN */ +#define _LESENSE_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH6PEN_DEFAULT (_LESENSE_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for LESENSE_CH7PEN */ +#define _LESENSE_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for LESENSE_CH7PEN */ +#define _LESENSE_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH7PEN_DEFAULT (_LESENSE_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for LESENSE_CH8PEN */ +#define _LESENSE_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for LESENSE_CH8PEN */ +#define _LESENSE_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH8PEN_DEFAULT (_LESENSE_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for LESENSE_CH9PEN */ +#define _LESENSE_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for LESENSE_CH9PEN */ +#define _LESENSE_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH9PEN_DEFAULT (_LESENSE_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for LESENSE_CH10PEN */ +#define _LESENSE_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for LESENSE_CH10PEN */ +#define _LESENSE_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH10PEN_DEFAULT (_LESENSE_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for LESENSE_CH11PEN */ +#define _LESENSE_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for LESENSE_CH11PEN */ +#define _LESENSE_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH11PEN_DEFAULT (_LESENSE_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for LESENSE_CH12PEN */ +#define _LESENSE_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for LESENSE_CH12PEN */ +#define _LESENSE_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH12PEN_DEFAULT (_LESENSE_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for LESENSE_CH13PEN */ +#define _LESENSE_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for LESENSE_CH13PEN */ +#define _LESENSE_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH13PEN_DEFAULT (_LESENSE_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for LESENSE_CH14PEN */ +#define _LESENSE_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for LESENSE_CH14PEN */ +#define _LESENSE_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH14PEN_DEFAULT (_LESENSE_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for LESENSE_CH15PEN */ +#define _LESENSE_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for LESENSE_CH15PEN */ +#define _LESENSE_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH15PEN_DEFAULT (_LESENSE_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX0PEN (0x1UL << 16) /**< ALTEX0 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_SHIFT 16 /**< Shift value for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_MASK 0x10000UL /**< Bit mask for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX1PEN (0x1UL << 17) /**< ALTEX1 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_SHIFT 17 /**< Shift value for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_MASK 0x20000UL /**< Bit mask for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX2PEN (0x1UL << 18) /**< ALTEX2 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_SHIFT 18 /**< Shift value for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX3PEN (0x1UL << 19) /**< ALTEX3 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_SHIFT 19 /**< Shift value for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_MASK 0x80000UL /**< Bit mask for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX4PEN (0x1UL << 20) /**< ALTEX4 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_SHIFT 20 /**< Shift value for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_MASK 0x100000UL /**< Bit mask for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX5PEN (0x1UL << 21) /**< ALTEX5 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_SHIFT 21 /**< Shift value for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX6PEN (0x1UL << 22) /**< ALTEX6 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_SHIFT 22 /**< Shift value for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_MASK 0x400000UL /**< Bit mask for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX7PEN (0x1UL << 23) /**< ALTEX7 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_SHIFT 23 /**< Shift value for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_MASK 0x800000UL /**< Bit mask for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ + +/* Bit fields for LESENSE ST_TCONFA */ +#define _LESENSE_ST_TCONFA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK 0x0007DFFFUL /**< Mask for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_COMP_DEFAULT (_LESENSE_ST_TCONFA_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_MASK_DEFAULT (_LESENSE_ST_TCONFA_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN (0x1UL << 14) /**< Enable state descriptor chaining */ +#define _LESENSE_ST_TCONFA_CHAIN_SHIFT 14 /**< Shift value for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_MASK 0x4000UL /**< Bit mask for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN_DEFAULT (_LESENSE_ST_TCONFA_CHAIN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF (0x1UL << 15) /**< Set interrupt flag enable */ +#define _LESENSE_ST_TCONFA_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF_DEFAULT (_LESENSE_ST_TCONFA_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */ + +/* Bit fields for LESENSE ST_TCONFB */ +#define _LESENSE_ST_TCONFB_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK 0x00079FFFUL /**< Mask for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_COMP_DEFAULT (_LESENSE_ST_TCONFB_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_MASK_DEFAULT (_LESENSE_ST_TCONFB_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF (0x1UL << 15) /**< Set interrupt flag */ +#define _LESENSE_ST_TCONFB_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF_DEFAULT (_LESENSE_ST_TCONFB_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */ + +/* Bit fields for LESENSE BUF_DATA */ +#define _LESENSE_BUF_DATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_DATA_SHIFT 0 /**< Shift value for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ +#define LESENSE_BUF_DATA_DATA_DEFAULT (_LESENSE_BUF_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_DATASRC_SHIFT 16 /**< Shift value for LESENSE_DATASRC */ +#define _LESENSE_BUF_DATA_DATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_DATASRC */ +#define _LESENSE_BUF_DATA_DATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ +#define LESENSE_BUF_DATA_DATASRC_DEFAULT (_LESENSE_BUF_DATA_DATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ + +/* Bit fields for LESENSE CH_TIMING */ +#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ + +/* Bit fields for LESENSE CH_INTERACT */ +#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_MASK 0x003FFFFFUL /**< Mask for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 12 /**< Shift value for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x3000UL /**< Bit mask for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 12) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 12) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 12) /**< Shifted mode ADC for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 12) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_SHIFT 14 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_MASK 0x1C000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 14) /**< Shifted mode NONE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 14) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 14) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 14) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 14) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 17 /**< Shift value for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x60000UL /**< Bit mask for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 17) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 17) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 17) /**< Shifted mode LOW for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 17) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 19) /**< Select clock used for excitation timing */ +#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 19 /**< Shift value for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x80000UL /**< Bit mask for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 20) /**< Select clock used for timing of sample delay */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 20 /**< Shift value for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x100000UL /**< Bit mask for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 21) /**< Use alternative excite pin */ +#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 21 /**< Shift value for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ + +/* Bit fields for LESENSE CH_EVAL */ +#define _LESENSE_CH_EVAL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MASK 0x007FFFFFUL /**< Mask for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMPTHRES_SHIFT 0 /**< Shift value for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMPTHRES_DEFAULT (_LESENSE_CH_EVAL_COMPTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP (0x1UL << 16) /**< Select mode for threshold comparison */ +#define _LESENSE_CH_EVAL_COMP_SHIFT 16 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_MASK 0x10000UL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_DEFAULT (_LESENSE_CH_EVAL_COMP_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_LESS (_LESENSE_CH_EVAL_COMP_LESS << 16) /**< Shifted mode LESS for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_GE (_LESENSE_CH_EVAL_COMP_GE << 16) /**< Shifted mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE (0x1UL << 17) /**< Send result to decoder */ +#define _LESENSE_CH_EVAL_DECODE_SHIFT 17 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_MASK 0x20000UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE_DEFAULT (_LESENSE_CH_EVAL_DECODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_SHIFT 18 /**< Shift value for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_MASK 0xC0000UL /**< Bit mask for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DEFAULT (_LESENSE_CH_EVAL_STRSAMPLE_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DISABLE (_LESENSE_CH_EVAL_STRSAMPLE_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DATA (_LESENSE_CH_EVAL_STRSAMPLE_DATA << 18) /**< Shifted mode DATA for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DATASRC (_LESENSE_CH_EVAL_STRSAMPLE_DATASRC << 18) /**< Shifted mode DATASRC for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV (0x1UL << 20) /**< Enable inversion of result */ +#define _LESENSE_CH_EVAL_SCANRESINV_SHIFT 20 /**< Shift value for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_MASK 0x100000UL /**< Bit mask for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV_DEFAULT (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_SHIFT 21 /**< Shift value for LESENSE_MODE */ +#define _LESENSE_CH_EVAL_MODE_MASK 0x600000UL /**< Bit mask for LESENSE_MODE */ +#define _LESENSE_CH_EVAL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_DEFAULT (_LESENSE_CH_EVAL_MODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_THRES (_LESENSE_CH_EVAL_MODE_THRES << 21) /**< Shifted mode THRES for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_SLIDINGWIN (_LESENSE_CH_EVAL_MODE_SLIDINGWIN << 21) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_STEPDET (_LESENSE_CH_EVAL_MODE_STEPDET << 21) /**< Shifted mode STEPDET for LESENSE_CH_EVAL */ + +/** @} End of group EFR32MG12P_LESENSE */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_buf.h new file mode 100644 index 00000000000..79c905dcbaf --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_buf.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efr32mg12p_lesense_buf.h + * @brief EFR32MG12P_LESENSE_BUF register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_BUF EFR32MG12P LESENSE BUF + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t DATA; /**< Scan results */ +} LESENSE_BUF_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_ch.h new file mode 100644 index 00000000000..d4f4be40180 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_ch.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efr32mg12p_lesense_ch.h + * @brief EFR32MG12P_LESENSE_CH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_CH EFR32MG12P LESENSE CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t TIMING; /**< Scan configuration */ + __IOM uint32_t INTERACT; /**< Scan configuration */ + __IOM uint32_t EVAL; /**< Scan configuration */ + uint32_t RESERVED0[1]; /**< Reserved future */ +} LESENSE_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_st.h new file mode 100644 index 00000000000..5a2346bc0d9 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_st.h @@ -0,0 +1,47 @@ +/**************************************************************************//** + * @file efr32mg12p_lesense_st.h + * @brief EFR32MG12P_LESENSE_ST register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_ST EFR32MG12P LESENSE ST + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t TCONFA; /**< State transition configuration A */ + __IOM uint32_t TCONFB; /**< State transition configuration B */ +} LESENSE_ST_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_letimer.h new file mode 100644 index 00000000000..1ceccc3c887 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_letimer.h @@ -0,0 +1,620 @@ +/**************************************************************************//** + * @file efr32mg12p_letimer.h + * @brief EFR32MG12P_LETIMER register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_LETIMER + * @{ + * @brief EFR32MG12P_LETIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IOM uint32_t PRSSEL; /**< PRS Input Select Register */ +} LETIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_LETIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000013FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IFS */ +#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */ +#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */ +#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set COMP0 Interrupt Flag */ +#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set COMP1 Interrupt Flag */ +#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF (0x1UL << 2) /**< Set UF Interrupt Flag */ +#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set REP0 Interrupt Flag */ +#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set REP1 Interrupt Flag */ +#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */ + +/* Bit fields for LETIMER IFC */ +#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */ +#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */ +#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear COMP0 Interrupt Flag */ +#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear COMP1 Interrupt Flag */ +#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear UF Interrupt Flag */ +#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear REP0 Interrupt Flag */ +#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear REP1 Interrupt Flag */ +#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< COMP0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< COMP1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< UF Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< REP0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< REP1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x00000002UL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER ROUTEPEN */ +#define _LETIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTEPEN */ +#define _LETIMER_ROUTEPEN_MASK 0x00000003UL /**< Mask for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */ +#define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTEPEN_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */ +#define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTEPEN_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ + +/* Bit fields for LETIMER ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT 0 /**< Shift value for LETIMER_OUT0LOC */ +#define _LETIMER_ROUTELOC0_OUT0LOC_MASK 0x1FUL /**< Bit mask for LETIMER_OUT0LOC */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC0 (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC1 (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC2 (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC3 (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC4 (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC5 (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC6 (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC7 (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC8 (_LETIMER_ROUTELOC0_OUT0LOC_LOC8 << 0) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC9 (_LETIMER_ROUTELOC0_OUT0LOC_LOC9 << 0) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC10 (_LETIMER_ROUTELOC0_OUT0LOC_LOC10 << 0) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC11 (_LETIMER_ROUTELOC0_OUT0LOC_LOC11 << 0) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC12 (_LETIMER_ROUTELOC0_OUT0LOC_LOC12 << 0) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC13 (_LETIMER_ROUTELOC0_OUT0LOC_LOC13 << 0) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC14 (_LETIMER_ROUTELOC0_OUT0LOC_LOC14 << 0) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC15 (_LETIMER_ROUTELOC0_OUT0LOC_LOC15 << 0) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC16 (_LETIMER_ROUTELOC0_OUT0LOC_LOC16 << 0) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC17 (_LETIMER_ROUTELOC0_OUT0LOC_LOC17 << 0) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC18 (_LETIMER_ROUTELOC0_OUT0LOC_LOC18 << 0) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC19 (_LETIMER_ROUTELOC0_OUT0LOC_LOC19 << 0) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC20 (_LETIMER_ROUTELOC0_OUT0LOC_LOC20 << 0) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC21 (_LETIMER_ROUTELOC0_OUT0LOC_LOC21 << 0) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC22 (_LETIMER_ROUTELOC0_OUT0LOC_LOC22 << 0) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC23 (_LETIMER_ROUTELOC0_OUT0LOC_LOC23 << 0) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC24 (_LETIMER_ROUTELOC0_OUT0LOC_LOC24 << 0) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC25 (_LETIMER_ROUTELOC0_OUT0LOC_LOC25 << 0) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC26 (_LETIMER_ROUTELOC0_OUT0LOC_LOC26 << 0) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC27 (_LETIMER_ROUTELOC0_OUT0LOC_LOC27 << 0) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC28 (_LETIMER_ROUTELOC0_OUT0LOC_LOC28 << 0) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC29 (_LETIMER_ROUTELOC0_OUT0LOC_LOC29 << 0) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC30 (_LETIMER_ROUTELOC0_OUT0LOC_LOC30 << 0) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC31 (_LETIMER_ROUTELOC0_OUT0LOC_LOC31 << 0) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT 8 /**< Shift value for LETIMER_OUT1LOC */ +#define _LETIMER_ROUTELOC0_OUT1LOC_MASK 0x1F00UL /**< Bit mask for LETIMER_OUT1LOC */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC0 (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC1 (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC2 (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC3 (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC4 (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC5 (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC6 (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC7 (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC8 (_LETIMER_ROUTELOC0_OUT1LOC_LOC8 << 8) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC9 (_LETIMER_ROUTELOC0_OUT1LOC_LOC9 << 8) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC10 (_LETIMER_ROUTELOC0_OUT1LOC_LOC10 << 8) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC11 (_LETIMER_ROUTELOC0_OUT1LOC_LOC11 << 8) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC12 (_LETIMER_ROUTELOC0_OUT1LOC_LOC12 << 8) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC13 (_LETIMER_ROUTELOC0_OUT1LOC_LOC13 << 8) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC14 (_LETIMER_ROUTELOC0_OUT1LOC_LOC14 << 8) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC15 (_LETIMER_ROUTELOC0_OUT1LOC_LOC15 << 8) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC16 (_LETIMER_ROUTELOC0_OUT1LOC_LOC16 << 8) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC17 (_LETIMER_ROUTELOC0_OUT1LOC_LOC17 << 8) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC18 (_LETIMER_ROUTELOC0_OUT1LOC_LOC18 << 8) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC19 (_LETIMER_ROUTELOC0_OUT1LOC_LOC19 << 8) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC20 (_LETIMER_ROUTELOC0_OUT1LOC_LOC20 << 8) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC21 (_LETIMER_ROUTELOC0_OUT1LOC_LOC21 << 8) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC22 (_LETIMER_ROUTELOC0_OUT1LOC_LOC22 << 8) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC23 (_LETIMER_ROUTELOC0_OUT1LOC_LOC23 << 8) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC24 (_LETIMER_ROUTELOC0_OUT1LOC_LOC24 << 8) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC25 (_LETIMER_ROUTELOC0_OUT1LOC_LOC25 << 8) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC26 (_LETIMER_ROUTELOC0_OUT1LOC_LOC26 << 8) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC27 (_LETIMER_ROUTELOC0_OUT1LOC_LOC27 << 8) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC28 (_LETIMER_ROUTELOC0_OUT1LOC_LOC28 << 8) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC29 (_LETIMER_ROUTELOC0_OUT1LOC_LOC29 << 8) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC30 (_LETIMER_ROUTELOC0_OUT1LOC_LOC30 << 8) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC31 (_LETIMER_ROUTELOC0_OUT1LOC_LOC31 << 8) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */ + +/* Bit fields for LETIMER PRSSEL */ +#define _LETIMER_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_MASK 0x0CCCF3CFUL /**< Mask for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT 0 /**< Shift value for LETIMER_PRSSTARTSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_MASK 0xFUL /**< Bit mask for LETIMER_PRSSTARTSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT 6 /**< Shift value for LETIMER_PRSSTOPSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_MASK 0x3C0UL /**< Bit mask for LETIMER_PRSSTOPSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT 12 /**< Shift value for LETIMER_PRSCLEARSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_MASK 0xF000UL /**< Bit mask for LETIMER_PRSCLEARSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_NONE (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_RISING (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_FALLING (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_BOTH (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_NONE (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_RISING (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_FALLING (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_BOTH (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_NONE (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_RISING (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */ + +/** @} End of group EFR32MG12P_LETIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_leuart.h new file mode 100644 index 00000000000..f6bf221ac98 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_leuart.h @@ -0,0 +1,835 @@ +/**************************************************************************//** + * @file efr32mg12p_leuart.h + * @brief EFR32MG12P_LEUART register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_LEUART + * @{ + * @brief EFR32MG12P_LEUART Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IOM uint32_t STARTFRAME; /**< Start Frame Register */ + __IOM uint32_t SIGFRAME; /**< Signal Frame Register */ + __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */ + __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PULSECTRL; /**< Pulse Control Register */ + + __IOM uint32_t FREEZE; /**< Freeze Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t INPUT; /**< LEUART Input Register */ +} LEUART_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_LEUART_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LEUART CTRL */ +#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */ +#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */ +#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */ +#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */ +#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */ +#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */ +#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */ +#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */ +#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */ +#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */ +#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */ +#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */ +#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */ +#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */ +#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */ +#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */ +#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */ +#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */ +#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */ +#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */ +#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */ +#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */ +#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */ +#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */ +#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */ +#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */ +#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */ +#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */ +#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */ +#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */ +#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */ +#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */ +#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */ +#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */ +#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */ +#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */ +#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */ +#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */ +#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */ +#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */ +#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */ +#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */ +#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */ +#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */ + +/* Bit fields for LEUART CMD */ +#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */ +#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */ +#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */ +#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */ +#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */ +#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */ +#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */ +#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */ +#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */ +#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */ +#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */ +#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */ +#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */ +#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */ +#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */ +#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */ +#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */ +#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */ +#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */ +#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */ + +/* Bit fields for LEUART STATUS */ +#define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */ +#define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */ +#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */ +#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */ +#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */ +#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */ +#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */ +#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */ +#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */ +#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */ +#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */ +#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */ +#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */ +#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */ +#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */ +#define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */ +#define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */ +#define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */ + +/* Bit fields for LEUART CLKDIV */ +#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */ +#define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */ +#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */ +#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */ + +/* Bit fields for LEUART STARTFRAME */ +#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */ +#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */ + +/* Bit fields for LEUART SIGFRAME */ +#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */ +#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */ + +/* Bit fields for LEUART RXDATAX */ +#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */ +#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */ +#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */ +#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */ +#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */ +#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ + +/* Bit fields for LEUART RXDATA */ +#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */ +#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */ +#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */ + +/* Bit fields for LEUART RXDATAXP */ +#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */ +#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */ +#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */ +#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */ +#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */ +#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */ +#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */ +#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */ +#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ + +/* Bit fields for LEUART TXDATAX */ +#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */ +#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */ +#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */ +#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */ +#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */ +#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */ +#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */ +#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ + +/* Bit fields for LEUART TXDATA */ +#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */ +#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */ +#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */ + +/* Bit fields for LEUART IF */ +#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */ +#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */ +#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */ +#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */ +#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */ +#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */ +#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */ +#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */ +#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */ +#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */ + +/* Bit fields for LEUART IFS */ +#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */ +#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */ +#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ +#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */ +#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */ +#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */ +#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */ +#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */ +#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */ +#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */ +#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */ +#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */ + +/* Bit fields for LEUART IFC */ +#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */ +#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */ +#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ +#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */ +#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */ +#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */ +#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */ +#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */ +#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */ +#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */ +#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */ +#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */ + +/* Bit fields for LEUART IEN */ +#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */ +#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */ +#define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ +#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ +#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ +#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */ +#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */ +#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */ +#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */ +#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */ +#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */ +#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */ +#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */ +#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */ + +/* Bit fields for LEUART PULSECTRL */ +#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */ +#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */ +#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */ +#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */ +#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */ +#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */ +#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */ +#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */ +#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ + +/* Bit fields for LEUART FREEZE */ +#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */ +#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */ +#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */ +#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */ + +/* Bit fields for LEUART SYNCBUSY */ +#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */ +#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */ +#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */ +#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */ +#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */ +#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */ +#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */ +#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */ +#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */ +#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */ +#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */ +#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */ +#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */ +#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */ +#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */ +#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */ +#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */ +#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */ +#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ + +/* Bit fields for LEUART ROUTEPEN */ +#define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */ +#define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ +#define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */ +#define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */ +#define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ +#define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */ +#define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */ +#define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ + +/* Bit fields for LEUART ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */ +#define _LEUART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for LEUART_RXLOC */ +#define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC6 (_LEUART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC7 (_LEUART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC8 (_LEUART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC9 (_LEUART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC10 (_LEUART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC11 (_LEUART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC12 (_LEUART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC13 (_LEUART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC14 (_LEUART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC15 (_LEUART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC16 (_LEUART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC17 (_LEUART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC18 (_LEUART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC19 (_LEUART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC20 (_LEUART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC21 (_LEUART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC22 (_LEUART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC23 (_LEUART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC24 (_LEUART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC25 (_LEUART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC26 (_LEUART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC27 (_LEUART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC28 (_LEUART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC29 (_LEUART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC30 (_LEUART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC31 (_LEUART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */ +#define _LEUART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for LEUART_TXLOC */ +#define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC6 (_LEUART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC7 (_LEUART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC8 (_LEUART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC9 (_LEUART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC10 (_LEUART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC11 (_LEUART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC12 (_LEUART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC13 (_LEUART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC14 (_LEUART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC15 (_LEUART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC16 (_LEUART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC17 (_LEUART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC18 (_LEUART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC19 (_LEUART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC20 (_LEUART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC21 (_LEUART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC22 (_LEUART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC23 (_LEUART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC24 (_LEUART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC25 (_LEUART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC26 (_LEUART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC27 (_LEUART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC28 (_LEUART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC29 (_LEUART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC30 (_LEUART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC31 (_LEUART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ + +/* Bit fields for LEUART INPUT */ +#define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */ +#define _LEUART_INPUT_MASK 0x0000002FUL /**< Mask for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */ +#define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */ +#define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */ +#define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */ +#define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */ +#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ +#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */ + +/** @} End of group EFR32MG12P_LEUART */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_msc.h new file mode 100644 index 00000000000..a9e27c6615e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_msc.h @@ -0,0 +1,664 @@ +/**************************************************************************//** + * @file efr32mg12p_msc.h + * @brief EFR32MG12P_MSC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_MSC + * @{ + * @brief EFR32MG12P_MSC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader read and write enable, write once register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control enable Register */ +} MSC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_MSC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000001FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up On Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass erase region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x0000017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< iCache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash controller write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x0000017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x0000017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x0000017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Enable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Eanble */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software unlock AAP command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00090101UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMCACHEEN (0x1UL << 0) /**< RAM CACHE Enable */ +#define _MSC_RAMCTRL_RAMCACHEEN_SHIFT 0 /**< Shift value for MSC_RAMCACHEEN */ +#define _MSC_RAMCTRL_RAMCACHEEN_MASK 0x1UL /**< Bit mask for MSC_RAMCACHEEN */ +#define _MSC_RAMCTRL_RAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMCACHEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1CACHEEN (0x1UL << 8) /**< RAM1 CACHE Enable */ +#define _MSC_RAMCTRL_RAM1CACHEEN_SHIFT 8 /**< Shift value for MSC_RAM1CACHEEN */ +#define _MSC_RAMCTRL_RAM1CACHEEN_MASK 0x100UL /**< Bit mask for MSC_RAM1CACHEEN */ +#define _MSC_RAMCTRL_RAM1CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM1CACHEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMSEQCACHEEN (0x1UL << 19) /**< RAMSEQ CACHE Enable */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_SHIFT 19 /**< Shift value for MSC_RAMSEQCACHEEN */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_MASK 0x80000UL /**< Bit mask for MSC_RAMSEQCACHEEN */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/** @} End of group EFR32MG12P_MSC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_pcnt.h new file mode 100644 index 00000000000..817768f6175 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_pcnt.h @@ -0,0 +1,706 @@ +/**************************************************************************//** + * @file efr32mg12p_pcnt.h + * @brief EFR32MG12P_PCNT register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_PCNT + * @{ + * @brief EFR32MG12P_PCNT Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t TOP; /**< Top Value Register */ + __IOM uint32_t TOPB; /**< Top Value Buffer Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t FREEZE; /**< Freeze Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED2[7]; /**< Reserved for future use **/ + __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ + __IOM uint32_t INPUT; /**< PCNT Input Register */ + __IOM uint32_t OVSCFG; /**< Oversampling Config Register */ +} PCNT_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_PCNT_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for PCNT CTRL */ +#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ +#define _PCNT_CTRL_MASK 0xBFDBFFFFUL /**< Mask for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ +#define _PCNT_CTRL_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ +#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD1X 0x00000004UL /**< Mode OVSQUAD1X for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD2X 0x00000005UL /**< Mode OVSQUAD2X for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD4X 0x00000006UL /**< Mode OVSQUAD4X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD1X (_PCNT_CTRL_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD2X (_PCNT_CTRL_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD4X (_PCNT_CTRL_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CTRL */ +#define PCNT_CTRL_FILT (0x1UL << 3) /**< Enable Digital Pulse Width Filter */ +#define _PCNT_CTRL_FILT_SHIFT 3 /**< Shift value for PCNT_FILT */ +#define _PCNT_CTRL_FILT_MASK 0x8UL /**< Bit mask for PCNT_FILT */ +#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN (0x1UL << 4) /**< Enable PCNT Clock Domain Reset */ +#define _PCNT_CTRL_RSTEN_SHIFT 4 /**< Shift value for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_MASK 0x10UL /**< Bit mask for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTRSTEN (0x1UL << 5) /**< Enable CNT Reset */ +#define _PCNT_CTRL_CNTRSTEN_SHIFT 5 /**< Shift value for PCNT_CNTRSTEN */ +#define _PCNT_CTRL_CNTRSTEN_MASK 0x20UL /**< Bit mask for PCNT_CNTRSTEN */ +#define _PCNT_CTRL_CNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTRSTEN_DEFAULT (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTRSTEN (0x1UL << 6) /**< Enable AUXCNT Reset */ +#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT 6 /**< Shift value for PCNT_AUXCNTRSTEN */ +#define _PCNT_CTRL_AUXCNTRSTEN_MASK 0x40UL /**< Bit mask for PCNT_AUXCNTRSTEN */ +#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_DEBUGHALT (0x1UL << 7) /**< Debug Mode Halt Enable */ +#define _PCNT_CTRL_DEBUGHALT_SHIFT 7 /**< Shift value for PCNT_DEBUGHALT */ +#define _PCNT_CTRL_DEBUGHALT_MASK 0x80UL /**< Bit mask for PCNT_DEBUGHALT */ +#define _PCNT_CTRL_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_DEBUGHALT_DEFAULT (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */ +#define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */ +#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */ +#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count direction determined by S1 */ +#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_SHIFT 12 /**< Shift value for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_MASK 0x3000UL /**< Bit mask for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 12) /**< Shifted mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 12) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 12) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 12) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR (0x1UL << 14) /**< Non-Quadrature Mode Counter Direction Control */ +#define _PCNT_CTRL_CNTDIR_SHIFT 14 /**< Shift value for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_MASK 0x4000UL /**< Bit mask for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 14) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_EDGE (0x1UL << 15) /**< Edge Select */ +#define _PCNT_CTRL_EDGE_SHIFT 15 /**< Shift value for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_MASK 0x8000UL /**< Bit mask for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 15) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 15) /**< Shifted mode POS for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 15) /**< Shifted mode NEG for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_SHIFT 16 /**< Shift value for PCNT_TCCMODE */ +#define _PCNT_CTRL_TCCMODE_MASK 0x30000UL /**< Bit mask for PCNT_TCCMODE */ +#define _PCNT_CTRL_TCCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_DISABLED 0x00000000UL /**< Mode DISABLED for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_LFA 0x00000001UL /**< Mode LFA for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_PRS 0x00000002UL /**< Mode PRS for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_DEFAULT (_PCNT_CTRL_TCCMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_DISABLED (_PCNT_CTRL_TCCMODE_DISABLED << 16) /**< Shifted mode DISABLED for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_LFA (_PCNT_CTRL_TCCMODE_LFA << 16) /**< Shifted mode LFA for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_PRS (_PCNT_CTRL_TCCMODE_PRS << 16) /**< Shifted mode PRS for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_SHIFT 19 /**< Shift value for PCNT_TCCPRESC */ +#define _PCNT_CTRL_TCCPRESC_MASK 0x180000UL /**< Bit mask for PCNT_TCCPRESC */ +#define _PCNT_CTRL_TCCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DEFAULT (_PCNT_CTRL_TCCPRESC_DEFAULT << 19) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV1 (_PCNT_CTRL_TCCPRESC_DIV1 << 19) /**< Shifted mode DIV1 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV2 (_PCNT_CTRL_TCCPRESC_DIV2 << 19) /**< Shifted mode DIV2 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV4 (_PCNT_CTRL_TCCPRESC_DIV4 << 19) /**< Shifted mode DIV4 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV8 (_PCNT_CTRL_TCCPRESC_DIV8 << 19) /**< Shifted mode DIV8 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_SHIFT 22 /**< Shift value for PCNT_TCCCOMP */ +#define _PCNT_CTRL_TCCCOMP_MASK 0xC00000UL /**< Bit mask for PCNT_TCCCOMP */ +#define _PCNT_CTRL_TCCCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_LTOE 0x00000000UL /**< Mode LTOE for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_GTOE 0x00000001UL /**< Mode GTOE for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_RANGE 0x00000002UL /**< Mode RANGE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_DEFAULT (_PCNT_CTRL_TCCCOMP_DEFAULT << 22) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */ +#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS gate enable */ +#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */ +#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */ +#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS polarity select */ +#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */ +#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */ +#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSPOL_RISING 0x00000000UL /**< Mode RISING for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSPOL_FALLING 0x00000001UL /**< Mode FALLING for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_DEFAULT (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_RISING (_PCNT_CTRL_TCCPRSPOL_RISING << 25) /**< Shifted mode RISING for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_FALLING (_PCNT_CTRL_TCCPRSPOL_FALLING << 25) /**< Shifted mode FALLING for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_SHIFT 26 /**< Shift value for PCNT_TCCPRSSEL */ +#define _PCNT_CTRL_TCCPRSSEL_MASK 0x3C000000UL /**< Bit mask for PCNT_TCCPRSSEL */ +#define _PCNT_CTRL_TCCPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_DEFAULT (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH0 (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26) /**< Shifted mode PRSCH0 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH1 (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26) /**< Shifted mode PRSCH1 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH2 (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26) /**< Shifted mode PRSCH2 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH3 (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26) /**< Shifted mode PRSCH3 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH4 (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26) /**< Shifted mode PRSCH4 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH5 (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26) /**< Shifted mode PRSCH5 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH6 (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26) /**< Shifted mode PRSCH6 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH7 (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26) /**< Shifted mode PRSCH7 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH8 (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26) /**< Shifted mode PRSCH8 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */ +#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High frequency value select */ +#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */ +#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */ +#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TOPBHFSEL_DEFAULT (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31) /**< Shifted mode DEFAULT for PCNT_CTRL */ + +/* Bit fields for PCNT CMD */ +#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ +#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */ +#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */ +#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */ +#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ + +/* Bit fields for PCNT STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ + +/* Bit fields for PCNT CNT */ +#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ +#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ +#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ +#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ + +/* Bit fields for PCNT TOP */ +#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ +#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ +#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ +#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ + +/* Bit fields for PCNT TOPB */ +#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ +#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ +#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ + +/* Bit fields for PCNT IF */ +#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ +#define _PCNT_IF_MASK 0x0000003FUL /**< Mask for PCNT_IF */ +#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered compare Interrupt Read Flag */ +#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_TCC_DEFAULT (_PCNT_IF_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR (0x1UL << 5) /**< Oversampling Quadrature State Error Interrupt */ +#define _PCNT_IF_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */ + +/* Bit fields for PCNT IFS */ +#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */ +#define _PCNT_IFS_MASK 0x0000003FUL /**< Mask for PCNT_IFS */ +#define PCNT_IFS_UF (0x1UL << 0) /**< Set UF Interrupt Flag */ +#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF (0x1UL << 1) /**< Set OF Interrupt Flag */ +#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Set DIRCNG Interrupt Flag */ +#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF (0x1UL << 3) /**< Set AUXOF Interrupt Flag */ +#define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_TCC (0x1UL << 4) /**< Set TCC Interrupt Flag */ +#define _PCNT_IFS_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IFS_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IFS_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_TCC_DEFAULT (_PCNT_IFS_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OQSTERR (0x1UL << 5) /**< Set OQSTERR Interrupt Flag */ +#define _PCNT_IFS_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IFS_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IFS_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OQSTERR_DEFAULT (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */ + +/* Bit fields for PCNT IFC */ +#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */ +#define _PCNT_IFC_MASK 0x0000003FUL /**< Mask for PCNT_IFC */ +#define PCNT_IFC_UF (0x1UL << 0) /**< Clear UF Interrupt Flag */ +#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF (0x1UL << 1) /**< Clear OF Interrupt Flag */ +#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Clear DIRCNG Interrupt Flag */ +#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF (0x1UL << 3) /**< Clear AUXOF Interrupt Flag */ +#define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_TCC (0x1UL << 4) /**< Clear TCC Interrupt Flag */ +#define _PCNT_IFC_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IFC_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IFC_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_TCC_DEFAULT (_PCNT_IFC_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OQSTERR (0x1UL << 5) /**< Clear OQSTERR Interrupt Flag */ +#define _PCNT_IFC_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IFC_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IFC_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OQSTERR_DEFAULT (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */ + +/* Bit fields for PCNT IEN */ +#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ +#define _PCNT_IEN_MASK 0x0000003FUL /**< Mask for PCNT_IEN */ +#define PCNT_IEN_UF (0x1UL << 0) /**< UF Interrupt Enable */ +#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF (0x1UL << 1) /**< OF Interrupt Enable */ +#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< DIRCNG Interrupt Enable */ +#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF (0x1UL << 3) /**< AUXOF Interrupt Enable */ +#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_TCC (0x1UL << 4) /**< TCC Interrupt Enable */ +#define _PCNT_IEN_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IEN_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IEN_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_TCC_DEFAULT (_PCNT_IEN_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR (0x1UL << 5) /**< OQSTERR Interrupt Enable */ +#define _PCNT_IEN_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */ + +/* Bit fields for PCNT ROUTELOC0 */ +#define _PCNT_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_SHIFT 0 /**< Shift value for PCNT_S0INLOC */ +#define _PCNT_ROUTELOC0_S0INLOC_MASK 0x1FUL /**< Bit mask for PCNT_S0INLOC */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC0 (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_DEFAULT (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC1 (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC2 (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC3 (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC4 (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC5 (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC6 (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC7 (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC8 (_PCNT_ROUTELOC0_S0INLOC_LOC8 << 0) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC9 (_PCNT_ROUTELOC0_S0INLOC_LOC9 << 0) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC10 (_PCNT_ROUTELOC0_S0INLOC_LOC10 << 0) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC11 (_PCNT_ROUTELOC0_S0INLOC_LOC11 << 0) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC12 (_PCNT_ROUTELOC0_S0INLOC_LOC12 << 0) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC13 (_PCNT_ROUTELOC0_S0INLOC_LOC13 << 0) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC14 (_PCNT_ROUTELOC0_S0INLOC_LOC14 << 0) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC15 (_PCNT_ROUTELOC0_S0INLOC_LOC15 << 0) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC16 (_PCNT_ROUTELOC0_S0INLOC_LOC16 << 0) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC17 (_PCNT_ROUTELOC0_S0INLOC_LOC17 << 0) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC18 (_PCNT_ROUTELOC0_S0INLOC_LOC18 << 0) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC19 (_PCNT_ROUTELOC0_S0INLOC_LOC19 << 0) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC20 (_PCNT_ROUTELOC0_S0INLOC_LOC20 << 0) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC21 (_PCNT_ROUTELOC0_S0INLOC_LOC21 << 0) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC22 (_PCNT_ROUTELOC0_S0INLOC_LOC22 << 0) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC23 (_PCNT_ROUTELOC0_S0INLOC_LOC23 << 0) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC24 (_PCNT_ROUTELOC0_S0INLOC_LOC24 << 0) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC25 (_PCNT_ROUTELOC0_S0INLOC_LOC25 << 0) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC26 (_PCNT_ROUTELOC0_S0INLOC_LOC26 << 0) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC27 (_PCNT_ROUTELOC0_S0INLOC_LOC27 << 0) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC28 (_PCNT_ROUTELOC0_S0INLOC_LOC28 << 0) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC29 (_PCNT_ROUTELOC0_S0INLOC_LOC29 << 0) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC30 (_PCNT_ROUTELOC0_S0INLOC_LOC30 << 0) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC31 (_PCNT_ROUTELOC0_S0INLOC_LOC31 << 0) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_SHIFT 8 /**< Shift value for PCNT_S1INLOC */ +#define _PCNT_ROUTELOC0_S1INLOC_MASK 0x1F00UL /**< Bit mask for PCNT_S1INLOC */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC0 (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_DEFAULT (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC1 (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC2 (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC3 (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC4 (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC5 (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC6 (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC7 (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC8 (_PCNT_ROUTELOC0_S1INLOC_LOC8 << 8) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC9 (_PCNT_ROUTELOC0_S1INLOC_LOC9 << 8) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC10 (_PCNT_ROUTELOC0_S1INLOC_LOC10 << 8) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC11 (_PCNT_ROUTELOC0_S1INLOC_LOC11 << 8) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC12 (_PCNT_ROUTELOC0_S1INLOC_LOC12 << 8) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC13 (_PCNT_ROUTELOC0_S1INLOC_LOC13 << 8) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC14 (_PCNT_ROUTELOC0_S1INLOC_LOC14 << 8) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC15 (_PCNT_ROUTELOC0_S1INLOC_LOC15 << 8) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC16 (_PCNT_ROUTELOC0_S1INLOC_LOC16 << 8) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC17 (_PCNT_ROUTELOC0_S1INLOC_LOC17 << 8) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC18 (_PCNT_ROUTELOC0_S1INLOC_LOC18 << 8) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC19 (_PCNT_ROUTELOC0_S1INLOC_LOC19 << 8) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC20 (_PCNT_ROUTELOC0_S1INLOC_LOC20 << 8) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC21 (_PCNT_ROUTELOC0_S1INLOC_LOC21 << 8) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC22 (_PCNT_ROUTELOC0_S1INLOC_LOC22 << 8) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC23 (_PCNT_ROUTELOC0_S1INLOC_LOC23 << 8) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC24 (_PCNT_ROUTELOC0_S1INLOC_LOC24 << 8) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC25 (_PCNT_ROUTELOC0_S1INLOC_LOC25 << 8) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC26 (_PCNT_ROUTELOC0_S1INLOC_LOC26 << 8) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC27 (_PCNT_ROUTELOC0_S1INLOC_LOC27 << 8) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC28 (_PCNT_ROUTELOC0_S1INLOC_LOC28 << 8) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC29 (_PCNT_ROUTELOC0_S1INLOC_LOC29 << 8) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC30 (_PCNT_ROUTELOC0_S1INLOC_LOC30 << 8) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC31 (_PCNT_ROUTELOC0_S1INLOC_LOC31 << 8) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */ + +/* Bit fields for PCNT FREEZE */ +#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */ +#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */ + +/* Bit fields for PCNT SYNCBUSY */ +#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_MASK 0x0000000FUL /**< Mask for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */ +#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCFG (0x1UL << 3) /**< OVSCFG Register Busy */ +#define _PCNT_SYNCBUSY_OVSCFG_SHIFT 3 /**< Shift value for PCNT_OVSCFG */ +#define _PCNT_SYNCBUSY_OVSCFG_MASK 0x8UL /**< Bit mask for PCNT_OVSCFG */ +#define _PCNT_SYNCBUSY_OVSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCFG_DEFAULT (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ + +/* Bit fields for PCNT AUXCNT */ +#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ +#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ + +/* Bit fields for PCNT INPUT */ +#define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */ +#define _PCNT_INPUT_MASK 0x00000BEFUL /**< Mask for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /**< Bit mask for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN (0x1UL << 5) /**< S0IN PRS Enable */ +#define _PCNT_INPUT_S0PRSEN_SHIFT 5 /**< Shift value for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_MASK 0x20UL /**< Bit mask for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /**< Bit mask for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN (0x1UL << 11) /**< S1IN PRS Enable */ +#define _PCNT_INPUT_S1PRSEN_SHIFT 11 /**< Shift value for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_MASK 0x800UL /**< Bit mask for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */ + +/* Bit fields for PCNT OVSCFG */ +#define _PCNT_OVSCFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCFG */ +#define _PCNT_OVSCFG_MASK 0x000010FFUL /**< Mask for PCNT_OVSCFG */ +#define _PCNT_OVSCFG_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ +#define _PCNT_OVSCFG_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ +#define _PCNT_OVSCFG_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FILTLEN_DEFAULT (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ +#define _PCNT_OVSCFG_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ +#define _PCNT_OVSCFG_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ +#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ + +/** @} End of group EFR32MG12P_PCNT */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs.h new file mode 100644 index 00000000000..c11b41cc088 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs.h @@ -0,0 +1,1089 @@ +/**************************************************************************//** + * @file efr32mg12p_prs.h + * @brief EFR32MG12P_PRS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_PRS + * @{ + * @brief EFR32MG12P_PRS Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + + uint32_t RESERVED1[5]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3]; /**< Reserved registers */ + PRS_CH_TypeDef CH[12]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_PRS_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00000FFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x0F07070FUL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0xFUL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC4 (_PRS_ROUTELOC0_CH0LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC5 (_PRS_ROUTELOC0_CH0LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC6 (_PRS_ROUTELOC0_CH0LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC7 (_PRS_ROUTELOC0_CH0LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC8 (_PRS_ROUTELOC0_CH0LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC9 (_PRS_ROUTELOC0_CH0LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC10 (_PRS_ROUTELOC0_CH0LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC11 (_PRS_ROUTELOC0_CH0LOC_LOC11 << 0) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC12 (_PRS_ROUTELOC0_CH0LOC_LOC12 << 0) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC13 (_PRS_ROUTELOC0_CH0LOC_LOC13 << 0) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x700UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC4 (_PRS_ROUTELOC0_CH1LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC5 (_PRS_ROUTELOC0_CH1LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC6 (_PRS_ROUTELOC0_CH1LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC7 (_PRS_ROUTELOC0_CH1LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x70000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC4 (_PRS_ROUTELOC0_CH2LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC5 (_PRS_ROUTELOC0_CH2LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC6 (_PRS_ROUTELOC0_CH2LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC7 (_PRS_ROUTELOC0_CH2LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC4 (_PRS_ROUTELOC0_CH3LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC5 (_PRS_ROUTELOC0_CH3LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC6 (_PRS_ROUTELOC0_CH3LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC7 (_PRS_ROUTELOC0_CH3LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC8 (_PRS_ROUTELOC0_CH3LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC9 (_PRS_ROUTELOC0_CH3LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC10 (_PRS_ROUTELOC0_CH3LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC11 (_PRS_ROUTELOC0_CH3LOC_LOC11 << 24) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC12 (_PRS_ROUTELOC0_CH3LOC_LOC12 << 24) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC13 (_PRS_ROUTELOC0_CH3LOC_LOC13 << 24) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC14 (_PRS_ROUTELOC0_CH3LOC_LOC14 << 24) /**< Shifted mode LOC14 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x0F1F0707UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x7UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC3 (_PRS_ROUTELOC1_CH4LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC4 (_PRS_ROUTELOC1_CH4LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC5 (_PRS_ROUTELOC1_CH4LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC6 (_PRS_ROUTELOC1_CH4LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x700UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC3 (_PRS_ROUTELOC1_CH5LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC4 (_PRS_ROUTELOC1_CH5LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC5 (_PRS_ROUTELOC1_CH5LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC6 (_PRS_ROUTELOC1_CH5LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x1F0000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC17 0x00000011UL /**< Mode LOC17 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC3 (_PRS_ROUTELOC1_CH6LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC4 (_PRS_ROUTELOC1_CH6LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC5 (_PRS_ROUTELOC1_CH6LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC6 (_PRS_ROUTELOC1_CH6LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC7 (_PRS_ROUTELOC1_CH6LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC8 (_PRS_ROUTELOC1_CH6LOC_LOC8 << 16) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC9 (_PRS_ROUTELOC1_CH6LOC_LOC9 << 16) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC10 (_PRS_ROUTELOC1_CH6LOC_LOC10 << 16) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC11 (_PRS_ROUTELOC1_CH6LOC_LOC11 << 16) /**< Shifted mode LOC11 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC12 (_PRS_ROUTELOC1_CH6LOC_LOC12 << 16) /**< Shifted mode LOC12 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC13 (_PRS_ROUTELOC1_CH6LOC_LOC13 << 16) /**< Shifted mode LOC13 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC14 (_PRS_ROUTELOC1_CH6LOC_LOC14 << 16) /**< Shifted mode LOC14 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC15 (_PRS_ROUTELOC1_CH6LOC_LOC15 << 16) /**< Shifted mode LOC15 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC16 (_PRS_ROUTELOC1_CH6LOC_LOC16 << 16) /**< Shifted mode LOC16 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC17 (_PRS_ROUTELOC1_CH6LOC_LOC17 << 16) /**< Shifted mode LOC17 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC3 (_PRS_ROUTELOC1_CH7LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC4 (_PRS_ROUTELOC1_CH7LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC5 (_PRS_ROUTELOC1_CH7LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC6 (_PRS_ROUTELOC1_CH7LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC7 (_PRS_ROUTELOC1_CH7LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC8 (_PRS_ROUTELOC1_CH7LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC9 (_PRS_ROUTELOC1_CH7LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC10 (_PRS_ROUTELOC1_CH7LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x07071F0FUL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0xFUL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC3 (_PRS_ROUTELOC2_CH8LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC4 (_PRS_ROUTELOC2_CH8LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC5 (_PRS_ROUTELOC2_CH8LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC6 (_PRS_ROUTELOC2_CH8LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC7 (_PRS_ROUTELOC2_CH8LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC8 (_PRS_ROUTELOC2_CH8LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC9 (_PRS_ROUTELOC2_CH8LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC10 (_PRS_ROUTELOC2_CH8LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x1F00UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC3 (_PRS_ROUTELOC2_CH9LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC4 (_PRS_ROUTELOC2_CH9LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC5 (_PRS_ROUTELOC2_CH9LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC6 (_PRS_ROUTELOC2_CH9LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC7 (_PRS_ROUTELOC2_CH9LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC8 (_PRS_ROUTELOC2_CH9LOC_LOC8 << 8) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC9 (_PRS_ROUTELOC2_CH9LOC_LOC9 << 8) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC10 (_PRS_ROUTELOC2_CH9LOC_LOC10 << 8) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC11 (_PRS_ROUTELOC2_CH9LOC_LOC11 << 8) /**< Shifted mode LOC11 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC12 (_PRS_ROUTELOC2_CH9LOC_LOC12 << 8) /**< Shifted mode LOC12 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC13 (_PRS_ROUTELOC2_CH9LOC_LOC13 << 8) /**< Shifted mode LOC13 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC14 (_PRS_ROUTELOC2_CH9LOC_LOC14 << 8) /**< Shifted mode LOC14 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC15 (_PRS_ROUTELOC2_CH9LOC_LOC15 << 8) /**< Shifted mode LOC15 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC16 (_PRS_ROUTELOC2_CH9LOC_LOC16 << 8) /**< Shifted mode LOC16 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x70000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC3 (_PRS_ROUTELOC2_CH10LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC4 (_PRS_ROUTELOC2_CH10LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC5 (_PRS_ROUTELOC2_CH10LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x7000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC3 (_PRS_ROUTELOC2_CH11LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC4 (_PRS_ROUTELOC2_CH11LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC5 (_PRS_ROUTELOC2_CH11LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000001FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x1EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000002UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000003UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000004UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000005UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000007UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000008UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x00000009UL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000000AUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x0000000BUL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x0000000CUL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000DUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000EUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000FUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x00000010UL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x00000011UL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000012UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000018UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000001AUL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x0000003EUL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x0000003FUL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} End of group EFR32MG12P_PRS */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_ch.h new file mode 100644 index 00000000000..c94f080dd67 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_ch.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efr32mg12p_prs_ch.h + * @brief EFR32MG12P_PRS_CH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief PRS_CH EFR32MG12P PRS CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Channel Control Register */ +} PRS_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_signals.h new file mode 100644 index 00000000000..5c1686a7464 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_signals.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efr32mg12p_prs_signals.h + * @brief EFR32MG12P_PRS_SIGNALS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @addtogroup EFR32MG12P_PRS_Signals + * @{ + * @brief PRS Signal names + *****************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_ACMP0_OUT ((3 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((5 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((5 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_LESENSE_SCANRES0 ((7 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((7 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((7 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((7 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((7 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((7 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((7 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((7 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((8 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((8 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((8 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((8 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((8 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((8 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((8 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((8 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((9 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((9 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((9 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((9 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((10 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_RTCC_CCV0 ((11 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((11 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((11 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((12 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((12 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((12 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((12 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((12 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((12 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((12 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((12 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((13 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((13 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((13 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((13 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((13 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((13 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((13 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((13 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((14 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((14 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((15 << 8) + 0) /**< PRS PCNT0 Triggered compare match */ +#define PRS_PCNT0_UFOF ((15 << 8) + 1) /**< PRS PCNT0 Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((15 << 8) + 2) /**< PRS PCNT0 Counter direction */ +#define PRS_PCNT1_TCC ((16 << 8) + 0) /**< PRS PCNT1 Triggered compare match */ +#define PRS_PCNT1_UFOF ((16 << 8) + 1) /**< PRS PCNT1 Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((16 << 8) + 2) /**< PRS PCNT1 Counter direction */ +#define PRS_PCNT2_TCC ((17 << 8) + 0) /**< PRS PCNT2 Triggered compare match */ +#define PRS_PCNT2_UFOF ((17 << 8) + 1) /**< PRS PCNT2 Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((17 << 8) + 2) /**< PRS PCNT2 Counter direction */ +#define PRS_CMU_CLKOUT0 ((18 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((18 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_VDAC0_CH0 ((24 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((24 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((24 << 8) + 2) /**< PRS OPA0 warmedup or outputvalid based on OPA0PRSOUTMODE mode in OPACTRL. */ +#define PRS_VDAC0_OPA1 ((24 << 8) + 3) /**< PRS OPA1 warmedup or outputvalid based on OPA1PRSOUTMODE mode in OPACTRL. */ +#define PRS_VDAC0_OPA2 ((24 << 8) + 4) /**< PRS OPA2 warmedup or outputvalid based on OPA2PRSOUTMODE mode in OPACTRL. */ +#define PRS_CRYOTIMER_PERIOD ((26 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS USART 0 IRDA out */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS USART 0 TX complete */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS USART 0 RX Data Valid */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS USART 0 RTS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS USART 0 TX */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS USART 0 CS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS USART 1 TX complete */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS USART 1 RX Data Valid */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS USART 1 RTS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS USART 1 TX */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS USART 1 CS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS USART 2 TX complete */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS USART 2 RX Data Valid */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS USART 2 RTS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS USART 2 TX */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS USART 2 CS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS USART 3 TX complete */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS USART 3 RX Data Valid */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS USART 3 RTS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS USART 3 TX */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS USART 3 CS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS Timer 0 Underflow */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS Timer 0 Overflow */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS Timer 1 Underflow */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS Timer 1 Overflow */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */ +#define PRS_WTIMER0_UF ((62 << 8) + 0) /**< PRS Timer 2 Underflow */ +#define PRS_WTIMER0_OF ((62 << 8) + 1) /**< PRS Timer 2 Overflow */ +#define PRS_WTIMER0_CC0 ((62 << 8) + 2) /**< PRS Timer 2 Compare/Capture 0 */ +#define PRS_WTIMER0_CC1 ((62 << 8) + 3) /**< PRS Timer 2 Compare/Capture 1 */ +#define PRS_WTIMER0_CC2 ((62 << 8) + 4) /**< PRS Timer 2 Compare/Capture 2 */ +#define PRS_WTIMER1_UF ((63 << 8) + 0) /**< PRS Timer 3 Underflow */ +#define PRS_WTIMER1_OF ((63 << 8) + 1) /**< PRS Timer 3 Overflow */ +#define PRS_WTIMER1_CC0 ((63 << 8) + 2) /**< PRS Timer 3 Compare/Capture 0 */ +#define PRS_WTIMER1_CC1 ((63 << 8) + 3) /**< PRS Timer 3 Compare/Capture 1 */ +#define PRS_WTIMER1_CC2 ((63 << 8) + 4) /**< PRS Timer 3 Compare/Capture 2 */ +#define PRS_WTIMER1_CC3 ((63 << 8) + 5) /**< PRS Timer 3 Compare/Capture 3 */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ + +/** @} End of group EFR32MG12P_PRS */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h new file mode 100644 index 00000000000..1e9600a9d66 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h @@ -0,0 +1,191 @@ +/**************************************************************************//** + * @file efr32mg12p_rmu.h + * @brief EFR32MG12P_RMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_RMU + * @{ + * @brief EFR32MG12P_RMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t RSTCAUSE; /**< Reset Cause Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t RST; /**< Reset Control Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ +} RMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_RMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for RMU CTRL */ +#define _RMU_CTRL_RESETVALUE 0x00004204UL /**< Default value for RMU_CTRL */ +#define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */ +#define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */ +#define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */ +#define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */ +#define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */ +#define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */ +#define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */ +#define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */ +#define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */ +#define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */ +#define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */ + +/* Bit fields for RMU RSTCAUSE */ +#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */ +#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */ +#define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */ +#define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */ +#define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */ +#define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */ +#define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */ +#define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */ +#define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */ +#define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */ +#define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */ +#define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */ +#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */ +#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */ +#define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */ +#define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ + +/* Bit fields for RMU CMD */ +#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */ +#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */ +#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */ +#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */ +#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */ + +/* Bit fields for RMU RST */ +#define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */ +#define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */ + +/* Bit fields for RMU LOCK */ +#define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */ +#define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */ +#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */ +#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */ + +/** @} End of group EFR32MG12P_RMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_romtable.h new file mode 100644 index 00000000000..a412a4c8ab1 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_romtable.h @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file efr32mg12p_romtable.h + * @brief EFR32MG12P_ROMTABLE register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_ROMTABLE + * @{ + * @brief Chip Information, Revision numbers + *****************************************************************************/ +typedef struct +{ + __IM uint32_t PID4; /**< JEP_106_BANK */ + __IM uint32_t PID5; /**< Unused */ + __IM uint32_t PID6; /**< Unused */ + __IM uint32_t PID7; /**< Unused */ + __IM uint32_t PID0; /**< Chip family LSB, chip major revision */ + __IM uint32_t PID1; /**< JEP_106_NO, Chip family MSB */ + __IM uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */ + __IM uint32_t PID3; /**< Chip minor rev LSB */ + __IM uint32_t CID0; /**< Unused */ +} ROMTABLE_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_ROMTABLE_BitFields + * @{ + *****************************************************************************/ +/* Bit fields for EFR32MG12P_ROMTABLE */ +#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */ +#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */ +#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */ +#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */ +#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */ + +/** @} End of group EFR32MG12P_ROMTABLE */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc.h new file mode 100644 index 00000000000..5de4e9177be --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc.h @@ -0,0 +1,695 @@ +/**************************************************************************//** + * @file efr32mg12p_rtcc.h + * @brief EFR32MG12P_RTCC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_RTCC + * @{ + * @brief EFR32MG12P_RTCC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */ + __IOM uint32_t TIME; /**< Time of day register */ + __IOM uint32_t DATE; /**< Date register */ + __IM uint32_t IF; /**< RTCC Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t POWERDOWN; /**< Retention RAM power-down register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ + + RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */ + + uint32_t RESERVED0[37]; /**< Reserved registers */ + RTCC_RET_TypeDef RET[32]; /**< RetentionReg */ +} RTCC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_RTCC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for RTCC CTRL */ +#define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */ +#define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */ +#define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */ +#define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */ +#define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */ +#define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */ +#define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */ +#define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */ +#define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 top value enable. */ +#define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */ +#define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */ +#define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 top value enable */ +#define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */ +#define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */ +#define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */ +#define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */ +#define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter prescaler mode. */ +#define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */ +#define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */ +#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator failure detection enable */ +#define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */ +#define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */ +#define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main counter mode */ +#define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */ +#define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */ +#define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */ +#define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */ +#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap year correction disabled. */ +#define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */ +#define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */ +#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */ + +/* Bit fields for RTCC PRECNT */ +#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ +#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ +#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ + +/* Bit fields for RTCC CNT */ +#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ +#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ +#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ +#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ + +/* Bit fields for RTCC COMBCNT */ +#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ + +/* Bit fields for RTCC TIME */ +#define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */ +#define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */ +#define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */ +#define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */ +#define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */ +#define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */ +#define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */ +#define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */ +#define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */ +#define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */ +#define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */ +#define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */ +#define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */ +#define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */ +#define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */ + +/* Bit fields for RTCC DATE */ +#define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */ +#define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */ +#define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */ +#define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */ +#define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */ +#define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */ +#define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */ +#define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */ +#define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */ +#define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */ +#define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */ +#define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */ +#define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */ +#define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */ +#define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */ +#define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */ +#define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */ +#define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */ + +/* Bit fields for RTCC IF */ +#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ +#define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */ +#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */ +#define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */ +#define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */ +#define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator failure Interrupt Flag */ +#define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main counter tick */ +#define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute tick */ +#define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour tick */ +#define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day tick */ +#define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of week overflow */ +#define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month tick */ +#define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */ + +/* Bit fields for RTCC IFS */ +#define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */ +#define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */ +#define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */ +#define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */ +#define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */ +#define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */ +#define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */ +#define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */ +#define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */ +#define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */ +#define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */ +#define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */ +#define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */ + +/* Bit fields for RTCC IFC */ +#define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */ +#define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */ +#define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */ +#define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */ +#define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */ +#define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */ +#define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */ +#define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */ +#define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */ +#define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */ +#define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */ +#define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */ +#define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */ + +/* Bit fields for RTCC IEN */ +#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ +#define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */ +#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */ +#define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */ +#define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */ +#define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */ +#define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */ +#define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */ +#define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */ +#define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */ +#define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */ +#define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */ +#define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */ + +/* Bit fields for RTCC STATUS */ +#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ +#define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */ + +/* Bit fields for RTCC CMD */ +#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ +#define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */ +#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS register. */ +#define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */ +#define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */ +#define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ + +/* Bit fields for RTCC SYNCBUSY */ +#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ +#define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */ +#define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */ +#define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */ +#define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ + +/* Bit fields for RTCC POWERDOWN */ +#define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */ +#define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */ +#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */ +#define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */ +#define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */ +#define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */ +#define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */ + +/* Bit fields for RTCC LOCK */ +#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ +#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ + +/* Bit fields for RTCC EM4WUEN */ +#define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */ +#define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */ +#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */ +#define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */ +#define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */ +#define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */ +#define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */ + +/* Bit fields for RTCC CC_CTRL */ +#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */ +#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */ +#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */ +#define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */ +#define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture compare channel comparison base. */ +#define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */ +#define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */ +#define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare selection */ +#define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */ +#define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */ +#define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */ + +/* Bit fields for RTCC CC_CCV */ +#define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */ +#define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */ +#define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */ +#define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */ +#define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */ +#define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */ + +/* Bit fields for RTCC CC_TIME */ +#define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */ +#define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */ +#define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */ +#define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */ +#define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */ +#define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */ +#define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */ +#define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */ +#define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */ +#define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */ +#define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */ +#define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */ +#define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ + +/* Bit fields for RTCC CC_DATE */ +#define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */ +#define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */ +#define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */ +#define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */ +#define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */ +#define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */ +#define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */ +#define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */ +#define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */ +#define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ + +/* Bit fields for RTCC RET_REG */ +#define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */ +#define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */ +#define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */ +#define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */ +#define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */ +#define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */ + +/** @} End of group EFR32MG12P_RTCC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_cc.h new file mode 100644 index 00000000000..b266ccc431f --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_cc.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efr32mg12p_rtcc_cc.h + * @brief EFR32MG12P_RTCC_CC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief RTCC_CC EFR32MG12P RTCC CC + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t CCV; /**< Capture/Compare Value Register */ + __IOM uint32_t TIME; /**< Capture/Compare Time Register */ + __IOM uint32_t DATE; /**< Capture/Compare Date Register */ +} RTCC_CC_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_ret.h new file mode 100644 index 00000000000..612723e91d2 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_ret.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efr32mg12p_rtcc_ret.h + * @brief EFR32MG12P_RTCC_RET register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief RTCC_RET EFR32MG12P RTCC RET + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t REG; /**< Retention register */ +} RTCC_RET_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h new file mode 100644 index 00000000000..faabd81a675 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h @@ -0,0 +1,400 @@ +/**************************************************************************//** + * @file efr32mg12p_smu.h + * @brief EFR32MG12P_SMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_SMU + * @{ + * @brief EFR32MG12P_SMU Register Declaration + *****************************************************************************/ +typedef struct +{ + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + + uint32_t RESERVED3[14]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_SMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0x3BFF7FA7UL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 2) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 2 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x4UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 5) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 5 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x20UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CryoTimer access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 8) /**< Advanced Encryption Standard Accelerator 0 access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 8 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x100UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO1 (0x1UL << 9) /**< Advanced Encryption Standard Accelerator 1 access control bit */ +#define _SMU_PPUPATD0_CRYPTO1_SHIFT 9 /**< Shift value for SMU_CRYPTO1 */ +#define _SMU_PPUPATD0_CRYPTO1_MASK 0x200UL /**< Bit mask for SMU_CRYPTO1 */ +#define _SMU_PPUPATD0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO1_DEFAULT (_SMU_PPUPATD0_CRYPTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 10) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 10 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x400UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 11) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 11 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x800UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 12) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 13) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 13 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 14) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 14 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x4000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 16) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 16 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 17) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 17 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x20000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 18) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 18 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x40000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 19) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 19 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x80000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 20) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 20 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x100000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 21) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 21 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x200000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 22) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 22 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x400000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 23) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 23 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x800000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 24) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 24 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x1000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 25) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 25 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x2000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT0 (0x1UL << 27) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD0_PCNT0_SHIFT 27 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD0_PCNT0_MASK 0x8000000UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD0_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT0_DEFAULT (_SMU_PPUPATD0_PCNT0_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT1 (0x1UL << 28) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD0_PCNT1_SHIFT 28 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD0_PCNT1_MASK 0x10000000UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD0_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT1_DEFAULT (_SMU_PPUPATD0_PCNT1_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT2 (0x1UL << 29) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD0_PCNT2_SHIFT 29 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD0_PCNT2_MASK 0x20000000UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD0_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT2_DEFAULT (_SMU_PPUPATD0_PCNT2_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x0000FFEEUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 1) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 1 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x2UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 2) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 2 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x4UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 3) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 5) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 5 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x20UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 6) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 6 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x40UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 7) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 7 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x80UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 8 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x100UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 9 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x200UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 10 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x400UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 11 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x800UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 12) /**< Watchdog 0 access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 12 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x1000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 13) /**< Watchdog 1 access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 13 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x2000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 14) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 14 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x4000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 15) /**< Wide Timer 1 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 15 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x8000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000002UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000005UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000007UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000008UL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO1 0x00000009UL /**< Mode CRYPTO1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000AUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000BUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000DUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000EUL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000014UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x00000016UL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x00000017UL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000018UL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x00000019UL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x0000001BUL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x0000001CUL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x0000001DUL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000021UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000022UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000023UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000025UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x00000026UL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000027UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000028UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000029UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x0000002AUL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x0000002BUL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000002CUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000002DUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000002EUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000002FUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO1 (_SMU_PPUFS_PERIPHID_CRYPTO1 << 0) /**< Shifted mode CRYPTO1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ + +/** @} End of group EFR32MG12P_SMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer.h new file mode 100644 index 00000000000..464acb33efe --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer.h @@ -0,0 +1,1575 @@ +/**************************************************************************//** + * @file efr32mg12p_timer.h + * @brief EFR32MG12P_TIMER register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_TIMER + * @{ + * @brief EFR32MG12P_TIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + + uint32_t RESERVED2[8]; /**< Reserved registers */ + TIMER_CC_TypeDef CC[4]; /**< Compare/Capture Channel */ + + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTTIME; /**< DTI Time Control Register */ + __IOM uint32_t DTFC; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_TIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _TIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _TIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _TIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV3_DEFAULT (_TIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _TIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _TIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _TIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV3_DEFAULT (_TIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _TIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _TIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _TIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_DEFAULT (_TIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_LOWRISE (_TIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_HIGHFALL (_TIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x00000FF7UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _TIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC3_DEFAULT (_TIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF3_DEFAULT (_TIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IFS */ +#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */ +#define _TIMER_IFS_MASK 0x00000FF7UL /**< Mask for TIMER_IFS */ +#define TIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _TIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_DIRCHG_DEFAULT (_TIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _TIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC3_DEFAULT (_TIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _TIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF3_DEFAULT (_TIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFS */ + +/* Bit fields for TIMER IFC */ +#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */ +#define _TIMER_IFC_MASK 0x00000FF7UL /**< Mask for TIMER_IFC */ +#define TIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _TIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_DIRCHG_DEFAULT (_TIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _TIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC3_DEFAULT (_TIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _TIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF3_DEFAULT (_TIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFC */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x00000FF7UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _TIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC3_DEFAULT (_TIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _TIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF3_DEFAULT (_TIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER ROUTEPEN */ +#define _TIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTEPEN */ +#define _TIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _TIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _TIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _TIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC0PEN_DEFAULT (_TIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _TIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _TIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _TIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC1PEN_DEFAULT (_TIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _TIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _TIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _TIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC2PEN_DEFAULT (_TIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _TIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _TIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _TIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC3PEN_DEFAULT (_TIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _TIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _TIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _TIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _TIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _TIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _TIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ + +/* Bit fields for TIMER ROUTELOC0 */ +#define _TIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _TIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC0 (_TIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_DEFAULT (_TIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC1 (_TIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC2 (_TIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC3 (_TIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC4 (_TIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC5 (_TIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC6 (_TIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC7 (_TIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC8 (_TIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC9 (_TIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC10 (_TIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC11 (_TIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC12 (_TIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC13 (_TIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC14 (_TIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC15 (_TIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC16 (_TIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC17 (_TIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC18 (_TIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC19 (_TIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC20 (_TIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC21 (_TIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC22 (_TIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC23 (_TIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC24 (_TIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC25 (_TIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC26 (_TIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC27 (_TIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC28 (_TIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC29 (_TIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC30 (_TIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC31 (_TIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _TIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC0 (_TIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_DEFAULT (_TIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC1 (_TIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC2 (_TIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC3 (_TIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC4 (_TIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC5 (_TIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC6 (_TIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC7 (_TIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC8 (_TIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC9 (_TIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC10 (_TIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC11 (_TIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC12 (_TIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC13 (_TIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC14 (_TIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC15 (_TIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC16 (_TIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC17 (_TIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC18 (_TIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC19 (_TIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC20 (_TIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC21 (_TIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC22 (_TIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC23 (_TIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC24 (_TIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC25 (_TIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC26 (_TIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC27 (_TIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC28 (_TIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC29 (_TIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC30 (_TIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC31 (_TIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _TIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC0 (_TIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_DEFAULT (_TIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC1 (_TIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC2 (_TIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC3 (_TIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC4 (_TIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC5 (_TIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC6 (_TIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC7 (_TIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC8 (_TIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC9 (_TIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC10 (_TIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC11 (_TIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC12 (_TIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC13 (_TIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC14 (_TIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC15 (_TIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC16 (_TIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC17 (_TIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC18 (_TIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC19 (_TIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC20 (_TIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC21 (_TIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC22 (_TIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC23 (_TIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC24 (_TIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC25 (_TIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC26 (_TIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC27 (_TIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC28 (_TIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC29 (_TIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC30 (_TIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC31 (_TIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _TIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC0 (_TIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_DEFAULT (_TIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC1 (_TIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC2 (_TIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC3 (_TIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC4 (_TIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC5 (_TIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC6 (_TIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC7 (_TIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC8 (_TIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC9 (_TIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC10 (_TIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC11 (_TIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC12 (_TIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC13 (_TIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC14 (_TIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC15 (_TIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC16 (_TIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC17 (_TIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC18 (_TIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC19 (_TIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC20 (_TIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC21 (_TIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC22 (_TIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC23 (_TIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC24 (_TIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC25 (_TIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC26 (_TIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC27 (_TIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC28 (_TIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC29 (_TIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC30 (_TIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC31 (_TIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ + +/* Bit fields for TIMER ROUTELOC2 */ +#define _TIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _TIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC0 (_TIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC1 (_TIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC2 (_TIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC3 (_TIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC4 (_TIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC5 (_TIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC6 (_TIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC7 (_TIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC8 (_TIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC9 (_TIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC10 (_TIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC11 (_TIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC12 (_TIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC13 (_TIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC14 (_TIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC15 (_TIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC16 (_TIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC17 (_TIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC18 (_TIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC19 (_TIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC20 (_TIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC21 (_TIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC22 (_TIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC23 (_TIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC24 (_TIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC25 (_TIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC26 (_TIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC27 (_TIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC28 (_TIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC29 (_TIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC30 (_TIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC31 (_TIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _TIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC0 (_TIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC1 (_TIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC2 (_TIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC3 (_TIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC4 (_TIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC5 (_TIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC6 (_TIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC7 (_TIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC8 (_TIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC9 (_TIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC10 (_TIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC11 (_TIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC12 (_TIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC13 (_TIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC14 (_TIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC15 (_TIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC16 (_TIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC17 (_TIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC18 (_TIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC19 (_TIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC20 (_TIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC21 (_TIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC22 (_TIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC23 (_TIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC24 (_TIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC25 (_TIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC26 (_TIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC27 (_TIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC28 (_TIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC29 (_TIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC30 (_TIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC31 (_TIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _TIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC0 (_TIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC1 (_TIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC2 (_TIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC3 (_TIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC4 (_TIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC5 (_TIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC6 (_TIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC7 (_TIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC8 (_TIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC9 (_TIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC10 (_TIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC11 (_TIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC12 (_TIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC13 (_TIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC14 (_TIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC15 (_TIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC16 (_TIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC17 (_TIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC18 (_TIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC19 (_TIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC20 (_TIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC21 (_TIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC22 (_TIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC23 (_TIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC24 (_TIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC25 (_TIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC26 (_TIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC27 (_TIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC28 (_TIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC29 (_TIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC30 (_TIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC31 (_TIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _TIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_DEFAULT (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_PULSE (_TIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_LEVEL (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _TIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _TIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_CCV */ +#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */ +#define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */ + +/* Bit fields for TIMER CC_CCVP */ +#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */ +#define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */ + +/* Bit fields for TIMER CC_CCVB */ +#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */ +#define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTAR_DEFAULT (_TIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTFATS_DEFAULT (_TIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTTIME */ +#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */ +#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */ + +/* Bit fields for TIMER DTFC */ +#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */ +#define _TIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH8 (_TIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH9 (_TIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH10 (_TIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH11 (_TIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH8 (_TIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH9 (_TIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH10 (_TIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH11 (_TIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} End of group EFR32MG12P_TIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer_cc.h new file mode 100644 index 00000000000..66cb6b400b1 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer_cc.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efr32mg12p_timer_cc.h + * @brief EFR32MG12P_TIMER_CC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief TIMER_CC EFR32MG12P TIMER CC + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t CCV; /**< CC Channel Value Register */ + __IM uint32_t CCVP; /**< CC Channel Value Peek Register */ + __IOM uint32_t CCVB; /**< CC Channel Buffer Register */ +} TIMER_CC_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_trng.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_trng.h new file mode 100644 index 00000000000..bb3e36a0513 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_trng.h @@ -0,0 +1,279 @@ +/**************************************************************************//** + * @file efr32mg12p_trng.h + * @brief EFR32MG12P_TRNG register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_TRNG + * @{ + * @brief EFR32MG12P_TRNG Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CONTROL; /**< Main Control Register */ + __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */ + __IOM uint32_t KEY0; /**< Key Register 0 */ + __IOM uint32_t KEY1; /**< Key Register 1 */ + __IOM uint32_t KEY2; /**< Key Register 2 */ + __IOM uint32_t KEY3; /**< Key Register 3 */ + __IOM uint32_t TESTDATA; /**< Test Data Register */ + + uint32_t RESERVED1[3]; /**< Reserved for future use **/ + __IOM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */ + uint32_t RESERVED2[50]; /**< Reserved for future use **/ + __IM uint32_t FIFO; /**< FIFO Data */ +} TRNG_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_TRNG_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for TRNG CONTROL */ +#define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */ +#define _TRNG_CONTROL_MASK 0x00003FFDUL /**< Mask for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */ +#define _TRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for TRNG_ENABLE */ +#define _TRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for TRNG_ENABLE */ +#define _TRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for TRNG_CONTROL */ +#define _TRNG_CONTROL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_DEFAULT (_TRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_DISABLED (_TRNG_CONTROL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_ENABLED (_TRNG_CONTROL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN (0x1UL << 2) /**< Test Enable */ +#define _TRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for TRNG_TESTEN */ +#define _TRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for TRNG_TESTEN */ +#define _TRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for TRNG_CONTROL */ +#define _TRNG_CONTROL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_DEFAULT (_TRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_NOISE (_TRNG_CONTROL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_TESTDATA (_TRNG_CONTROL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */ +#define _TRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for TRNG_CONDBYPASS */ +#define _TRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for TRNG_CONDBYPASS */ +#define _TRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt enable for Repetition Count Test failure */ +#define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */ +#define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */ +#define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt enable for Adaptive Proportion Test failure (64-sample window) */ +#define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */ +#define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */ +#define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt enable for Adaptive Proportion Test failure (4096-sample window) */ +#define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */ +#define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */ +#define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt enable for FIFO full */ +#define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */ +#define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */ +#define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FULLIEN_DEFAULT (_TRNG_CONTROL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET (0x1UL << 8) /**< Software Reset */ +#define _TRNG_CONTROL_SOFTRESET_SHIFT 8 /**< Shift value for TRNG_SOFTRESET */ +#define _TRNG_CONTROL_SOFTRESET_MASK 0x100UL /**< Bit mask for TRNG_SOFTRESET */ +#define _TRNG_CONTROL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_DEFAULT (_TRNG_CONTROL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_NORMAL (_TRNG_CONTROL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_RESET (_TRNG_CONTROL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for TRNG_CONTROL */ +#define TRNG_CONTROL_PREIEN (0x1UL << 9) /**< Interrupt enable for AIS31 preliminary noise alarm */ +#define _TRNG_CONTROL_PREIEN_SHIFT 9 /**< Shift value for TRNG_PREIEN */ +#define _TRNG_CONTROL_PREIEN_MASK 0x200UL /**< Bit mask for TRNG_PREIEN */ +#define _TRNG_CONTROL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_PREIEN_DEFAULT (_TRNG_CONTROL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ALMIEN (0x1UL << 10) /**< Interrupt enable for AIS31 noise alarm */ +#define _TRNG_CONTROL_ALMIEN_SHIFT 10 /**< Shift value for TRNG_ALMIEN */ +#define _TRNG_CONTROL_ALMIEN_MASK 0x400UL /**< Bit mask for TRNG_ALMIEN */ +#define _TRNG_CONTROL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ALMIEN_DEFAULT (_TRNG_CONTROL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */ +#define _TRNG_CONTROL_FORCERUN_SHIFT 11 /**< Shift value for TRNG_FORCERUN */ +#define _TRNG_CONTROL_FORCERUN_MASK 0x800UL /**< Bit mask for TRNG_FORCERUN */ +#define _TRNG_CONTROL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_DEFAULT (_TRNG_CONTROL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_NORMAL (_TRNG_CONTROL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_RUN (_TRNG_CONTROL_FORCERUN_RUN << 11) /**< Shifted mode RUN for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */ +#define _TRNG_CONTROL_BYPNIST_SHIFT 12 /**< Shift value for TRNG_BYPNIST */ +#define _TRNG_CONTROL_BYPNIST_MASK 0x1000UL /**< Bit mask for TRNG_BYPNIST */ +#define _TRNG_CONTROL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_DEFAULT (_TRNG_CONTROL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_NORMAL (_TRNG_CONTROL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_BYPASS (_TRNG_CONTROL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */ +#define _TRNG_CONTROL_BYPAIS31_SHIFT 13 /**< Shift value for TRNG_BYPAIS31 */ +#define _TRNG_CONTROL_BYPAIS31_MASK 0x2000UL /**< Bit mask for TRNG_BYPAIS31 */ +#define _TRNG_CONTROL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_DEFAULT (_TRNG_CONTROL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_NORMAL (_TRNG_CONTROL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_BYPASS (_TRNG_CONTROL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for TRNG_CONTROL */ + +/* Bit fields for TRNG FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFOLEVEL_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFOLEVEL_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFOLEVEL */ +#define TRNG_FIFOLEVEL_VALUE_DEFAULT (_TRNG_FIFOLEVEL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFOLEVEL */ + +/* Bit fields for TRNG FIFODEPTH */ +#define _TRNG_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for TRNG_FIFODEPTH */ +#define _TRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFODEPTH */ +#define _TRNG_FIFODEPTH_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFODEPTH_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFODEPTH_VALUE_DEFAULT 0x00000040UL /**< Mode DEFAULT for TRNG_FIFODEPTH */ +#define TRNG_FIFODEPTH_VALUE_DEFAULT (_TRNG_FIFODEPTH_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFODEPTH */ + +/* Bit fields for TRNG KEY0 */ +#define _TRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY0 */ +#define _TRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY0 */ +#define _TRNG_KEY0_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY0_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY0_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY0 */ +#define TRNG_KEY0_VALUE_DEFAULT (_TRNG_KEY0_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY0 */ + +/* Bit fields for TRNG KEY1 */ +#define _TRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY1 */ +#define _TRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY1 */ +#define _TRNG_KEY1_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY1_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY1_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY1 */ +#define TRNG_KEY1_VALUE_DEFAULT (_TRNG_KEY1_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY1 */ + +/* Bit fields for TRNG KEY2 */ +#define _TRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY2 */ +#define _TRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY2 */ +#define _TRNG_KEY2_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY2_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY2_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY2 */ +#define TRNG_KEY2_VALUE_DEFAULT (_TRNG_KEY2_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY2 */ + +/* Bit fields for TRNG KEY3 */ +#define _TRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY3 */ +#define _TRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY3 */ +#define _TRNG_KEY3_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY3_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY3_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY3 */ +#define TRNG_KEY3_VALUE_DEFAULT (_TRNG_KEY3_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY3 */ + +/* Bit fields for TRNG TESTDATA */ +#define _TRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for TRNG_TESTDATA */ +#define _TRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for TRNG_TESTDATA */ +#define _TRNG_TESTDATA_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_TESTDATA */ +#define TRNG_TESTDATA_VALUE_DEFAULT (_TRNG_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_TESTDATA */ + +/* Bit fields for TRNG STATUS */ +#define _TRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for TRNG_STATUS */ +#define _TRNG_STATUS_MASK 0x000003F1UL /**< Mask for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */ +#define _TRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for TRNG_TESTDATABUSY */ +#define _TRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for TRNG_TESTDATABUSY */ +#define _TRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define _TRNG_STATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for TRNG_STATUS */ +#define _TRNG_STATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */ +#define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */ +#define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */ +#define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */ +#define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_REPCOUNTIF_DEFAULT (_TRNG_STATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT64IF (0x1UL << 5) /**< Adaptive Proportion test failure (64-sample window) interrupt status */ +#define _TRNG_STATUS_APT64IF_SHIFT 5 /**< Shift value for TRNG_APT64IF */ +#define _TRNG_STATUS_APT64IF_MASK 0x20UL /**< Bit mask for TRNG_APT64IF */ +#define _TRNG_STATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT64IF_DEFAULT (_TRNG_STATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT4096IF (0x1UL << 6) /**< Adaptive Proportion test failure (4096-sample window) interrupt status */ +#define _TRNG_STATUS_APT4096IF_SHIFT 6 /**< Shift value for TRNG_APT4096IF */ +#define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */ +#define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */ +#define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */ +#define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */ +#define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_FULLIF_DEFAULT (_TRNG_STATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm interrupt status */ +#define _TRNG_STATUS_PREIF_SHIFT 8 /**< Shift value for TRNG_PREIF */ +#define _TRNG_STATUS_PREIF_MASK 0x100UL /**< Bit mask for TRNG_PREIF */ +#define _TRNG_STATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_PREIF_DEFAULT (_TRNG_STATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */ +#define _TRNG_STATUS_ALMIF_SHIFT 9 /**< Shift value for TRNG_ALMIF */ +#define _TRNG_STATUS_ALMIF_MASK 0x200UL /**< Bit mask for TRNG_ALMIF */ +#define _TRNG_STATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_ALMIF_DEFAULT (_TRNG_STATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_STATUS */ + +/* Bit fields for TRNG INITWAITVAL */ +#define _TRNG_INITWAITVAL_RESETVALUE 0x000000FFUL /**< Default value for TRNG_INITWAITVAL */ +#define _TRNG_INITWAITVAL_MASK 0x000000FFUL /**< Mask for TRNG_INITWAITVAL */ +#define _TRNG_INITWAITVAL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_INITWAITVAL_VALUE_MASK 0xFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_INITWAITVAL_VALUE_DEFAULT 0x000000FFUL /**< Mode DEFAULT for TRNG_INITWAITVAL */ +#define TRNG_INITWAITVAL_VALUE_DEFAULT (_TRNG_INITWAITVAL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_INITWAITVAL */ + +/* Bit fields for TRNG FIFO */ +#define _TRNG_FIFO_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFO */ +#define _TRNG_FIFO_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFO */ +#define _TRNG_FIFO_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFO_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */ +#define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */ + +/** @} End of group EFR32MG12P_TRNG */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_usart.h new file mode 100644 index 00000000000..5640971c080 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_usart.h @@ -0,0 +1,1972 @@ +/**************************************************************************//** + * @file efr32mg12p_usart.h + * @brief EFR32MG12P_USART register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_USART + * @{ + * @brief EFR32MG12P_USART Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t INPUT; /**< USART Input Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Used to generate interrupts and various delays */ + __IOM uint32_t TIMECMP1; /**< Used to generate interrupts and various delays */ + __IOM uint32_t TIMECMP2; /**< Used to generate interrupts and various delays */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ +} USART_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_USART_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */ +#define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */ +#define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IFS */ +#define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */ +#define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */ +#define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ +#define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */ +#define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */ +#define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */ +#define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */ +#define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */ +#define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */ +#define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */ +#define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */ +#define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */ +#define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */ +#define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */ +#define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */ +#define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */ +#define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */ +#define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */ + +/* Bit fields for USART IFC */ +#define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */ +#define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */ +#define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ +#define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */ +#define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */ +#define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */ +#define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */ +#define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */ +#define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */ +#define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */ +#define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */ +#define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */ +#define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */ +#define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */ +#define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */ +#define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */ +#define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */ +#define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ +#define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ +#define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ +#define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */ +#define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */ +#define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */ + +/* Bit fields for USART INPUT */ +#define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */ +#define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ +#define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */ +#define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */ +#define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */ +#define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */ +#define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */ +#define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */ +#define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */ +#define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ + +/* Bit fields for USART ROUTEPEN */ +#define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */ +#define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ +#define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ +#define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ +#define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ +#define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ +#define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ +#define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */ +#define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ +#define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ +#define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ +#define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ +#define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ +#define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */ +#define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */ +#define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */ +#define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */ +#define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */ +#define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */ +#define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ + +/* Bit fields for USART ROUTELOC0 */ +#define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */ +#define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */ +#define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */ +#define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */ +#define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */ +#define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */ +#define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */ +#define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */ +#define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ + +/* Bit fields for USART ROUTELOC1 */ +#define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */ +#define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */ +#define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */ +#define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */ +#define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ + +/** @} End of group EFR32MG12P_USART */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h new file mode 100644 index 00000000000..dd1912f6b3b --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h @@ -0,0 +1,1539 @@ +/**************************************************************************//** + * @file efr32mg12p_vdac.h + * @brief EFR32MG12P_VDAC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_VDAC + * @{ + * @brief EFR32MG12P_VDAC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */ + __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */ + __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */ + __IOM uint32_t COMBDATA; /**< Combined Data Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + + uint32_t RESERVED0[27]; /**< Reserved registers */ + VDAC_OPA_TypeDef OPA[3]; /**< OPA Registers */ +} VDAC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_VDAC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for VDAC CTRL */ +#define _VDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CTRL */ +#define _VDAC_CTRL_MASK 0x937F0771UL /**< Mask for VDAC_CTRL */ +#define VDAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */ +#define _VDAC_CTRL_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ +#define _VDAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ +#define _VDAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_DIFF_DEFAULT (_VDAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_SINEMODE (0x1UL << 4) /**< Sine Mode */ +#define _VDAC_CTRL_SINEMODE_SHIFT 4 /**< Shift value for VDAC_SINEMODE */ +#define _VDAC_CTRL_SINEMODE_MASK 0x10UL /**< Bit mask for VDAC_SINEMODE */ +#define _VDAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_SINEMODE_DEFAULT (_VDAC_CTRL_SINEMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_OUTENPRS (0x1UL << 5) /**< PRS Controlled Output Enable */ +#define _VDAC_CTRL_OUTENPRS_SHIFT 5 /**< Shift value for VDAC_OUTENPRS */ +#define _VDAC_CTRL_OUTENPRS_MASK 0x20UL /**< Bit mask for VDAC_OUTENPRS */ +#define _VDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_OUTENPRS_DEFAULT (_VDAC_CTRL_OUTENPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_CH0PRESCRST (0x1UL << 6) /**< Channel 0 Start Reset Prescaler */ +#define _VDAC_CTRL_CH0PRESCRST_SHIFT 6 /**< Shift value for VDAC_CH0PRESCRST */ +#define _VDAC_CTRL_CH0PRESCRST_MASK 0x40UL /**< Bit mask for VDAC_CH0PRESCRST */ +#define _VDAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_CH0PRESCRST_DEFAULT (_VDAC_CTRL_CH0PRESCRST_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for VDAC_REFSEL */ +#define _VDAC_CTRL_REFSEL_MASK 0x700UL /**< Bit mask for VDAC_REFSEL */ +#define _VDAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_1V25LN 0x00000000UL /**< Mode 1V25LN for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_2V5LN 0x00000001UL /**< Mode 2V5LN for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_1V25 0x00000002UL /**< Mode 1V25 for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_2V5 0x00000003UL /**< Mode 2V5 for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_VDD 0x00000004UL /**< Mode VDD for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_EXT 0x00000006UL /**< Mode EXT for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_DEFAULT (_VDAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_1V25LN (_VDAC_CTRL_REFSEL_1V25LN << 8) /**< Shifted mode 1V25LN for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_2V5LN (_VDAC_CTRL_REFSEL_2V5LN << 8) /**< Shifted mode 2V5LN for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_1V25 (_VDAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_2V5 (_VDAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_VDD (_VDAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_EXT (_VDAC_CTRL_REFSEL_EXT << 8) /**< Shifted mode EXT for VDAC_CTRL */ +#define _VDAC_CTRL_PRESC_SHIFT 16 /**< Shift value for VDAC_PRESC */ +#define _VDAC_CTRL_PRESC_MASK 0x7F0000UL /**< Bit mask for VDAC_PRESC */ +#define _VDAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for VDAC_CTRL */ +#define VDAC_CTRL_PRESC_DEFAULT (_VDAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_PRESC_NODIVISION (_VDAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_SHIFT 24 /**< Shift value for VDAC_REFRESHPERIOD */ +#define _VDAC_CTRL_REFRESHPERIOD_MASK 0x3000000UL /**< Bit mask for VDAC_REFRESHPERIOD */ +#define _VDAC_CTRL_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_8CYCLES 0x00000000UL /**< Mode 8CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_16CYCLES 0x00000001UL /**< Mode 16CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_32CYCLES 0x00000002UL /**< Mode 32CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_64CYCLES 0x00000003UL /**< Mode 64CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_DEFAULT (_VDAC_CTRL_REFRESHPERIOD_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_8CYCLES (_VDAC_CTRL_REFRESHPERIOD_8CYCLES << 24) /**< Shifted mode 8CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_16CYCLES (_VDAC_CTRL_REFRESHPERIOD_16CYCLES << 24) /**< Shifted mode 16CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_32CYCLES (_VDAC_CTRL_REFRESHPERIOD_32CYCLES << 24) /**< Shifted mode 32CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_64CYCLES (_VDAC_CTRL_REFRESHPERIOD_64CYCLES << 24) /**< Shifted mode 64CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE (0x1UL << 28) /**< Warm-up Mode */ +#define _VDAC_CTRL_WARMUPMODE_SHIFT 28 /**< Shift value for VDAC_WARMUPMODE */ +#define _VDAC_CTRL_WARMUPMODE_MASK 0x10000000UL /**< Bit mask for VDAC_WARMUPMODE */ +#define _VDAC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CTRL */ +#define _VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_DEFAULT (_VDAC_CTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_NORMAL (_VDAC_CTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY (_VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY << 28) /**< Shifted mode KEEPINSTANDBY for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE (0x1UL << 31) /**< Clock Mode */ +#define _VDAC_CTRL_DACCLKMODE_SHIFT 31 /**< Shift value for VDAC_DACCLKMODE */ +#define _VDAC_CTRL_DACCLKMODE_MASK 0x80000000UL /**< Bit mask for VDAC_DACCLKMODE */ +#define _VDAC_CTRL_DACCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_DACCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for VDAC_CTRL */ +#define _VDAC_CTRL_DACCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_DEFAULT (_VDAC_CTRL_DACCLKMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_SYNC (_VDAC_CTRL_DACCLKMODE_SYNC << 31) /**< Shifted mode SYNC for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_ASYNC (_VDAC_CTRL_DACCLKMODE_ASYNC << 31) /**< Shifted mode ASYNC for VDAC_CTRL */ + +/* Bit fields for VDAC STATUS */ +#define _VDAC_STATUS_RESETVALUE 0x0000000CUL /**< Default value for VDAC_STATUS */ +#define _VDAC_STATUS_MASK 0x7777003FUL /**< Mask for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ +#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ +#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0BL (0x1UL << 2) /**< Channel 0 Buffer Level */ +#define _VDAC_STATUS_CH0BL_SHIFT 2 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_STATUS_CH0BL_MASK 0x4UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_STATUS_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0BL_DEFAULT (_VDAC_STATUS_CH0BL_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1BL (0x1UL << 3) /**< Channel 1 Buffer Level */ +#define _VDAC_STATUS_CH1BL_SHIFT 3 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_STATUS_CH1BL_MASK 0x8UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_STATUS_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1BL_DEFAULT (_VDAC_STATUS_CH1BL_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warm */ +#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warm */ +#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0ENS (0x1UL << 20) /**< OPA0 Enabled Status */ +#define _VDAC_STATUS_OPA0ENS_SHIFT 20 /**< Shift value for VDAC_OPA0ENS */ +#define _VDAC_STATUS_OPA0ENS_MASK 0x100000UL /**< Bit mask for VDAC_OPA0ENS */ +#define _VDAC_STATUS_OPA0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0ENS_DEFAULT (_VDAC_STATUS_OPA0ENS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1ENS (0x1UL << 21) /**< OPA1 Enabled Status */ +#define _VDAC_STATUS_OPA1ENS_SHIFT 21 /**< Shift value for VDAC_OPA1ENS */ +#define _VDAC_STATUS_OPA1ENS_MASK 0x200000UL /**< Bit mask for VDAC_OPA1ENS */ +#define _VDAC_STATUS_OPA1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1ENS_DEFAULT (_VDAC_STATUS_OPA1ENS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2ENS (0x1UL << 22) /**< OPA2 Enabled Status */ +#define _VDAC_STATUS_OPA2ENS_SHIFT 22 /**< Shift value for VDAC_OPA2ENS */ +#define _VDAC_STATUS_OPA2ENS_MASK 0x400000UL /**< Bit mask for VDAC_OPA2ENS */ +#define _VDAC_STATUS_OPA2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2ENS_DEFAULT (_VDAC_STATUS_OPA2ENS_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0WARM (0x1UL << 24) /**< OPA0 Warm Status */ +#define _VDAC_STATUS_OPA0WARM_SHIFT 24 /**< Shift value for VDAC_OPA0WARM */ +#define _VDAC_STATUS_OPA0WARM_MASK 0x1000000UL /**< Bit mask for VDAC_OPA0WARM */ +#define _VDAC_STATUS_OPA0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0WARM_DEFAULT (_VDAC_STATUS_OPA0WARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1WARM (0x1UL << 25) /**< OPA1 Warm Status */ +#define _VDAC_STATUS_OPA1WARM_SHIFT 25 /**< Shift value for VDAC_OPA1WARM */ +#define _VDAC_STATUS_OPA1WARM_MASK 0x2000000UL /**< Bit mask for VDAC_OPA1WARM */ +#define _VDAC_STATUS_OPA1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1WARM_DEFAULT (_VDAC_STATUS_OPA1WARM_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2WARM (0x1UL << 26) /**< OPA2 Warm Status */ +#define _VDAC_STATUS_OPA2WARM_SHIFT 26 /**< Shift value for VDAC_OPA2WARM */ +#define _VDAC_STATUS_OPA2WARM_MASK 0x4000000UL /**< Bit mask for VDAC_OPA2WARM */ +#define _VDAC_STATUS_OPA2WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2WARM_DEFAULT (_VDAC_STATUS_OPA2WARM_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Status */ +#define _VDAC_STATUS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_STATUS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_STATUS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0OUTVALID_DEFAULT (_VDAC_STATUS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Status */ +#define _VDAC_STATUS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_STATUS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_STATUS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1OUTVALID_DEFAULT (_VDAC_STATUS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2OUTVALID (0x1UL << 30) /**< OPA2 Output Valid Status */ +#define _VDAC_STATUS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_STATUS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_STATUS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2OUTVALID_DEFAULT (_VDAC_STATUS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ + +/* Bit fields for VDAC CH0CTRL */ +#define _VDAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ +#define _VDAC_CH0CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH0CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH0CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_DEFAULT (_VDAC_CH0CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_CONTINUOUS (_VDAC_CH0CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH0CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH0CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH0CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_DEFAULT (_VDAC_CH0CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SW (_VDAC_CH0CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_PRS (_VDAC_CH0CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_REFRESH (_VDAC_CH0CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SWPRS (_VDAC_CH0CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SWREFRESH (_VDAC_CH0CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_LESENSE (_VDAC_CH0CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSASYNC (0x1UL << 8) /**< Channel 0 PRS Asynchronous Enable */ +#define _VDAC_CH0CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ +#define _VDAC_CH0CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ +#define _VDAC_CH0CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSASYNC_DEFAULT (_VDAC_CH0CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ +#define _VDAC_CH0CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ +#define _VDAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_DEFAULT (_VDAC_CH0CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH0 (_VDAC_CH0CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH1 (_VDAC_CH0CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH2 (_VDAC_CH0CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH3 (_VDAC_CH0CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH4 (_VDAC_CH0CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH5 (_VDAC_CH0CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH6 (_VDAC_CH0CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH7 (_VDAC_CH0CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH8 (_VDAC_CH0CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH9 (_VDAC_CH0CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH10 (_VDAC_CH0CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH11 (_VDAC_CH0CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH0CTRL */ + +/* Bit fields for VDAC CH1CTRL */ +#define _VDAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ +#define _VDAC_CH1CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH1CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH1CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_DEFAULT (_VDAC_CH1CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_CONTINUOUS (_VDAC_CH1CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH1CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH1CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH1CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_DEFAULT (_VDAC_CH1CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SW (_VDAC_CH1CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_PRS (_VDAC_CH1CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_REFRESH (_VDAC_CH1CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SWPRS (_VDAC_CH1CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SWREFRESH (_VDAC_CH1CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_LESENSE (_VDAC_CH1CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSASYNC (0x1UL << 8) /**< Channel 1 PRS Asynchronous Enable */ +#define _VDAC_CH1CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ +#define _VDAC_CH1CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ +#define _VDAC_CH1CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSASYNC_DEFAULT (_VDAC_CH1CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ +#define _VDAC_CH1CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ +#define _VDAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_DEFAULT (_VDAC_CH1CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH0 (_VDAC_CH1CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH1 (_VDAC_CH1CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH2 (_VDAC_CH1CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH3 (_VDAC_CH1CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH4 (_VDAC_CH1CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH5 (_VDAC_CH1CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH6 (_VDAC_CH1CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH7 (_VDAC_CH1CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH8 (_VDAC_CH1CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH9 (_VDAC_CH1CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH10 (_VDAC_CH1CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH11 (_VDAC_CH1CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH1CTRL */ + +/* Bit fields for VDAC CMD */ +#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ +#define _VDAC_CMD_MASK 0x003F000FUL /**< Mask for VDAC_CMD */ +#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ +#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ +#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN (0x1UL << 2) /**< DAC Channel 1 Enable */ +#define _VDAC_CMD_CH1EN_SHIFT 2 /**< Shift value for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_MASK 0x4UL /**< Bit mask for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS (0x1UL << 3) /**< DAC Channel 1 Disable */ +#define _VDAC_CMD_CH1DIS_SHIFT 3 /**< Shift value for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_MASK 0x8UL /**< Bit mask for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0EN (0x1UL << 16) /**< OPA0 Enable */ +#define _VDAC_CMD_OPA0EN_SHIFT 16 /**< Shift value for VDAC_OPA0EN */ +#define _VDAC_CMD_OPA0EN_MASK 0x10000UL /**< Bit mask for VDAC_OPA0EN */ +#define _VDAC_CMD_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0EN_DEFAULT (_VDAC_CMD_OPA0EN_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0DIS (0x1UL << 17) /**< OPA0 Disable */ +#define _VDAC_CMD_OPA0DIS_SHIFT 17 /**< Shift value for VDAC_OPA0DIS */ +#define _VDAC_CMD_OPA0DIS_MASK 0x20000UL /**< Bit mask for VDAC_OPA0DIS */ +#define _VDAC_CMD_OPA0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0DIS_DEFAULT (_VDAC_CMD_OPA0DIS_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1EN (0x1UL << 18) /**< OPA1 Enable */ +#define _VDAC_CMD_OPA1EN_SHIFT 18 /**< Shift value for VDAC_OPA1EN */ +#define _VDAC_CMD_OPA1EN_MASK 0x40000UL /**< Bit mask for VDAC_OPA1EN */ +#define _VDAC_CMD_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1EN_DEFAULT (_VDAC_CMD_OPA1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1DIS (0x1UL << 19) /**< OPA1 Disable */ +#define _VDAC_CMD_OPA1DIS_SHIFT 19 /**< Shift value for VDAC_OPA1DIS */ +#define _VDAC_CMD_OPA1DIS_MASK 0x80000UL /**< Bit mask for VDAC_OPA1DIS */ +#define _VDAC_CMD_OPA1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1DIS_DEFAULT (_VDAC_CMD_OPA1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2EN (0x1UL << 20) /**< OPA2 Enable */ +#define _VDAC_CMD_OPA2EN_SHIFT 20 /**< Shift value for VDAC_OPA2EN */ +#define _VDAC_CMD_OPA2EN_MASK 0x100000UL /**< Bit mask for VDAC_OPA2EN */ +#define _VDAC_CMD_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2EN_DEFAULT (_VDAC_CMD_OPA2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2DIS (0x1UL << 21) /**< OPA2 Disable */ +#define _VDAC_CMD_OPA2DIS_SHIFT 21 /**< Shift value for VDAC_OPA2DIS */ +#define _VDAC_CMD_OPA2DIS_MASK 0x200000UL /**< Bit mask for VDAC_OPA2DIS */ +#define _VDAC_CMD_OPA2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2DIS_DEFAULT (_VDAC_CMD_OPA2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_CMD */ + +/* Bit fields for VDAC IF */ +#define _VDAC_IF_RESETVALUE 0x000000C0UL /**< Default value for VDAC_IF */ +#define _VDAC_IF_MASK 0x707780FFUL /**< Mask for VDAC_IF */ +#define VDAC_IF_CH0CD (0x1UL << 0) /**< Channel 0 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD (0x1UL << 1) /**< Channel 1 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF (0x1UL << 2) /**< Channel 0 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF (0x1UL << 3) /**< Channel 1 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0BL (0x1UL << 6) /**< Channel 0 Buffer Level Interrupt Flag */ +#define _VDAC_IF_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_IF_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_IF_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0BL_DEFAULT (_VDAC_IF_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1BL (0x1UL << 7) /**< Channel 1 Buffer Level Interrupt Flag */ +#define _VDAC_IF_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_IF_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_IF_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1BL_DEFAULT (_VDAC_IF_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_EM23ERR (0x1UL << 15) /**< EM2/3 Entry Error Flag */ +#define _VDAC_IF_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IF_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_EM23ERR_DEFAULT (_VDAC_IF_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IF_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IF_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0APORTCONFLICT_DEFAULT (_VDAC_IF_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IF_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IF_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1APORTCONFLICT_DEFAULT (_VDAC_IF_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IF_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IF_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2APORTCONFLICT_DEFAULT (_VDAC_IF_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IF_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IF_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IF_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IF_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IF_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IF_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IF_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IF_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0OUTVALID_DEFAULT (_VDAC_IF_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IF_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IF_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1OUTVALID_DEFAULT (_VDAC_IF_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2OUTVALID (0x1UL << 30) /**< OPA3 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IF_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IF_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2OUTVALID_DEFAULT (_VDAC_IF_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IF */ + +/* Bit fields for VDAC IFS */ +#define _VDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFS */ +#define _VDAC_IFS_MASK 0x7077803FUL /**< Mask for VDAC_IFS */ +#define VDAC_IFS_CH0CD (0x1UL << 0) /**< Set CH0CD Interrupt Flag */ +#define _VDAC_IFS_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IFS_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IFS_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0CD_DEFAULT (_VDAC_IFS_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1CD (0x1UL << 1) /**< Set CH1CD Interrupt Flag */ +#define _VDAC_IFS_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IFS_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IFS_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1CD_DEFAULT (_VDAC_IFS_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0OF (0x1UL << 2) /**< Set CH0OF Interrupt Flag */ +#define _VDAC_IFS_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IFS_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IFS_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0OF_DEFAULT (_VDAC_IFS_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1OF (0x1UL << 3) /**< Set CH1OF Interrupt Flag */ +#define _VDAC_IFS_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IFS_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IFS_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1OF_DEFAULT (_VDAC_IFS_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0UF (0x1UL << 4) /**< Set CH0UF Interrupt Flag */ +#define _VDAC_IFS_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0UF_DEFAULT (_VDAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1UF (0x1UL << 5) /**< Set CH1UF Interrupt Flag */ +#define _VDAC_IFS_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1UF_DEFAULT (_VDAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_EM23ERR (0x1UL << 15) /**< Set EM23ERR Interrupt Flag */ +#define _VDAC_IFS_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IFS_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_EM23ERR_DEFAULT (_VDAC_IFS_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0APORTCONFLICT (0x1UL << 16) /**< Set OPA0APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1APORTCONFLICT (0x1UL << 17) /**< Set OPA1APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2APORTCONFLICT (0x1UL << 18) /**< Set OPA2APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0PRSTIMEDERR (0x1UL << 20) /**< Set OPA0PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1PRSTIMEDERR (0x1UL << 21) /**< Set OPA1PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2PRSTIMEDERR (0x1UL << 22) /**< Set OPA2PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0OUTVALID (0x1UL << 28) /**< Set OPA0OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IFS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IFS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0OUTVALID_DEFAULT (_VDAC_IFS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1OUTVALID (0x1UL << 29) /**< Set OPA1OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IFS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IFS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1OUTVALID_DEFAULT (_VDAC_IFS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2OUTVALID (0x1UL << 30) /**< Set OPA2OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IFS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IFS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2OUTVALID_DEFAULT (_VDAC_IFS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFS */ + +/* Bit fields for VDAC IFC */ +#define _VDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFC */ +#define _VDAC_IFC_MASK 0x7077803FUL /**< Mask for VDAC_IFC */ +#define VDAC_IFC_CH0CD (0x1UL << 0) /**< Clear CH0CD Interrupt Flag */ +#define _VDAC_IFC_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IFC_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IFC_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0CD_DEFAULT (_VDAC_IFC_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1CD (0x1UL << 1) /**< Clear CH1CD Interrupt Flag */ +#define _VDAC_IFC_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IFC_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IFC_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1CD_DEFAULT (_VDAC_IFC_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0OF (0x1UL << 2) /**< Clear CH0OF Interrupt Flag */ +#define _VDAC_IFC_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IFC_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IFC_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0OF_DEFAULT (_VDAC_IFC_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1OF (0x1UL << 3) /**< Clear CH1OF Interrupt Flag */ +#define _VDAC_IFC_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IFC_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IFC_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1OF_DEFAULT (_VDAC_IFC_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0UF (0x1UL << 4) /**< Clear CH0UF Interrupt Flag */ +#define _VDAC_IFC_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0UF_DEFAULT (_VDAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1UF (0x1UL << 5) /**< Clear CH1UF Interrupt Flag */ +#define _VDAC_IFC_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1UF_DEFAULT (_VDAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_EM23ERR (0x1UL << 15) /**< Clear EM23ERR Interrupt Flag */ +#define _VDAC_IFC_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IFC_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_EM23ERR_DEFAULT (_VDAC_IFC_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0APORTCONFLICT (0x1UL << 16) /**< Clear OPA0APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFC_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFC_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1APORTCONFLICT (0x1UL << 17) /**< Clear OPA1APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFC_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFC_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2APORTCONFLICT (0x1UL << 18) /**< Clear OPA2APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFC_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFC_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0PRSTIMEDERR (0x1UL << 20) /**< Clear OPA0PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1PRSTIMEDERR (0x1UL << 21) /**< Clear OPA1PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2PRSTIMEDERR (0x1UL << 22) /**< Clear OPA2PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0OUTVALID (0x1UL << 28) /**< Clear OPA0OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IFC_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IFC_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0OUTVALID_DEFAULT (_VDAC_IFC_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1OUTVALID (0x1UL << 29) /**< Clear OPA1OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IFC_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IFC_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1OUTVALID_DEFAULT (_VDAC_IFC_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2OUTVALID (0x1UL << 30) /**< Clear OPA2OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IFC_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IFC_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2OUTVALID_DEFAULT (_VDAC_IFC_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFC */ + +/* Bit fields for VDAC IEN */ +#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ +#define _VDAC_IEN_MASK 0x707780FFUL /**< Mask for VDAC_IEN */ +#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0CD Interrupt Enable */ +#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1CD Interrupt Enable */ +#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF (0x1UL << 2) /**< CH0OF Interrupt Enable */ +#define _VDAC_IEN_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF (0x1UL << 3) /**< CH1OF Interrupt Enable */ +#define _VDAC_IEN_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF (0x1UL << 4) /**< CH0UF Interrupt Enable */ +#define _VDAC_IEN_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF (0x1UL << 5) /**< CH1UF Interrupt Enable */ +#define _VDAC_IEN_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0BL (0x1UL << 6) /**< CH0BL Interrupt Enable */ +#define _VDAC_IEN_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_IEN_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_IEN_CH0BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0BL_DEFAULT (_VDAC_IEN_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1BL (0x1UL << 7) /**< CH1BL Interrupt Enable */ +#define _VDAC_IEN_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_IEN_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_IEN_CH1BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1BL_DEFAULT (_VDAC_IEN_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_EM23ERR (0x1UL << 15) /**< EM23ERR Interrupt Enable */ +#define _VDAC_IEN_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IEN_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_EM23ERR_DEFAULT (_VDAC_IEN_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IEN_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IEN_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IEN_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IEN_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IEN_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IEN_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0OUTVALID (0x1UL << 28) /**< OPA0OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IEN_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IEN_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0OUTVALID_DEFAULT (_VDAC_IEN_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1OUTVALID (0x1UL << 29) /**< OPA1OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IEN_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IEN_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1OUTVALID_DEFAULT (_VDAC_IEN_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2OUTVALID (0x1UL << 30) /**< OPA2OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IEN_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IEN_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2OUTVALID_DEFAULT (_VDAC_IEN_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IEN */ + +/* Bit fields for VDAC CH0DATA */ +#define _VDAC_CH0DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH0DATA */ +#define _VDAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH0DATA */ +#define _VDAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH0DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH0DATA */ +#define VDAC_CH0DATA_DATA_DEFAULT (_VDAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0DATA */ + +/* Bit fields for VDAC CH1DATA */ +#define _VDAC_CH1DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH1DATA */ +#define _VDAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH1DATA */ +#define _VDAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH1DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH1DATA */ +#define VDAC_CH1DATA_DATA_DEFAULT (_VDAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1DATA */ + +/* Bit fields for VDAC COMBDATA */ +#define _VDAC_COMBDATA_RESETVALUE 0x08000800UL /**< Default value for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for VDAC_CH0DATA */ +#define _VDAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for VDAC_CH0DATA */ +#define _VDAC_COMBDATA_CH0DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ +#define VDAC_COMBDATA_CH0DATA_DEFAULT (_VDAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for VDAC_CH1DATA */ +#define _VDAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for VDAC_CH1DATA */ +#define _VDAC_COMBDATA_CH1DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ +#define VDAC_COMBDATA_CH1DATA_DEFAULT (_VDAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ + +/* Bit fields for VDAC CAL */ +#define _VDAC_CAL_RESETVALUE 0x00082004UL /**< Default value for VDAC_CAL */ +#define _VDAC_CAL_MASK 0x000F3F07UL /**< Mask for VDAC_CAL */ +#define _VDAC_CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for VDAC_OFFSETTRIM */ +#define _VDAC_CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for VDAC_OFFSETTRIM */ +#define _VDAC_CAL_OFFSETTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_OFFSETTRIM_DEFAULT (_VDAC_CAL_OFFSETTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CAL */ +#define _VDAC_CAL_GAINERRTRIM_SHIFT 8 /**< Shift value for VDAC_GAINERRTRIM */ +#define _VDAC_CAL_GAINERRTRIM_MASK 0x3F00UL /**< Bit mask for VDAC_GAINERRTRIM */ +#define _VDAC_CAL_GAINERRTRIM_DEFAULT 0x00000020UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_GAINERRTRIM_DEFAULT (_VDAC_CAL_GAINERRTRIM_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CAL */ +#define _VDAC_CAL_GAINERRTRIMCH1_SHIFT 16 /**< Shift value for VDAC_GAINERRTRIMCH1 */ +#define _VDAC_CAL_GAINERRTRIMCH1_MASK 0xF0000UL /**< Bit mask for VDAC_GAINERRTRIMCH1 */ +#define _VDAC_CAL_GAINERRTRIMCH1_DEFAULT 0x00000008UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_GAINERRTRIMCH1_DEFAULT (_VDAC_CAL_GAINERRTRIMCH1_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CAL */ + +/* Bit fields for VDAC OPA_APORTREQ */ +#define _VDAC_OPA_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTREQ */ +#define _VDAC_OPA_APORTREQ_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XREQ */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XREQ */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YREQ */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YREQ */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XREQ */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XREQ */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YREQ */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YREQ */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XREQ */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XREQ */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YREQ */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YREQ */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XREQ */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XREQ */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YREQ */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YREQ */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ + +/* Bit fields for VDAC OPA_APORTCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ + +/* Bit fields for VDAC OPA_CTRL */ +#define _VDAC_OPA_CTRL_RESETVALUE 0x0000000EUL /**< Default value for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_MASK 0x00313F1FUL /**< Mask for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for VDAC_OPADRIVESTRENGTH */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_MASK 0x3UL /**< Bit mask for VDAC_OPADRIVESTRENGTH */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT (_VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_INCBW (0x1UL << 2) /**< OPAx unity gain bandwidth scale. */ +#define _VDAC_OPA_CTRL_INCBW_SHIFT 2 /**< Shift value for VDAC_OPAINCBW */ +#define _VDAC_OPA_CTRL_INCBW_MASK 0x4UL /**< Bit mask for VDAC_OPAINCBW */ +#define _VDAC_OPA_CTRL_INCBW_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_INCBW_DEFAULT (_VDAC_OPA_CTRL_INCBW_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_HCMDIS (0x1UL << 3) /**< High Common Mode Disable. */ +#define _VDAC_OPA_CTRL_HCMDIS_SHIFT 3 /**< Shift value for VDAC_OPAHCMDIS */ +#define _VDAC_OPA_CTRL_HCMDIS_MASK 0x8UL /**< Bit mask for VDAC_OPAHCMDIS */ +#define _VDAC_OPA_CTRL_HCMDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_HCMDIS_DEFAULT (_VDAC_OPA_CTRL_HCMDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE (0x1UL << 4) /**< Scale OPAx output driving strength. */ +#define _VDAC_OPA_CTRL_OUTSCALE_SHIFT 4 /**< Shift value for VDAC_OPAOUTSCALE */ +#define _VDAC_OPA_CTRL_OUTSCALE_MASK 0x10UL /**< Bit mask for VDAC_OPAOUTSCALE */ +#define _VDAC_OPA_CTRL_OUTSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_OUTSCALE_FULL 0x00000000UL /**< Mode FULL for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_OUTSCALE_HALF 0x00000001UL /**< Mode HALF for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_DEFAULT (_VDAC_OPA_CTRL_OUTSCALE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_FULL (_VDAC_OPA_CTRL_OUTSCALE_FULL << 4) /**< Shifted mode FULL for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_HALF (_VDAC_OPA_CTRL_OUTSCALE_HALF << 4) /**< Shifted mode HALF for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSEN (0x1UL << 8) /**< OPAx PRS Trigger Enable */ +#define _VDAC_OPA_CTRL_PRSEN_SHIFT 8 /**< Shift value for VDAC_OPAPRSEN */ +#define _VDAC_OPA_CTRL_PRSEN_MASK 0x100UL /**< Bit mask for VDAC_OPAPRSEN */ +#define _VDAC_OPA_CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSEN_DEFAULT (_VDAC_OPA_CTRL_PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE (0x1UL << 9) /**< OPAx PRS Trigger Mode */ +#define _VDAC_OPA_CTRL_PRSMODE_SHIFT 9 /**< Shift value for VDAC_OPAPRSMODE */ +#define _VDAC_OPA_CTRL_PRSMODE_MASK 0x200UL /**< Bit mask for VDAC_OPAPRSMODE */ +#define _VDAC_OPA_CTRL_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_DEFAULT (_VDAC_OPA_CTRL_PRSMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_PULSED (_VDAC_OPA_CTRL_PRSMODE_PULSED << 9) /**< Shifted mode PULSED for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_TIMED (_VDAC_OPA_CTRL_PRSMODE_TIMED << 9) /**< Shifted mode TIMED for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_SHIFT 10 /**< Shift value for VDAC_OPAPRSSEL */ +#define _VDAC_OPA_CTRL_PRSSEL_MASK 0x3C00UL /**< Bit mask for VDAC_OPAPRSSEL */ +#define _VDAC_OPA_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_DEFAULT (_VDAC_OPA_CTRL_PRSSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH0 (_VDAC_OPA_CTRL_PRSSEL_PRSCH0 << 10) /**< Shifted mode PRSCH0 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH1 (_VDAC_OPA_CTRL_PRSSEL_PRSCH1 << 10) /**< Shifted mode PRSCH1 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH2 (_VDAC_OPA_CTRL_PRSSEL_PRSCH2 << 10) /**< Shifted mode PRSCH2 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH3 (_VDAC_OPA_CTRL_PRSSEL_PRSCH3 << 10) /**< Shifted mode PRSCH3 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH4 (_VDAC_OPA_CTRL_PRSSEL_PRSCH4 << 10) /**< Shifted mode PRSCH4 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH5 (_VDAC_OPA_CTRL_PRSSEL_PRSCH5 << 10) /**< Shifted mode PRSCH5 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH6 (_VDAC_OPA_CTRL_PRSSEL_PRSCH6 << 10) /**< Shifted mode PRSCH6 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH7 (_VDAC_OPA_CTRL_PRSSEL_PRSCH7 << 10) /**< Shifted mode PRSCH7 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH8 (_VDAC_OPA_CTRL_PRSSEL_PRSCH8 << 10) /**< Shifted mode PRSCH8 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH9 (_VDAC_OPA_CTRL_PRSSEL_PRSCH9 << 10) /**< Shifted mode PRSCH9 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH10 (_VDAC_OPA_CTRL_PRSSEL_PRSCH10 << 10) /**< Shifted mode PRSCH10 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH11 (_VDAC_OPA_CTRL_PRSSEL_PRSCH11 << 10) /**< Shifted mode PRSCH11 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE (0x1UL << 16) /**< OPAx PRS Output Select. */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_SHIFT 16 /**< Shift value for VDAC_OPAPRSOUTMODE */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_MASK 0x10000UL /**< Bit mask for VDAC_OPAPRSOUTMODE */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_WARM 0x00000000UL /**< Mode WARM for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID 0x00000001UL /**< Mode OUTVALID for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT (_VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_WARM (_VDAC_OPA_CTRL_PRSOUTMODE_WARM << 16) /**< Shifted mode WARM for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID (_VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID << 16) /**< Shifted mode OUTVALID for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTXMASTERDIS (0x1UL << 20) /**< APORT Bus Master Disable */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_SHIFT 20 /**< Shift value for VDAC_OPAAPORTXMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_MASK 0x100000UL /**< Bit mask for VDAC_OPAAPORTXMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTYMASTERDIS (0x1UL << 21) /**< APORT Bus Master Disable */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_SHIFT 21 /**< Shift value for VDAC_OPAAPORTYMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_MASK 0x200000UL /**< Bit mask for VDAC_OPAAPORTYMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ + +/* Bit fields for VDAC OPA_TIMER */ +#define _VDAC_OPA_TIMER_RESETVALUE 0x00010700UL /**< Default value for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_MASK 0x03FF7F3FUL /**< Mask for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_STARTUPDLY_SHIFT 0 /**< Shift value for VDAC_OPASTARTUPDLY */ +#define _VDAC_OPA_TIMER_STARTUPDLY_MASK 0x3FUL /**< Bit mask for VDAC_OPASTARTUPDLY */ +#define _VDAC_OPA_TIMER_STARTUPDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_STARTUPDLY_DEFAULT (_VDAC_OPA_TIMER_STARTUPDLY_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_WARMUPTIME_SHIFT 8 /**< Shift value for VDAC_OPAWARMUPTIME */ +#define _VDAC_OPA_TIMER_WARMUPTIME_MASK 0x7F00UL /**< Bit mask for VDAC_OPAWARMUPTIME */ +#define _VDAC_OPA_TIMER_WARMUPTIME_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_WARMUPTIME_DEFAULT (_VDAC_OPA_TIMER_WARMUPTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_SETTLETIME_SHIFT 16 /**< Shift value for VDAC_OPASETTLETIME */ +#define _VDAC_OPA_TIMER_SETTLETIME_MASK 0x3FF0000UL /**< Bit mask for VDAC_OPASETTLETIME */ +#define _VDAC_OPA_TIMER_SETTLETIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_SETTLETIME_DEFAULT (_VDAC_OPA_TIMER_SETTLETIME_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ + +/* Bit fields for VDAC OPA_MUX */ +#define _VDAC_OPA_MUX_RESETVALUE 0x0016F2F1UL /**< Default value for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_MASK 0x0717FFFFUL /**< Mask for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_SHIFT 0 /**< Shift value for VDAC_OPAPOSSEL */ +#define _VDAC_OPA_MUX_POSSEL_MASK 0xFFUL /**< Bit mask for VDAC_OPAPOSSEL */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH2 0x00000021UL /**< Mode APORT1XCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH4 0x00000022UL /**< Mode APORT1XCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH6 0x00000023UL /**< Mode APORT1XCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH8 0x00000024UL /**< Mode APORT1XCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH10 0x00000025UL /**< Mode APORT1XCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH12 0x00000026UL /**< Mode APORT1XCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH14 0x00000027UL /**< Mode APORT1XCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH16 0x00000028UL /**< Mode APORT1XCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH18 0x00000029UL /**< Mode APORT1XCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH20 0x0000002AUL /**< Mode APORT1XCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH22 0x0000002BUL /**< Mode APORT1XCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH24 0x0000002CUL /**< Mode APORT1XCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH26 0x0000002DUL /**< Mode APORT1XCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH28 0x0000002EUL /**< Mode APORT1XCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH30 0x0000002FUL /**< Mode APORT1XCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH1 0x00000040UL /**< Mode APORT2XCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH3 0x00000041UL /**< Mode APORT2XCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH5 0x00000042UL /**< Mode APORT2XCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH7 0x00000043UL /**< Mode APORT2XCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH9 0x00000044UL /**< Mode APORT2XCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH11 0x00000045UL /**< Mode APORT2XCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH13 0x00000046UL /**< Mode APORT2XCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH15 0x00000047UL /**< Mode APORT2XCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH17 0x00000048UL /**< Mode APORT2XCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH19 0x00000049UL /**< Mode APORT2XCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH21 0x0000004AUL /**< Mode APORT2XCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH23 0x0000004BUL /**< Mode APORT2XCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH25 0x0000004CUL /**< Mode APORT2XCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH27 0x0000004DUL /**< Mode APORT2XCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH29 0x0000004EUL /**< Mode APORT2XCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH31 0x0000004FUL /**< Mode APORT2XCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH2 0x00000061UL /**< Mode APORT3XCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH4 0x00000062UL /**< Mode APORT3XCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH6 0x00000063UL /**< Mode APORT3XCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH8 0x00000064UL /**< Mode APORT3XCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH10 0x00000065UL /**< Mode APORT3XCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH12 0x00000066UL /**< Mode APORT3XCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH14 0x00000067UL /**< Mode APORT3XCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH16 0x00000068UL /**< Mode APORT3XCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH18 0x00000069UL /**< Mode APORT3XCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH20 0x0000006AUL /**< Mode APORT3XCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH22 0x0000006BUL /**< Mode APORT3XCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH24 0x0000006CUL /**< Mode APORT3XCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH26 0x0000006DUL /**< Mode APORT3XCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH28 0x0000006EUL /**< Mode APORT3XCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH30 0x0000006FUL /**< Mode APORT3XCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH1 0x00000080UL /**< Mode APORT4XCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH3 0x00000081UL /**< Mode APORT4XCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH5 0x00000082UL /**< Mode APORT4XCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH7 0x00000083UL /**< Mode APORT4XCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH9 0x00000084UL /**< Mode APORT4XCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH11 0x00000085UL /**< Mode APORT4XCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH13 0x00000086UL /**< Mode APORT4XCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH15 0x00000087UL /**< Mode APORT4XCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH17 0x00000088UL /**< Mode APORT4XCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH19 0x00000089UL /**< Mode APORT4XCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH21 0x0000008AUL /**< Mode APORT4XCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH23 0x0000008BUL /**< Mode APORT4XCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH25 0x0000008CUL /**< Mode APORT4XCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH27 0x0000008DUL /**< Mode APORT4XCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH29 0x0000008EUL /**< Mode APORT4XCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH31 0x0000008FUL /**< Mode APORT4XCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DEFAULT 0x000000F1UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DAC 0x000000F1UL /**< Mode DAC for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_POSPAD 0x000000F2UL /**< Mode POSPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_OPANEXT 0x000000F3UL /**< Mode OPANEXT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_OPATAP 0x000000F4UL /**< Mode OPATAP for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH0 (_VDAC_OPA_MUX_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH2 (_VDAC_OPA_MUX_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH4 (_VDAC_OPA_MUX_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH6 (_VDAC_OPA_MUX_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH8 (_VDAC_OPA_MUX_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH10 (_VDAC_OPA_MUX_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH12 (_VDAC_OPA_MUX_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH14 (_VDAC_OPA_MUX_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH16 (_VDAC_OPA_MUX_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH18 (_VDAC_OPA_MUX_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH20 (_VDAC_OPA_MUX_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH22 (_VDAC_OPA_MUX_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH24 (_VDAC_OPA_MUX_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH26 (_VDAC_OPA_MUX_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH28 (_VDAC_OPA_MUX_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH30 (_VDAC_OPA_MUX_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH1 (_VDAC_OPA_MUX_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH3 (_VDAC_OPA_MUX_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH5 (_VDAC_OPA_MUX_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH7 (_VDAC_OPA_MUX_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH9 (_VDAC_OPA_MUX_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH11 (_VDAC_OPA_MUX_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH13 (_VDAC_OPA_MUX_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH15 (_VDAC_OPA_MUX_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH17 (_VDAC_OPA_MUX_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH19 (_VDAC_OPA_MUX_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH21 (_VDAC_OPA_MUX_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH23 (_VDAC_OPA_MUX_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH25 (_VDAC_OPA_MUX_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH27 (_VDAC_OPA_MUX_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH29 (_VDAC_OPA_MUX_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH31 (_VDAC_OPA_MUX_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH0 (_VDAC_OPA_MUX_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH2 (_VDAC_OPA_MUX_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH4 (_VDAC_OPA_MUX_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH6 (_VDAC_OPA_MUX_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH8 (_VDAC_OPA_MUX_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH10 (_VDAC_OPA_MUX_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH12 (_VDAC_OPA_MUX_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH14 (_VDAC_OPA_MUX_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH16 (_VDAC_OPA_MUX_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH18 (_VDAC_OPA_MUX_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH20 (_VDAC_OPA_MUX_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH22 (_VDAC_OPA_MUX_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH24 (_VDAC_OPA_MUX_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH26 (_VDAC_OPA_MUX_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH28 (_VDAC_OPA_MUX_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH30 (_VDAC_OPA_MUX_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH1 (_VDAC_OPA_MUX_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH3 (_VDAC_OPA_MUX_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH5 (_VDAC_OPA_MUX_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH7 (_VDAC_OPA_MUX_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH9 (_VDAC_OPA_MUX_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH11 (_VDAC_OPA_MUX_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH13 (_VDAC_OPA_MUX_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH15 (_VDAC_OPA_MUX_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH17 (_VDAC_OPA_MUX_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH19 (_VDAC_OPA_MUX_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH21 (_VDAC_OPA_MUX_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH23 (_VDAC_OPA_MUX_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH25 (_VDAC_OPA_MUX_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH27 (_VDAC_OPA_MUX_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH29 (_VDAC_OPA_MUX_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH31 (_VDAC_OPA_MUX_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DISABLE (_VDAC_OPA_MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DEFAULT (_VDAC_OPA_MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DAC (_VDAC_OPA_MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_POSPAD (_VDAC_OPA_MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_OPANEXT (_VDAC_OPA_MUX_POSSEL_OPANEXT << 0) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_OPATAP (_VDAC_OPA_MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_SHIFT 8 /**< Shift value for VDAC_OPANEGSEL */ +#define _VDAC_OPA_MUX_NEGSEL_MASK 0xFF00UL /**< Bit mask for VDAC_OPANEGSEL */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_UG 0x000000F1UL /**< Mode UG for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_DEFAULT 0x000000F2UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_OPATAP 0x000000F2UL /**< Mode OPATAP for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_NEGPAD 0x000000F3UL /**< Mode NEGPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_DISABLE (_VDAC_OPA_MUX_NEGSEL_DISABLE << 8) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_UG (_VDAC_OPA_MUX_NEGSEL_UG << 8) /**< Shifted mode UG for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_DEFAULT (_VDAC_OPA_MUX_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_OPATAP (_VDAC_OPA_MUX_NEGSEL_OPATAP << 8) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_NEGPAD (_VDAC_OPA_MUX_NEGSEL_NEGPAD << 8) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_SHIFT 16 /**< Shift value for VDAC_OPARESINMUX */ +#define _VDAC_OPA_MUX_RESINMUX_MASK 0x70000UL /**< Bit mask for VDAC_OPARESINMUX */ +#define _VDAC_OPA_MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_OPANEXT 0x00000001UL /**< Mode OPANEXT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_COMPAD 0x00000004UL /**< Mode COMPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_CENTER 0x00000005UL /**< Mode CENTER for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_DEFAULT 0x00000006UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_VSS 0x00000006UL /**< Mode VSS for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_DISABLE (_VDAC_OPA_MUX_RESINMUX_DISABLE << 16) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_OPANEXT (_VDAC_OPA_MUX_RESINMUX_OPANEXT << 16) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_NEGPAD (_VDAC_OPA_MUX_RESINMUX_NEGPAD << 16) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_POSPAD (_VDAC_OPA_MUX_RESINMUX_POSPAD << 16) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_COMPAD (_VDAC_OPA_MUX_RESINMUX_COMPAD << 16) /**< Shifted mode COMPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_CENTER (_VDAC_OPA_MUX_RESINMUX_CENTER << 16) /**< Shifted mode CENTER for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_DEFAULT (_VDAC_OPA_MUX_RESINMUX_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_VSS (_VDAC_OPA_MUX_RESINMUX_VSS << 16) /**< Shifted mode VSS for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_GAIN3X (0x1UL << 20) /**< OPAx Dedicated 3x gain resistor ladder. */ +#define _VDAC_OPA_MUX_GAIN3X_SHIFT 20 /**< Shift value for VDAC_OPAGAIN3X */ +#define _VDAC_OPA_MUX_GAIN3X_MASK 0x100000UL /**< Bit mask for VDAC_OPAGAIN3X */ +#define _VDAC_OPA_MUX_GAIN3X_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_GAIN3X_DEFAULT (_VDAC_OPA_MUX_GAIN3X_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_SHIFT 24 /**< Shift value for VDAC_OPARESSEL */ +#define _VDAC_OPA_MUX_RESSEL_MASK 0x7000000UL /**< Bit mask for VDAC_OPARESSEL */ +#define _VDAC_OPA_MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_DEFAULT (_VDAC_OPA_MUX_RESSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES0 (_VDAC_OPA_MUX_RESSEL_RES0 << 24) /**< Shifted mode RES0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES1 (_VDAC_OPA_MUX_RESSEL_RES1 << 24) /**< Shifted mode RES1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES2 (_VDAC_OPA_MUX_RESSEL_RES2 << 24) /**< Shifted mode RES2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES3 (_VDAC_OPA_MUX_RESSEL_RES3 << 24) /**< Shifted mode RES3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES4 (_VDAC_OPA_MUX_RESSEL_RES4 << 24) /**< Shifted mode RES4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES5 (_VDAC_OPA_MUX_RESSEL_RES5 << 24) /**< Shifted mode RES5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES6 (_VDAC_OPA_MUX_RESSEL_RES6 << 24) /**< Shifted mode RES6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES7 (_VDAC_OPA_MUX_RESSEL_RES7 << 24) /**< Shifted mode RES7 for VDAC_OPA_MUX */ + +/* Bit fields for VDAC OPA_OUT */ +#define _VDAC_OPA_OUT_RESETVALUE 0x00000001UL /**< Default value for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_MASK 0x00FF01FFUL /**< Mask for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_MAINOUTEN (0x1UL << 0) /**< OPAx Main Output Enable */ +#define _VDAC_OPA_OUT_MAINOUTEN_SHIFT 0 /**< Shift value for VDAC_OPAMAINOUTEN */ +#define _VDAC_OPA_OUT_MAINOUTEN_MASK 0x1UL /**< Bit mask for VDAC_OPAMAINOUTEN */ +#define _VDAC_OPA_OUT_MAINOUTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_MAINOUTEN_DEFAULT (_VDAC_OPA_OUT_MAINOUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTEN (0x1UL << 1) /**< OPAx Alternative Output Enable */ +#define _VDAC_OPA_OUT_ALTOUTEN_SHIFT 1 /**< Shift value for VDAC_OPAALTOUTEN */ +#define _VDAC_OPA_OUT_ALTOUTEN_MASK 0x2UL /**< Bit mask for VDAC_OPAALTOUTEN */ +#define _VDAC_OPA_OUT_ALTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTEN (0x1UL << 2) /**< OPAx Aport Output Enable */ +#define _VDAC_OPA_OUT_APORTOUTEN_SHIFT 2 /**< Shift value for VDAC_OPAAPORTOUTEN */ +#define _VDAC_OPA_OUT_APORTOUTEN_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORTOUTEN */ +#define _VDAC_OPA_OUT_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTEN_DEFAULT (_VDAC_OPA_OUT_APORTOUTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_SHORT (0x1UL << 3) /**< OPAx Main and Alternative Output Short */ +#define _VDAC_OPA_OUT_SHORT_SHIFT 3 /**< Shift value for VDAC_OPASHORT */ +#define _VDAC_OPA_OUT_SHORT_MASK 0x8UL /**< Bit mask for VDAC_OPASHORT */ +#define _VDAC_OPA_OUT_SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_SHORT_DEFAULT (_VDAC_OPA_OUT_SHORT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_SHIFT 4 /**< Shift value for VDAC_OPAALTOUTPADEN */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_MASK 0x1F0UL /**< Bit mask for VDAC_OPAALTOUTPADEN */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT0 0x00000001UL /**< Mode OUT0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT1 0x00000002UL /**< Mode OUT1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT2 0x00000004UL /**< Mode OUT2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT3 0x00000008UL /**< Mode OUT3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT4 0x00000010UL /**< Mode OUT4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT0 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT0 << 4) /**< Shifted mode OUT0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT1 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT1 << 4) /**< Shifted mode OUT1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT2 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT2 << 4) /**< Shifted mode OUT2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT3 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT3 << 4) /**< Shifted mode OUT3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT4 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT4 << 4) /**< Shifted mode OUT4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_SHIFT 16 /**< Shift value for VDAC_OPAAPORTOUTSEL */ +#define _VDAC_OPA_OUT_APORTOUTSEL_MASK 0xFF0000UL /**< Bit mask for VDAC_OPAAPORTOUTSEL */ +#define _VDAC_OPA_OUT_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_DEFAULT (_VDAC_OPA_OUT_APORTOUTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for VDAC_OPA_OUT */ + +/* Bit fields for VDAC OPA_CAL */ +#define _VDAC_OPA_CAL_RESETVALUE 0x000080E7UL /**< Default value for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_MASK 0x7DF6EDEFUL /**< Mask for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM1_SHIFT 0 /**< Shift value for VDAC_OPACM1 */ +#define _VDAC_OPA_CAL_CM1_MASK 0xFUL /**< Bit mask for VDAC_OPACM1 */ +#define _VDAC_OPA_CAL_CM1_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM1_DEFAULT (_VDAC_OPA_CAL_CM1_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM2_SHIFT 5 /**< Shift value for VDAC_OPACM2 */ +#define _VDAC_OPA_CAL_CM2_MASK 0x1E0UL /**< Bit mask for VDAC_OPACM2 */ +#define _VDAC_OPA_CAL_CM2_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM2_DEFAULT (_VDAC_OPA_CAL_CM2_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM3_SHIFT 10 /**< Shift value for VDAC_OPACM3 */ +#define _VDAC_OPA_CAL_CM3_MASK 0xC00UL /**< Bit mask for VDAC_OPACM3 */ +#define _VDAC_OPA_CAL_CM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM3_DEFAULT (_VDAC_OPA_CAL_CM3_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_GM_SHIFT 13 /**< Shift value for VDAC_OPAGM */ +#define _VDAC_OPA_CAL_GM_MASK 0xE000UL /**< Bit mask for VDAC_OPAGM */ +#define _VDAC_OPA_CAL_GM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_GM_DEFAULT (_VDAC_OPA_CAL_GM_DEFAULT << 13) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_GM3_SHIFT 17 /**< Shift value for VDAC_OPAGM3 */ +#define _VDAC_OPA_CAL_GM3_MASK 0x60000UL /**< Bit mask for VDAC_OPAGM3 */ +#define _VDAC_OPA_CAL_GM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_GM3_DEFAULT (_VDAC_OPA_CAL_GM3_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_OFFSETP_SHIFT 20 /**< Shift value for VDAC_OPAOFFSETP */ +#define _VDAC_OPA_CAL_OFFSETP_MASK 0x1F00000UL /**< Bit mask for VDAC_OPAOFFSETP */ +#define _VDAC_OPA_CAL_OFFSETP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_OFFSETP_DEFAULT (_VDAC_OPA_CAL_OFFSETP_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_OFFSETN_SHIFT 26 /**< Shift value for VDAC_OPAOFFSETN */ +#define _VDAC_OPA_CAL_OFFSETN_MASK 0x7C000000UL /**< Bit mask for VDAC_OPAOFFSETN */ +#define _VDAC_OPA_CAL_OFFSETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_OFFSETN_DEFAULT (_VDAC_OPA_CAL_OFFSETN_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ + +/** @} End of group EFR32MG12P_VDAC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac_opa.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac_opa.h new file mode 100644 index 00000000000..ad0e6b87292 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac_opa.h @@ -0,0 +1,53 @@ +/**************************************************************************//** + * @file efr32mg12p_vdac_opa.h + * @brief EFR32MG12P_VDAC_OPA register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief VDAC_OPA EFR32MG12P VDAC OPA + *****************************************************************************/ +typedef struct +{ + __IM uint32_t APORTREQ; /**< Operational Amplifier APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< Operational Amplifier APORT Conflict Status Register */ + __IOM uint32_t CTRL; /**< Operational Amplifier Control Register */ + __IOM uint32_t TIMER; /**< Operational Amplifier Timer Control Register */ + __IOM uint32_t MUX; /**< Operational Amplifier Mux Configuration Register */ + __IOM uint32_t OUT; /**< Operational Amplifier Output Configuration Register */ + __IOM uint32_t CAL; /**< Operational Amplifier Calibration Register */ + uint32_t RESERVED0[1]; /**< Reserved future */ +} VDAC_OPA_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h new file mode 100644 index 00000000000..8f29cf766a1 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h @@ -0,0 +1,335 @@ +/**************************************************************************//** + * @file efr32mg12p_wdog.h + * @brief EFR32MG12P_WDOG register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_WDOG + * @{ + * @brief EFR32MG12P_WDOG Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + WDOG_PCH_TypeDef PCH[2]; /**< PCH */ + + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Watchdog Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} WDOG_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_WDOG_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for WDOG CTRL */ +#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */ +#define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */ +#define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */ +#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */ +#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */ +#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */ +#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */ +#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */ +#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_HFCORECLK 0x00000003UL /**< Mode HFCORECLK for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_HFCORECLK (_WDOG_CTRL_CLKSEL_HFCORECLK << 12) /**< Shifted mode HFCORECLK for WDOG_CTRL */ +#define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */ +#define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */ +#define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */ +#define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */ +#define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/* Bit fields for WDOG PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IFS */ +#define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */ +#define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */ +#define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */ +#define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */ +#define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */ +#define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */ +#define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */ +#define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */ + +/* Bit fields for WDOG IFC */ +#define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */ +#define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */ +#define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */ +#define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */ +#define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */ +#define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */ +#define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */ +#define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/** @} End of group EFR32MG12P_WDOG */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog_pch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog_pch.h new file mode 100644 index 00000000000..2447840919b --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog_pch.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efr32mg12p_wdog_pch.h + * @brief EFR32MG12P_WDOG_PCH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief WDOG_PCH EFR32MG12P WDOG PCH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t PRSCTRL; /**< PRS Control Register */ +} WDOG_PCH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/em_device.h new file mode 100644 index 00000000000..5dba5054751 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/em_device.h @@ -0,0 +1,80 @@ +/**************************************************************************//** + * @file em_device.h + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + * + * + * @endverbatim + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H + +#if defined(EFR32MG12P132F1024GL125) +#include "efr32mg12p132f1024gl125.h" + +#elif defined(EFR32MG12P132F1024GM48) +#include "efr32mg12p132f1024gm48.h" + +#elif defined(EFR32MG12P232F1024GL125) +#include "efr32mg12p232f1024gl125.h" + +#elif defined(EFR32MG12P232F1024GM48) +#include "efr32mg12p232f1024gm48.h" + +#elif defined(EFR32MG12P332F1024GL125) +#include "efr32mg12p332f1024gl125.h" + +#elif defined(EFR32MG12P332F1024GM48) +#include "efr32mg12p332f1024gm48.h" + +#elif defined(EFR32MG12P432F1024GL125) +#include "efr32mg12p432f1024gl125.h" + +#elif defined(EFR32MG12P432F1024GM48) +#include "efr32mg12p432f1024gm48.h" + +#elif defined(EFR32MG12P433F1024GL125) +#include "efr32mg12p433f1024gl125.h" + +#elif defined(EFR32MG12P433F1024GM48) +#include "efr32mg12p433f1024gm48.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif +#endif /* EM_DEVICE_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.c new file mode 100644 index 00000000000..8737716b138 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.c @@ -0,0 +1,384 @@ +/***************************************************************************//** + * @file system_efr32mg12p.c + * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** LFRCO frequency, tuned to below frequency during manufacturing. */ +#define EFR32_LFRCO_FREQ (32768UL) +#define EFR32_ULFRCO_FREQ (1000UL) + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +/* System oscillator frequencies. These frequencies are normally constant */ +/* for a target, but they are made configurable in order to allow run-time */ +/* handling of different boards. The crystal oscillator clocks can be set */ +/* compile time to a non-default value by defining respective EFR_nFXO_FREQ */ +/* values according to board design. By defining the EFR_nFXO_FREQ to 0, */ +/* one indicates that the oscillator is not present, in order to save some */ +/* SW footprint. */ + +#ifndef EFR32_HFRCO_MAX_FREQ +#define EFR32_HFRCO_MAX_FREQ (38000000UL) +#endif + +#ifndef EFR32_HFXO_FREQ +#define EFR32_HFXO_FREQ (38400000UL) +#endif + +#ifndef EFR32_HFRCO_STARTUP_FREQ +#define EFR32_HFRCO_STARTUP_FREQ (19000000UL) +#endif + + +/* Do not define variable if HF crystal oscillator not present */ +#if (EFR32_HFXO_FREQ > 0UL) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System HFXO clock. */ +static uint32_t SystemHFXOClock = EFR32_HFXO_FREQ; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + +#ifndef EFR32_LFXO_FREQ +#define EFR32_LFXO_FREQ (EFR32_LFRCO_FREQ) +#endif +/* Do not define variable if LF crystal oscillator not present */ +#if (EFR32_LFXO_FREQ > 0UL) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System LFXO clock. */ +static uint32_t SystemLFXOClock = 32768UL; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock; + + +/** + * @brief + * System HFRCO frequency + * + * @note + * This is an EFR32 proprietary variable, not part of the CMSIS definition. + * + * @details + * Frequency of the system HFRCO oscillator + */ +uint32_t SystemHfrcoFreq = EFR32_HFRCO_STARTUP_FREQ; + + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the current core clock frequency. + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is an EFR32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemCoreClockGet(void) +{ + uint32_t ret; + uint32_t presc; + + ret = SystemHFClockGet(); + presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >> + _CMU_HFCOREPRESC_PRESC_SHIFT; + ret /= (presc + 1); + + /* Keep CMSIS system clock variable up-to-date */ + SystemCoreClock = ret; + + return ret; +} + + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is an EFR32 proprietary function, not part of the CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return (EFR32_HFRCO_MAX_FREQ > EFR32_HFXO_FREQ ? \ + EFR32_HFRCO_MAX_FREQ : EFR32_HFXO_FREQ); +} + + +/***************************************************************************//** + * @brief + * Get the current HFCLK frequency. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @return + * The current HFCLK frequency in Hz. + ******************************************************************************/ +uint32_t SystemHFClockGet(void) +{ + uint32_t ret; + + switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) + { + case CMU_HFCLKSTATUS_SELECTED_LFXO: +#if (EFR32_LFXO_FREQ > 0) + ret = SystemLFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + case CMU_HFCLKSTATUS_SELECTED_LFRCO: + ret = EFR32_LFRCO_FREQ; + break; + + case CMU_HFCLKSTATUS_SELECTED_HFXO: +#if (EFR32_HFXO_FREQ > 0) + ret = SystemHFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */ + ret = SystemHfrcoFreq; + break; + } + + return ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT)); +} + + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @return + * HFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFR32_HFXO_FREQ > 0) + return SystemHFXOClock; +#else + return 0; +#endif +} + + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFR32_HFXO_FREQ > 0) + SystemHFXOClock = freq; + + /* Update core clock frequency if HFXO is used to clock core */ + if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_HFXO) + { + /* The function will update the global variable */ + SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} + + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Set floating point coprosessor access mode. */ + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif +} + + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + /* Currently we assume that this frequency is properly tuned during */ + /* manufacturing and is not changed after reset. If future requirements */ + /* for re-tuning by user, we can add support for that. */ + return EFR32_LFRCO_FREQ; +} + + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + /* The ULFRCO frequency is not tuned, and can be very inaccurate */ + return EFR32_ULFRCO_FREQ; +} + + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFR32_LFXO_FREQ > 0) + return SystemLFXOClock; +#else + return 0; +#endif +} + + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFR_LFXO_FREQ > 0) + SystemLFXOClock = freq; + + /* Update core clock frequency if LFXO is used to clock core */ + if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_LFXO) + { + /* The function will update the global variable */ + SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.h new file mode 100644 index 00000000000..8e00b80fdbb --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.h @@ -0,0 +1,154 @@ +/***************************************************************************//** + * @file system_efr32mg12p.h + * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef SYSTEM_EFR32_H +#define SYSTEM_EFR32_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void EMU_IRQHandler(void); +void FRC_PRI_IRQHandler(void); +void WDOG0_IRQHandler(void); +void WDOG1_IRQHandler(void); +void FRC_IRQHandler(void); +void MODEM_IRQHandler(void); +void RAC_SEQ_IRQHandler(void); +void RAC_RSM_IRQHandler(void); +void BUFC_IRQHandler(void); +void LDMA_IRQHandler(void); +void GPIO_EVEN_IRQHandler(void); +void TIMER0_IRQHandler(void); +void USART0_RX_IRQHandler(void); +void USART0_TX_IRQHandler(void); +void ACMP0_IRQHandler(void); +void ADC0_IRQHandler(void); +void IDAC0_IRQHandler(void); +void I2C0_IRQHandler(void); +void GPIO_ODD_IRQHandler(void); +void TIMER1_IRQHandler(void); +void USART1_RX_IRQHandler(void); +void USART1_TX_IRQHandler(void); +void LEUART0_IRQHandler(void); +void PCNT0_IRQHandler(void); +void CMU_IRQHandler(void); +void MSC_IRQHandler(void); +void CRYPTO0_IRQHandler(void); +void LETIMER0_IRQHandler(void); +void AGC_IRQHandler(void); +void PROTIMER_IRQHandler(void); +void RTCC_IRQHandler(void); +void SYNTH_IRQHandler(void); +void CRYOTIMER_IRQHandler(void); +void RFSENSE_IRQHandler(void); +void FPUEH_IRQHandler(void); +void SMU_IRQHandler(void); +void WTIMER0_IRQHandler(void); +void WTIMER1_IRQHandler(void); +void PCNT1_IRQHandler(void); +void PCNT2_IRQHandler(void); +void USART2_RX_IRQHandler(void); +void USART2_TX_IRQHandler(void); +void I2C1_IRQHandler(void); +void USART3_RX_IRQHandler(void); +void USART3_TX_IRQHandler(void); +void VDAC0_IRQHandler(void); +void CSEN_IRQHandler(void); +void LESENSE_IRQHandler(void); +void CRYPTO1_IRQHandler(void); +void TRNG0_IRQHandler(void); +void SYSCFG_IRQHandler(void); + +uint32_t SystemCoreClockGet(void); + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EFR CMU + * API, this variable will be kept updated. This function is only provided + * for CMSIS compliance and if a user modifies the the core clock outside + * the CMU API. + *****************************************************************************/ +static __INLINE void SystemCoreClockUpdate(void) +{ + SystemCoreClockGet(); +} + +uint32_t SystemMaxCoreClockGet(void); + +void SystemInit(void); +uint32_t SystemHFClockGet(void); + +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); + +uint32_t SystemLFRCOClockGet(void); +uint32_t SystemULFRCOClockGet(void); + +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_EFR32_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h index dd6847ac578..47bc0c03fb4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h @@ -30,14 +30,17 @@ * bits represent port number (A = 0, B = 1, ...) */ #define EFM32_STANDARD_PIN_DEFINITIONS \ - PA0 = 0 << 4, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, \ - PB0 = 1 << 4, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, \ - PC0 = 2 << 4, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, \ - PD0 = 3 << 4, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, \ - PE0 = 4 << 4, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, \ - PF0 = 5 << 4, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, \ - PG0 = 5 << 4, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, \ - PH0 = 5 << 4, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, \ + PA0 = 0 << 4, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, \ + PB0 = 1 << 4, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, \ + PC0 = 2 << 4, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, \ + PD0 = 3 << 4, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, \ + PE0 = 4 << 4, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, \ + PF0 = 5 << 4, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, \ + PG0 = 6 << 4, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, \ + PH0 = 7 << 4, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, \ + PI0 = 8 << 4, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, \ + PJ0 = 9 << 4, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, \ + PK0 = 10 << 4, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, \ NC = (int) 0xFFFFFFFF #ifdef __cplusplus diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/PortNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/PortNames.h index ebece26ee94..65c44da1396 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/PortNames.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/PortNames.h @@ -46,13 +46,22 @@ typedef enum { PortE = gpioPortE, /**< Port E */ #endif #if ( _GPIO_PORT_F_PIN_COUNT > 0 ) - PortF = gpioPortF /**< Port F */ + PortF = gpioPortF, /**< Port F */ #endif #if defined( _GPIO_PORT_G_PIN_COUNT ) && ( _GPIO_PORT_G_PIN_COUNT > 0 ) - PortG = gpioPortG /**< Port F */ + PortG = gpioPortG, /**< Port G */ #endif #if defined( _GPIO_PORT_H_PIN_COUNT ) && ( _GPIO_PORT_H_PIN_COUNT > 0 ) - PortH = gpioPortH /**< Port F */ + PortH = gpioPortH, /**< Port H */ +#endif +#if defined( _GPIO_PORT_I_PIN_COUNT ) && ( _GPIO_PORT_I_PIN_COUNT > 0 ) + PortI = gpioPortI, /**< Port I */ +#endif +#if defined( _GPIO_PORT_J_PIN_COUNT ) && ( _GPIO_PORT_J_PIN_COUNT > 0 ) + PortJ = gpioPortJ, /**< Port J */ +#endif +#if defined( _GPIO_PORT_K_PIN_COUNT ) && ( _GPIO_PORT_K_PIN_COUNT > 0 ) + PortK = gpioPortK, /**< Port K */ #endif } PortName; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c index 34aed53b18e..c0032139590 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c @@ -42,12 +42,15 @@ void mbed_sdk_init() EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT; EMU_DCDCInit(&dcdcInit); -#if defined(DEVICE_RF_2P4GHZ) || defined(DEVICE_RF_SUBGHZ) +#if defined(_EFR_DEVICE) CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_WSTK_DEFAULT; // Initialize the HFXO using the settings from the WSTK bspconfig.h // Note: This configures things like the capacitive tuning CTUNE variable // which can vary based on your hardware design. - CMU_HFXOInit(&hfxoInit); + CMU_HFXOInit(&hfxoInit); +#else + CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_STK_DEFAULT; + CMU_HFXOInit(&hfxoInit); #endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt index 2e8ebff97bc..c7eda3458e6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt @@ -1,4 +1,45 @@ ================ Revision history ============================================ +5.1.2: + Misc. bugfixes and improvements. + +5.1.1: + - Enabled errata CMU_E113 workaround for EFM32GG revE. + +5.1.0: + - em_timer: Added support for WTIMER0 and WTIMER1. Added EFM_ASSERT in + em_timer to check that operations on a 16 bit timer is always <= 0xFFFF. + - em_usart: Updated the baudrate sync calculation in USART_BaudrateSyncSet(). + The calculated baudrate is not using any fractional bits and it is always + lower than or equal to the specified frequency. + - em_emu: added function EMU_DCDCConductionModeSet() to allow switching + between DCDC Low-Noise Continuous Conduction Mode (CCM) and + Discontinuous Conduction Mode (DCM). + - SYSTEM_GetSRAMSize() updated to return size of SRAM excluding RAMH for EFR32xG1. + - em_csen: Added support for CSEN (Capacitive Sense Module). + - em_adc: updated ADC_PosSel_TypeDef enum names. + - em_vdac: Added support for VDAC (voltage DAC). + - em_smu: Added support for SMU (Security Management Unit) module. + SMU is used to restrict access to device peripherals. + - Updated emlib to use the _SILICON_LABS_32B_SERIES_x, + _SILICON_LABS_32B_SERIES_x_CONFIG and _SILICON_LABS_GECKO_INTERNAL_SDID_x + macros instead of the _SILICON_LABS_32B_PLATFORM_x and + _SILICON_LABS_32B_PLATFORM_x_GEN_x macros. + - em_rtcc: added workarounds for errata RTCC_E203 and RTCC_E204 for + EFR32xG12, EFM32xG12, EFR32xG13 and EFM32xG13 devices. + - em_lesense: added LESENSE_DecoderPrsOut() for configuring PRS output + from the LESENSE decoder on EFM32xG12 and EFR32xG12. + - em_lesense: added support for the new evaluation modes for EFM32xG12 and + EFR32xG12. + - em_emu: added EMU_RamPowerDown() function for powering down a memory range + and deprecating EMU_MemPwrDown(). + - em_emu: added support for voltage scaling. + - em_emu: added support for EM2 and 3 peripheral retention control. + - em_chip: added current consumption fixes for EFM32xG12 and EFR32xG12. + - em_emu: added support for DCDC EM01-LP mode. + - em_lesense: Support for Series 1 devices + - em_acmp: Added ACMP_ExternalInputSelect() which is used when the ACMP is + controlled by an external module like LESENSE. + 5.0.0: - em_core: New module, contains API for enabling/disabling interrupts and implementing critical regions. diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h index 19345e9a974..ed9de1b4dde 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_acmp.h * @brief Analog Comparator (ACMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -283,7 +283,7 @@ typedef enum } ACMP_VLPInput_Typedef; #endif -#if defined(_SILICON_LABS_32B_PLATFORM_2) +#if defined(_ACMP_INPUTSEL_POSSEL_APORT0XCH0) /** ACMP Input Selection */ typedef enum { @@ -447,8 +447,12 @@ typedef enum acmpInputAPORT4YCH14 = _ACMP_INPUTSEL_POSSEL_APORT4YCH14, acmpInputAPORT4XCH15 = _ACMP_INPUTSEL_POSSEL_APORT4XCH15, acmpInputAPORT4XCH31 = _ACMP_INPUTSEL_POSSEL_APORT4XCH31, +#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT0) acmpInputDACOUT0 = _ACMP_INPUTSEL_POSSEL_DACOUT0, +#endif +#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT1) acmpInputDACOUT1 = _ACMP_INPUTSEL_POSSEL_DACOUT1, +#endif acmpInputVLP = _ACMP_INPUTSEL_POSSEL_VLP, acmpInputVBDIV = _ACMP_INPUTSEL_POSSEL_VBDIV, acmpInputVADIV = _ACMP_INPUTSEL_POSSEL_VADIV, @@ -500,6 +504,31 @@ typedef enum } ACMP_Channel_TypeDef; #endif +#if defined(_ACMP_EXTIFCTRL_MASK) +/** + * ACMP External input select. This type is used to select which APORT that is + * used by an external module like LESENSE when it's taking control over + * the ACMP input. + */ +typedef enum +{ + acmpExternalInputAPORT0X = _ACMP_EXTIFCTRL_APORTSEL_APORT0X, + acmpExternalInputAPORT0Y = _ACMP_EXTIFCTRL_APORTSEL_APORT0Y, + acmpExternalInputAPORT1X = _ACMP_EXTIFCTRL_APORTSEL_APORT1X, + acmpExternalInputAPORT1Y = _ACMP_EXTIFCTRL_APORTSEL_APORT1Y, + acmpExternalInputAPORT1XY = _ACMP_EXTIFCTRL_APORTSEL_APORT1XY, + acmpExternalInputAPORT2X = _ACMP_EXTIFCTRL_APORTSEL_APORT2X, + acmpExternalInputAPORT2Y = _ACMP_EXTIFCTRL_APORTSEL_APORT2Y, + acmpExternalInputAPORT2YX = _ACMP_EXTIFCTRL_APORTSEL_APORT2YX, + acmpExternalInputAPORT3X = _ACMP_EXTIFCTRL_APORTSEL_APORT3X, + acmpExternalInputAPORT3Y = _ACMP_EXTIFCTRL_APORTSEL_APORT3Y, + acmpExternalInputAPORT3XY = _ACMP_EXTIFCTRL_APORTSEL_APORT3XY, + acmpExternalInputAPORT4X = _ACMP_EXTIFCTRL_APORTSEL_APORT4X, + acmpExternalInputAPORT4Y = _ACMP_EXTIFCTRL_APORTSEL_APORT4Y, + acmpExternalInputAPORT4YX = _ACMP_EXTIFCTRL_APORTSEL_APORT4YX, +} ACMP_ExternalInput_Typedef; +#endif + /******************************************************************************* ****************************** STRUCTS ************************************ ******************************************************************************/ @@ -824,6 +853,9 @@ void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel); void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel, ACMP_Channel_TypeDef posSel); void ACMP_Disable(ACMP_TypeDef *acmp); void ACMP_Enable(ACMP_TypeDef *acmp); +#if defined(_ACMP_EXTIFCTRL_MASK) +void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport); +#endif void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert); void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init); void ACMP_Reset(ACMP_TypeDef *acmp); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h index 0cd23c792a8..08bb52614da 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_adc.h * @brief Analog to Digital Converter (ADC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -494,25 +494,26 @@ typedef enum adcPosSelAPORT4YCH30 = _ADC_SINGLECTRL_POSSEL_APORT4YCH30, adcPosSelAPORT4XCH31 = _ADC_SINGLECTRL_POSSEL_APORT4XCH31, adcPosSelAVDD = _ADC_SINGLECTRL_POSSEL_AVDD, - adcPosSelBU = _ADC_SINGLECTRL_POSSEL_BU, - adcPosSelAREG = _ADC_SINGLECTRL_POSSEL_AREG, - adcPosSelVREGOUTPA = _ADC_SINGLECTRL_POSSEL_VREGOUTPA, - adcPosSelPDBU = _ADC_SINGLECTRL_POSSEL_PDBU, - adcPosSelIO0 = _ADC_SINGLECTRL_POSSEL_IO0, - adcPosSelIO1 = _ADC_SINGLECTRL_POSSEL_IO1, - adcPosSelVSP = _ADC_SINGLECTRL_POSSEL_VSP, + adcPosSelDVDD = _ADC_SINGLECTRL_POSSEL_AREG, + adcPosSelPAVDD = _ADC_SINGLECTRL_POSSEL_VREGOUTPA, + adcPosSelDECOUPLE = _ADC_SINGLECTRL_POSSEL_PDBU, + adcPosSelIOVDD = _ADC_SINGLECTRL_POSSEL_IO0, adcPosSelOPA2 = _ADC_SINGLECTRL_POSSEL_OPA2, adcPosSelOPA3 = _ADC_SINGLECTRL_POSSEL_OPA3, adcPosSelTEMP = _ADC_SINGLECTRL_POSSEL_TEMP, adcPosSelDAC0OUT0 = _ADC_SINGLECTRL_POSSEL_DAC0OUT0, - adcPosSelTESTP = _ADC_SINGLECTRL_POSSEL_TESTP, - adcPosSelSP1 = _ADC_SINGLECTRL_POSSEL_SP1, - adcPosSelSP2 = _ADC_SINGLECTRL_POSSEL_SP2, adcPosSelDAC0OUT1 = _ADC_SINGLECTRL_POSSEL_DAC0OUT1, adcPosSelSUBLSB = _ADC_SINGLECTRL_POSSEL_SUBLSB, adcPosSelDEFAULT = _ADC_SINGLECTRL_POSSEL_DEFAULT, adcPosSelVSS = _ADC_SINGLECTRL_POSSEL_VSS } ADC_PosSel_TypeDef; + +/* Map legacy or incorrectly named select enums to correct enums. */ +#define adcPosSelIO0 adcPosSelIOVDD +#define adcPosSelVREGOUTPA adcPosSelPAVDD +#define adcPosSelAREG adcPosSelDVDD +#define adcPosSelPDBU adcPosSelDECOUPLE + #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h index b7aee281d9a..63c76353f42 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_aes.h * @brief Advanced encryption standard (AES) accelerator peripheral API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h index fb4d2f0d93d..d0a2a922598 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_assert.h * @brief Emlib peripheral API "assert" implementation. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h index 1303111ef94..5787aa377c9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_burtc.h * @brief Backup Real Time Counter (BURTC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h index c775e3437a2..fc13eaf9f36 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_bus.h * @brief RAM and peripheral bit-field set and clear API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -30,8 +30,8 @@ * ******************************************************************************/ -#ifndef EM_BUS__ -#define EM_BUS__ +#ifndef EM_BUS_H +#define EM_BUS_H #include "em_device.h" @@ -46,9 +46,9 @@ extern "C" { /***************************************************************************//** * @addtogroup BUS - * @brief BUS RAM and register bit/field read/write API + * @brief BUS register and RAM bit/field read/write API * @details - * API to perform bitbanded and masked accesses to SRAM and peripheral memory. + * API to perform bit-band and field set/clear access to RAM and peripherals. * @{ ******************************************************************************/ @@ -280,7 +280,10 @@ __STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr, * @param[in] mask Peripheral register mask * * @param[in] val Peripheral register value. The value must be shifted to the - correct bit position in the register. + correct bit position in the register corresponding to the field + defined by the mask parameter. The register value must be + contained in the field defined by the mask parameter. This + function is not performing masking of val internally. ******************************************************************************/ __STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, @@ -326,4 +329,4 @@ __STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, } #endif -#endif /* EM_BUS__ */ +#endif /* EM_BUS_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h index 41979c626b0..75989934b18 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_chip.h * @brief Chip Initialization API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -49,7 +49,7 @@ extern "C" { /***************************************************************************//** * @addtogroup CHIP - * @brief Chip Initialization API + * @brief Chip errata workarounds initialization API * @details * API to initialize chip for errata workarounds. * @{ @@ -69,7 +69,7 @@ extern "C" { *****************************************************************************/ __STATIC_INLINE void CHIP_Init(void) { -#if defined(_EFM32_GECKO_FAMILY) +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) uint32_t rev; SYSTEM_ChipRevision_TypeDef chipRev; volatile uint32_t *reg; @@ -161,26 +161,31 @@ __STATIC_INLINE void CHIP_Init(void) } #endif -#if defined(_EFM32_GIANT_FAMILY) - uint32_t rev; +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) + + /****************************/ + /* Fix for errata CMU_E113. */ + + uint8_t prodRev; SYSTEM_ChipRevision_TypeDef chipRev; - rev = *(volatile uint32_t *)(0x0FE081FC); + prodRev = SYSTEM_GetProdRev(); SYSTEM_ChipRevisionGet(&chipRev); - if (((rev >> 24) > 15) && (chipRev.minor == 3)) + if ((prodRev >= 16) && (chipRev.minor >= 3)) { /* This fixes an issue with the LFXO on high temperatures. */ *(volatile uint32_t*)0x400C80C0 = - ( *(volatile uint32_t*)0x400C80C0 & ~(1<<6) ) | (1<<4); + ( *(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4); } #endif -#if defined(_EFM32_HAPPY_FAMILY) - uint32_t rev; - rev = *(volatile uint32_t *)(0x0FE081FC); +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) + + uint8_t prodRev; + prodRev = SYSTEM_GetProdRev(); - if ((rev >> 24) <= 129) + if (prodRev <= 129) { /* This fixes a mistaken internal connection between PC0 and PC4 */ /* This disables an internal pulldown on PC4 */ @@ -190,7 +195,7 @@ __STATIC_INLINE void CHIP_Init(void) } #endif -#if defined(_SILICON_LABS_32B_PLATFORM_2_GEN_1) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /**************************** * Fixes for errata GPIO_E201 (slewrate) and @@ -244,11 +249,33 @@ __STATIC_INLINE void CHIP_Init(void) } #endif -#if defined(_SILICON_LABS_32B_PLATFORM_2_GEN_2) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - /* No fixes required. */ + uint8_t prodRev = SYSTEM_GetProdRev(); + /* EM2 current fixes for early samples */ + if (prodRev == 0) + { + *(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0000ADE8UL; + *(volatile uint32_t *)(EMU_BASE + 0x198) |= (0x1 << 2); + *(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0; + } + if (prodRev < 2) + { + *(volatile uint32_t *)(EMU_BASE + 0x164) |= (0x1 << 13); + } + + /* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of vref */ + CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK) + | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES + | CMU_LFRCOCTRL_ENVREF; #endif + +#if defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84) + MSC->CTRL |= 0x1 << 8; +#endif + + } /** @} (end addtogroup CHIP) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h index 733ae8c0220..b049ff9881e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cmu.h * @brief Clock management unit (CMU) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -130,10 +130,15 @@ extern "C" { #define CMU_LCDPRE_CLK_BRANCH 19 #define CMU_LCD_CLK_BRANCH 20 #define CMU_LESENSE_CLK_BRANCH 21 +#define CMU_CSEN_LF_CLK_BRANCH 22 #define CMU_CLK_BRANCH_POS 17 #define CMU_CLK_BRANCH_MASK 0x1f +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/* Max clock frequency for VSCALE voltages */ +#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000 +#endif /** @endcond */ /******************************************************************************* @@ -161,7 +166,7 @@ extern "C" { /** Clock divider configuration */ typedef uint32_t CMU_ClkDiv_TypeDef; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /** Clockprescaler configuration */ typedef uint32_t CMU_ClkPresc_TypeDef; #endif @@ -853,7 +858,7 @@ typedef enum | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), + | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined( CMU_LFBCLKEN0_LEUART1 ) @@ -938,7 +943,10 @@ typedef enum cmuOsc_USHFRCO, /**< USB high frequency RC oscillator */ #endif #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO ) - cmuOsc_ULFRCO /**< Ultra low frequency RC oscillator. */ + cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */ +#endif +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */ #endif } CMU_Osc_TypeDef; @@ -953,24 +961,27 @@ typedef enum /** Selectable clock sources. */ typedef enum { - cmuSelect_Error, /**< Usage error. */ - cmuSelect_Disabled, /**< Clock selector disabled. */ - cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ - cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ - cmuSelect_HFXO, /**< High frequency crystal oscillator. */ - cmuSelect_HFRCO, /**< High frequency RC oscillator. */ - cmuSelect_HFCLKLE, /**< High frequency LE clock divided by 2 or 4. */ - cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */ - cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on - Tiny Gecko and for USBC (not used on Gecko) */ + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ + cmuSelect_HFXO, /**< High frequency crystal oscillator. */ + cmuSelect_HFRCO, /**< High frequency RC oscillator. */ + cmuSelect_HFCLKLE, /**< High frequency LE clock divided by 2 or 4. */ + cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */ + cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on + Tiny Gecko and for USBC (not used on Gecko) */ #if defined( CMU_STATUS_USHFRCOENS ) - cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */ + cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */ #endif #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 ) - cmuSelect_USHFRCODIV2,/**< USB high frequency RC oscillator */ + cmuSelect_USHFRCODIV2, /**< USB high frequency RC oscillator */ #endif #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO ) - cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ + cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ +#endif +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */ #endif } CMU_Select_TypeDef; @@ -1192,7 +1203,7 @@ CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div); uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc); uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock); #endif @@ -1441,7 +1452,7 @@ __STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2) } -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /***************************************************************************//** * @brief * Convert prescaler dividend to logarithmic value. Only works for even diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h index 03d00b53eb9..e22df15fa58 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_common.h * @brief General purpose utilities. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -107,6 +107,9 @@ extern "C" { /** MDK-ARM compiler: Macro for handling weak symbols. */ #define SL_WEAK __attribute__ ((weak)) +/** MDK-ARM compiler: Macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + /** MDK-ARM compiler: Macro for handling section placement */ #define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) #endif @@ -118,6 +121,9 @@ extern "C" { /** @brief IAR Embedded Workbench: Macros for handling weak symbols. */ #define SL_WEAK __weak +/** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */ +#define SL_NORETURN __noreturn + /** IAR Embedded Workbench: Macro for handling section placement */ #define SL_ATTRIBUTE_SECTION(X) @ X #endif @@ -164,6 +170,9 @@ extern "C" { /** @brief Macro for defining a weak symbol. */ #define SL_WEAK __attribute__ ((weak)) +/** @brief Macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + /** Macro for placing a variable in a section. * @n Use this macro after the variable definition, before the = or ;. * @n X denotes the section to place the variable in. @@ -174,13 +183,13 @@ extern "C" { /***************************************************************************//** * @brief - * Count trailing number of zero's. Use CLZ instruction if available. + * Count trailing number of zeros. Use CLZ instruction if available. * * @param[in] value * Data value to check for number of trailing zero bits. * * @return - * Number of trailing zero's in value. + * Number of trailing zeros in value. ******************************************************************************/ __STATIC_INLINE uint32_t SL_CTZ(uint32_t value) { @@ -194,31 +203,14 @@ __STATIC_INLINE uint32_t SL_CTZ(uint32_t value) #endif } -/***************************************************************************//** - * @brief - * Count trailing number of zero's. Use CLZ instruction if available. - * - * @deprecated - * Deprecated function. New code should use @ref SL_CTZ(). - * @param[in] value - * Data value to check for number of trailing zero bits. - * - * @return - * Number of trailing zero's in value. - ******************************************************************************/ +/* Deprecated function. New code should use @ref SL_CTZ. */ __STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value) { -#if (__CORTEX_M >= 3) - return __CLZ(__RBIT(value)); - -#else - uint32_t zeros; - for(zeros=0; (zeros<32) && ((value&0x1) == 0); zeros++, value>>=1); - return zeros; -#endif + return SL_CTZ(value); } + /** @} (end addtogroup COMMON) */ /** @} (end addtogroup emlib) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h index c30af030476..45131f3fba6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_core.h * @brief Core interrupt handling API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h index 4ae47098bda..43403b81e80 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cryotimer.h * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h index 3b44aa15850..977f9da95ae 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_crypto.h * @brief Cryptography accelerator peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h new file mode 100644 index 00000000000..aacf4cbc25b --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h @@ -0,0 +1,778 @@ +/***************************************************************************//** + * @file em_csen.h + * @brief Capacitive Sense Module (CSEN) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#ifndef EM_CSEN_H +#define EM_CSEN_H + +#include "em_device.h" +#if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 ) + +#include +#include "em_bus.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup CSEN + * @brief Capacitive Sense (CSEN) Peripheral API + * + * @details + * This module provides functions for controlling the capacitive sense + * peripheral of Silicon Labs 32-bit MCUs and SoCs. The CSEN includes a + * capacitance-to-digital circuit that measures capacitance on selected + * inputs. Measurements are performed using either a successive approximation + * register (SAR) or a delta modulator (DM) analog to digital converter. + * + * The CSEN can be configured to measure capacitance on a single port pin + * or to automatically measure multiple port pins in succession using scan + * mode. Also several port pins can be shorted together to measure the + * combined capacitance. + * + * The CSEN includes an accumulator which can be configured to average + * multiple conversions on the selected input. Additionally, an exponential + * moving average (EMA) calculator is included to provide data smoothing. + * A comparator is also included and can be used to terminate a continuous + * conversion when the configured threshold condition is met. + * + * The following example shows how to intialize and start a single + * conversion on one input: + * + * @include em_csen_single.c + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Comparator Mode. Selects the operation of the digital comparator. */ +typedef enum +{ + /** Comparator is disabled. */ + csenCmpModeDisabled = 0, + + /** Comparator trips when the result is greater than the threshold. */ + csenCmpModeGreater = CSEN_CTRL_CMPEN | CSEN_CTRL_CMPPOL_GT, + + /** Comparator trips when the result is less or equal to the threshold. */ + csenCmpModeLessOrEqual = CSEN_CTRL_CMPEN | CSEN_CTRL_CMPPOL_LTE, + + /** Comparator trips when the EMA is within the threshold window. */ + csenCmpModeEMAWindow = CSEN_CTRL_EMACMPEN, +} CSEN_CmpMode_TypeDef; + + +/** Converter Select. Determines the converter operational mode. */ +typedef enum +{ + /** Successive Approximation (SAR) converter. */ + csenConvSelSAR = CSEN_CTRL_CONVSEL_SAR, + + /** Successive Approximation (SAR) converter with low freq attenuation. */ + csenConvSelSARChop = CSEN_CTRL_CONVSEL_SAR | CSEN_CTRL_CHOPEN_ENABLE, + + /** Delta Modulation (DM) converter. */ + csenConvSelDM = CSEN_CTRL_CONVSEL_DM, + + /** Delta Modulation (DM) converter with low frequency attenuation. */ + csenConvSelDMChop = CSEN_CTRL_CONVSEL_DM | CSEN_CTRL_CHOPEN_ENABLE, +} CSEN_ConvSel_TypeDef; + + +/** Sample Mode. Determines how inputs are sampled for a conversion. */ +typedef enum +{ + /** Convert multiple inputs shorted together and stop. */ + csenSampleModeBonded = CSEN_CTRL_CM_SGL | CSEN_CTRL_MCEN_ENABLE, + + /** Convert one input and stop. */ + csenSampleModeSingle = CSEN_CTRL_CM_SGL, + + /** Convert multiple inputs one at a time and stop. */ + csenSampleModeScan = CSEN_CTRL_CM_SCAN, + + /** Continuously convert multiple inputs shorted together. */ + csenSampleModeContBonded = CSEN_CTRL_CM_CONTSGL | CSEN_CTRL_MCEN_ENABLE, + + /** Continuously convert one input. */ + csenSampleModeContSingle = CSEN_CTRL_CM_CONTSGL, + + /** Continuously convert multiple inputs one at a time. */ + csenSampleModeContScan = CSEN_CTRL_CM_CONTSCAN, +} CSEN_SampleMode_TypeDef; + + +/** Start Trigger Select. */ +typedef enum +{ + csenTrigSelPRS = _CSEN_CTRL_STM_PRS, /**< PRS system. */ + csenTrigSelTimer = _CSEN_CTRL_STM_TIMER, /**< CSEN PC timer. */ + csenTrigSelStart = _CSEN_CTRL_STM_START, /**< Start bit. */ +} CSEN_TrigSel_TypeDef; + + +/** Accumulator Mode Select. */ +typedef enum +{ + csenAccMode1 = _CSEN_CTRL_ACU_ACC1, /**< Accumulate 1 sample. */ + csenAccMode2 = _CSEN_CTRL_ACU_ACC2, /**< Accumulate 2 samples. */ + csenAccMode4 = _CSEN_CTRL_ACU_ACC4, /**< Accumulate 4 samples. */ + csenAccMode8 = _CSEN_CTRL_ACU_ACC8, /**< Accumulate 8 samples. */ + csenAccMode16 = _CSEN_CTRL_ACU_ACC16, /**< Accumulate 16 samples. */ + csenAccMode32 = _CSEN_CTRL_ACU_ACC32, /**< Accumulate 32 samples. */ + csenAccMode64 = _CSEN_CTRL_ACU_ACC64, /**< Accumulate 64 samples. */ +} CSEN_AccMode_TypeDef; + + +/** Successive Approximation (SAR) Conversion Resolution. */ +typedef enum +{ + csenSARRes10 = _CSEN_CTRL_SARCR_CLK10, /**< 10-bit resolution. */ + csenSARRes12 = _CSEN_CTRL_SARCR_CLK12, /**< 12-bit resolution. */ + csenSARRes14 = _CSEN_CTRL_SARCR_CLK14, /**< 14-bit resolution. */ + csenSARRes16 = _CSEN_CTRL_SARCR_CLK16, /**< 16-bit resolution. */ +} CSEN_SARRes_TypeDef; + + +/** Delta Modulator (DM) Conversion Resolution. */ +typedef enum +{ + csenDMRes10 = _CSEN_DMCFG_CRMODE_DM10, /**< 10-bit resolution. */ + csenDMRes12 = _CSEN_DMCFG_CRMODE_DM12, /**< 12-bit resolution. */ + csenDMRes14 = _CSEN_DMCFG_CRMODE_DM14, /**< 14-bit resolution. */ + csenDMRes16 = _CSEN_DMCFG_CRMODE_DM16, /**< 16-bit resolution. */ +} CSEN_DMRes_TypeDef; + + +/** Period counter clock pre-scaler. See the reference manual for source clock + * information. */ +typedef enum +{ + csenPCPrescaleDiv1 = _CSEN_TIMCTRL_PCPRESC_DIV1, /**< Divide by 1. */ + csenPCPrescaleDiv2 = _CSEN_TIMCTRL_PCPRESC_DIV2, /**< Divide by 2. */ + csenPCPrescaleDiv4 = _CSEN_TIMCTRL_PCPRESC_DIV4, /**< Divide by 4. */ + csenPCPrescaleDiv8 = _CSEN_TIMCTRL_PCPRESC_DIV8, /**< Divide by 8. */ + csenPCPrescaleDiv16 = _CSEN_TIMCTRL_PCPRESC_DIV16, /**< Divide by 16. */ + csenPCPrescaleDiv32 = _CSEN_TIMCTRL_PCPRESC_DIV32, /**< Divide by 32. */ + csenPCPrescaleDiv64 = _CSEN_TIMCTRL_PCPRESC_DIV64, /**< Divide by 64. */ + csenPCPrescaleDiv128 = _CSEN_TIMCTRL_PCPRESC_DIV128, /**< Divide by 128. */ +} CSEN_PCPrescale_TypeDef; + + +/** Exponential Moving Average sample weight. */ +typedef enum +{ + csenEMASampleW1 = _CSEN_EMACTRL_EMASAMPLE_W1, /**< Weight 1. */ + csenEMASampleW2 = _CSEN_EMACTRL_EMASAMPLE_W2, /**< Weight 2. */ + csenEMASampleW4 = _CSEN_EMACTRL_EMASAMPLE_W4, /**< Weight 4. */ + csenEMASampleW8 = _CSEN_EMACTRL_EMASAMPLE_W8, /**< Weight 8. */ + csenEMASampleW16 = _CSEN_EMACTRL_EMASAMPLE_W16, /**< Weight 16. */ + csenEMASampleW32 = _CSEN_EMACTRL_EMASAMPLE_W32, /**< Weight 32. */ + csenEMASampleW64 = _CSEN_EMACTRL_EMASAMPLE_W64, /**< Weight 64. */ +} CSEN_EMASample_TypeDef; + + +/** Reset Phase Timing Select (units are microseconds). */ +typedef enum +{ + csenResetPhaseSel0 = 0, /**< Reset phase time = 0.75 usec. */ + csenResetPhaseSel1 = 1, /**< Reset phase time = 1.00 usec. */ + csenResetPhaseSel2 = 2, /**< Reset phase time = 1.20 usec. */ + csenResetPhaseSel3 = 3, /**< Reset phase time = 1.50 usec. */ + csenResetPhaseSel4 = 4, /**< Reset phase time = 2.00 usec. */ + csenResetPhaseSel5 = 5, /**< Reset phase time = 3.00 usec. */ + csenResetPhaseSel6 = 6, /**< Reset phase time = 6.00 usec. */ + csenResetPhaseSel7 = 7, /**< Reset phase time = 12.0 usec. */ +} CSEN_ResetPhaseSel_TypeDef; + + +/** Drive Strength Select. Scales the output current. */ +typedef enum +{ + csenDriveSelFull = 0, /**< Drive strength = fully on. */ + csenDriveSel1 = 1, /**< Drive strength = 1/8 full scale. */ + csenDriveSel2 = 2, /**< Drive strength = 1/4 full scale. */ + csenDriveSel3 = 3, /**< Drive strength = 3/8 full scale. */ + csenDriveSel4 = 4, /**< Drive strength = 1/2 full scale. */ + csenDriveSel5 = 5, /**< Drive strength = 5/8 full scale. */ + csenDriveSel6 = 6, /**< Drive strength = 3/4 full scale. */ + csenDriveSel7 = 7, /**< Drive strength = 7/8 full scale. */ +} CSEN_DriveSel_TypeDef; + + +/** Gain Select. See reference manual for information on each setting. */ +typedef enum +{ + csenGainSel1X = 0, /**< Gain = 1x. */ + csenGainSel2X = 1, /**< Gain = 2x. */ + csenGainSel3X = 2, /**< Gain = 3x. */ + csenGainSel4X = 3, /**< Gain = 4x. */ + csenGainSel5X = 4, /**< Gain = 5x. */ + csenGainSel6X = 5, /**< Gain = 6x. */ + csenGainSel7X = 6, /**< Gain = 7x. */ + csenGainSel8X = 7, /**< Gain = 8x. */ +} CSEN_GainSel_TypeDef; + + +/** Peripheral Reflex System signal used to trigger conversion. */ +typedef enum +{ + csenPRSSELCh0 = _CSEN_PRSSEL_PRSSEL_PRSCH0, /**< PRS channel 0. */ + csenPRSSELCh1 = _CSEN_PRSSEL_PRSSEL_PRSCH1, /**< PRS channel 1. */ + csenPRSSELCh2 = _CSEN_PRSSEL_PRSSEL_PRSCH2, /**< PRS channel 2. */ + csenPRSSELCh3 = _CSEN_PRSSEL_PRSSEL_PRSCH3, /**< PRS channel 3. */ + csenPRSSELCh4 = _CSEN_PRSSEL_PRSSEL_PRSCH4, /**< PRS channel 4. */ + csenPRSSELCh5 = _CSEN_PRSSEL_PRSSEL_PRSCH5, /**< PRS channel 5. */ + csenPRSSELCh6 = _CSEN_PRSSEL_PRSSEL_PRSCH6, /**< PRS channel 6. */ + csenPRSSELCh7 = _CSEN_PRSSEL_PRSSEL_PRSCH7, /**< PRS channel 7. */ + csenPRSSELCh8 = _CSEN_PRSSEL_PRSSEL_PRSCH8, /**< PRS channel 8. */ + csenPRSSELCh9 = _CSEN_PRSSEL_PRSSEL_PRSCH9, /**< PRS channel 9. */ + csenPRSSELCh10 = _CSEN_PRSSEL_PRSSEL_PRSCH10, /**< PRS channel 10. */ + csenPRSSELCh11 = _CSEN_PRSSEL_PRSSEL_PRSCH11, /**< PRS channel 11. */ +} CSEN_PRSSel_TypeDef; + + +/** APORT channel to CSEN input selection. */ +typedef enum +{ + csenInputSelDefault = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT, + csenInputSelAPORT1CH0TO7 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7, + csenInputSelAPORT1CH8TO15 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15, + csenInputSelAPORT1CH16TO23 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23, + csenInputSelAPORT1CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31, + csenInputSelAPORT3CH0TO7 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7, + csenInputSelAPORT3CH8TO15 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15, + csenInputSelAPORT3CH16TO23 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23, + csenInputSelAPORT3CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31, +} CSEN_InputSel_TypeDef; + + +/** APORT channel to CSEN single input selection. */ +typedef enum +{ + csenSingleSelDefault = _CSEN_SINGLECTRL_SINGLESEL_DEFAULT, + csenSingleSelAPORT1XCH0 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0, + csenSingleSelAPORT1YCH1 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1, + csenSingleSelAPORT1XCH2 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2, + csenSingleSelAPORT1YCH3 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3, + csenSingleSelAPORT1XCH4 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4, + csenSingleSelAPORT1YCH5 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5, + csenSingleSelAPORT1XCH6 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6, + csenSingleSelAPORT1YCH7 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7, + csenSingleSelAPORT1XCH8 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8, + csenSingleSelAPORT1YCH9 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9, + csenSingleSelAPORT1XCH10 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10, + csenSingleSelAPORT1YCH11 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11, + csenSingleSelAPORT1XCH12 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12, + csenSingleSelAPORT1YCH13 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13, + csenSingleSelAPORT1XCH14 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14, + csenSingleSelAPORT1YCH15 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15, + csenSingleSelAPORT1XCH16 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16, + csenSingleSelAPORT1YCH17 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17, + csenSingleSelAPORT1XCH18 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18, + csenSingleSelAPORT1YCH19 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19, + csenSingleSelAPORT1XCH20 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20, + csenSingleSelAPORT1YCH21 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21, + csenSingleSelAPORT1XCH22 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22, + csenSingleSelAPORT1YCH23 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23, + csenSingleSelAPORT1XCH24 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24, + csenSingleSelAPORT1YCH25 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25, + csenSingleSelAPORT1XCH26 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26, + csenSingleSelAPORT1YCH27 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27, + csenSingleSelAPORT1XCH28 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28, + csenSingleSelAPORT1YCH29 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29, + csenSingleSelAPORT1XCH30 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30, + csenSingleSelAPORT1YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31, + csenSingleSelAPORT3XCH0 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0, + csenSingleSelAPORT3YCH1 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1, + csenSingleSelAPORT3XCH2 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2, + csenSingleSelAPORT3YCH3 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3, + csenSingleSelAPORT3XCH4 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4, + csenSingleSelAPORT3YCH5 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5, + csenSingleSelAPORT3XCH6 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6, + csenSingleSelAPORT3YCH7 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7, + csenSingleSelAPORT3XCH8 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8, + csenSingleSelAPORT3YCH9 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9, + csenSingleSelAPORT3XCH10 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10, + csenSingleSelAPORT3YCH11 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11, + csenSingleSelAPORT3XCH12 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12, + csenSingleSelAPORT3YCH13 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13, + csenSingleSelAPORT3XCH14 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14, + csenSingleSelAPORT3YCH15 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15, + csenSingleSelAPORT3XCH16 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16, + csenSingleSelAPORT3YCH17 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17, + csenSingleSelAPORT3XCH18 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18, + csenSingleSelAPORT3YCH19 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19, + csenSingleSelAPORT3XCH20 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20, + csenSingleSelAPORT3YCH21 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21, + csenSingleSelAPORT3XCH22 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22, + csenSingleSelAPORT3YCH23 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23, + csenSingleSelAPORT3XCH24 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24, + csenSingleSelAPORT3YCH25 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25, + csenSingleSelAPORT3XCH26 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26, + csenSingleSelAPORT3YCH27 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27, + csenSingleSelAPORT3XCH28 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28, + csenSingleSelAPORT3YCH29 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29, + csenSingleSelAPORT3XCH30 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30, + csenSingleSelAPORT3YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31, +} CSEN_SingleSel_TypeDef; + + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** CSEN init structure, common for all measurement modes. */ +typedef struct +{ + /** Requests system charge pump high accuracy mode. */ + bool cpAccuracyHi; + + /** Disables external kelvin connection and senses capacitor locally. */ + bool localSense; + + /** Keeps the converter warm allowing continuous conversions. */ + bool keepWarm; + + /** Converter warmup time is warmUpCount + 3 converter clock cycles. */ + uint8_t warmUpCount; + + /** Period counter reload value. */ + uint8_t pcReload; + + /** Period counter pre-scaler. */ + CSEN_PCPrescale_TypeDef pcPrescale; + + /** Peripheral reflex system trigger selection. */ + CSEN_PRSSel_TypeDef prsSel; + + /** CSEN input to APORT channel mapping. */ + CSEN_InputSel_TypeDef input0To7; + CSEN_InputSel_TypeDef input8To15; + CSEN_InputSel_TypeDef input16To23; + CSEN_InputSel_TypeDef input24To31; + CSEN_InputSel_TypeDef input32To39; + CSEN_InputSel_TypeDef input40To47; + CSEN_InputSel_TypeDef input48To55; + CSEN_InputSel_TypeDef input56To63; +} CSEN_Init_TypeDef; + +#define CSEN_INIT_DEFAULT \ +{ \ + false, /* Charge pump low accuracy mode. */ \ + false, /* Use external kelvin connection. */ \ + false, /* Disable keep warm. */ \ + 0, /* 0+3 cycle warmup time. */ \ + 0, /* Period counter reload. */ \ + csenPCPrescaleDiv1, /* Period counter prescale. */ \ + csenPRSSELCh0, /* PRS channel 0. */ \ + csenInputSelAPORT1CH0TO7, /* input0To7 -> aport1ch0to7 */ \ + csenInputSelAPORT1CH8TO15, /* input8To15 -> aport1ch8to15 */ \ + csenInputSelAPORT1CH16TO23, /* input16To23 -> aport1ch16to23 */ \ + csenInputSelAPORT1CH24TO31, /* input24To31 -> aport1ch24to31 */ \ + csenInputSelAPORT3CH0TO7, /* input32To39 -> aport3ch0to7 */ \ + csenInputSelAPORT3CH8TO15, /* input40To47 -> aport3ch8to15 */ \ + csenInputSelAPORT3CH16TO23, /* input48To55 -> aport3ch16to23 */ \ + csenInputSelAPORT3CH24TO31, /* input56To63 -> aport3ch24to31 */ \ +} + + +/** Measurement mode init structure. */ +typedef struct +{ + /** Selects the conversion sample mode. */ + CSEN_SampleMode_TypeDef sampleMode; + + /** Selects the conversion trigger source. */ + CSEN_TrigSel_TypeDef trigSel; + + /** Enables DMA operation. */ + bool enableDma; + + /** Disables dividing the accumulated result. */ + bool sumOnly; + + /** Selects the number of samples to accumulate per conversion. */ + CSEN_AccMode_TypeDef accMode; + + /** Selects the Exponential Moving Average sample weighting. */ + CSEN_EMASample_TypeDef emaSample; + + /** Enables the comparator and selects the comparison type. */ + CSEN_CmpMode_TypeDef cmpMode; + + /** Comparator threshold value. Meaning depends on @p cmpMode. */ + uint16_t cmpThr; + + /** Selects an APORT channel for a single conversion. */ + CSEN_SingleSel_TypeDef singleSel; + + /** + * Mask selects inputs 0 to 31. Effect depends on @p sampleMode. If sample + * mode is bonded, then mask selects inputs to short together. If sample + * mode is scan, then mask selects which inputs will be scanned. If sample + * mode is single and auto-ground is on (@p autoGnd is true), mask selects + * which pins are grounded. + */ + uint32_t inputMask0; + + /** Mask selects inputs 32 to 63. See @p inputMask0 for more information. */ + uint32_t inputMask1; + + /** Ground inactive inputs during a conversion. */ + bool autoGnd; + + /** Selects the converter type. */ + CSEN_ConvSel_TypeDef convSel; + + /** Selects the Successive Approximation (SAR) converter resolution. */ + CSEN_SARRes_TypeDef sarRes; + + /** Selects the Delta Modulation (DM) converter resolution. */ + CSEN_DMRes_TypeDef dmRes; + + /** Sets the number of DM iterations (comparisons) per cycle. Only applies + * to the Delta Modulation converter. */ + uint8_t dmIterPerCycle; + + /** Sets number of DM converter cycles. Only applies to the + * Delta Modulation converter. */ + uint8_t dmCycles; + + /** Sets the DM converter initial delta value. Only applies to the + * Delta Modulation converter. */ + uint8_t dmDelta; + + /** Disable DM automatic delta size reduction per cycle. Only applies to the + * Delta Modulation converter. */ + bool dmFixedDelta; + + /** Selects the reset phase timing. Most measurements should use the default + * value. See reference manual for details on when to adjust. */ + CSEN_ResetPhaseSel_TypeDef resetPhase; + + /** Selects the output drive strength. Most measurements should use the + * default value. See reference manual for details on when to adjust. */ + CSEN_DriveSel_TypeDef driveSel; + + /** Selects the converter gain. */ + CSEN_GainSel_TypeDef gainSel; +} CSEN_InitMode_TypeDef; + +#define CSEN_INITMODE_DEFAULT \ +{ \ + csenSampleModeSingle, /* Sample one input and stop. */ \ + csenTrigSelStart, /* Use start bit to trigger. */ \ + false, /* Disable DMA. */ \ + false, /* Average the accumulated result. */ \ + csenAccMode1, /* Accumulate 1 sample. */ \ + csenEMASampleW1, /* Disable the EMA. */ \ + csenCmpModeDisabled, /* Disable the comparator. */ \ + 0, /* Comparator threshold not used. */ \ + csenSingleSelDefault, /* Disconnect the single input. */ \ + 0, /* Disable inputs 0 to 31. */ \ + 0, /* Disable inputs 32 to 63. */ \ + false, /* Do not ground inactive inputs. */ \ + csenConvSelSAR, /* Use the SAR converter. */ \ + csenSARRes10, /* Set SAR resolution to 10 bits. */ \ + csenDMRes10, /* Set DM resolution to 10 bits. */ \ + 0, /* Set DM conv/cycle to default. */ \ + 0, /* Set DM cycles to default. */ \ + 0, /* Set DM initial delta to default. */ \ + false, /* Use DM auto delta reduction. */ \ + csenResetPhaseSel0, /* Use shortest reset phase time. */ \ + csenDriveSelFull, /* Use full output current. */ \ + csenGainSel8X, /* Use highest converter gain. */ \ +} + + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get last conversion result. + * + * @note + * Check conversion busy flag before calling this function. In addition, + * the result width and format depend on the parameters passed to the + * @ref CSEN_InitMode() function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * Result data from last conversion. + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_DataGet(CSEN_TypeDef *csen) +{ + return csen->DATA; +} + +/***************************************************************************//** + * @brief + * Get last exponential moving average. + * + * @note + * Confirm CSEN is idle before calling this function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * Exponential moving average from last conversion. + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_EMAGet(CSEN_TypeDef *csen) +{ + return (csen->EMA & _CSEN_EMA_EMA_MASK); +} + +/***************************************************************************//** + * @brief + * Set exponential moving average initial value. + * + * @note + * Call this function before starting a conversion. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] ema + * Initial value for the exponential moving average. + ******************************************************************************/ +__STATIC_INLINE void CSEN_EMASet(CSEN_TypeDef *csen, uint32_t ema) +{ + csen->EMA = ema & _CSEN_EMA_EMA_MASK; +} + +/***************************************************************************//** + * @brief + * Disables the CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void CSEN_Disable(CSEN_TypeDef *csen) +{ + BUS_RegBitWrite(&csen->CTRL, _CSEN_CTRL_EN_SHIFT, 0); +} + +/***************************************************************************//** + * @brief + * Enables the CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void CSEN_Enable(CSEN_TypeDef *csen) +{ + BUS_RegBitWrite(&csen->CTRL, _CSEN_CTRL_EN_SHIFT, 1); +} + +void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down); +void CSEN_Init(CSEN_TypeDef *csen, const CSEN_Init_TypeDef *init); +void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init); +void CSEN_Reset(CSEN_TypeDef *csen); + + +/***************************************************************************//** + * @brief + * Clear one or more pending CSEN interrupts. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * Pending CSEN interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntClear(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IFC = flags; +} + + +/***************************************************************************//** + * @brief + * Disable one or more CSEN interrupts. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * CSEN interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntDisable(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IEN &= ~flags; +} + + +/***************************************************************************//** + * @brief + * Enable one or more CSEN interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using CSEN_IntClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * CSEN interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntEnable(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IEN |= flags; +} + + +/***************************************************************************//** + * @brief + * Get pending CSEN interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * CSEN interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_IntGet(CSEN_TypeDef *csen) +{ + return csen->IF; +} + + +/***************************************************************************//** + * @brief + * Get enabled and pending CSEN interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled CSEN interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in CSENx_IEN_nnn + * register (CSENx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the CSEN module + * (CSENx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_IntGetEnabled(CSEN_TypeDef *csen) +{ + uint32_t ien; + + /* Store CSENx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = csen->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return csen->IF & ien; +} + + +/***************************************************************************//** + * @brief + * Set one or more pending CSEN interrupts from SW. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * CSEN interrupt sources to set to pending. Use a bitwise logic OR combination + * of valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntSet(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IFS = flags; +} + + +/***************************************************************************//** + * @brief + * Return CSEN conversion busy status. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * True if CSEN conversion is in progress. + ******************************************************************************/ +__STATIC_INLINE bool CSEN_IsBusy(CSEN_TypeDef *csen) +{ + return (bool)(csen->STATUS & _CSEN_STATUS_CSENBUSY_MASK); +} + + +/***************************************************************************//** + * @brief + * Start scan sequence and/or single conversion. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void CSEN_Start(CSEN_TypeDef *csen) +{ + csen->CMD = CSEN_CMD_START; +} + + +/** @} (end addtogroup CSEN) */ +/** @} (end addtogroup emlib) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(CSEN_COUNT) && (CSEN_COUNT > 0) */ +#endif /* EM_CSEN_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h index 4218d611384..e9df3b6051f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dac.h * @brief Digital to Analog Converter (DAC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h index 0baca2a731b..bc96fc93cac 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dbg.h * @brief Debug (DBG) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h index 5d557684f81..c79f23fbfc4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dma.h * @brief Direct memory access (DMA) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -360,21 +360,21 @@ typedef struct void DMA_ActivateAuto(unsigned int channel, bool primary, void *dst, - void *src, + const void *src, unsigned int nMinus1); void DMA_ActivateBasic(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1); void DMA_ActivatePingPong(unsigned int channel, bool useBurst, void *primDst, - void *primSrc, + const void *primSrc, unsigned int primNMinus1, void *altDst, - void *altSrc, + const void *altSrc, unsigned int altNMinus1); void DMA_ActivateScatterGather(unsigned int channel, bool useBurst, @@ -446,7 +446,7 @@ void DMA_RefreshPingPong(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1, bool last); void DMA_Reset(void); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h index 8515bac98c0..86c772a09eb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ebi.h * @brief External Bus Iterface (EBI) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h index 0594f3cfd00..49ace576491 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_emu.h * @brief Energy management unit (EMU) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -151,15 +151,13 @@ typedef enum } EMU_EM4PinRetention_TypeDef; #endif - -#if defined( _EMU_PWRCFG_MASK ) -/** Power configurations */ +/** Power configurations. DCDC-to-DVDD is currently the only supported mode. */ typedef enum { /** DCDC is connected to DVDD */ - emuPowerConfig_DcdcToDvdd = EMU_PWRCFG_PWRCFG_DCDCTODVDD, + emuPowerConfig_DcdcToDvdd, } EMU_PowerConfig_TypeDef; -#endif + #if defined( _EMU_DCDCCTRL_MASK ) /** DCDC operating modes */ @@ -176,6 +174,19 @@ typedef enum } EMU_DcdcMode_TypeDef; #endif +#if defined( _EMU_DCDCCTRL_MASK ) +/** DCDC conduction modes */ +typedef enum +{ + /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization + features are available in this mode. */ + emuDcdcConductionMode_ContinuousLN, + /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or + when the EFR32 radio is not enabled. */ + emuDcdcConductionMode_DiscontinuousLN, +} EMU_DcdcConductionMode_TypeDef; +#endif + #if defined( _EMU_PWRCTRL_MASK ) /** DCDC to DVDD mode analog peripheral power supply select */ typedef enum @@ -194,7 +205,7 @@ typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef; /** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ #define emuDcdcLnHighEfficiency -1 -/** Deprecated. Fast transient response mode. Specify a reverse current limit instead. */ +/** Default reverse current for fast transient response mode (low noise). */ #define emuDcdcLnFastTransient 160 #endif @@ -258,7 +269,7 @@ typedef enum } EMU_VmonChannel_TypeDef; #endif /* EMU_STATUS_VMONRDY */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) /** Bias mode configurations */ typedef enum { @@ -268,56 +279,184 @@ typedef enum } EMU_BiasMode_TypeDef; #endif +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/** Supported EM0/1 Voltage Scaling Levels */ +typedef enum +{ + /** High-performance voltage level. HF clock can be set to any frequency. */ + emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2, + /** Low-power optimized voltage level. The HF clock must be limited + to @ref CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage. + EM0/1 voltage scaling is applied when the core clock frequency is + changed from @ref CMU or when calling @ref EMU_EM01Init() when the HF + clock is already below the limit. */ + emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0, +} EMU_VScaleEM01_TypeDef; +#endif + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) +/** Supported EM2/3 Voltage Scaling Levels */ +typedef enum +{ + /** Fast-wakeup voltage level. */ + emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM2 and 3 + adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled + up to @ref emuVScaleEM01_HighPerformance on EM2 or 3 exit. */ + emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0, +} EMU_VScaleEM23_TypeDef; +#endif + +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) +/** Supported EM4H Voltage Scaling Levels */ +typedef enum +{ + /** Fast-wakeup voltage level. */ + emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM4H + adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled + up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */ + emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0, +} EMU_VScaleEM4H_TypeDef; +#endif + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/** Peripheral EM2 and 3 retention control */ +typedef enum +{ + emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /* Select LEUART0 retention control */ + emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /* Select CSEN retention control */ + emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /* Select LESENSE0 retention control */ + emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /* Select LETIMER0 retention control */ + emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /* Select ADC0 retention control */ + emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /* Select IDAC0 retention control */ + emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK, /* Select DAC0 retention control */ + emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select I2C1 retention control */ + emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /* Select I2C0 retention control */ + emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /* Select ACMP1 retention control */ + emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /* Select ACMP0 retention control */ +#if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK ) + emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /* Select PCNT2 retention control */ + emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /* Select PCNT1 retention control */ +#endif + emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /* Select PCNT0 retention control */ + + emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/* Select all peripherals in domain 1 */ + emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK + | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK + | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK +#if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK ) + | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK +#endif + | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select all peripherals in domain 2 */ + emuPeripheralRetention_ALL = emuPeripheralRetention_D1 + | emuPeripheralRetention_D2, /* Select all peripherals with retention control */ +} EMU_PeripheralRetention_TypeDef; +#endif + /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ -/** Energy Mode 2 and 3 initialization structure */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/** EM0 and 1 initialization structure. Voltage scaling is applied when + the core clock frequency is changed from @ref CMU. EM0 an 1 emuVScaleEM01_HighPerformance + is always enabled. */ typedef struct { - bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3 */ + bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status */ +} EMU_EM01Init_TypeDef; +#endif + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/** Default initialization of EM0 and 1 configuration */ +#define EMU_EM01INIT_DEFAULT \ +{ \ + false /** Do not scale down in EM0/1 */ \ +} +#endif + +/** EM2 and 3 initialization structure */ +typedef struct +{ + bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3 */ +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level */ +#endif } EMU_EM23Init_TypeDef; /** Default initialization of EM2 and 3 configuration */ -#define EMU_EM23INIT_DEFAULT \ -{ false } /* Reduced voltage regulator drive strength in EM2 and EM3 */ - +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) +#define EMU_EM23INIT_DEFAULT \ +{ \ + false, /* Reduced voltage regulator drive strength in EM2/3 */ \ + emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3 */ \ +} +#else +#define EMU_EM23INIT_DEFAULT \ +{ \ + false, /* Reduced voltage regulator drive strength in EM2/3 */ \ +} +#endif #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK ) -/** Energy Mode 4 initialization structure */ +/** EM4 initialization structure */ typedef struct { #if defined( _EMU_EM4CONF_MASK ) - /* Init parameters for platforms with EMU->EM4CONF register */ - bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator */ - bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4 */ - EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator */ - bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt */ - bool vreg; /**< Enable EM4 voltage regulator */ - + /* Init parameters for platforms with EMU->EM4CONF register (Series 0) */ + bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator */ + bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4 */ + EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator */ + bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt */ + bool vreg; /**< Enable EM4 voltage regulator */ #elif defined( _EMU_EM4CTRL_MASK ) - /* Init parameters for platforms with EMU->EM4CTRL register */ + /* Init parameters for platforms with EMU->EM4CTRL register (Series 1) */ bool retainLfxo; /**< Disable the LFXO upon EM4 entry */ bool retainLfrco; /**< Disable the LFRCO upon EM4 entry */ bool retainUlfrco; /**< Disable the ULFRCO upon EM4 entry */ EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state */ EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode */ #endif +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) + EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level */ +#endif } EMU_EM4Init_TypeDef; #endif -/** Default initialization of EM4 configuration */ #if defined( _EMU_EM4CONF_MASK ) +/** Default initialization of EM4 configuration (Series 0) */ #define EMU_EM4INIT_DEFAULT \ { \ false, /* Dont't lock configuration after it's been set */ \ - false, /* No reset will be asserted due to Brownout when in EM4 */ \ + false, /* No reset will be asserted due to BOD in EM4 */ \ emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator */ \ true, /* Wake up on EM4 BURTC interrupt */ \ true, /* Enable VREG */ \ } -#endif -#if defined( _EMU_EM4CTRL_MASK ) + +#elif defined( _EMU_CTRL_EM4HVSCALE_MASK ) +/** Default initialization of EM4 configuration (Series 1 with VSCALE) */ +#define EMU_EM4INIT_DEFAULT \ +{ \ + false, /* Retain LFXO configuration upon EM4 entry */ \ + false, /* Retain LFRCO configuration upon EM4 entry */ \ + false, /* Retain ULFRCO configuration upon EM4 entry */ \ + emuEM4Shutoff, /* Use EM4 shutoff state */ \ + emuPinRetentionDisable, /* Do not retain pins in EM4 */ \ + emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H */ \ +} + +#elif defined( _EMU_EM4CTRL_MASK ) +/** Default initialization of EM4 configuration (Series 1 without VSCALE) */ #define EMU_EM4INIT_DEFAULT \ { \ false, /* Retain LFXO configuration upon EM4 entry */ \ @@ -380,7 +519,8 @@ typedef struct /** DCDC initialization structure */ typedef struct { - EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration */ + EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration. + @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */ EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1 */ uint16_t mVout; /**< Target output voltage (mV) */ uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1 (mA). @@ -407,11 +547,11 @@ typedef struct /** Default DCDC initialization */ #if defined( _EFM_DEVICE ) -#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG) && (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) #define EMU_DCDCINIT_DEFAULT \ { \ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ - emuDcdcMode_LowNoise, /* Low-niose mode in EM0 (can be set to LowPower on EFM32PG revB0) */ \ + emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \ 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ 5, /* Nominal EM0/1 load current of less than 5mA */ \ 10, /* Nominal EM2/3/4 load current less than 10uA */ \ @@ -419,14 +559,13 @@ typedef struct (assume strong battery or other power source) */ \ emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ + emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \ } - #else #define EMU_DCDCINIT_DEFAULT \ { \ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ - emuDcdcMode_LowNoise, /* Low-niose mode in EM0 (can be set to LowPower on EFM32PG revB0) */ \ + emuDcdcMode_LowPower, /* Low-power mode in EM0 */ \ 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ 5, /* Nominal EM0/1 load current of less than 5mA */ \ 10, /* Nominal EM2/3/4 load current less than 10uA */ \ @@ -434,12 +573,12 @@ typedef struct (assume strong battery or other power source) */ \ emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \ - emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ } #endif #else /* EFR32 device */ -#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG) && (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) #define EMU_DCDCINIT_DEFAULT \ { \ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ @@ -451,9 +590,8 @@ typedef struct (assume strong battery or other power source) */ \ emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ 160, /* Maximum reverse current of 160mA */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ + emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \ } - #else #define EMU_DCDCINIT_DEFAULT \ { \ @@ -466,7 +604,7 @@ typedef struct (assume strong battery or other power source) */ \ emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ 160, /* Maximum reverse current of 160mA */ \ - emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ } #endif #endif @@ -522,49 +660,92 @@ typedef struct ***************************** PROTOTYPES ********************************** ******************************************************************************/ -/***************************************************************************//** - * @brief - * Enter energy mode 1 (EM1). - ******************************************************************************/ -__STATIC_INLINE void EMU_EnterEM1(void) -{ - /* Enter sleep mode */ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __WFI(); -} - -void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init); +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init); +#endif +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init); #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK ) -void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init); +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init); #endif void EMU_EnterEM2(bool restore); void EMU_EnterEM3(bool restore); +void EMU_Restore(void); void EMU_EnterEM4(void); #if defined( _EMU_EM4CTRL_MASK ) void EMU_EnterEM4H(void); void EMU_EnterEM4S(void); #endif void EMU_MemPwrDown(uint32_t blocks); +void EMU_RamPowerDown(uint32_t start, uint32_t end); +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable); +#endif void EMU_UpdateOscConfig(void); +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait); +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait); +#endif #if defined( BU_PRESENT ) -void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit); +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit); void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); #endif #if defined( _EMU_DCDCCTRL_MASK ) -bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit); +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit); void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet); bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent); void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); bool EMU_DCDCPowerOff(void); #endif #if defined( EMU_STATUS_VMONRDY ) -void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit); -void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit); +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit); +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit); void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); +#endif +/***************************************************************************//** + * @brief + * Enter energy mode 1 (EM1). + ******************************************************************************/ +__STATIC_INLINE void EMU_EnterEM1(void) +{ + /* Enter sleep mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); +} + + +#if defined( _EMU_STATUS_VSCALE_MASK ) +/***************************************************************************//** + * @brief + * Wait for voltage scaling to complete + ******************************************************************************/ +__STATIC_INLINE void EMU_VScaleWait(void) +{ + while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT)); +} +#endif + +#if defined( _EMU_STATUS_VSCALE_MASK ) +/***************************************************************************//** + * @brief + * Get current voltage scaling level + * + * @return + * Current voltage scaling level + ******************************************************************************/ +__STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void) +{ + EMU_VScaleWait(); + return (EMU_VScaleEM01_TypeDef)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); +} +#endif + +#if defined( _EMU_STATUS_VMONRDY_MASK ) /***************************************************************************//** * @brief * Get the status of the voltage monitor (VMON). @@ -577,7 +758,7 @@ __STATIC_INLINE bool EMU_VmonStatusGet(void) { return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT); } -#endif /* EMU_STATUS_VMONRDY */ +#endif /* _EMU_STATUS_VMONRDY_MASK */ #if defined( _EMU_IF_MASK ) /***************************************************************************//** @@ -805,7 +986,7 @@ __STATIC_INLINE void EMU_UnlatchPinRetention(void) } #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode); #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h index f66b4efe9dd..5ce0660d4cb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h index ec09bdf8af0..049d8114971 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_gpio.h * @brief General Purpose IO (GPIO) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -68,6 +68,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 9 #define _GPIO_PORT_E_PIN_COUNT 12 #define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xF77F #define _GPIO_PORT_B_PIN_MASK 0x79F8 @@ -75,6 +80,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0x01FF #define _GPIO_PORT_E_PIN_MASK 0xFFF0 #define _GPIO_PORT_F_PIN_MASK 0x003F +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined( _EFM32_HAPPY_FAMILY ) @@ -84,6 +94,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 4 #define _GPIO_PORT_E_PIN_COUNT 4 #define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x0707 #define _GPIO_PORT_B_PIN_MASK 0x6980 @@ -91,6 +106,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0x00F0 #define _GPIO_PORT_E_PIN_MASK 0x3C00 #define _GPIO_PORT_F_PIN_MASK 0x003F +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined( _EFM32_GIANT_FAMILY ) \ || defined( _EFM32_WONDER_FAMILY ) @@ -101,6 +121,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 16 #define _GPIO_PORT_E_PIN_COUNT 16 #define _GPIO_PORT_F_PIN_COUNT 13 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xFFFF #define _GPIO_PORT_B_PIN_MASK 0xFFFF @@ -108,6 +133,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFFFF #define _GPIO_PORT_E_PIN_MASK 0xFFFF #define _GPIO_PORT_F_PIN_MASK 0x1FFF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined( _EFM32_GECKO_FAMILY ) @@ -117,6 +147,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 16 #define _GPIO_PORT_E_PIN_COUNT 16 #define _GPIO_PORT_F_PIN_COUNT 10 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xFFFF #define _GPIO_PORT_B_PIN_MASK 0xFFFF @@ -124,11 +159,13 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFFFF #define _GPIO_PORT_E_PIN_MASK 0xFFFF #define _GPIO_PORT_F_PIN_MASK 0x03FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 -#elif defined( _EFR32_MIGHTY_FAMILY ) \ - || defined( _EFR32_BLUE_FAMILY ) \ - || defined( _EFR32_FLEX_FAMILY ) \ - || defined( _EFR32_ZAPPY_FAMILY ) +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) && defined( _EFR_DEVICE ) #define _GPIO_PORT_A_PIN_COUNT 6 #define _GPIO_PORT_B_PIN_COUNT 5 @@ -136,6 +173,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 6 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x003F #define _GPIO_PORT_B_PIN_MASK 0xF800 @@ -143,9 +185,13 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFC00 #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0x00FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 -#elif defined( _EFM32_PEARL_FAMILY ) \ - || defined( _EFM32_JADE_FAMILY ) +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) && defined( _EFM_DEVICE ) #define _GPIO_PORT_A_PIN_COUNT 6 #define _GPIO_PORT_B_PIN_COUNT 5 @@ -153,6 +199,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 7 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x003F #define _GPIO_PORT_B_PIN_MASK 0xF800 @@ -160,54 +211,95 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFE00 #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0x00FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 + +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_84 ) + +#define _GPIO_PORT_A_PIN_COUNT 10 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 12 +#define _GPIO_PORT_D_PIN_COUNT 8 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 16 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 4 +#define _GPIO_PORT_J_PIN_COUNT 2 +#define _GPIO_PORT_K_PIN_COUNT 3 + +#define _GPIO_PORT_A_PIN_MASK 0x03FF +#define _GPIO_PORT_B_PIN_MASK 0xFFC0 +#define _GPIO_PORT_C_PIN_MASK 0x0FFF +#define _GPIO_PORT_D_PIN_MASK 0xFF00 +#define _GPIO_PORT_E_PIN_MASK 0x0000 +#define _GPIO_PORT_F_PIN_MASK 0xFFFF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x000F +#define _GPIO_PORT_J_PIN_MASK 0xC000 +#define _GPIO_PORT_K_PIN_MASK 0x0007 + +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_89 ) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 6 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003F +#define _GPIO_PORT_B_PIN_MASK 0xF800 +#define _GPIO_PORT_C_PIN_MASK 0x0FC0 +#define _GPIO_PORT_D_PIN_MASK 0xFC00 +#define _GPIO_PORT_E_PIN_MASK 0x0000 +#define _GPIO_PORT_F_PIN_MASK 0x00FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #else #warning "Port and pin masks are not defined for this family." #endif -#if defined( _GPIO_PORT_G_PIN_COUNT ) && defined( _GPIO_PORT_H_PIN_COUNT ) -#define _GPIO_PORT_SIZE(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \ - (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \ - (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \ - (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \ - (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \ - (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \ - (port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \ - (port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \ - 0) -#else -#define _GPIO_PORT_SIZE(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \ - (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \ - (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \ - (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \ - (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \ - (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \ +#define _GPIO_PORT_SIZE(port) ( \ + (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \ + (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \ + (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \ + (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \ + (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \ + (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \ + (port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \ + (port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \ + (port) == 8 ? _GPIO_PORT_I_PIN_COUNT : \ + (port) == 9 ? _GPIO_PORT_J_PIN_COUNT : \ + (port) == 10 ? _GPIO_PORT_K_PIN_COUNT : \ 0) -#endif -#if defined( _GPIO_PORT_G_PIN_MASK ) && defined( _GPIO_PORT_H_PIN_MASK ) -#define _GPIO_PORT_MASK(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \ - (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \ - (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \ - (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \ - (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \ - (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \ - (port) == 6 ? _GPIO_PORT_G_PIN_MASK : \ - (port) == 7 ? _GPIO_PORT_H_PIN_MASK : \ - 0) -#else -#define _GPIO_PORT_MASK(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \ - (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \ - (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \ - (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \ - (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \ - (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \ +#define _GPIO_PORT_MASK(port) ( \ + (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \ + (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \ + (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \ + (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \ + (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \ + (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \ + (port) == 6 ? _GPIO_PORT_G_PIN_MASK : \ + (port) == 7 ? _GPIO_PORT_H_PIN_MASK : \ + (port) == 8 ? _GPIO_PORT_I_PIN_MASK : \ + (port) == 9 ? _GPIO_PORT_J_PIN_MASK : \ + (port) == 10 ? _GPIO_PORT_K_PIN_MASK : \ 0) -#endif /** Validation of port and pin */ #define GPIO_PORT_VALID(port) ( _GPIO_PORT_MASK(port) ) @@ -224,15 +316,17 @@ extern "C" { #define GPIO_PIN_MAX 15 /** Highest GPIO port number */ -#if defined( _GPIO_PORT_J_PIN_COUNT ) +#if ( _GPIO_PORT_K_PIN_COUNT > 0 ) +#define GPIO_PORT_MAX 10 +#elif ( _GPIO_PORT_J_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 9 -#elif defined( _GPIO_PORT_I_PIN_COUNT ) +#elif ( _GPIO_PORT_I_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 8 -#elif defined( _GPIO_PORT_H_PIN_COUNT ) +#elif ( _GPIO_PORT_H_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 7 -#elif defined( _GPIO_PORT_G_PIN_COUNT ) +#elif ( _GPIO_PORT_G_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 6 -#elif defined( _GPIO_PORT_F_PIN_COUNT ) +#elif ( _GPIO_PORT_F_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 5 #else #error "Max GPIO port number is undefined for this part." @@ -266,13 +360,22 @@ typedef enum gpioPortE = 4, #endif #if ( _GPIO_PORT_F_PIN_COUNT > 0 ) - gpioPortF = 5 + gpioPortF = 5, +#endif +#if ( _GPIO_PORT_G_PIN_COUNT > 0 ) + gpioPortG = 6, +#endif +#if ( _GPIO_PORT_H_PIN_COUNT > 0 ) + gpioPortH = 7, +#endif +#if ( _GPIO_PORT_I_PIN_COUNT > 0 ) + gpioPortI = 8, #endif -#if defined( _GPIO_PORT_G_PIN_COUNT ) && ( _GPIO_PORT_G_PIN_COUNT > 0 ) - gpioPortG = 6 +#if ( _GPIO_PORT_J_PIN_COUNT > 0 ) + gpioPortJ = 9, #endif -#if defined( _GPIO_PORT_H_PIN_COUNT ) && ( _GPIO_PORT_H_PIN_COUNT > 0 ) - gpioPortH = 7 +#if ( _GPIO_PORT_K_PIN_COUNT > 0 ) + gpioPortK = 10, #endif } GPIO_Port_TypeDef; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h index 659a2186122..356cfb86feb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_i2c.h * @brief Inter-intergrated circuit (I2C) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -68,12 +68,17 @@ extern "C" { * @note * Due to chip characteristics, the max value is somewhat reduced. */ -#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_TINY_FAMILY) \ - || defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY) +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GECKO_FAMILY) \ + || defined(_EFM32_TINY_FAMILY) \ + || defined(_EFM32_ZERO_FAMILY) \ + || defined(_EFM32_HAPPY_FAMILY)) #define I2C_FREQ_STANDARD_MAX 93000 -#elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EFM32_WONDER_FAMILY)) #define I2C_FREQ_STANDARD_MAX 92000 -#elif defined(_SILICON_LABS_32B_PLATFORM_2) +#elif defined(_SILICON_LABS_32B_SERIES_1) // None of the chips on this platform has been characterized on this parameter. // Use same value as on Wonder until further notice. #define I2C_FREQ_STANDARD_MAX 92000 diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h index 7d253e5550c..47c4d18415d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_idac.h * @brief Current Digital to Analog Converter (IDAC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h index adbc7c1b1fc..c7325001d69 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_int.h * @brief Interrupt enable/disable unit API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h index 583a26cfc42..62a54059d3c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lcd.h * @brief Liquid Crystal Display (LCD) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h index a40d6f873f9..9dfb127e589 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ldma.h * @brief Direct memory access (LDMA) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -239,15 +239,12 @@ typedef enum typedef enum { ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. - #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SCAN ) + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE ) + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_AGCRSSI ) - ldmaPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC, ///< Trig on AGC_RSSI. - #endif #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD ) ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD. #endif @@ -263,107 +260,182 @@ typedef enum #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR ) ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1WR. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV ) - ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV. + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) + ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0RD. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0TXBL ) - ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_TXBL. + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) + ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0WR. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV ) - ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_RXDATAV. + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) + ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0XWR. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL ) - ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXBL. + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) + ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1RD. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY ) - ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY. + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) + ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1WR. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG ) - ldmaPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM, ///< Trig on MODEM_DEBUG. + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) + ldmaPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0RD. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_MSCWDATA ) - ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA. + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) + ldmaPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0WR. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF ) - ldmaPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_BOF. + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) + ldmaPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0XWR. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 ) - ldmaPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC0. + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) + ldmaPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1RD. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 ) - ldmaPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC1. + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) + ldmaPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1WR. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 ) - ldmaPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC2. + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) + ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_BSLN. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 ) - ldmaPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC3. + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) + ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_DATA. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 ) - ldmaPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC4. + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) + ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) + ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_TXBL. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF ) - ldmaPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_POF. + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) + ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_RXDATAV. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF ) - ldmaPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_WOF. + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) + ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV) + ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trig on LESENSE_BUFDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) + ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) + ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) + ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) + ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ0 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ0. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ1 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ1. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC0. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC1. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC2. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_UFOF. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC0. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC1. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC2. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC3. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXBL ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXBL. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXEMPTY. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAV. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAVRIGHT. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBL ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBL. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBLRIGHT. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY ) - ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1 ///< Trig on USART1_TXEMPTY. + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) + ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) + ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) + ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) + ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) + ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) + ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) + ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) + ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) + ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) + ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) + ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) + ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) + ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) + ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) + ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) + ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) + ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) + ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) + ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) + ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1 ///< Trig on WTIMER1_UFOF. #endif } LDMA_PeripheralSignal_t; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h index 95bde6dcf14..3f74bf0706c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lesense.h * @brief Low Energy Sensor (LESENSE) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -35,9 +35,7 @@ #include "em_device.h" -/* LESENSE is currently only supported on Platform 1. Full support for Platform 2 LESENSE - will be included in the next release. */ -#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) && defined(_SILICON_LABS_32B_PLATFORM_1) +#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) #include #include @@ -56,11 +54,11 @@ extern "C" { * @{ ******************************************************************************/ -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** Number of decoder states supported by current device. */ +#define LESENSE_NUM_DECODER_STATES (_LESENSE_DECSTATE_DECSTATE_MASK + 1) - - -/** @endcond */ +/** Number of LESENSE channels. */ +#define LESENSE_NUM_CHANNELS 16 /******************************************************************************* ******************************** ENUMS ************************************ @@ -139,8 +137,16 @@ typedef enum /** Alternate excitation is mapped to the LES_ALTEX pins. */ lesenseAltExMapALTEX = _LESENSE_CTRL_ALTEXMAP_ALTEX, +#if defined(_LESENSE_CTRL_ALTEXMAP_ACMP) /** Alternate excitation is mapped to the pins of the other ACMP. */ - lesenseAltExMapACMP = _LESENSE_CTRL_ALTEXMAP_ACMP + lesenseAltExMapACMP = _LESENSE_CTRL_ALTEXMAP_ACMP, +#endif + +#if defined(_LESENSE_CTRL_ALTEXMAP_CH) + /** Alternative excitation is mapped to the pin of LESENSE channel + * (X+8 mod 16), X being the active channel. */ + lesenseAltExMapCH = _LESENSE_CTRL_ALTEXMAP_CH, +#endif } LESENSE_AltExMap_TypeDef; @@ -213,12 +219,20 @@ typedef enum * Note: this value could be used for both DAC Ch0 and Ch1. */ lesenseDACIfData = _LESENSE_PERCTRL_DACCH0DATA_DACDATA, +#if defined(_LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES) /** DAC channel x data is defined by ACMPTHRES in LESENSE_CHx_INTERACT. * Note: this value could be used for both DAC Ch0 and Ch1. */ - lesenseACMPThres = _LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES -} LESENSE_ControlDACData_TypeDef; + lesenseACMPThres = _LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES, +#endif +#if defined(_LESENSE_PERCTRL_DACCH0DATA_THRES) + /** DAC channel x data is defined by THRES in LESENSE_CHx_INTERACT. + * Note: this value could be used for both DAC Ch0 and Ch1. */ + lesenseThres = _LESENSE_PERCTRL_DACCH0DATA_THRES, +#endif +} LESENSE_ControlDACData_TypeDef; +#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK) /** DAC channel x conversion mode configuration. */ typedef enum { @@ -238,8 +252,9 @@ typedef enum * Note: this value could be used for both DAC Ch0 and Ch1. */ lesenseDACConvModeSampleOff = _LESENSE_PERCTRL_DACCH0CONV_SAMPLEOFF } LESENSE_ControlDACConv_TypeDef; +#endif - +#if defined(_LESENSE_PERCTRL_DACCH0OUT_MASK) /** DAC channel x output mode configuration. */ typedef enum { @@ -259,8 +274,10 @@ typedef enum * Note: this value could be used for both DAC Ch0 and Ch1. */ lesenseDACOutModePinADCACMP = _LESENSE_PERCTRL_DACCH0OUT_PINADCACMP } LESENSE_ControlDACOut_TypeDef; +#endif +#if defined(_LESENSE_PERCTRL_DACREF_MASK) /** DAC reference configuration. */ typedef enum { @@ -270,6 +287,7 @@ typedef enum /** DAC uses bandgap reference. */ lesenseDACRefBandGap = LESENSE_PERCTRL_DACREF_BANDGAP } LESENSE_DACRef_TypeDef; +#endif /** ACMPx control configuration. */ @@ -321,10 +339,18 @@ typedef enum typedef enum { /** Counter output will be used in comparison. */ - lesenseSampleModeCounter = LESENSE_CH_INTERACT_SAMPLE_COUNTER, + lesenseSampleModeCounter = 0x0 << _LESENSE_CH_INTERACT_SAMPLE_SHIFT, /** ACMP output will be used in comparison. */ - lesenseSampleModeACMP = LESENSE_CH_INTERACT_SAMPLE_ACMP + lesenseSampleModeACMP = LESENSE_CH_INTERACT_SAMPLE_ACMP, + +#if defined(LESENSE_CH_INTERACT_SAMPLE_ADC) + /** ADC output will be used in comparison. */ + lesenseSampleModeADC = LESENSE_CH_INTERACT_SAMPLE_ADC, + + /** Differential ADC output will be used in comparison. */ + lesenseSampleModeADCDiff = LESENSE_CH_INTERACT_SAMPLE_ADCDIFF, +#endif } LESENSE_ChSampleMode_TypeDef; @@ -377,13 +403,19 @@ typedef enum * Note: this value could be used for all channels. */ lesenseChPinIdleLow = _LESENSE_IDLECONF_CH0_LOW, +#if defined(_LESENSE_IDLECONF_CH0_DAC) + /** Channel pin is connected to DAC output in idle phase. + * Note: this value could be used for all channels. */ + lesenseChPinIdleDACC = _LESENSE_IDLECONF_CH0_DAC +#else /** Channel pin is connected to DAC CH0 output in idle phase. * Note: only applies to channel 0, 1, 2, 3. */ lesenseChPinIdleDACCh0 = _LESENSE_IDLECONF_CH0_DACCH0, /** Channel pin is connected to DAC CH1 output in idle phase. * Note: only applies to channel 12, 13, 14, 15. */ - lesenseChPinIdleDACCh1 = _LESENSE_IDLECONF_CH12_DACCH1 + lesenseChPinIdleDACCh1 = _LESENSE_IDLECONF_CH12_DACCH1, +#endif } LESENSE_ChPinIdleMode_TypeDef; @@ -401,16 +433,43 @@ typedef enum /** Compare modes for counter comparison. */ typedef enum { - /** Set interrupt flag if counter value is less than CTRTHRESHOLD, or if the - * ACMP output is 0. */ + /** Comparison evaluates to 1 if the sensor data is less than the counter + * threshold, or if the ACMP output is 0. */ lesenseCompModeLess = LESENSE_CH_EVAL_COMP_LESS, - /** Set interrupt flag if counter value is greater than, or equal to - * CTRTHRESHOLD, or if the ACMP output is 1. */ + /** Comparison evaluates to 1 if the sensor data is greater than, or equal to + * the counter threshold, or if the ACMP output is 1. */ lesenseCompModeGreaterOrEq = LESENSE_CH_EVAL_COMP_GE } LESENSE_ChCompMode_TypeDef; +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +/** Sensor evaluation modes. */ +typedef enum +{ + /** Threshold comparison evaluation mode. In this mode the sensor data + * is compared to the configured threshold value. Two possible comparison + * operators can be used on the sensor data, either >= (GE) or < (LT). + * Which operator to use is given using the + * @ref LESENSE_ChDesc_TypeDef::compMode member. */ + lesenseEvalModeThreshold = _LESENSE_CH_EVAL_MODE_THRES, + + /** Sliding window evaluation mode. In this mode the sensor data is + * evaluated against the upper and lower limits of a window range. The + * windows range is defined by a base value and a window size. */ + lesenseEvalModeSlidingWindow = _LESENSE_CH_EVAL_MODE_SLIDINGWIN, + + /** Step detection evaluation mode. In this mode the sensor data is compared + * to the sensor data from the previous measurement. The sensor evaluation + * will result in a "1" if the difference between the current measurement + * and the previous one is greater than a configurable "step size". If the + * difference is less than the configured step size then the sensor + * evaluation will result in a "0". */ + lesenseEvalModeStepDetection = _LESENSE_CH_EVAL_MODE_STEPDET, +} LESENSE_ChEvalMode_TypeDef; +#endif + + /** Idle phase configuration of alternate excitation channels. */ typedef enum { @@ -533,19 +592,25 @@ typedef struct true /* Keep LESENSE running in debug mode. */ \ } - /** LESENSE timing control descriptor structure. */ typedef struct { /** Set the number of LFACLK cycles to delay sensor interaction on * each channel. Valid range: 0-3 (2 bit). */ uint8_t startDelay; + + /** + * Set to true do delay the startup of AUXHFRCO until the system enters + * the excite phase. This will reduce the time AUXHFRCO is enabled and + * reduce power usage. */ + bool delayAuxStartup; } LESENSE_TimeCtrlDesc_TypeDef; /** Default configuration for LESENSE_TimeCtrlDesc_TypeDef structure. */ -#define LESENSE_TIMECTRL_DESC_DEFAULT \ -{ \ - 0U /* No sensor interaction delay. */ \ +#define LESENSE_TIMECTRL_DESC_DEFAULT \ +{ \ + 0U, /* No sensor interaction delay. */ \ + false /* Don't delay the AUXHFRCO startup. */ \ } @@ -555,28 +620,36 @@ typedef struct /** Configure DAC channel 0 data control. */ LESENSE_ControlDACData_TypeDef dacCh0Data; +#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK) /** Configure how LESENSE controls conversion on DAC channel 0. */ LESENSE_ControlDACConv_TypeDef dacCh0ConvMode; /** Configure how LESENSE controls output on DAC channel 0. */ LESENSE_ControlDACOut_TypeDef dacCh0OutMode; +#endif /** Configure DAC channel 1 data control. */ LESENSE_ControlDACData_TypeDef dacCh1Data; +#if defined(_LESENSE_PERCTRL_DACCH1CONV_MASK) /** Configure how LESENSE controls conversion on DAC channel 1. */ LESENSE_ControlDACConv_TypeDef dacCh1ConvMode; /** Configure how LESENSE controls output on DAC channel 1. */ LESENSE_ControlDACOut_TypeDef dacCh1OutMode; +#endif +#if defined(_LESENSE_PERCTRL_DACPRESC_MASK) /** Configure the prescaling factor for the LESENSE - DAC interface. * Valid range: 0-31 (5bit). */ uint8_t dacPresc; +#endif +#if defined(_LESENSE_PERCTRL_DACREF_MASK) /** Configure the DAC reference to be used. Set to #lesenseDACRefVdd to use * VDD and set to #lesenseDACRefBandGap to use bandgap as reference. */ LESENSE_DACRef_TypeDef dacRef; +#endif /** Configure how LESENSE controls ACMP 0. */ LESENSE_ControlACMP_TypeDef acmp0Mode; @@ -586,24 +659,41 @@ typedef struct /** Configure how LESENSE controls ACMPs and the DAC in idle mode. */ LESENSE_WarmupMode_TypeDef warmupMode; + +#if defined(_LESENSE_PERCTRL_DACCONVTRIG_MASK) + /** When set to true the DAC is only enabled once for each scan. When + * set to false the DAC is enabled before every channel measurement. */ + bool dacScan; +#endif } LESENSE_PerCtrlDesc_TypeDef; /** Default configuration for LESENSE_PerCtrl_TypeDef structure. */ +#if defined(_SILICON_LABS_32B_SERIES_0) #define LESENSE_PERCTRL_DESC_DEFAULT \ { \ - lesenseDACIfData, /**/ \ - lesenseDACConvModeDisable, /**/ \ - lesenseDACOutModeDisable, /**/ \ - lesenseDACIfData, /**/ \ - lesenseDACConvModeDisable, /**/ \ - lesenseDACOutModeDisable, /**/ \ - 0U, /**/ \ - lesenseDACRefVdd, /**/ \ - lesenseACMPModeMuxThres, /**/ \ - lesenseACMPModeMuxThres, /**/ \ - lesenseWarmupModeKeepWarm, /**/ \ + lesenseDACIfData, /* DAC channel 0 data is defined by DAC_CH0DATA register */ \ + lesenseDACConvModeDisable, /* LESENSE does not control DAC CH0. */ \ + lesenseDACOutModeDisable, /* DAC channel 0 output to pin disabled. */ \ + lesenseDACIfData, /* DAC channel 1 data is defined by DAC_CH1DATA register */ \ + lesenseDACConvModeDisable, /* LESENSE does not control DAC CH1. */ \ + lesenseDACOutModeDisable, /* DAC channel 1 output to pin disabled. */ \ + 0U, /* DAC prescaling factor of 1 (0+1). */ \ + lesenseDACRefVdd, /* DAC uses VDD reference. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \ + lesenseWarmupModeKeepWarm, /* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \ } - +#else +#define LESENSE_PERCTRL_DESC_DEFAULT \ +{ \ + lesenseDACIfData, /* DAC channel 0 data is defined by DAC_CH0DATA register. */ \ + lesenseDACIfData, /* DAC channel 1 data is defined by DAC_CH1DATA register. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \ + lesenseWarmupModeKeepWarm, /* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \ + false, /* DAC is enable for before every channel measurement. */ \ +} +#endif /** LESENSE decoder control descriptor structure. */ typedef struct @@ -615,7 +705,7 @@ typedef struct uint32_t initState; /** Set to enable the decoder to check the present state in addition - * to the states defined in DECCONF. */ + * to the states defined in TCONF. */ bool chkState; /** When set, a transition from state x in the decoder will set interrupt flag @@ -658,19 +748,19 @@ typedef struct /** Default configuration for LESENSE_PerCtrl_TypeDef structure. */ #define LESENSE_DECCTRL_DESC_DEFAULT \ { \ - lesenseDecInputSensorSt, /**/ \ - 0U, /**/ \ - false, /**/ \ - true, /**/ \ - true, /**/ \ - true, /**/ \ - true, /**/ \ - true, /**/ \ - false, /**/ \ - lesensePRSCh0, /**/ \ - lesensePRSCh1, /**/ \ - lesensePRSCh2, /**/ \ - lesensePRSCh3, /**/ \ + lesenseDecInputSensorSt, /* The SENSORSTATE register is used as input to the decoder. */ \ + 0U, /* State 0 is the initial state of the decoder. */ \ + false, /* Disable check of current state. */ \ + true, /* Enable channel x % 16 interrupt on state x change. */ \ + true, /* Enable decoder hysteresis on PRS0 output. */ \ + true, /* Enable decoder hysteresis on PRS1 output. */ \ + true, /* Enable decoder hysteresis on PRS2 output. */ \ + true, /* Enable decoder hysteresis on PRS3 output. */ \ + false, /* Disable count mode on decoder PRS channels 0 and 1*/ \ + lesensePRSCh0, /* PRS Channel 0 as input for bit 0 of the LESENSE decoder. */ \ + lesensePRSCh1, /* PRS Channel 1 as input for bit 1 of the LESENSE decoder. */ \ + lesensePRSCh2, /* PRS Channel 2 as input for bit 2 of the LESENSE decoder. */ \ + lesensePRSCh3, /* PRS Channel 3 as input for bit 3 of the LESENSE decoder. */ \ } @@ -745,14 +835,16 @@ typedef struct uint8_t exTime; /** Configure sample delay. Sampling will occur after sampleDelay+1 sample - * clock cycles. Valid range: 0-127 (7 bits). */ + * clock cycles. Valid range: 0-127 (7 bits) or 0-255 (8 bits) depending on + * device. */ uint8_t sampleDelay; /** Configure measure delay. Sensor measuring is delayed for measDelay - * excitation clock cycles. Valid range: 0-127 (7 bits). */ - uint8_t measDelay; + * excitation clock cycles. Valid range: 0-127 (7 bits) or 0-1023 (10 bits) + * depending on device. */ + uint16_t measDelay; - /** Configure ACMP threshold. + /** Configure ACMP threshold or DAC data. * If perCtrl.dacCh0Data or perCtrl.dacCh1Data is set to #lesenseDACIfData, * acmpThres defines the 12-bit DAC data in the corresponding data register * of the DAC interface (DACn_CH0DATA and DACn_CH1DATA). @@ -763,29 +855,61 @@ typedef struct * In this case, the valid range is: 0-63 (6 bits). */ uint16_t acmpThres; - /** Select if ACMP output or counter output should be used in comparison. */ + /** Select if ACMP output, ADC output or counter output should be used in + * comparison. */ LESENSE_ChSampleMode_TypeDef sampleMode; /** Configure interrupt generation mode for CHx interrupt flag. */ LESENSE_ChIntMode_TypeDef intMode; - /** Configure decision threshold for counter comparison. + /** Configure decision threshold for sensor data comparison. * Valid range: 0-65535 (16 bits). */ uint16_t cntThres; /** Select mode for counter comparison. */ LESENSE_ChCompMode_TypeDef compMode; + +#if defined(_LESENSE_CH_EVAL_MODE_MASK) + /** Select sensor evaluation mode. */ + LESENSE_ChEvalMode_TypeDef evalMode; +#endif + } LESENSE_ChDesc_TypeDef; /** Configuration structure for all scan channels. */ typedef struct { - /** Channel descriptor for all 16 channels. */ - LESENSE_ChDesc_TypeDef Ch[16]; + /** Channel descriptor for all LESENSE channels. */ + LESENSE_ChDesc_TypeDef Ch[LESENSE_NUM_CHANNELS]; } LESENSE_ChAll_TypeDef; /** Default configuration for scan channel. */ +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +#define LESENSE_CH_CONF_DEFAULT \ +{ \ + true, /* Enable scan channel. */ \ + true, /* Enable the assigned pin on scan channel. */ \ + true, /* Enable interrupts on channel. */ \ + lesenseChPinExHigh, /* Channel pin is high during the excitation period. */ \ + lesenseChPinIdleLow, /* Channel pin is low during the idle period. */ \ + false, /* Don't use alternate excitation pins for excitation. */ \ + false, /* Disabled to shift results from this channel to the decoder register. */ \ + false, /* Disabled to invert the scan result bit. */ \ + false, /* Disabled to store counter value in the result buffer. */ \ + lesenseClkLF, /* Use the LF clock for excitation timing. */ \ + lesenseClkLF, /* Use the LF clock for sample timing. */ \ + 0x03U, /* Excitation time is set to 3(+1) excitation clock cycles. */ \ + 0x09U, /* Sample delay is set to 9(+1) sample clock cycles. */ \ + 0x06U, /* Measure delay is set to 6 excitation clock cycles.*/ \ + 0x00U, /* ACMP threshold has been set to 0. */ \ + lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \ + lesenseSetIntNone, /* No interrupt is generated by the channel. */ \ + 0xFFU, /* Counter threshold has bee set to 0xFF. */ \ + lesenseCompModeLess, /* Compare mode has been set to trigger interrupt on "less". */ \ + lesenseEvalModeThreshold /* Compare mode has been set to trigger interrupt on "less". */ \ +} +#else #define LESENSE_CH_CONF_DEFAULT \ { \ true, /* Enable scan channel. */ \ @@ -808,6 +932,8 @@ typedef struct 0xFFU, /* Counter threshold has bee set to 0xFF. */ \ lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \ } +#endif + /** Default configuration for all sensor channels. */ #define LESENSE_SCAN_CONF_DEFAULT \ @@ -887,6 +1013,7 @@ typedef struct } /** Default configuration for all alternate excitation channels. */ +#if defined(_LESENSE_CTRL_ALTEXMAP_ACMP) #define LESENSE_ALTEX_CONF_DEFAULT \ { \ lesenseAltExMapACMP, \ @@ -909,7 +1036,30 @@ typedef struct LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \ } \ } - +#else +#define LESENSE_ALTEX_CONF_DEFAULT \ +{ \ + lesenseAltExMapCH, \ + { \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 0. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 1. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 2. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 3. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 4. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 5. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 6. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 7. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 8. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 9. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 10. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 11. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 12. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 13. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 14. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \ + } \ +} +#endif /** Decoder state condition descriptor structure. */ typedef struct @@ -966,11 +1116,12 @@ typedef struct /** Configuration structure for the decoder. */ typedef struct { - /** Descriptor of the 16 decoder states. */ - LESENSE_DecStDesc_TypeDef St[16]; + /** Descriptor of the 16 or 32 decoder states depending on the device. */ + LESENSE_DecStDesc_TypeDef St[LESENSE_NUM_DECODER_STATES]; } LESENSE_DecStAll_TypeDef; /** Default configuration for all decoder states. */ +#if defined(_SILICON_LABS_32B_SERIES_0) #define LESENSE_DECODER_CONF_DEFAULT \ { /* chain | Descriptor A | Descriptor B */ \ { \ @@ -992,44 +1143,93 @@ typedef struct { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 15. */ \ } \ } +#else +#define LESENSE_DECODER_CONF_DEFAULT \ +{ /* chain | Descriptor A | Descriptor B */ \ + { \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 0. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 1. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 2. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 3. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 4. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 5. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 6. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 7. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 8. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 9. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 10. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 11. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 12. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 13. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 14. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 15. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 16. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 17. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 18. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 19. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 20. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 21. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 22. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 23. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 24. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 25. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 26. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 27. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 28. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 29. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 30. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 31. */ \ + } \ +} +#endif /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ -void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset); +void LESENSE_Init(const LESENSE_Init_TypeDef * init, bool reqReset); void LESENSE_Reset(void); -uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t const scanFreq); -void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef const scanMode, - bool const start); - -void LESENSE_StartDelaySet(uint8_t const startDelay); +uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t scanFreq); +void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef scanMode, bool start); +void LESENSE_StartDelaySet(uint8_t startDelay); +void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef clk, + LESENSE_ClkPresc_TypeDef clkDiv); + +void LESENSE_ChannelAllConfig(const LESENSE_ChAll_TypeDef * confChAll); +void LESENSE_ChannelConfig(const LESENSE_ChDesc_TypeDef * confCh, + uint32_t chIdx); +void LESENSE_ChannelEnable(uint8_t chIdx, + bool enaScanCh, + bool enaPin); +void LESENSE_ChannelEnableMask(uint16_t chMask, uint16_t pinMask); +void LESENSE_ChannelTimingSet(uint8_t chIdx, + uint8_t exTime, + uint8_t sampleDelay, + uint16_t measDelay); +void LESENSE_ChannelThresSet(uint8_t chIdx, + uint16_t acmpThres, + uint16_t cntThres); +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +void LESENSE_ChannelSlidingWindow(uint8_t chIdx, + uint32_t windowSize, + uint32_t initValue); +void LESENSE_ChannelStepDetection(uint8_t chIdx, + uint32_t stepSize, + uint32_t initValue); +void LESENSE_WindowSizeSet(uint32_t windowSize); +void LESENSE_StepSizeSet(uint32_t stepSize); +#endif -void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef const clk, - LESENSE_ClkPresc_TypeDef const clkDiv); +void LESENSE_AltExConfig(const LESENSE_ConfAltEx_TypeDef * confAltEx); -void LESENSE_ChannelAllConfig(LESENSE_ChAll_TypeDef const *confChAll); -void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, - uint32_t const chIdx); -void LESENSE_ChannelEnable(uint8_t const chIdx, - bool const enaScanCh, - bool const enaPin); -void LESENSE_ChannelEnableMask(uint16_t chMask, uint16_t pinMask); -void LESENSE_ChannelTimingSet(uint8_t const chIdx, - uint8_t const exTime, - uint8_t const sampleDelay, - uint8_t const measDelay); -void LESENSE_ChannelThresSet(uint8_t const chIdx, - uint16_t const acmpThres, - uint16_t const cntThres); - -void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx); - -void LESENSE_DecoderStateAllConfig(LESENSE_DecStAll_TypeDef const *confDecStAll); -void LESENSE_DecoderStateConfig(LESENSE_DecStDesc_TypeDef const *confDecSt, - uint32_t const decSt); +void LESENSE_DecoderStateAllConfig(const LESENSE_DecStAll_TypeDef * confDecStAll); +void LESENSE_DecoderStateConfig(const LESENSE_DecStDesc_TypeDef * confDecSt, + uint32_t decSt); void LESENSE_DecoderStateSet(uint32_t decSt); uint32_t LESENSE_DecoderStateGet(void); +#if defined(_LESENSE_PRSCTRL_MASK) +void LESENSE_DecoderPrsOut(bool enable, uint32_t decMask, uint32_t decCmp); +#endif void LESENSE_ScanStart(void); void LESENSE_ScanStop(void); @@ -1126,7 +1326,7 @@ __STATIC_INLINE uint32_t LESENSE_ChannelActiveGet(void) ******************************************************************************/ __STATIC_INLINE uint32_t LESENSE_ScanResultGet(void) { - return LESENSE->SCANRES; + return LESENSE->SCANRES & _LESENSE_SCANRES_SCANRES_MASK; } @@ -1184,6 +1384,7 @@ __STATIC_INLINE uint32_t LESENSE_SensorStateGet(void) } +#if defined(LESENSE_POWERDOWN_RAM) /***************************************************************************//** * @brief * Shut off power to the LESENSE RAM, disables LESENSE. @@ -1201,6 +1402,7 @@ __STATIC_INLINE void LESENSE_RAMPowerDown(void) /* Power down LESENSE RAM */ LESENSE->POWERDOWN = LESENSE_POWERDOWN_RAM; } +#endif /***************************************************************************//** diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h index 782a9b8740b..9a3eeb83405 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_letimer.h * @brief Low Energy Timer (LETIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h index ac6f842ced3..656c0e4b97b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h @@ -2,7 +2,7 @@ * @file em_leuart.h * @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) * peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h index 3b5c5283814..b562694d396 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_mpu.h * @brief Memory protection unit (MPU) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h index 895ef37ccc6..9a71be990f0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_msc.h * @brief Flash controller (MSC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -132,7 +132,7 @@ extern "C" { /** Return codes for writing/erasing the flash */ typedef enum { - mscReturnOk = 0, /**< Flash write/erase successful. */ + mscReturnOk = 0, /**< Flash write/erase successful. */ mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not flash. */ mscReturnLocked = -2, /**< Flash address is locked. */ mscReturnTimeOut = -3, /**< Timeout while writing to flash. */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h index cdb22019860..204bfd16697 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file em_opamp.h * @brief Operational Amplifier (OPAMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -34,7 +34,8 @@ #define EM_OPAMP_H #include "em_device.h" -#if defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) +#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ + || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) #ifdef __cplusplus extern "C" { @@ -42,7 +43,12 @@ extern "C" { #include #include + +#if defined(_SILICON_LABS_32B_SERIES_0) #include "em_dac.h" +#elif defined (_SILICON_LABS_32B_SERIES_1) +#include "em_vdac.h" +#endif /***************************************************************************//** * @addtogroup emlib @@ -57,7 +63,11 @@ extern "C" { /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Validation of DAC OPA number for assert statements. */ +#if defined(_SILICON_LABS_32B_SERIES_0) #define DAC_OPA_VALID(opa) ((opa) <= OPA2) +#elif defined(_SILICON_LABS_32B_SERIES_1) +#define VDAC_OPA_VALID(opa) ((opa) <= OPA2) +#endif /** @endcond */ @@ -76,34 +86,249 @@ typedef enum /** OPAMP negative terminal input selection values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */ opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */ opaNegSelResTap = DAC_OPA0MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ opaNegSelNegPad = DAC_OPA0MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaNegSelAPORT1YCH1 = VDAC_OPA_MUX_NEGSEL_APORT1YCH1, /**< APORT1YCH1 */ + opaNegSelAPORT1YCH3 = VDAC_OPA_MUX_NEGSEL_APORT1YCH3, /**< APORT1YCH3 */ + opaNegSelAPORT1YCH5 = VDAC_OPA_MUX_NEGSEL_APORT1YCH5, /**< APORT1YCH5 */ + opaNegSelAPORT1YCH7 = VDAC_OPA_MUX_NEGSEL_APORT1YCH7, /**< APORT1YCH7 */ + opaNegSelAPORT1YCH9 = VDAC_OPA_MUX_NEGSEL_APORT1YCH9, /**< APORT1YCH9 */ + opaNegSelAPORT1YCH11 = VDAC_OPA_MUX_NEGSEL_APORT1YCH11, /**< APORT1YCH11 */ + opaNegSelAPORT1YCH13 = VDAC_OPA_MUX_NEGSEL_APORT1YCH13, /**< APORT1YCH13 */ + opaNegSelAPORT1YCH15 = VDAC_OPA_MUX_NEGSEL_APORT1YCH15, /**< APORT1YCH15 */ + opaNegSelAPORT1YCH17 = VDAC_OPA_MUX_NEGSEL_APORT1YCH17, /**< APORT1YCH17 */ + opaNegSelAPORT1YCH19 = VDAC_OPA_MUX_NEGSEL_APORT1YCH19, /**< APORT1YCH19 */ + opaNegSelAPORT1YCH21 = VDAC_OPA_MUX_NEGSEL_APORT1YCH21, /**< APORT1YCH21 */ + opaNegSelAPORT1YCH23 = VDAC_OPA_MUX_NEGSEL_APORT1YCH23, /**< APORT1YCH23 */ + opaNegSelAPORT1YCH25 = VDAC_OPA_MUX_NEGSEL_APORT1YCH25, /**< APORT1YCH25 */ + opaNegSelAPORT1YCH27 = VDAC_OPA_MUX_NEGSEL_APORT1YCH27, /**< APORT1YCH27 */ + opaNegSelAPORT1YCH29 = VDAC_OPA_MUX_NEGSEL_APORT1YCH29, /**< APORT1YCH29 */ + opaNegSelAPORT1YCH31 = VDAC_OPA_MUX_NEGSEL_APORT1YCH31, /**< APORT1YCH31 */ + opaNegSelAPORT2YCH0 = VDAC_OPA_MUX_NEGSEL_APORT2YCH0, /**< APORT2YCH0 */ + opaNegSelAPORT2YCH2 = VDAC_OPA_MUX_NEGSEL_APORT2YCH2, /**< APORT2YCH2 */ + opaNegSelAPORT2YCH4 = VDAC_OPA_MUX_NEGSEL_APORT2YCH4, /**< APORT2YCH4 */ + opaNegSelAPORT2YCH6 = VDAC_OPA_MUX_NEGSEL_APORT2YCH6, /**< APORT2YCH6 */ + opaNegSelAPORT2YCH8 = VDAC_OPA_MUX_NEGSEL_APORT2YCH8, /**< APORT2YCH8 */ + opaNegSelAPORT2YCH10 = VDAC_OPA_MUX_NEGSEL_APORT2YCH10, /**< APORT2YCH10 */ + opaNegSelAPORT2YCH12 = VDAC_OPA_MUX_NEGSEL_APORT2YCH12, /**< APORT2YCH12 */ + opaNegSelAPORT2YCH14 = VDAC_OPA_MUX_NEGSEL_APORT2YCH14, /**< APORT2YCH14 */ + opaNegSelAPORT2YCH16 = VDAC_OPA_MUX_NEGSEL_APORT2YCH16, /**< APORT2YCH16 */ + opaNegSelAPORT2YCH18 = VDAC_OPA_MUX_NEGSEL_APORT2YCH18, /**< APORT2YCH18 */ + opaNegSelAPORT2YCH20 = VDAC_OPA_MUX_NEGSEL_APORT2YCH20, /**< APORT2YCH20 */ + opaNegSelAPORT2YCH22 = VDAC_OPA_MUX_NEGSEL_APORT2YCH22, /**< APORT2YCH22 */ + opaNegSelAPORT2YCH24 = VDAC_OPA_MUX_NEGSEL_APORT2YCH24, /**< APORT2YCH24 */ + opaNegSelAPORT2YCH26 = VDAC_OPA_MUX_NEGSEL_APORT2YCH26, /**< APORT2YCH26 */ + opaNegSelAPORT2YCH28 = VDAC_OPA_MUX_NEGSEL_APORT2YCH28, /**< APORT2YCH28 */ + opaNegSelAPORT2YCH30 = VDAC_OPA_MUX_NEGSEL_APORT2YCH30, /**< APORT2YCH30 */ + opaNegSelAPORT3YCH1 = VDAC_OPA_MUX_NEGSEL_APORT3YCH1, /**< APORT3YCH1 */ + opaNegSelAPORT3YCH3 = VDAC_OPA_MUX_NEGSEL_APORT3YCH3, /**< APORT3YCH3 */ + opaNegSelAPORT3YCH5 = VDAC_OPA_MUX_NEGSEL_APORT3YCH5, /**< APORT3YCH5 */ + opaNegSelAPORT3YCH7 = VDAC_OPA_MUX_NEGSEL_APORT3YCH7, /**< APORT3YCH7 */ + opaNegSelAPORT3YCH9 = VDAC_OPA_MUX_NEGSEL_APORT3YCH9, /**< APORT3YCH9 */ + opaNegSelAPORT3YCH11 = VDAC_OPA_MUX_NEGSEL_APORT3YCH11, /**< APORT3YCH11 */ + opaNegSelAPORT3YCH13 = VDAC_OPA_MUX_NEGSEL_APORT3YCH13, /**< APORT3YCH13 */ + opaNegSelAPORT3YCH15 = VDAC_OPA_MUX_NEGSEL_APORT3YCH15, /**< APORT3YCH15 */ + opaNegSelAPORT3YCH17 = VDAC_OPA_MUX_NEGSEL_APORT3YCH17, /**< APORT3YCH17 */ + opaNegSelAPORT3YCH19 = VDAC_OPA_MUX_NEGSEL_APORT3YCH19, /**< APORT3YCH19 */ + opaNegSelAPORT3YCH21 = VDAC_OPA_MUX_NEGSEL_APORT3YCH21, /**< APORT3YCH21 */ + opaNegSelAPORT3YCH23 = VDAC_OPA_MUX_NEGSEL_APORT3YCH23, /**< APORT3YCH23 */ + opaNegSelAPORT3YCH25 = VDAC_OPA_MUX_NEGSEL_APORT3YCH25, /**< APORT3YCH25 */ + opaNegSelAPORT3YCH27 = VDAC_OPA_MUX_NEGSEL_APORT3YCH27, /**< APORT3YCH27 */ + opaNegSelAPORT3YCH29 = VDAC_OPA_MUX_NEGSEL_APORT3YCH29, /**< APORT3YCH29 */ + opaNegSelAPORT3YCH31 = VDAC_OPA_MUX_NEGSEL_APORT3YCH31, /**< APORT3YCH31 */ + opaNegSelAPORT4YCH0 = VDAC_OPA_MUX_NEGSEL_APORT4YCH0, /**< APORT4YCH0 */ + opaNegSelAPORT4YCH2 = VDAC_OPA_MUX_NEGSEL_APORT4YCH2, /**< APORT4YCH2 */ + opaNegSelAPORT4YCH4 = VDAC_OPA_MUX_NEGSEL_APORT4YCH4, /**< APORT4YCH4 */ + opaNegSelAPORT4YCH6 = VDAC_OPA_MUX_NEGSEL_APORT4YCH6, /**< APORT4YCH6 */ + opaNegSelAPORT4YCH8 = VDAC_OPA_MUX_NEGSEL_APORT4YCH8, /**< APORT4YCH8 */ + opaNegSelAPORT4YCH10 = VDAC_OPA_MUX_NEGSEL_APORT4YCH10, /**< APORT4YCH10 */ + opaNegSelAPORT4YCH12 = VDAC_OPA_MUX_NEGSEL_APORT4YCH12, /**< APORT4YCH12 */ + opaNegSelAPORT4YCH14 = VDAC_OPA_MUX_NEGSEL_APORT4YCH14, /**< APORT4YCH14 */ + opaNegSelAPORT4YCH16 = VDAC_OPA_MUX_NEGSEL_APORT4YCH16, /**< APORT4YCH16 */ + opaNegSelAPORT4YCH18 = VDAC_OPA_MUX_NEGSEL_APORT4YCH18, /**< APORT4YCH18 */ + opaNegSelAPORT4YCH20 = VDAC_OPA_MUX_NEGSEL_APORT4YCH20, /**< APORT4YCH20 */ + opaNegSelAPORT4YCH22 = VDAC_OPA_MUX_NEGSEL_APORT4YCH22, /**< APORT4YCH22 */ + opaNegSelAPORT4YCH24 = VDAC_OPA_MUX_NEGSEL_APORT4YCH24, /**< APORT4YCH24 */ + opaNegSelAPORT4YCH26 = VDAC_OPA_MUX_NEGSEL_APORT4YCH26, /**< APORT4YCH26 */ + opaNegSelAPORT4YCH28 = VDAC_OPA_MUX_NEGSEL_APORT4YCH28, /**< APORT4YCH28 */ + opaNegSelAPORT4YCH30 = VDAC_OPA_MUX_NEGSEL_APORT4YCH30, /**< APORT4YCH30 */ + opaNegSelDisable = VDAC_OPA_MUX_NEGSEL_DISABLE, /**< Input disabled. */ + opaNegSelUnityGain = VDAC_OPA_MUX_NEGSEL_UG, /**< Unity gain feedback path. */ + opaNegSelResTap = VDAC_OPA_MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ + opaNegSelNegPad = VDAC_OPA_MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_NegSel_TypeDef; /** OPAMP positive terminal input selection values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */ opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ opaPosSelPosPad = DAC_OPA0MUX_POSSEL_POSPAD, /**< Positive pad as input. */ opaPosSelOpaIn = DAC_OPA0MUX_POSSEL_OPA0INP, /**< Input from OPAx. */ opaPosSelResTapOpa0 = DAC_OPA0MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap from OPA0. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaPosSelAPORT1XCH0 = VDAC_OPA_MUX_POSSEL_APORT1XCH0, /**< APORT1XCH0 */ + opaPosSelAPORT1XCH2 = VDAC_OPA_MUX_POSSEL_APORT1XCH2, /**< APORT1XCH2 */ + opaPosSelAPORT1XCH4 = VDAC_OPA_MUX_POSSEL_APORT1XCH4, /**< APORT1XCH4 */ + opaPosSelAPORT1XCH6 = VDAC_OPA_MUX_POSSEL_APORT1XCH6, /**< APORT1XCH6 */ + opaPosSelAPORT1XCH8 = VDAC_OPA_MUX_POSSEL_APORT1XCH8, /**< APORT1XCH8 */ + opaPosSelAPORT1XCH10 = VDAC_OPA_MUX_POSSEL_APORT1XCH10, /**< APORT1XCH10 */ + opaPosSelAPORT1XCH12 = VDAC_OPA_MUX_POSSEL_APORT1XCH12, /**< APORT1XCH12 */ + opaPosSelAPORT1XCH14 = VDAC_OPA_MUX_POSSEL_APORT1XCH14, /**< APORT1XCH14 */ + opaPosSelAPORT1XCH16 = VDAC_OPA_MUX_POSSEL_APORT1XCH16, /**< APORT1XCH16 */ + opaPosSelAPORT1XCH18 = VDAC_OPA_MUX_POSSEL_APORT1XCH18, /**< APORT1XCH18 */ + opaPosSelAPORT1XCH20 = VDAC_OPA_MUX_POSSEL_APORT1XCH20, /**< APORT1XCH20 */ + opaPosSelAPORT1XCH22 = VDAC_OPA_MUX_POSSEL_APORT1XCH22, /**< APORT1XCH22 */ + opaPosSelAPORT1XCH24 = VDAC_OPA_MUX_POSSEL_APORT1XCH24, /**< APORT1XCH24 */ + opaPosSelAPORT1XCH26 = VDAC_OPA_MUX_POSSEL_APORT1XCH26, /**< APORT1XCH26 */ + opaPosSelAPORT1XCH28 = VDAC_OPA_MUX_POSSEL_APORT1XCH28, /**< APORT1XCH28 */ + opaPosSelAPORT1XCH30 = VDAC_OPA_MUX_POSSEL_APORT1XCH30, /**< APORT1XCH30 */ + opaPosSelAPORT2XCH1 = VDAC_OPA_MUX_POSSEL_APORT2XCH1, /**< APORT2XCH1 */ + opaPosSelAPORT2XCH3 = VDAC_OPA_MUX_POSSEL_APORT2XCH3, /**< APORT2XCH3 */ + opaPosSelAPORT2XCH5 = VDAC_OPA_MUX_POSSEL_APORT2XCH5, /**< APORT2XCH5 */ + opaPosSelAPORT2XCH7 = VDAC_OPA_MUX_POSSEL_APORT2XCH7, /**< APORT2XCH7 */ + opaPosSelAPORT2XCH9 = VDAC_OPA_MUX_POSSEL_APORT2XCH9, /**< APORT2XCH9 */ + opaPosSelAPORT2XCH11 = VDAC_OPA_MUX_POSSEL_APORT2XCH11, /**< APORT2XCH11 */ + opaPosSelAPORT2XCH13 = VDAC_OPA_MUX_POSSEL_APORT2XCH13, /**< APORT2XCH13 */ + opaPosSelAPORT2XCH15 = VDAC_OPA_MUX_POSSEL_APORT2XCH15, /**< APORT2XCH15 */ + opaPosSelAPORT2XCH17 = VDAC_OPA_MUX_POSSEL_APORT2XCH17, /**< APORT2XCH17 */ + opaPosSelAPORT2XCH19 = VDAC_OPA_MUX_POSSEL_APORT2XCH19, /**< APORT2XCH19 */ + opaPosSelAPORT2XCH21 = VDAC_OPA_MUX_POSSEL_APORT2XCH21, /**< APORT2XCH21 */ + opaPosSelAPORT2XCH23 = VDAC_OPA_MUX_POSSEL_APORT2XCH23, /**< APORT2XCH23 */ + opaPosSelAPORT2XCH25 = VDAC_OPA_MUX_POSSEL_APORT2XCH25, /**< APORT2XCH25 */ + opaPosSelAPORT2XCH27 = VDAC_OPA_MUX_POSSEL_APORT2XCH27, /**< APORT2XCH27 */ + opaPosSelAPORT2XCH29 = VDAC_OPA_MUX_POSSEL_APORT2XCH29, /**< APORT2XCH29 */ + opaPosSelAPORT2XCH31 = VDAC_OPA_MUX_POSSEL_APORT2XCH31, /**< APORT2XCH31 */ + opaPosSelAPORT3XCH0 = VDAC_OPA_MUX_POSSEL_APORT3XCH0, /**< APORT3XCH0 */ + opaPosSelAPORT3XCH2 = VDAC_OPA_MUX_POSSEL_APORT3XCH2, /**< APORT3XCH2 */ + opaPosSelAPORT3XCH4 = VDAC_OPA_MUX_POSSEL_APORT3XCH4, /**< APORT3XCH4 */ + opaPosSelAPORT3XCH6 = VDAC_OPA_MUX_POSSEL_APORT3XCH6, /**< APORT3XCH6 */ + opaPosSelAPORT3XCH8 = VDAC_OPA_MUX_POSSEL_APORT3XCH8, /**< APORT3XCH8 */ + opaPosSelAPORT3XCH10 = VDAC_OPA_MUX_POSSEL_APORT3XCH10, /**< APORT3XCH10 */ + opaPosSelAPORT3XCH12 = VDAC_OPA_MUX_POSSEL_APORT3XCH12, /**< APORT3XCH12 */ + opaPosSelAPORT3XCH14 = VDAC_OPA_MUX_POSSEL_APORT3XCH14, /**< APORT3XCH14 */ + opaPosSelAPORT3XCH16 = VDAC_OPA_MUX_POSSEL_APORT3XCH16, /**< APORT3XCH16 */ + opaPosSelAPORT3XCH18 = VDAC_OPA_MUX_POSSEL_APORT3XCH18, /**< APORT3XCH18 */ + opaPosSelAPORT3XCH20 = VDAC_OPA_MUX_POSSEL_APORT3XCH20, /**< APORT3XCH20 */ + opaPosSelAPORT3XCH22 = VDAC_OPA_MUX_POSSEL_APORT3XCH22, /**< APORT3XCH22 */ + opaPosSelAPORT3XCH24 = VDAC_OPA_MUX_POSSEL_APORT3XCH24, /**< APORT3XCH24 */ + opaPosSelAPORT3XCH26 = VDAC_OPA_MUX_POSSEL_APORT3XCH26, /**< APORT3XCH26 */ + opaPosSelAPORT3XCH28 = VDAC_OPA_MUX_POSSEL_APORT3XCH28, /**< APORT3XCH28 */ + opaPosSelAPORT3XCH30 = VDAC_OPA_MUX_POSSEL_APORT3XCH30, /**< APORT3XCH30 */ + opaPosSelAPORT4XCH1 = VDAC_OPA_MUX_POSSEL_APORT4XCH1, /**< APORT4XCH1 */ + opaPosSelAPORT4XCH3 = VDAC_OPA_MUX_POSSEL_APORT4XCH3, /**< APORT4XCH3 */ + opaPosSelAPORT4XCH5 = VDAC_OPA_MUX_POSSEL_APORT4XCH5, /**< APORT4XCH5 */ + opaPosSelAPORT4XCH7 = VDAC_OPA_MUX_POSSEL_APORT4XCH7, /**< APORT4XCH7 */ + opaPosSelAPORT4XCH9 = VDAC_OPA_MUX_POSSEL_APORT4XCH9, /**< APORT4XCH9 */ + opaPosSelAPORT4XCH11 = VDAC_OPA_MUX_POSSEL_APORT4XCH11, /**< APORT4XCH11 */ + opaPosSelAPORT4XCH13 = VDAC_OPA_MUX_POSSEL_APORT4XCH13, /**< APORT4XCH13 */ + opaPosSelAPORT4XCH15 = VDAC_OPA_MUX_POSSEL_APORT4XCH15, /**< APORT4XCH15 */ + opaPosSelAPORT4XCH17 = VDAC_OPA_MUX_POSSEL_APORT4XCH17, /**< APORT4XCH17 */ + opaPosSelAPORT4XCH19 = VDAC_OPA_MUX_POSSEL_APORT4XCH19, /**< APORT4XCH19 */ + opaPosSelAPORT4XCH21 = VDAC_OPA_MUX_POSSEL_APORT4XCH21, /**< APORT4XCH21 */ + opaPosSelAPORT4XCH23 = VDAC_OPA_MUX_POSSEL_APORT4XCH23, /**< APORT4XCH23 */ + opaPosSelAPORT4XCH25 = VDAC_OPA_MUX_POSSEL_APORT4XCH25, /**< APORT4XCH25 */ + opaPosSelAPORT4XCH27 = VDAC_OPA_MUX_POSSEL_APORT4XCH27, /**< APORT4XCH27 */ + opaPosSelAPORT4XCH29 = VDAC_OPA_MUX_POSSEL_APORT4XCH29, /**< APORT4XCH29 */ + opaPosSelAPORT4XCH31 = VDAC_OPA_MUX_POSSEL_APORT4XCH31, /**< APORT4XCH31 */ + opaPosSelDisable = VDAC_OPA_MUX_POSSEL_DISABLE, /**< Input disabled. */ + opaPosSelDac = VDAC_OPA_MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ + opaPosSelPosPad = VDAC_OPA_MUX_POSSEL_POSPAD, /**< Positive pad as input. */ + opaPosSelOpaIn = VDAC_OPA_MUX_POSSEL_OPANEXT, /**< Input from OPAx. */ + opaPosSelResTap = VDAC_OPA_MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_PosSel_TypeDef; /** OPAMP output terminal selection values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */ opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */ opaOutModeAlt = DAC_OPA0MUX_OUTMODE_ALT, /**< Alternate output(s) enabled (not OPA2). */ opaOutModeAll = DAC_OPA0MUX_OUTMODE_ALL /**< Both main and alternate enabled (not OPA2). */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaOutModeDisable = 0, /**< OPA output disabled. */ + opaOutModeMain = VDAC_OPA_OUT_MAINOUTEN, /**< Main output to pin enabled. */ + opaOutModeAlt = VDAC_OPA_OUT_ALTOUTEN, /**< Alternate output(s) enabled (not OPA2). */ + opaOutModeAll = VDAC_OPA_OUT_SHORT, /**< Both main and alternate enabled (not OPA2). */ + opaOutModeAPORT1YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1), /**< APORT output to APORT1YCH1 pin enabled. */ + opaOutModeAPORT1YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3), /**< APORT output to APORT1YCH3 pin enabled. */ + opaOutModeAPORT1YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5), /**< APORT output to APORT1YCH5 pin enabled. */ + opaOutModeAPORT1YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7), /**< APORT output to APORT1YCH7 pin enabled. */ + opaOutModeAPORT1YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9), /**< APORT output to APORT1YCH9 pin enabled. */ + opaOutModeAPORT1YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11), /**< APORT output to APORT1YCH11 pin enabled. */ + opaOutModeAPORT1YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13), /**< APORT output to APORT1YCH13 pin enabled. */ + opaOutModeAPORT1YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15), /**< APORT output to APORT1YCH15 pin enabled. */ + opaOutModeAPORT1YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17), /**< APORT output to APORT1YCH17 pin enabled. */ + opaOutModeAPORT1YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19), /**< APORT output to APORT1YCH19 pin enabled. */ + opaOutModeAPORT1YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21), /**< APORT output to APORT1YCH21 pin enabled. */ + opaOutModeAPORT1YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23), /**< APORT output to APORT1YCH23 pin enabled. */ + opaOutModeAPORT1YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25), /**< APORT output to APORT1YCH25 pin enabled. */ + opaOutModeAPORT1YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27), /**< APORT output to APORT1YCH27 pin enabled. */ + opaOutModeAPORT1YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29), /**< APORT output to APORT1YCH29 pin enabled. */ + opaOutModeAPORT1YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31), /**< APORT output to APORT1YCH31 pin enabled. */ + opaOutModeAPORT2YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0), /**< APORT output to APORT2YCH0 pin enabled. */ + opaOutModeAPORT2YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2), /**< APORT output to APORT2YCH2 pin enabled. */ + opaOutModeAPORT2YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4), /**< APORT output to APORT2YCH4 pin enabled. */ + opaOutModeAPORT2YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6), /**< APORT output to APORT2YCH6 pin enabled. */ + opaOutModeAPORT2YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8), /**< APORT output to APORT2YCH8 pin enabled. */ + opaOutModeAPORT2YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10), /**< APORT output to APORT2YCH10 pin enabled. */ + opaOutModeAPORT2YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12), /**< APORT output to APORT2YCH12 pin enabled. */ + opaOutModeAPORT2YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14), /**< APORT output to APORT2YCH14 pin enabled. */ + opaOutModeAPORT2YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16), /**< APORT output to APORT2YCH16 pin enabled. */ + opaOutModeAPORT2YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18), /**< APORT output to APORT2YCH18 pin enabled. */ + opaOutModeAPORT2YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20), /**< APORT output to APORT2YCH20 pin enabled. */ + opaOutModeAPORT2YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22), /**< APORT output to APORT2YCH22 pin enabled. */ + opaOutModeAPORT2YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24), /**< APORT output to APORT2YCH24 pin enabled. */ + opaOutModeAPORT2YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26), /**< APORT output to APORT2YCH26 pin enabled. */ + opaOutModeAPORT2YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28), /**< APORT output to APORT2YCH28 pin enabled. */ + opaOutModeAPORT2YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30), /**< APORT output to APORT2YCH30 pin enabled. */ + opaOutModeAPORT3YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1), /**< APORT output to APORT3YCH1 pin enabled. */ + opaOutModeAPORT3YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3), /**< APORT output to APORT3YCH3 pin enabled. */ + opaOutModeAPORT3YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5), /**< APORT output to APORT3YCH5 pin enabled. */ + opaOutModeAPORT3YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7), /**< APORT output to APORT3YCH7 pin enabled. */ + opaOutModeAPORT3YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9), /**< APORT output to APORT3YCH9 pin enabled. */ + opaOutModeAPORT3YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11), /**< APORT output to APORT3YCH11 pin enabled. */ + opaOutModeAPORT3YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13), /**< APORT output to APORT3YCH13 pin enabled. */ + opaOutModeAPORT3YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15), /**< APORT output to APORT3YCH15 pin enabled. */ + opaOutModeAPORT3YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17), /**< APORT output to APORT3YCH17 pin enabled. */ + opaOutModeAPORT3YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19), /**< APORT output to APORT3YCH19 pin enabled. */ + opaOutModeAPORT3YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21), /**< APORT output to APORT3YCH21 pin enabled. */ + opaOutModeAPORT3YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23), /**< APORT output to APORT3YCH23 pin enabled. */ + opaOutModeAPORT3YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25), /**< APORT output to APORT3YCH25 pin enabled. */ + opaOutModeAPORT3YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27), /**< APORT output to APORT3YCH27 pin enabled. */ + opaOutModeAPORT3YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29), /**< APORT output to APORT3YCH29 pin enabled. */ + opaOutModeAPORT3YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31), /**< APORT output to APORT3YCH31 pin enabled. */ + opaOutModeAPORT4YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0), /**< APORT output to APORT4YCH0 pin enabled. */ + opaOutModeAPORT4YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2), /**< APORT output to APORT4YCH2 pin enabled. */ + opaOutModeAPORT4YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4), /**< APORT output to APORT4YCH4 pin enabled. */ + opaOutModeAPORT4YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6), /**< APORT output to APORT4YCH6 pin enabled. */ + opaOutModeAPORT4YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8), /**< APORT output to APORT4YCH8 pin enabled. */ + opaOutModeAPORT4YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10), /**< APORT output to APORT4YCH10 pin enabled. */ + opaOutModeAPORT4YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12), /**< APORT output to APORT4YCH12 pin enabled. */ + opaOutModeAPORT4YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14), /**< APORT output to APORT4YCH14 pin enabled. */ + opaOutModeAPORT4YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16), /**< APORT output to APORT4YCH16 pin enabled. */ + opaOutModeAPORT4YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18), /**< APORT output to APORT4YCH18 pin enabled. */ + opaOutModeAPORT4YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20), /**< APORT output to APORT4YCH20 pin enabled. */ + opaOutModeAPORT4YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22), /**< APORT output to APORT4YCH22 pin enabled. */ + opaOutModeAPORT4YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24), /**< APORT output to APORT4YCH24 pin enabled. */ + opaOutModeAPORT4YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26), /**< APORT output to APORT4YCH26 pin enabled. */ + opaOutModeAPORT4YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28), /**< APORT output to APORT4YCH28 pin enabled. */ + opaOutModeAPORT4YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30), /**< APORT output to APORT4YCH30 pin enabled. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_OutMode_TypeDef; /** OPAMP gain values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ opaResSelR2eqR1 = DAC_OPA0MUX_RESSEL_RES1, /**< R2 = R1 */ @@ -113,18 +338,94 @@ typedef enum opaResSelR2eq4_33R1 = DAC_OPA0MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ opaResSelR2eq7R1 = DAC_OPA0MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ opaResSelR2eq15R1 = DAC_OPA0MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaResSelDefault = VDAC_OPA_MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ + opaResSelR2eq0_33R1 = VDAC_OPA_MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ + opaResSelR2eqR1 = VDAC_OPA_MUX_RESSEL_RES1, /**< R2 = R1 */ + opaResSelR1eq1_67R1 = VDAC_OPA_MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ + opaResSelR2eq2_2R1 = VDAC_OPA_MUX_RESSEL_RES3, /**< R2 = 2.2 * R1 */ + opaResSelR2eq3R1 = VDAC_OPA_MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ + opaResSelR2eq4_33R1 = VDAC_OPA_MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ + opaResSelR2eq7R1 = VDAC_OPA_MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ + opaResSelR2eq15R1 = VDAC_OPA_MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_ResSel_TypeDef; /** OPAMP resistor ladder input selector values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP, /**< Input from OPAx. */ opaResInMuxNegPad = DAC_OPA0MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ opaResInMuxPosPad = DAC_OPA0MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ opaResInMuxVss = DAC_OPA0MUX_RESINMUX_VSS /**< Input connected to Vss. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaResInMuxDisable = VDAC_OPA_MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ + opaResInMuxOpaIn = VDAC_OPA_MUX_RESINMUX_OPANEXT, /**< Input from OPAx. */ + opaResInMuxNegPad = VDAC_OPA_MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ + opaResInMuxPosPad = VDAC_OPA_MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ + opaResInMuxComPad = VDAC_OPA_MUX_RESINMUX_COMPAD, /**< Input from negative pad of OPA0. + Direct input to support common reference. */ + opaResInMuxCenter = VDAC_OPA_MUX_RESINMUX_CENTER, /**< OPA0 and OPA1 Resmux connected to form fully + differential instrumentation amplifier. */ + opaResInMuxVss = VDAC_OPA_MUX_RESINMUX_VSS, /**< Input connected to Vss. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_ResInMux_TypeDef; +#if defined(_SILICON_LABS_32B_SERIES_1) +typedef enum +{ + opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT, /**< Default value when PRS is not the trigger. */ + opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED, /**< PRS trigger is a pulse that starts the OPAMP + warmup sequence. The end of the warmup sequence + is controlled by timeout settings in OPAxTIMER. */ + opaPrsModeTimed = VDAC_OPA_CTRL_PRSMODE_TIMED, /**< PRS trigger is a pulse long enough to provide the + OPAMP warmup sequence. The end of the warmup + sequence is controlled by the edge of the pulse. */ +} OPAMP_PrsMode_TypeDef; + +typedef enum +{ + opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT, /**< Default value when PRS is not the trigger. */ + opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0 triggers OPAMP. */ + opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1 triggers OPAMP. */ + opaPrsSelCh2 = VDAC_OPA_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2 triggers OPAMP. */ + opaPrsSelCh3 = VDAC_OPA_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3 triggers OPAMP. */ + opaPrsSelCh4 = VDAC_OPA_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4 triggers OPAMP. */ + opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5 triggers OPAMP. */ + opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6 triggers OPAMP. */ + opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7 triggers OPAMP. */ + opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8 triggers OPAMP. */ + opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9 triggers OPAMP. */ + opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 triggers OPAMP. */ + opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 triggers OPAMP. */ +} OPAMP_PrsSel_TypeDef; + +typedef enum +{ + opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT, /**< Default value. */ + opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM, /**< Warm status available on PRS. */ + opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID, /**< Outvalid status available on PRS. */ +} OPAMP_PrsOut_TypeDef; + +typedef enum +{ + opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT, /**< Default OPAM output drive strength. */ + opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL, /**< OPAMP uses full output drive strength. */ + opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF, /**< OPAMP uses half output drive strength. */ +} OPAMP_OutScale_Typedef; + +typedef enum +{ + opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT, /**< Default value. */ + opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Lower accuracy with low drive stregth. */ + opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Low accuracy with low drive stregth. */ + opaDrvStrHighAccHighStr = (2 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< High accuracy with high drive stregth. */ + opaDrvStrHigherAccHighStr = (3 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Higher accuracy with high drive stregth. */ +} OPAMP_DrvStr_Typedef; +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ @@ -139,6 +440,7 @@ typedef struct OPAMP_ResInMux_TypeDef resInMux; /**< Select input source for resistor ladder. */ uint32_t outPen; /**< Alternate output enable bit mask. This value should consist of one or more of the + @if DOXYDOC_P1_DEVICE DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags (defined in \_dac.h) OR'ed together. @n @n @@ -163,7 +465,24 @@ typedef struct E.g: @n init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 | DAC_OPA0MUX_OUTPEN_OUT2 | - DAC_OPA0MUX_OUTPEN_OUT4; */ + DAC_OPA0MUX_OUTPEN_OUT4; + + @elseif DOXYDOC_P2_DEVICE + VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags + (defined in \_vdac.h) OR'ed together. + @n @n + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 + + E.g: @n + init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | + VDAC_OPA_OUT_ALTOUTPADEN_OUT2 | + VDAC_OPA_OUT_ALTOUTPADEN_OUT4; + @endif */ +#if defined(_SILICON_LABS_32B_SERIES_0) uint32_t bias; /**< Set OPAMP bias current. */ bool halfBias; /**< Divide OPAMP bias current by 2. */ bool lpfPosPadDisable; /**< Disable low pass filter on positive pad. */ @@ -174,9 +493,34 @@ typedef struct bool shortInputs; /**< Short OPAMP input terminals. */ bool hcmDisable; /**< Disable input rail-to-rail capability. */ bool defaultOffset; /**< Use factory calibrated opamp offset value. */ - uint32_t offset; /**< Opamp offset value when @ref defaultOffset is false.*/ + uint32_t offset; /**< Opamp offset value when @ref defaultOffset is + false. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + OPAMP_DrvStr_Typedef drvStr; /**< OPAx operation mode. */ + bool gain3xEn; /**< Enable 3x gain resistor ladder. */ + bool halfDrvStr; /**< Half or full output drive strength. */ + bool ugBwScale; /**< Unity gain bandwidth scaled by factor of 2.5. */ + bool prsEn; /**< Enable PRS as OPAMP trigger. */ + OPAMP_PrsMode_TypeDef prsMode; /**< Selects PRS trigger mode. */ + OPAMP_PrsSel_TypeDef prsSel; /**< PRS channel trigger select. */ + OPAMP_PrsOut_TypeDef prsOutSel; /**< PRS output select. */ + bool aportYMasterDisable; /**< Disable bus master request on APORT Y. */ + bool aportXMasterDisable; /**< Disable bus master request on APORT X. */ + uint32_t settleTime; /**< Number of clock cycles to drive the output. */ + uint32_t startupDly; /**< OPAx startup delay in us. */ + bool hcmDisable; /**< Disable input rail-to-rail capability. */ + bool defaultOffsetN; /**< Use factory calibrated opamp inverting input + offset value. */ + uint32_t offsetN; /**< Opamp inverting input offset value when + @ref defaultOffsetInv is false. */ + bool defaultOffsetP; /**< Use factory calibrated opamp non-inverting + input offset value. */ + uint32_t offsetP; /**< Opamp non-inverting input offset value when + @ref defaultOffsetNon is false. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_1) */ } OPAMP_Init_TypeDef; +#if defined(_SILICON_LABS_32B_SERIES_0) /** Configuration of OPA0/1 in unity gain voltage follower mode. */ #define OPA_INIT_UNITY_GAIN \ { \ @@ -551,12 +895,468 @@ typedef struct 0 /* Opamp offset value (not used). */ \ } +#elif defined(_SILICON_LABS_32B_SERIES_1) +/** Configuration of OPA in unity gain voltage follower mode. */ +#define OPA_INIT_UNITY_GAIN \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA in non-inverting amplifier mode. */ +#define OPA_INIT_NON_INVERTING \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA in inverting amplifier mode. */ +#define OPA_INIT_INVERTING \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Pos input from OPA0 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Pos input from OPA1 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA0 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA1 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA2 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA2 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA0 \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA1 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA0 \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA1 \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Disable resistor ladder. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA2 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA2 \ +{ \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in two-opamp instrumentation amplifier mode. */ +#define OPA_INIT_INSTR_AMP_OPA0 \ +{ \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in two-opamp instrumentation amplifier mode. */ +#define OPA_INIT_INSTR_AMP_OPA1 \ +{ \ + opaNegSelNegPad, /* Neg input from pad. */ \ + opaPosSelResTap, /* Input from resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_0) void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa); void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); +#elif defined(_SILICON_LABS_32B_SERIES_1) +void OPAMP_Disable(VDAC_TypeDef *dac, OPAMP_TypeDef opa); +void OPAMP_Enable(VDAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ /** @} (end addtogroup OPAMP) */ /** @} (end addtogroup emlib) */ @@ -565,5 +1365,6 @@ void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_Typ } #endif -#endif /* defined( OPAMP_PRESENT ) && ( OPAMP_COUNT == 1 ) */ +#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) + || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ #endif /* EM_OPAMP_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h index c2a7b95c504..7dabb414272 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_pcnt.h * @brief Pulse Counter (PCNT) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h index 26306b70c4d..1d995a7df6d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_prs.h * @brief Peripheral Reflex System (PRS) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h index 51dee93b30d..5476c265bbd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ramfunc.h * @brief RAM code support. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h index 81404cdcdae..f8ea76bbe7a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_rmu.h * @brief Reset Management Unit (RMU) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h index c3cb033095f..14b28ed06c7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_rtc.h * @brief Real Time Counter (RTC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h index 3f6789a1cde..388a69ff486 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief Real Time Counter (RTCC) peripheral API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -53,6 +53,21 @@ extern "C" { * @{ ******************************************************************************/ +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +/* Enable fix for errata "RTCC_E203 - Potential Stability Issue with RTCC + * Registers". */ +#define ERRATA_FIX_RTCC_E203 +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) +/* Enable fix for errata "RTCC_E204 - Disabling the RTCC Backup RAM may consume extra + * current". */ +#define ERRATA_FIX_RTCC_E204 +#endif +/** @endcond */ + /******************************************************************************* ********************************* ENUM ************************************ ******************************************************************************/ @@ -588,7 +603,26 @@ __STATIC_INLINE void RTCC_IntSet( uint32_t flags ) ******************************************************************************/ __STATIC_INLINE void RTCC_Lock( void ) { +#if defined(ERRATA_FIX_RTCC_E203) + /* RTCC_E203 - Potential Stability Issue with RTCC Registers + * RTCC_LOCK register must be modified while RTCC clock is disabled. */ + uint32_t lfeReg = CMU->LFECLKEN0; + bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; + } + CMU->LFECLKEN0 = 0x0; +#endif RTCC->LOCK = RTCC_LOCK_LOCKKEY_LOCK; +#if defined(ERRATA_FIX_RTCC_E203) + /* Restore clock state after RTCC_E203 fix. */ + CMU->LFECLKEN0 = lfeReg; + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; + } +#endif } /***************************************************************************//** @@ -626,7 +660,11 @@ void RTCC_Reset( void ); ******************************************************************************/ __STATIC_INLINE void RTCC_RetentionRamPowerDown( void ) { +#if !defined(ERRATA_FIX_RTCC_E204) + /* Devices that are affected by RTCC_E204 should always keep the RTCC + * backup RAM retained. */ RTCC->POWERDOWN = RTCC_POWERDOWN_RAM; +#endif } void RTCC_StatusClear( void ); @@ -682,7 +720,26 @@ __STATIC_INLINE void RTCC_TimeSet( uint32_t time ) ******************************************************************************/ __STATIC_INLINE void RTCC_Unlock( void ) { +#if defined(ERRATA_FIX_RTCC_E203) + /* RTCC_E203 - Potential Stability Issue with RTCC Registers + * RTCC_LOCK register must be modified while RTCC clock is disabled. */ + uint32_t lfeReg = CMU->LFECLKEN0; + bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; + } + CMU->LFECLKEN0 = 0x0; +#endif RTCC->LOCK = RTCC_LOCK_LOCKKEY_UNLOCK; +#if defined(ERRATA_FIX_RTCC_E203) + /* Restore clock state after RTCC_E203 fix. */ + CMU->LFECLKEN0 = lfeReg; + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; + } +#endif } /** @} (end addtogroup RTCC) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h new file mode 100644 index 00000000000..140bc825fdc --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h @@ -0,0 +1,466 @@ +/***************************************************************************//** + * @file em_smu.h + * @brief Security Management Unit (SMU) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#ifndef EM_SMU_H +#define EM_SMU_H + +#include "em_device.h" +#if defined(SMU_COUNT) && (SMU_COUNT > 0) + +#include "em_assert.h" +#include "em_bus.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup SMU + * @brief Security Management Unit (SMU) Peripheral API + * + * @details + * The Security Management Unit (SMU) forms the control and status/reporting + * component of bus-level security in EFM32/EFR32 devices. + * + * Peripheral-level protection is provided via the peripheral protection unit + * (PPU). The PPU provides a hardware access barrier to any peripheral that is + * configured to be protected. When an attempt is made to access a peripheral + * without the required privilege/security level, the PPU detects the fault + * and intercepts the access. No write or read of the peripheral register + * space occurs, and an all-zero value is returned if the access is a read. + * + * @subsection Usage example + * @include em_smu_init.c + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** SMU peripheral identifiers. */ +typedef enum { + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */ + smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1 */ + smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2 */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */ + +#else +#error "No peripherals defined for SMU for this device configuration." +#endif + smuPeripheralEnd +} SMU_Peripheral_TypeDef; + +/** SMU peripheral privileged access enablers. */ +typedef struct { + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1 */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1 */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2 */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1 */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedReserved9 : 1; /**< Reserved privileged access enabler */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */ + +#else +#error "No peripherals defined for SMU for this device configuration" +#endif +} SMU_PrivilegedAccess_TypeDef; + +/******************************************************************************* + ****************************** STRUCTS ************************************ + ******************************************************************************/ + +/** SMU initialization structure. */ +typedef struct { + union { + uint32_t reg[2]; /**< Periperal access control array.*/ + SMU_PrivilegedAccess_TypeDef access; /**< Periperal access control array.*/ + } ppu; + bool enable; /**< SMU enable flag, when set SMU_Init() will enable SMU.*/ +} SMU_Init_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID > 80) +/** Default SMU initialization struct settings. */ +#define SMU_INIT_DEFAULT { \ + {{0}}, /* No peripherals acsess protected. */ \ + true /* Enable SMU.*/ \ +} +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable or disable the Peripheral Protection Unit of the SMU. + * + * @param[in] enable + * True if the PPU should be enabled, false if it should be disabled. + ******************************************************************************/ +__STATIC_INLINE void SMU_EnablePPU(bool enable) +{ + BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable); +} + +/***************************************************************************//** + * @brief + * Initialize the Peripheral Protection Unit of the SMU. + * + * @param[in] init + * Pointer to initialization struct defining which peripherals should only + * be accessed from privileged mode, and whether the PPU should be enabled. + ******************************************************************************/ +__STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init) +{ + SMU->PPUPATD0 = init->ppu.reg[0]; + SMU->PPUPATD1 = init->ppu.reg[1]; + + SMU_EnablePPU(init->enable); +} + +/***************************************************************************//** + * @brief + * Change the access settings for a peripheral + * + * @details + * Set whether the peripheral can only be accessed from privileged mode + * + * @param[in] peripheral + * ID of the peripheral to change access settings for + * + * @param[in] privileged + * True if the peripheral should only be allowed to be accessed from + * privileged mode, false if the peripheral can be accessed from unprivileged + * mode. + ******************************************************************************/ +__STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral, + bool privileged) +{ + EFM_ASSERT(peripheral < smuPeripheralEnd); + + if (peripheral < 32) { + BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged); + } else { + BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged); + } +} + +/***************************************************************************//** + * @brief + * Get the ID of the peripheral that caused an access fault. + * + * @note + * The return value is only valid if the @ref SMU_IF_PPUPRIV interrupt flag + * is set. + * + * @return + * ID of the faulting peripheral. + ******************************************************************************/ +__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void) +{ + return (SMU_Peripheral_TypeDef)SMU->PPUFS; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending SMU interrupts. + * + * @param[in] flags + * Bitwise logic OR of SMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntClear(uint32_t flags) +{ + SMU->IFC = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more SMU interrupts. + * + * @param[in] flags + * SMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntDisable(uint32_t flags) +{ + SMU->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more SMU interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using SMU_IntClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] flags + * SMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntEnable(uint32_t flags) +{ + SMU->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending SMU interrupts. + * + * @return + * SMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGet(void) +{ + return SMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending SMU interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled SMU interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in SMU_IEN register + * and + * - the OR combination of valid interrupt flags in SMU_IF register. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGetEnabled(void) +{ + uint32_t tmp; + + // Store SMU->IEN in temporary variable in order to define explicit order + // of volatile accesses. + tmp = SMU->IEN; + + // Bitwise AND of pending and enabled interrupts + return SMU->IF & tmp; +} + +/************************************************************************Æ**//** + * @brief + * Set one or more pending SMU interrupts from SW. + * + * @param[in] flags + * SMU interrupt sources to set to pending. + *************************************************************************Æ****/ +__STATIC_INLINE void SMU_IntSet(uint32_t flags) +{ + SMU->IFS = flags; +} + +/** @} (end addtogroup SMU) */ +/** @} (end addtogroup emlib) */ + +#ifdef __cplusplus +} +#endif + +#endif // defined(SMU_COUNT) && (SMU_COUNT > 0) +#endif // EM_SMU_H diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h index 34810a81c03..84d2049eddb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_system.h * @brief System API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -86,10 +86,22 @@ typedef enum systemPartFamilyEfm32Happy = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG, /**< EFM32 Happy Gecko Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B) - systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Gen1 Basic Device Family */ + systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B) - systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Gen1 Basic Device Family */ + systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Series 1 Config 1 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B) + systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Config 2 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B) + systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Config 2 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B) + systemPartFamilyEfm32Pearl13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B, /**< EFM32 Pearl Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B) + systemPartFamilyEfm32Jade13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B, /**< EFM32 Jade Gecko Series 1 Config 3 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG) systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family */ @@ -101,78 +113,89 @@ typedef enum systemPartFamilyEzr32Happy = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG, /**< EZR32 Happy Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P) - systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Gen1 Premium Device Family */ + systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Series 1 Config 1 Premium Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B) - systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Gen1 Basic Device Family */ + systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V) - systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Gen1 Value Device Family */ + systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Series 1 Config 1 Value Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P) - systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Gen1 Premium Device Family */ + systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Series 1 Config 1 Premium Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B) - systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Gen1 Basic Device Family */ + systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V) - systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Gen1 Value Device Family */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P) - systemPartFamilyZappy1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P, /**< EFR32 Zappy Gecko Gen1 Premium Device Family */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B) - systemPartFamilyZappy1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B, /**< EFR32 Zappy Gecko Gen1 Basic Device Family */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V) - systemPartFamilyZappy1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V, /**< EFR32 Zappy Gecko Gen1 Value Device Family */ + systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Series 1 Config 1 Value Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P) - systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Gen1 Premium Device Family */ + systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Series 1 Config 1 Premium Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B) - systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Gen1 Basic Device Family */ + systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V) - systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Gen1 Value Device Family */ + systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Series 1 Config 1 Value Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P) - systemPartFamilyMighty2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P, /**< EFR32 Mighty Gecko Gen2 Premium Device Family */ + systemPartFamilyMighty2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P, /**< EFR32 Mighty Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2B) - systemPartFamilyMighty2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2B, /**< EFR32 Mighty Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P) + systemPartFamilyMighty12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P, /**< EFR32 Mighty Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2V) - systemPartFamilyMighty2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2V, /**< EFR32 Mighty Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B) + systemPartFamilyMighty12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B, /**< EFR32 Mighty Gecko Series 1 Config 2 Basic Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG2P) - systemPartFamilyBlue2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG2P, /**< EFR32 Blue Gecko Gen2 Premium Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V) + systemPartFamilyMighty12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V, /**< EFR32 Mighty Gecko Series 1 Config 2 Value Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG2B) - systemPartFamilyBlue2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG2B, /**< EFR32 Blue Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P) + systemPartFamilyBlue12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P, /**< EFR32 Blue Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG2V) - systemPartFamilyBlue2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG2V, /**< EFR32 Blue Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B) + systemPartFamilyBlue12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B, /**< EFR32 Blue Gecko Series 1 Config 2 Basic Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2P) - systemPartFamilyZappy2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2P, /**< EFR32 Zappy Gecko Gen2 Premium Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V) + systemPartFamilyBlue12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V, /**< EFR32 Blue Gecko Series 1 Config 2 Value Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2B) - systemPartFamilyZappy2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2B, /**< EFR32 Zappy Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P) + systemPartFamilyFlex12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P, /**< EFR32 Flex Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2V) - systemPartFamilyZappy2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2V, /**< EFR32 Zappy Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B) + systemPartFamilyFlex12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B, /**< EFR32 Flex Gecko Series 1 Config 2 Basic Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG2P) - systemPartFamilyFlex2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG2P, /**< EFR32 Flex Gecko Gen2 Premium Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V) + systemPartFamilyFlex12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V, /**< EFR32 Flex Gecko Series 1 Config 2 Value Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG2B) - systemPartFamilyFlex2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG2B, /**< EFR32 Flex Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P) + systemPartFamilyMighty13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P, /**< EFR32 Mighty Gecko Series 1 Config 3 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG2V) - systemPartFamilyFlex2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG2V, /**< EFR32 Flex Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B) + systemPartFamilyMighty13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B, /**< EFR32 Mighty Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V) + systemPartFamilyMighty13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V, /**< EFR32 Mighty Gecko Series 1 Config 3 Value Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P) + systemPartFamilyBlue13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P, /**< EFR32 Blue Gecko Series 1 Config 3 Premium Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B) + systemPartFamilyBlue13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B, /**< EFR32 Blue Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V) + systemPartFamilyBlue13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V, /**< EFR32 Blue Gecko Series 1 Config 3 Value Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P) + systemPartFamilyFlex13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P, /**< EFR32 Flex Gecko Series 1 Config 3 Premium Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B) + systemPartFamilyFlex13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B, /**< EFR32 Flex Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V) + systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Config 3 Value Device Family */ #endif - @@ -290,23 +313,32 @@ __STATIC_INLINE uint8_t SYSTEM_GetProdRev(void) * @note * This function retrievs the correct value by reading the chip device * info structure. If your binary is made for one specific device only, - * the \#define SRAM_SIZE can be used instead. + * @ref SRAM_SIZE can be used instead. * * @return * The size of the internal SRAM (in KB). ******************************************************************************/ __STATIC_INLINE uint16_t SYSTEM_GetSRAMSize(void) { + uint16_t sizekb; + #if defined(_EFM32_GECKO_FAMILY) /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ if (SYSTEM_GetProdRev() < 5) { - return (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) - >> _DEVINFO_MSIZE_FLASH_SHIFT; + sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) + >> _DEVINFO_MSIZE_FLASH_SHIFT; } #endif - return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) - >> _DEVINFO_MSIZE_SRAM_SHIFT; + sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) + >> _DEVINFO_MSIZE_SRAM_SHIFT; + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) + /* Do not include EFR32xG1 RAMH */ + sizekb--; +#endif + + return sizekb; } /***************************************************************************//** @@ -316,7 +348,7 @@ __STATIC_INLINE uint16_t SYSTEM_GetSRAMSize(void) * @note * This function retrievs the correct value by reading the chip device * info structure. If your binary is made for one specific device only, - * the \#define FLASH_SIZE can be used instead. + * @ref FLASH_SIZE can be used instead. * * @return * The size of the internal flash (in KB). @@ -343,7 +375,7 @@ __STATIC_INLINE uint16_t SYSTEM_GetFlashSize(void) * @note * This function retrievs the correct value by reading the chip device * info structure. If your binary is made for one specific device only, - * the \#define FLASH_PAGE_SIZE can be used instead. + * @ref FLASH_PAGE_SIZE can be used instead. * * @return * The page size of the internal flash in bytes. diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h index dce5bbc174d..cc5d48bb634 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_timer.h * @brief Timer/counter (TIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -59,32 +59,16 @@ extern "C" { /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - /** Validation of TIMER register block pointer reference for assert statements. */ -#if (TIMER_COUNT == 1) -#define TIMER_REF_VALID(ref) ((ref) == TIMER0) -#elif (TIMER_COUNT == 2) -#define TIMER_REF_VALID(ref) (((ref) == TIMER0) || ((ref) == TIMER1)) -#elif (TIMER_COUNT == 3) -#define TIMER_REF_VALID(ref) (((ref) == TIMER0) \ - || ((ref) == TIMER1) \ - || ((ref) == TIMER2)) -#elif (TIMER_COUNT == 4) -#define TIMER_REF_VALID(ref) (((ref) == TIMER0) \ - || ((ref) == TIMER1) \ - || ((ref) == TIMER2) \ - || ((ref) == TIMER3)) -#else -#error "Undefined number of timers." -#endif +#define TIMER_REF_VALID(ref) TIMER_Valid(ref) /** Validation of TIMER compare/capture channel number */ -#if defined(_SILICON_LABS_32B_PLATFORM_1) +#if defined(_SILICON_LABS_32B_SERIES_0) #define TIMER_CH_VALID(ch) ((ch) < 3) -#elif defined(_SILICON_LABS_32B_PLATFORM_2) +#elif defined(_SILICON_LABS_32B_SERIES_1) #define TIMER_CH_VALID(ch) ((ch) < 4) #else -#error "Unknown platform. Undefined number of channels." +#error "Unknown device. Undefined number of channels." #endif /** @endcond */ @@ -499,6 +483,66 @@ typedef struct ***************************** PROTOTYPES ********************************** ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Validate the TIMER register block pointer + * + * @param[in] ref + * Pointer to TIMER peripheral register block. + * + * @return + * true if ref points to a valid timer, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref) +{ + return (ref == TIMER0) +#if defined(TIMER1) + || (ref == TIMER1) +#endif +#if defined(TIMER2) + || (ref == TIMER2) +#endif +#if defined(TIMER3) + || (ref == TIMER3) +#endif +#if defined(WTIMER0) + || (ref == WTIMER0) +#endif +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif + ; +} + +/***************************************************************************//** + * @brief + * Get the Max count of the timer + * + * @param[in] timer + * Pointer to TIMER peripheral register block. + * + * @return + * The max count value of the timer. This is 0xFFFF for 16 bit timers + * and 0xFFFFFFFF for 32 bit timers. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref) +{ +#if defined(WTIMER_PRESENT) + if ((ref == WTIMER0) +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif + ) + { + return 0xFFFFFFFFUL; + } +#else + (void) ref; +#endif + return 0xFFFFUL; +} + /***************************************************************************//** * @brief * Get capture value for compare/capture channel when operating in capture @@ -542,6 +586,7 @@ __STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer, unsigned int ch, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->CC[ch].CCVB = val; } @@ -564,6 +609,7 @@ __STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer, unsigned int ch, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->CC[ch].CCV = val; } @@ -596,6 +642,7 @@ __STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer) ******************************************************************************/ __STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->CNT = val; } @@ -867,6 +914,7 @@ void TIMER_Reset(TIMER_TypeDef *timer); ******************************************************************************/ __STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->TOPB = val; } @@ -899,6 +947,7 @@ __STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer) ******************************************************************************/ __STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->TOP = val; } @@ -919,7 +968,6 @@ __STATIC_INLINE void TIMER_Unlock(TIMER_TypeDef *timer) } #endif - /** @} (end addtogroup TIMER) */ /** @} (end addtogroup emlib) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h index b80642c9e4f..ac79f8d18cc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h @@ -2,7 +2,7 @@ * @file em_usart.h * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) * peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -86,7 +86,7 @@ extern "C" { * @if DOXYDOC_P1_DEVICE * @include em_usart_route_p1.c * @note UART hardware flow control is not directly supported in hardware on - * @ref _SILICON_LABS_32B_PLATFORM_1 parts. + * @ref _SILICON_LABS_32B_SERIES_0 parts. * @endif * @if DOXYDOC_P2_DEVICE * @include em_usart_route_p2.c diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h index 66b55c3c859..fdb3e36a2c5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_vcmp.h * @brief Voltage Comparator (VCMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h new file mode 100644 index 00000000000..6997dd2ee34 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h @@ -0,0 +1,420 @@ +/***************************************************************************//** + * @file em_vdac.h + * @brief Digital to Analog Converter (VDAC) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#ifndef EM_VDAC_H +#define EM_VDAC_H + +#include "em_device.h" + +#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) + +#include "em_assert.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup VDAC + * @brief Digital to Analog Voltage Converter (VDAC) Peripheral API + * + * @details + * This module contains functions to control the VDAC peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The VDAC converts digital values to analog + * signals at up to 500 ksps with 12-bit accuracy. The VDAC is designed for + * low energy consumption, but can also provide very good performance. + * + * The following steps are necessary for basic operation: + * + * Clock enable: + * @code + CMU_ClockEnable(cmuClock_VDAC0, true);@endcode + * + * Initialize the VDAC with default settings and modify selected fields: + * @code + VDAC_Init_TypeDef vdacInit = VDAC_INIT_DEFAULT; + VDAC_InitChannel_TypeDef vdacChInit = VDAC_INITCHANNEL_DEFAULT; + + // Set prescaler to get 1 MHz VDAC clock frequency. + vdacInit.prescaler = VDAC_PrescaleCalc(1000000, true, 0); + VDAC_Init(VDAC0, &vdacInit); + + vdacChInit.enable = true; + VDAC_InitChannel(VDAC0, &vdacChInit, 0);@endcode + * + * Perform a conversion: + * @code + VDAC_ChannelOutputSet(VDAC0, 0, 250);@endcode + * + * @note The output stage of a VDAC channel consist of an onchip operational + * amplifier in the OPAMP module. This opamp is highly configurable and to + * exploit the VDAC functionality fully, you might need to configure the opamp + * using the OPAMP API. By using the OPAMP API you will also load opamp + * calibration values. The default (reset) settings of the opamp will be + * sufficient for many applications. + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of VDAC register block pointer reference for assert statements.*/ +#define VDAC_REF_VALID(ref) ((ref) == VDAC0) + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Channel refresh period. */ +typedef enum +{ + vdacRefresh8 = _VDAC_CTRL_REFRESHPERIOD_8CYCLES, /**< Refresh every 8 clock cycles. */ + vdacRefresh16 = _VDAC_CTRL_REFRESHPERIOD_16CYCLES, /**< Refresh every 16 clock cycles. */ + vdacRefresh32 = _VDAC_CTRL_REFRESHPERIOD_32CYCLES, /**< Refresh every 32 clock cycles. */ + vdacRefresh64 = _VDAC_CTRL_REFRESHPERIOD_64CYCLES, /**< Refresh every 64 clock cycles. */ +} VDAC_Refresh_TypeDef; + +/** Reference voltage for VDAC. */ +typedef enum +{ + vdacRef1V25Ln = _VDAC_CTRL_REFSEL_1V25LN, /**< Internal low noise 1.25 V bandgap reference. */ + vdacRef2V5Ln = _VDAC_CTRL_REFSEL_2V5LN, /**< Internal low noise 2.5 V bandgap reference. */ + vdacRef1V25 = _VDAC_CTRL_REFSEL_1V25, /**< Internal 1.25 V bandgap reference. */ + vdacRef2V5 = _VDAC_CTRL_REFSEL_2V5, /**< Internal 2.5 V bandgap reference. */ + vdacRefAvdd = _VDAC_CTRL_REFSEL_VDD, /**< AVDD reference. */ + vdacRefExtPin = _VDAC_CTRL_REFSEL_EXT, /**< External pin reference. */ +} VDAC_Ref_TypeDef; + +/** Peripheral Reflex System signal used to trig VDAC channel conversion. */ +typedef enum +{ + vdacPrsSelCh0 = _VDAC_CH0CTRL_PRSSEL_PRSCH0 , /**< PRS ch 0 triggers conversion. */ + vdacPrsSelCh1 = _VDAC_CH0CTRL_PRSSEL_PRSCH1 , /**< PRS ch 1 triggers conversion. */ + vdacPrsSelCh2 = _VDAC_CH0CTRL_PRSSEL_PRSCH2 , /**< PRS ch 2 triggers conversion. */ + vdacPrsSelCh3 = _VDAC_CH0CTRL_PRSSEL_PRSCH3 , /**< PRS ch 3 triggers conversion. */ + vdacPrsSelCh4 = _VDAC_CH0CTRL_PRSSEL_PRSCH4 , /**< PRS ch 4 triggers conversion. */ + vdacPrsSelCh5 = _VDAC_CH0CTRL_PRSSEL_PRSCH5 , /**< PRS ch 5 triggers conversion. */ + vdacPrsSelCh6 = _VDAC_CH0CTRL_PRSSEL_PRSCH6 , /**< PRS ch 6 triggers conversion. */ + vdacPrsSelCh7 = _VDAC_CH0CTRL_PRSSEL_PRSCH7 , /**< PRS ch 7 triggers conversion. */ + vdacPrsSelCh8 = _VDAC_CH0CTRL_PRSSEL_PRSCH8 , /**< PRS ch 8 triggers conversion. */ + vdacPrsSelCh9 = _VDAC_CH0CTRL_PRSSEL_PRSCH9 , /**< PRS ch 9 triggers conversion. */ + vdacPrsSelCh10 = _VDAC_CH0CTRL_PRSSEL_PRSCH10, /**< PRS ch 10 triggers conversion. */ + vdacPrsSelCh11 = _VDAC_CH0CTRL_PRSSEL_PRSCH11, /**< PRS ch 11 triggers conversion. */ +} VDAC_PrsSel_TypeDef; + +/** Channel conversion trigger mode. */ +typedef enum +{ + vdacTrigModeSw = _VDAC_CH0CTRL_TRIGMODE_SW, /**< Channel is triggered by CHnDATA or COMBDATA write. */ + vdacTrigModePrs = _VDAC_CH0CTRL_TRIGMODE_PRS, /**< Channel is triggered by PRS input. */ + vdacTrigModeRefresh = _VDAC_CH0CTRL_TRIGMODE_REFRESH, /**< Channel is triggered by Refresh timer. */ + vdacTrigModeSwPrs = _VDAC_CH0CTRL_TRIGMODE_SWPRS, /**< Channel is triggered by CHnDATA/COMBDATA write or PRS input. */ + vdacTrigModeSwRefresh = _VDAC_CH0CTRL_TRIGMODE_SWREFRESH, /**< Channel is triggered by CHnDATA/COMBDATA write or Refresh timer. */ + vdacTrigModeLesense = _VDAC_CH0CTRL_TRIGMODE_LESENSE, /**< Channel is triggered by LESENSE. */ +} VDAC_TrigMode_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** VDAC init structure, common for both channels. */ +typedef struct +{ + /** Select between main and alternate output path calibration values. */ + bool mainCalibration; + + /** Selects clock from asynchronous or synchronous (with respect to + peripheral clock) source */ + bool asyncClockMode; + + /** Warmup mode, keep VDAC on (in idle) - or shutdown between conversions.*/ + bool warmupKeepOn; + + /** Channel refresh period. */ + VDAC_Refresh_TypeDef refresh; + + /** Prescaler for VDAC clock. Clock is source clock divided by prescaler+1. */ + uint32_t prescaler; + + /** Reference voltage to use. */ + VDAC_Ref_TypeDef reference; + + /** Enable/disable reset of prescaler on CH 0 start. */ + bool ch0ResetPre; + + /** Enable/disable output enable control by CH1 PRS signal. */ + bool outEnablePRS; + + /** Enable/disable sine mode. */ + bool sineEnable; + + /** Select if single ended or differential output mode. */ + bool diff; +} VDAC_Init_TypeDef; + +/** Default config for VDAC init structure. */ +#define VDAC_INIT_DEFAULT \ +{ \ + true, /* Use main output path calibration values. */ \ + false, /* Use synchronous clock mode. */ \ + false, /* Turn off between sample off conversions.*/ \ + vdacRefresh8, /* Refresh every 8th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25Ln, /* 1.25V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* VDAC output enable always on. */ \ + false, /* Disable sine mode. */ \ + false /* Single ended mode. */ \ +} + +/** VDAC channel init structure. */ +typedef struct +{ + /** Enable channel. */ + bool enable; + + /** + * Peripheral reflex system trigger selection. Only applicable if @p trigMode + * is set to @p vdacTrigModePrs or @p vdacTrigModeSwPrs. */ + VDAC_PrsSel_TypeDef prsSel; + + /** Treat the PRS signal asynchronously. */ + bool prsAsync; + + /** Channel conversion trigger mode. */ + VDAC_TrigMode_TypeDef trigMode; + + /** Set channel conversion mode to sample/shut-off mode. Default is + * continous.*/ + bool sampleOffMode; +} VDAC_InitChannel_TypeDef; + +/** Default config for VDAC channel init structure. */ +#define VDAC_INITCHANNEL_DEFAULT \ +{ \ + false, /* Leave channel disabled when init done. */ \ + vdacPrsSelCh0, /* PRS CH 0 triggers conversion. */ \ + false, /* Treat PRS channel as a synchronous signal. */ \ + vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \ + false, /* Channel conversion set to continous. */ \ +} + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, + unsigned int channel, + uint32_t value); +void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable); +void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init); +void VDAC_InitChannel(VDAC_TypeDef *vdac, + const VDAC_InitChannel_TypeDef *init, + unsigned int ch); + +/***************************************************************************//** + * @brief + * Set the output signal of VDAC channel 0 to a given value. + * + * @details + * This function sets the output signal of VDAC channel 0 by writing @p value + * to the CH0DATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] value + * Value to write to channel 0 output register CH0DATA. + ******************************************************************************/ +__STATIC_INLINE void VDAC_Channel0OutputSet(VDAC_TypeDef *vdac, + uint32_t value) +{ + EFM_ASSERT(value<=_VDAC_CH0DATA_MASK); + vdac->CH0DATA = value; +} + +/***************************************************************************//** + * @brief + * Set the output signal of VDAC channel 1 to a given value. + * + * @details + * This function sets the output signal of VDAC channel 1 by writing @p value + * to the CH1DATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] value + * Value to write to channel 1 output register CH1DATA. + ******************************************************************************/ +__STATIC_INLINE void VDAC_Channel1OutputSet(VDAC_TypeDef *vdac, + uint32_t value) +{ + EFM_ASSERT(value<=_VDAC_CH1DATA_MASK); + vdac->CH1DATA = value; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending VDAC interrupts. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * Pending VDAC interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntClear(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IFC = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more VDAC interrupts. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntDisable(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more VDAC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using VDAC_IntClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntEnable(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending VDAC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @return + * VDAC interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_IntGet(VDAC_TypeDef *vdac) +{ + return vdac->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending VDAC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled VDAC interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in VDACx_IEN_nnn + * register (VDACx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the VDAC module + * (VDACx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_IntGetEnabled(VDAC_TypeDef *vdac) +{ + uint32_t ien = vdac->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return vdac->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending VDAC interrupts from SW. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to set to pending. Use a bitwise logic OR + * combination of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntSet(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IFS = flags; +} + +uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq); +void VDAC_Reset(VDAC_TypeDef *vdac); + +/** @} (end addtogroup VDAC) */ +/** @} (end addtogroup emlib) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ +#endif /* EM_VDAC_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h index 2ec5de44431..a4e1ca8599e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_version.h * @brief Assign correct part number for include file - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -53,18 +53,18 @@ extern "C" { ******************************************************************************/ /** Version number of emlib peripheral API. */ -#define _EMLIB_VERSION 5.0.0 +#define _EMLIB_VERSION 5.1.2 /** Major version of emlib. Bumped when incompatible API changes introduced. */ #define _EMLIB_VERSION_MAJOR 5 /** Minor version of emlib. Bumped when functionality is added in a backwards- compatible manner. */ -#define _EMLIB_VERSION_MINOR 0 +#define _EMLIB_VERSION_MINOR 1 /** Patch revision of emlib. Bumped when adding backwards-compatible bug fixes.*/ -#define _EMLIB_VERSION_PATCH 0 +#define _EMLIB_VERSION_PATCH 2 /** Version number of targeted CMSIS package. */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h index a554109410a..0e4c4a40f02 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_wdog.h * @brief Watchdog (WDOG) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c index 9a2bb69f361..ac0c9440440 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_acmp.c * @brief Analog Comparator (ACMP) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -230,6 +230,32 @@ void ACMP_Enable(ACMP_TypeDef *acmp) acmp->CTRL |= ACMP_CTRL_EN; } +#if defined(_ACMP_EXTIFCTRL_MASK) +/***************************************************************************//** + * @brief + * Select and enable an external input. + * + * @details + * This is used when an external module needs to take control of the ACMP + * POSSEL field in order to configure the APORT input for the ACMP. Modules + * like LESENSE use this to change the ACMP input during a scan sequence. + * + * @param[in] acmp + * Pointer to ACMP peripheral register block. + * + * @param[in] aport + * This parameter decides which APORT(s) the ACMP will use when it's being + * controlled by an external module. + ******************************************************************************/ +void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport) +{ + acmp->EXTIFCTRL = (aport << _ACMP_EXTIFCTRL_APORTSEL_SHIFT) + | ACMP_EXTIFCTRL_EN; + while (!(acmp->STATUS & ACMP_STATUS_EXTIFACT)) + ; +} +#endif + /***************************************************************************//** * @brief * Reset ACMP to same state as after a HW reset. @@ -351,7 +377,8 @@ void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init) EFM_ASSERT(ACMP_REF_VALID(acmp)); /* Make sure biasprog is within bounds */ - EFM_ASSERT(init->biasProg < 16); + EFM_ASSERT(init->biasProg <= + (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); /* Make sure the ACMP is disable since we might be changing the * ACMP power source */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c index a14f6b821e5..612c5fe494c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_adc.c * @brief Analog to Digital Converter (ADC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -62,7 +62,7 @@ #define ADC_REF_VALID(ref) ((ref) == ADC0) /** Max ADC clock */ -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) #define ADC_MAX_CLOCK 13000000 #else #define ADC_MAX_CLOCK 16000000 @@ -180,7 +180,7 @@ #define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) #define FIX_ADC_TEMP_BIAS_EN #endif /** @endcond */ @@ -418,8 +418,8 @@ void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init) init->em2ClockConfig); #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) - /* Fix for errata ADC_EXXX */ +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) + /* A debugger can trigger the SCANUF interrupt on EFM32xG1 or EFR32xG1 */ ADC_IntClear(adc, ADC_IFC_SCANUF); #endif } @@ -750,9 +750,10 @@ void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init) if (init->rep) { -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) - /* Scan repeat mode does not work on platform 2 as described in errata ADC_EXXX. */ - EFM_ASSERT(false); +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) + /* Scan repeat mode does not work on EFM32JG1, EFM32PG1 or EFR32xG1x devices. + * The errata is called ADC_E211 in the errata document. */ + EFM_ASSERT(false); #endif tmp |= ADC_SCANCTRL_REP; } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c index 10c302527d1..715535ceee7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_aes.c * @brief Advanced Encryption Standard (AES) accelerator peripheral API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c index 9050c63a81e..b9bd09a8996 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_assert.c * @brief Assert API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c index 018761e4bf0..a81a4446b2d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_burtc.c * @brief Backup Real Time Counter (BURTC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c index 5b878b892de..dba72ff21f0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cmu.c * @brief Clock management unit (CMU) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -37,6 +37,7 @@ #include "em_assert.h" #include "em_bus.h" #include "em_emu.h" +#include "em_cmu.h" #include "em_system.h" #include "em_common.h" @@ -60,12 +61,12 @@ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /** Maximum allowed core frequency when using 0 wait-states on flash access. */ #define CMU_MAX_FREQ_0WS 26000000 /** Maximum allowed core frequency when using 1 wait-states on flash access */ #define CMU_MAX_FREQ_1WS 40000000 -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) /** Maximum allowed core frequency when using 0 wait-states on flash access. */ #define CMU_MAX_FREQ_0WS 16000000 /** Maximum allowed core frequency when using 1 wait-states on flash access */ @@ -76,19 +77,21 @@ /** Maximum frequency for HFLE interface */ #if defined( CMU_CTRL_HFLE ) -/** Maximum HFLE frequency for EFM32 and EZR32 Wonder Gecko. */ -#if defined( _EFM32_WONDER_FAMILY ) \ - || defined( _EZR32_WONDER_FAMILY ) +/** Maximum HFLE frequency for series 0 EFM32 and EZR32 Wonder Gecko. */ +#if defined( _SILICON_LABS_32B_SERIES_0 ) \ + && (defined( _EFM32_WONDER_FAMILY ) \ + || defined( _EZR32_WONDER_FAMILY )) #define CMU_MAX_FREQ_HFLE 24000000 -/** Maximum HFLE frequency for other platform 1 parts with maximum core clock +/** Maximum HFLE frequency for other series 0 parts with maximum core clock higher than 32MHz. */ -#elif defined( _EFM32_GIANT_FAMILY ) \ - || defined( _EFM32_LEOPARD_FAMILY ) \ - || defined( _EZR32_LEOPARD_FAMILY ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) \ + && (defined( _EFM32_GIANT_FAMILY ) \ + || defined( _EFM32_LEOPARD_FAMILY ) \ + || defined( _EZR32_LEOPARD_FAMILY )) #define CMU_MAX_FREQ_HFLE maxFreqHfle() #endif #elif defined( CMU_CTRL_WSHFLE ) -/** Maximum HFLE frequency for platform 2 parts */ +/** Maximum HFLE frequency for series 1 parts */ #define CMU_MAX_FREQ_HFLE 32000000 #endif @@ -112,9 +115,10 @@ static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz; /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined( _EFM32_GIANT_FAMILY ) \ - || defined( _EFM32_LEOPARD_FAMILY ) \ - || defined( _EZR32_LEOPARD_FAMILY ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) \ + && (defined( _EFM32_GIANT_FAMILY ) \ + || defined( _EFM32_LEOPARD_FAMILY ) \ + || defined( _EZR32_LEOPARD_FAMILY )) /***************************************************************************//** * @brief * Return max allowed frequency for low energy peripherals. @@ -235,7 +239,7 @@ static uint32_t auxClkGet(void) ret = auxHfrcoFreq; #elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK ) - /* All platform 1 families except EFM32G */ + /* All series 0 families except EFM32G */ switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) { case CMU_AUXHFRCOCTRL_BAND_1MHZ: @@ -585,6 +589,12 @@ static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch) ret = SystemULFRCOClockGet(); break; +#if defined( CMU_LFACLKSEL_LFA_PLFRCO ) + case _CMU_LFACLKSEL_LFA_PLFRCO: + ret = SystemLFRCOClockGet(); + break; +#endif + #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE ) case _CMU_LFACLKSEL_LFA_HFCLKLE: ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) @@ -1101,10 +1111,10 @@ uint32_t CMU_CalibrateCountGet(void) ******************************************************************************/ CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) { -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) return 1 + (uint32_t)CMU_ClockPrescGet(clock); -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) uint32_t divReg; CMU_ClkDiv_TypeDef ret; @@ -1233,10 +1243,10 @@ CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) ******************************************************************************/ void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) { -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1)); -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) uint32_t freq; uint32_t divReg; @@ -1560,7 +1570,7 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #endif break; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) #if defined( CRYPTO_PRESENT ) \ || defined( LDMA_PRESENT ) \ || defined( GPCRC_PRESENT ) \ @@ -1584,7 +1594,7 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) break; #endif -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) #if defined( AES_PRESENT ) \ || defined( DMA_PRESENT ) \ || defined( EBI_PRESENT ) \ @@ -1617,10 +1627,10 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #if defined( _CMU_LFACLKEN0_LETIMER0_MASK ) case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFA); -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >> _CMU_LFAPRESC0_LETIMER0_SHIFT; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >> _CMU_LFAPRESC0_LETIMER0_SHIFT); #endif @@ -1659,10 +1669,10 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #if defined( _CMU_LFBCLKEN0_LEUART0_MASK ) case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFB); -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >> _CMU_LFBPRESC0_LEUART0_SHIFT; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >> _CMU_LFBPRESC0_LEUART0_SHIFT); #endif @@ -1672,17 +1682,25 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #if defined( _CMU_LFBCLKEN0_LEUART1_MASK ) case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFB); -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >> _CMU_LFBPRESC0_LEUART1_SHIFT; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >> _CMU_LFBPRESC0_LEUART1_SHIFT); #endif break; #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _CMU_LFBCLKEN0_CSEN_MASK ) + case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); + ret /= CMU_Log2ToDiv(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT) + 4); + break; +#endif + +#if defined( _SILICON_LABS_32B_SERIES_1 ) case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFE); break; @@ -1712,7 +1730,7 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) } -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /***************************************************************************//** * @brief * Get clock prescaler. @@ -1809,6 +1827,15 @@ uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) break; #endif +#if defined( _CMU_LFBPRESC0_CSEN_MASK ) + case cmuClock_CSEN_LF: + ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT)); + /* Convert the exponent to prescaler value. */ + ret = CMU_Log2ToDiv(ret + 4) - 1U; + break; +#endif + default: EFM_ASSERT(0); ret = 0U; @@ -1845,7 +1872,7 @@ uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /***************************************************************************//** * @brief * Set clock prescaler. @@ -2044,6 +2071,22 @@ void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) break; #endif +#if defined( _CMU_LFBPRESC0_CSEN_MASK ) + case cmuClock_CSEN_LF: + EFM_ASSERT((presc <= 127U) && (presc >= 15U)); + + /* Convert prescaler value to DIV exponent scale. + * DIV16 is the lowest supported prescaler. */ + presc = CMU_PrescToLog2(presc) - 4; + + /* LF register about to be modified require sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK) + | (presc << _CMU_LFBPRESC0_CSEN_SHIFT); + break; +#endif + default: EFM_ASSERT(0); break; @@ -2089,7 +2132,7 @@ void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) * @li #cmuClock_LFA * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO * @li #cmuClock_LFC - * @endif @if _SILICON_LABS_32B_PLATFORM_2 + * @endif @if _SILICON_LABS_32B_SERIES_1 * @li #cmuClock_LFE * @endif * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT @@ -2217,6 +2260,12 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) break; #endif +#if defined( CMU_LFACLKSEL_LFA_PLFRCO ) + case CMU_LFACLKSEL_LFA_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + default: ret = cmuSelect_Disabled; break; @@ -2282,6 +2331,12 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) ret = cmuSelect_HFCLKLE; break; +#if defined( CMU_LFBCLKSEL_LFB_PLFRCO ) + case CMU_LFBCLKSEL_LFB_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + default: ret = cmuSelect_Disabled; break; @@ -2331,6 +2386,12 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) break; #endif +#if defined( CMU_LFECLKSEL_LFE_PLFRCO ) + case CMU_LFECLKSEL_LFE_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + default: ret = cmuSelect_Disabled; break; @@ -2436,7 +2497,7 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) * @li #cmuClock_LFA * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO * @li #cmuClock_LFC - * @endif @if _SILICON_LABS_32B_PLATFORM_2 + * @endif @if _SILICON_LABS_32B_SERIES_1 * @li #cmuClock_LFE * @endif * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT @@ -2454,20 +2515,43 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) * @li #cmuSelect_AUXHFRCO * @li #cmuSelect_HFCLK @ifnot DOXYDOC_EFM32_GECKO_FAMILY * @li #cmuSelect_ULFRCO + * @li #cmuSelect_PLFRCO * @endif ******************************************************************************/ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) { - uint32_t select = cmuOsc_HFRCO; - CMU_Osc_TypeDef osc = cmuOsc_HFRCO; - uint32_t freq; - uint32_t tmp; - uint32_t selRegId; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) - volatile uint32_t *selReg = NULL; + uint32_t select = cmuOsc_HFRCO; + CMU_Osc_TypeDef osc = cmuOsc_HFRCO; + uint32_t freq; + uint32_t tmp; + uint32_t selRegId; +#if defined( _SILICON_LABS_32B_SERIES_1 ) + volatile uint32_t *selReg = NULL; #endif #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) - uint32_t lfExtended = 0; + uint32_t lfExtended = 0; +#endif + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + uint32_t vScaleFrequency = 0; /* Use default */ + + /* Start voltage upscaling before clock is set. */ + if (clock == cmuClock_HF) + { + if (ref == cmuSelect_HFXO) + { + vScaleFrequency = SystemHFXOClockGet(); + } + else if ((ref == cmuSelect_HFRCO) + && (CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) + { + vScaleFrequency = CMU_HFRCOBandGet(); + } + if (vScaleFrequency != 0) + { + EMU_VScaleEM01ByClock(vScaleFrequency, false); + } + } #endif selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; @@ -2478,18 +2562,18 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) switch (ref) { case cmuSelect_LFXO: -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) select = CMU_HFCLKSEL_HF_LFXO; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) select = CMU_CMD_HFCLKSEL_LFXO; #endif osc = cmuOsc_LFXO; break; case cmuSelect_LFRCO: -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) select = CMU_HFCLKSEL_HF_LFRCO; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) select = CMU_CMD_HFCLKSEL_LFRCO; #endif osc = cmuOsc_LFRCO; @@ -2523,9 +2607,9 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) break; case cmuSelect_HFRCO: -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) select = CMU_HFCLKSEL_HF_HFRCO; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) select = CMU_CMD_HFCLKSEL_HFRCO; #endif osc = cmuOsc_HFRCO; @@ -2561,6 +2645,14 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) /* Configure worst case wait states for flash access before selecting */ flashWaitStateMax(); +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Wait for voltage upscaling to complete before clock is set. */ + if (vScaleFrequency != 0) + { + EMU_VScaleWait(); + } +#endif + /* Switch to selected oscillator */ #if defined( _CMU_HFCLKSEL_MASK ) CMU->HFCLKSEL = select; @@ -2573,18 +2665,24 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE); #endif - /* Keep EMU module informed */ - EMU_UpdateOscConfig(); - /* Update CMSIS core clock variable */ /* (The function will update the global variable) */ freq = SystemCoreClockGet(); /* Optimize flash access wait state setting for currently selected core clk */ flashWaitStateControl(freq); + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Keep EMU module informed on source HF clock frequency. This will apply voltage + downscaling after clock is set if downscaling is configured. */ + if (vScaleFrequency == 0) + { + EMU_VScaleEM01ByClock(0, true); + } +#endif break; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) case CMU_LFACLKSEL_REG: selReg = (selReg == NULL) ? &CMU->LFACLKSEL : selReg; #if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE ) @@ -2633,6 +2731,14 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) tmp = _CMU_LFACLKSEL_LFA_ULFRCO; break; +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + case cmuSelect_PLFRCO: + /* Ensure selected oscillator is enabled, waiting for it to stabilize */ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); + tmp = _CMU_LFACLKSEL_LFA_PLFRCO; + break; +#endif + default: EFM_ASSERT(0); return; @@ -2640,7 +2746,7 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) *selReg = tmp; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) case CMU_LFACLKSEL_REG: case CMU_LFBCLKSEL_REG: switch (ref) @@ -3154,6 +3260,11 @@ void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq) /* Reduce HFLE frequency if possible. */ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE); + + /* Update voltage scaling */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + EMU_VScaleEM01ByClock(0, true); +#endif } #endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */ @@ -3238,15 +3349,17 @@ void CMU_HFXOAutostartEnable(uint32_t userSel, | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0) | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0); - CMU->HFXOCTRL = hfxoCtrl; - /* Set wait-states for HFXO if automatic start and select is configured. */ if (userSel || enEM0EM1StartSel) { hfxoFreq = SystemHFXOClockGet(); flashWaitStateControl(hfxoFreq); - setHfLeConfig(hfxoFreq, CMU_MAX_FREQ_HFLE); + setHfLeConfig(hfxoFreq, CMU_MAX_FREQ_HFLE); } + + /* Update HFXOCTRL after wait-states are updated as HF may automatically switch + to HFXO when automatic select is enabled . */ + CMU->HFXOCTRL = hfxoCtrl; } #endif @@ -3268,6 +3381,11 @@ void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) /* Do not disable HFXO if it is currently selected as HF/Core clock */ EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO); + /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */ +#if defined( _EMU_PWRCTRL_REGPWRSEL_MASK ) + EFM_ASSERT(EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD); +#endif + /* HFXO must be disabled before reconfiguration */ CMU_OscillatorEnable(cmuOsc_HFXO, false, true); @@ -3476,7 +3594,7 @@ void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) { uint32_t rdyBitPos; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) uint32_t ensBitPos; #endif #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK ) @@ -3492,7 +3610,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_HFRCOEN; disBit = CMU_OSCENCMD_HFRCODIS; rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT; #endif break; @@ -3501,7 +3619,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_HFXOEN; disBit = CMU_OSCENCMD_HFXODIS; rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_HFXOENS_SHIFT; #endif break; @@ -3510,7 +3628,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_AUXHFRCOEN; disBit = CMU_OSCENCMD_AUXHFRCODIS; rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT; #endif break; @@ -3519,7 +3637,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_LFRCOEN; disBit = CMU_OSCENCMD_LFRCODIS; rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT; #endif break; @@ -3528,7 +3646,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_LFXOEN; disBit = CMU_OSCENCMD_LFXODIS; rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_LFXOENS_SHIFT; #endif break; @@ -3538,12 +3656,21 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_USHFRCOEN; disBit = CMU_OSCENCMD_USHFRCODIS; rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT; #endif break; #endif +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + case cmuOsc_PLFRCO: + enBit = CMU_OSCENCMD_PLFRCOEN; + disBit = CMU_OSCENCMD_PLFRCODIS; + rdyBitPos = _CMU_STATUS_PLFRCORDY_SHIFT; + ensBitPos = _CMU_STATUS_PLFRCOENS_SHIFT; + break; +#endif + default: /* Undefined clock source or cmuOsc_ULFRCO. ULFRCO is always enabled, and cannot be disabled. Ie. the definition of cmuOsc_ULFRCO is primarely @@ -3576,7 +3703,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) #endif CMU->OSCENCMD = enBit; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /* Always wait for ENS to go high */ while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos)) { @@ -3618,16 +3745,13 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) { CMU->OSCENCMD = disBit; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /* Always wait for ENS to go low */ while (BUS_RegBitRead(&CMU->STATUS, ensBitPos)) { } #endif } - - /* Keep EMU module informed */ - EMU_UpdateOscConfig(); } @@ -3715,7 +3839,7 @@ void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT)); #endif CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) @@ -3726,7 +3850,7 @@ void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT)) { } @@ -3739,7 +3863,7 @@ void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT)) { } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c index 90283edf827..8f1895e8448 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_core.c * @brief Core interrupt handling API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -63,11 +63,13 @@ blocking capabilities. @li CRITICAL section: Inside a critical sections all interrupts are - disabled (except for fault handlers). The PRIMASK register is used for + disabled (except for fault handlers). The PRIMASK register is always used for interrupt disable/enable. - @li ATOMIC section: Interrupts with priority equal to or lower than a - given level are disabled. The interrupt disable priority level is defined - at compile time. The BASEPRI register is used for interrupt disable/enable. + @li ATOMIC section: This type of section is configurable and the default + method is to use PRIMASK. With BASEPRI configuration, interrupts with priority + equal to or lower than a given configurable level are disabled. The interrupt + disable priority level is defined at compile time. The BASEPRI register is not + available for all architectures. @li NVIC mask section: Disable NVIC (external interrupts) on an individual manner. @@ -535,7 +537,7 @@ void CORE_NvicDisableMask(const CORE_nvicMask_t *disable) /***************************************************************************//** * @brief - * Get current NVIC interrupt enable mask. + * Set current NVIC interrupt enable mask. * * @param[out] enable * Mask specifying which NVIC interrupts are currently enabled. @@ -556,7 +558,7 @@ void CORE_NvicEnableMask(const CORE_nvicMask_t *enable) * Mask specifying which NVIC interrupts to briefly enable. * * @note - * Usully used within a NVIC mask section. + * Usually used within a NVIC mask section. ******************************************************************************/ void CORE_YieldNvicMask(const CORE_nvicMask_t *enable) { diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c index 7a4b67acdb8..871a0b8641e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cryotimer.c * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c index fd6b29a44c6..d3c526abc6b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_crypto.c * @brief Cryptography accelerator peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -1139,12 +1139,13 @@ void CRYPTO_AES_DecryptKey128(CRYPTO_TypeDef * crypto, uint32_t * _out = (uint32_t *) out; const uint32_t * _in = (const uint32_t *) in; + /* Setup CRYPTO in AES-128 mode. */ + crypto->CTRL = CRYPTO_CTRL_AES_AES128; + /* Load key */ CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[0]); /* Do dummy encryption to generate decrypt key */ - crypto->CTRL = CRYPTO_CTRL_AES_AES128; - CRYPTO_IntClear(crypto, CRYPTO_IF_INSTRDONE); crypto->CMD = CRYPTO_CMD_INSTR_AESENC; /* Save decryption key */ @@ -1176,12 +1177,14 @@ void CRYPTO_AES_DecryptKey256(CRYPTO_TypeDef * crypto, uint32_t * _out = (uint32_t *) out; const uint32_t * _in = (const uint32_t *) in; + /* Setup CRYPTO in AES-256 mode. */ + crypto->CTRL = CRYPTO_CTRL_AES_AES256; + /* Load key */ CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[0]); CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[4]); /* Do dummy encryption to generate decrypt key */ - crypto->CTRL = CRYPTO_CTRL_AES_AES256; crypto->CMD = CRYPTO_CMD_INSTR_AESENC; /* Save decryption key */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c new file mode 100644 index 00000000000..331fa724e59 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c @@ -0,0 +1,294 @@ +/***************************************************************************//** + * @file em_csen.c + * @brief Capacitive Sense Module (CSEN) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#include "em_csen.h" +#if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 ) + +#include "em_assert.h" +#include "em_cmu.h" +#include + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup CSEN + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of CSEN register block pointer reference for assert statements. */ +#define CSEN_REF_VALID(ref) ((ref) == CSEN) + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Set the DM integrator initial value. + * + * @details + * Sets the initial value of the integrator(s) for the Delta Modulation (DM) + * converter. The initial value for the ramp-down integrator has no effect + * if low frequency attenuation was not selected by the mode initialization + * function @ref CSEN_InitMode(). + * + * @note + * Confirm CSEN is idle before calling this function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] up + * Initial value for the ramp-up integrator. + * + * @param[in] down + * Initial value for the ramp-down integrator. Has no effect if low frequency + * attenuation is not configured. + ******************************************************************************/ +void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down) +{ + EFM_ASSERT(up < 0x10000); + EFM_ASSERT(down < 0x10000); + + csen->DMBASELINE = (up << _CSEN_DMBASELINE_BASELINEUP_SHIFT) + | (down << _CSEN_DMBASELINE_BASELINEDN_SHIFT); +} + + +/***************************************************************************//** + * @brief + * Initialize CSEN. + * + * @details + * Initializes common functionality for all measurement types. In addition, + * measurement mode must be configured, please refer to @ref CSEN_InitMode(). + * + * @note + * This function will stop any ongoing conversion and disable CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] init + * Pointer to CSEN initialization structure. + ******************************************************************************/ +void CSEN_Init(CSEN_TypeDef *csen, const CSEN_Init_TypeDef *init) +{ + uint32_t tmp; + + EFM_ASSERT(CSEN_REF_VALID(csen)); + EFM_ASSERT(init->warmUpCount < 4); + + /* Initialize CTRL. This will stop any conversion in progress. */ + tmp = CSEN_CTRL_STM_DEFAULT; + + if (init->cpAccuracyHi) + { + tmp |= CSEN_CTRL_CPACCURACY_HI; + } + + if (init->localSense) + { + tmp |= _CSEN_CTRL_LOCALSENS_MASK; + } + + if (init->keepWarm) + { + tmp |= CSEN_CTRL_WARMUPMODE_KEEPCSENWARM; + } + + csen->CTRL = tmp; + + /* Initialize TIMCTRL. */ + csen->TIMCTRL = (init->warmUpCount << _CSEN_TIMCTRL_WARMUPCNT_SHIFT) + | (init->pcReload << _CSEN_TIMCTRL_PCTOP_SHIFT) + | (init->pcPrescale << _CSEN_TIMCTRL_PCPRESC_SHIFT); + + /* PRSSEL only has one field */ + csen->PRSSEL = init->prsSel << _CSEN_PRSSEL_PRSSEL_SHIFT; + + /* Set input selections for inputs 0 to 31 */ + csen->SCANINPUTSEL0 = (init->input0To7 << _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT) + | (init->input8To15 << _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT) + | (init->input16To23 << _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT) + | (init->input24To31 << _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT); + + /* Set input selections for inputs 32 to 63 */ + csen->SCANINPUTSEL1 = (init->input32To39 << _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT) + | (init->input40To47 << _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT) + | (init->input48To55 << _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT) + | (init->input56To63 << _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT); +} + + +/***************************************************************************//** + * @brief + * Initialize a CSEN measurement mode. + * + * @details + * Used to configure any type of measurement mode. After the measurement + * has been configured, calling @ref CSEN_Enable() will enable CSEN and + * allow it to start a conversion from the selected trigger source. To + * manually start a conversion use @ref CSEN_Start(). To check if a + * conversion is in progress use @ref CSEN_IsBusy(), or alternatively + * use the interrupt flags returned by @ref CSEN_IntGet() to detect when + * a conversion is completed. + * + * @note + * This function will stop any ongoing conversion and disable CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] init + * Pointer to CSEN measurement mode initialization structure. + ******************************************************************************/ +void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init) +{ + uint32_t tmp; + + EFM_ASSERT(CSEN_REF_VALID(csen)); + EFM_ASSERT(init->dmIterPerCycle < 0x10); + EFM_ASSERT(init->dmCycles < 0x10); + + /* Initialize CTRL. This will stop any conversion in progress. + * These composite inputs set multiple fields. They do not need + * to be shifted. */ + tmp = ((uint32_t)init->sampleMode + | (uint32_t)init->convSel + | (uint32_t)init->cmpMode); + + tmp |= (init->trigSel << _CSEN_CTRL_STM_SHIFT) + | (init->accMode << _CSEN_CTRL_ACU_SHIFT) + | (init->sarRes << _CSEN_CTRL_SARCR_SHIFT); + + if (init->enableDma) + { + tmp |= CSEN_CTRL_DMAEN_ENABLE; + } + + if (init->sumOnly) + { + tmp |= CSEN_CTRL_DRSF_ENABLE; + } + + if (init->autoGnd) + { + tmp |= CSEN_CTRL_AUTOGND_ENABLE; + } + + /* Preserve the fields that were initialized by CSEN_Init(). */ + tmp |= csen->CTRL & (_CSEN_CTRL_CPACCURACY_MASK + | _CSEN_CTRL_LOCALSENS_MASK + | _CSEN_CTRL_WARMUPMODE_MASK); + + csen->CTRL = tmp; + + /* EMACTRL only has one field */ + csen->EMACTRL = init->emaSample << _CSEN_EMACTRL_EMASAMPLE_SHIFT; + + /* CMPTHR only has one field */ + csen->CMPTHR = init->cmpThr << _CSEN_CMPTHR_CMPTHR_SHIFT; + + /* SINGLECTRL only has one field */ + csen->SINGLECTRL = init->singleSel << _CSEN_SINGLECTRL_SINGLESEL_SHIFT; + + /* Set all input enables */ + csen->SCANMASK0 = init->inputMask0; + csen->SCANMASK1 = init->inputMask1; + + /* Initialize DMCFG. */ + tmp = (init->dmRes << _CSEN_DMCFG_CRMODE_SHIFT) + | (init->dmCycles << _CSEN_DMCFG_DMCR_SHIFT) + | (init->dmIterPerCycle << _CSEN_DMCFG_DMR_SHIFT) + | (init->dmDelta << _CSEN_DMCFG_DMG_SHIFT); + + if (init->dmFixedDelta) + { + tmp |= CSEN_DMCFG_DMGRDIS; + } + + csen->DMCFG = tmp; + + /* Initialize ANACTRL. */ + csen->ANACTRL = (init->resetPhase << _CSEN_ANACTRL_TRSTPROG_SHIFT) + | (init->driveSel << _CSEN_ANACTRL_IDACIREFS_SHIFT) + | (init->gainSel << _CSEN_ANACTRL_IREFPROG_SHIFT); +} + + +/***************************************************************************//** + * @brief + * Reset CSEN to same state as after a HW reset. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +void CSEN_Reset(CSEN_TypeDef *csen) +{ + EFM_ASSERT(CSEN_REF_VALID(csen)); + + /* Resetting CTRL stops any conversion in progress. */ + csen->CTRL = _CSEN_CTRL_RESETVALUE; + csen->TIMCTRL = _CSEN_TIMCTRL_RESETVALUE; + csen->PRSSEL = _CSEN_PRSSEL_RESETVALUE; + csen->DATA = _CSEN_DATA_RESETVALUE; + csen->SCANMASK0 = _CSEN_SCANMASK0_RESETVALUE; + csen->SCANINPUTSEL0 = _CSEN_SCANINPUTSEL0_RESETVALUE; + csen->SCANMASK1 = _CSEN_SCANMASK1_RESETVALUE; + csen->SCANINPUTSEL1 = _CSEN_SCANINPUTSEL1_RESETVALUE; + csen->CMPTHR = _CSEN_CMPTHR_RESETVALUE; + csen->EMA = _CSEN_EMA_RESETVALUE; + csen->EMACTRL = _CSEN_EMACTRL_RESETVALUE; + csen->SINGLECTRL = _CSEN_SINGLECTRL_RESETVALUE; + csen->DMBASELINE = _CSEN_DMBASELINE_RESETVALUE; + csen->DMCFG = _CSEN_DMCFG_RESETVALUE; + csen->ANACTRL = _CSEN_ANACTRL_RESETVALUE; + csen->IEN = _CSEN_IEN_RESETVALUE; + csen->IFC = _CSEN_IF_MASK; +} + + +/** @} (end addtogroup CSEN) */ +/** @} (end addtogroup emlib) */ +#endif /* defined(CSEN_COUNT) && (CSEN_COUNT > 0) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c index de6694d365a..074dc945302 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dac.c * @brief Digital to Analog Converter (DAC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c index 08882258972..c259a967bd2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dbg.c * @brief Debug (DBG) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c index 7dae4a395e6..4ad4cdb8fab 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dma.c * @brief Direct memory access (DMA) module peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -173,7 +173,7 @@ static void DMA_Prepare(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1) { DMA_DESCRIPTOR_TypeDef *descr; @@ -209,7 +209,7 @@ static void DMA_Prepare(unsigned int channel, inc = (descr->CTRL & _DMA_CTRL_SRC_INC_MASK) >> _DMA_CTRL_SRC_INC_SHIFT; if (inc == _DMA_CTRL_SRC_INC_NONE) { - descr->SRCEND = src; + descr->SRCEND = (volatile void*)src; } else { @@ -386,7 +386,7 @@ void DMA_IRQHandler(void) void DMA_ActivateAuto(unsigned int channel, bool primary, void *dst, - void *src, + const void *src, unsigned int nMinus1) { uint32_t chBit; @@ -450,7 +450,7 @@ void DMA_ActivateBasic(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1) { EFM_ASSERT(channel < DMA_CHAN_COUNT); @@ -521,10 +521,10 @@ void DMA_ActivateBasic(unsigned int channel, void DMA_ActivatePingPong(unsigned int channel, bool useBurst, void *primDst, - void *primSrc, + const void *primSrc, unsigned int primNMinus1, void *altDst, - void *altSrc, + const void *altSrc, unsigned int altNMinus1) { EFM_ASSERT(channel < DMA_CHAN_COUNT); @@ -1136,7 +1136,7 @@ void DMA_RefreshPingPong(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1, bool stop) { @@ -1174,7 +1174,7 @@ void DMA_RefreshPingPong(unsigned int channel, inc = (descr->CTRL & _DMA_CTRL_SRC_INC_MASK) >> _DMA_CTRL_SRC_INC_SHIFT; if (inc == _DMA_CTRL_SRC_INC_NONE) { - descr->SRCEND = src; + descr->SRCEND = (volatile void*)src; } else { diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c index 6c1c5178c02..fd114788f7f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ebi.c * @brief External Bus Interface (EBI) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c index c5d329e6c6f..154bae1252b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_emu.c * @brief Energy Management Unit (EMU) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -70,9 +70,10 @@ #error Conflict in LFXOENS and LFXOEN bitpositions #endif - /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Fix for errata EMU_E107 - non-WIC interrupt masks. */ +#if defined( _SILICON_LABS_32B_SERIES_0 ) +/* Fix for errata EMU_E107 - non-WIC interrupt masks. + * Zero Gecko and future families are not affected by errata EMU_E107 */ #if defined( _EFM32_GECKO_FAMILY ) #define ERRATA_FIX_EMU_E107_EN #define NON_WIC_INT_MASK_0 (~(0x0dfc0323U)) @@ -93,41 +94,65 @@ #define NON_WIC_INT_MASK_0 (~(0xff020e63U)) #define NON_WIC_INT_MASK_1 (~(0x00000046U)) -#else -/* Zero Gecko and future families are not affected by errata EMU_E107 */ +#endif #endif /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ -#if defined( _EFM32_HAPPY_FAMILY ) +#if defined(_SILICON_LABS_32B_SERIES_0) && defined( _EFM32_HAPPY_FAMILY ) #define ERRATA_FIX_EMU_E108_EN #endif /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) #define ERRATA_FIX_EMU_E208_EN #endif /* Enable FETCNT tuning errata fix */ -#if defined( _EMU_DCDCCTRL_MASK ) && defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) #define ERRATA_FIX_DCDC_FETCNT_SET_EN #endif /* Enable LN handshake errata fix */ -#if defined( _EMU_DCDCCTRL_MASK ) && ( _SILICON_LABS_32B_PLATFORM_2_GEN < 3 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) #define ERRATA_FIX_DCDC_LNHS_BLOCK_EN -#endif - -/* Enable bypass current limiter enable timing fix */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_2 ) -#define ERRATA_FIX_BYPLIMEN_TIMING_EN -#endif - -#define EMU_DCDCCLIMCTRL (uint32_t *)(EMU_BASE + 0x054) -#if !defined(_EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT) -#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 -#endif -#if !defined(_EMU_PWRCTRL_DVDDBODDIS_SHIFT) -#define EMU_PWRCTRL_DVDDBODDIS (1 << 12) +typedef enum +{ + errataFixDcdcHsInit, + errataFixDcdcHsTrimSet, + errataFixDcdcHsBypassLn, + errataFixDcdcHsLnWaitDone +} errataFixDcdcHs_TypeDef; +static errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; +#endif + +/* Used to figure out if a memory address is inside or outside of a RAM block. + * A memory address is inside a RAM block if the address is greater than the + * RAM block address. */ +#define ADDRESS_NOT_IN_BLOCK(addr, block) ((addr) <= (block)) + +/* RAM Block layout for various device families. Note that some devices + * have special layout in RAM0. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) +#define RAM1_BLOCKS 2 +#define RAM1_BLOCK_SIZE 0x10000 // 64 kB blocks +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +#define RAM0_BLOCKS 2 +#define RAM0_BLOCK_SIZE 0x4000 +#define RAM1_BLOCKS 2 +#define RAM1_BLOCK_SIZE 0x4000 // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) +#define RAM0_BLOCKS 4 +#define RAM0_BLOCK_SIZE 0x8000 // 32 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) +#define RAM0_BLOCKS 4 +#define RAM0_BLOCK_SIZE 0x1000 // 4 kB blocks +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) +/* RAM_MEM_END on Gecko devices have a value larger than the SRAM_SIZE */ +#define RAM0_END (SRAM_BASE + SRAM_SIZE - 1) +#else +#define RAM0_END RAM_MEM_END #endif /** @endcond */ @@ -141,41 +166,23 @@ #if !defined(PWRCFG_DCDCTODVDD_VMAX) #define PWRCFG_DCDCTODVDD_VMAX 3000 #endif - -typedef enum -{ - errataFixDcdcHsInit, - errataFixDcdcHsTrimSet, - errataFixDcdcHsBypassLn, - errataFixDcdcHsLnWaitDone -} errataFixDcdcHs_TypeDef; -errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; #endif /******************************************************************************* - ************************** LOCAL VARIABLES ******************************** + *************************** LOCAL VARIABLES ******************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** - * CMU configured oscillator selection and oscillator enable status. When a - * user configures oscillators, this varaiable shall shadow the configuration. - * It is used by the EMU module in order to be able to restore the oscillator - * config after having been in certain energy modes (since HW may automatically - * alter config when going into an energy mode). It is the responsibility of - * the CMU module to keep it up-to-date (or a user if not using the CMU API - * for oscillator control). - */ -static uint32_t cmuStatus; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) -static uint16_t cmuHfclkStatus; -#endif + +/* Static user configuration */ #if defined( _EMU_DCDCCTRL_MASK ) static uint16_t dcdcMaxCurrent_mA; static uint16_t dcdcEm01LoadCurrent_mA; static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; #endif - +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +static EMU_EM01Init_TypeDef vScaleEM01Config = {false}; +#endif /** @endcond */ @@ -185,147 +192,105 @@ static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/* Convert from level to EM0 and 1 command bit */ +__STATIC_INLINE uint32_t vScaleEM01Cmd(EMU_VScaleEM01_TypeDef level) +{ + return EMU_CMD_EM01VSCALE0 << (_EMU_STATUS_VSCALE_VSCALE0 - (uint32_t)level); +} +#endif + /***************************************************************************//** * @brief - * Restore oscillators and core clock after having been in EM2 or EM3. + * Save/restore/update oscillator, core clock and voltage scaling configuration on + * EM2 or EM3 entry/exit. + * + * @details + * Hardware may automatically change oscillator and voltage scaling configuration + * when going into or out of an energy mode. Static data in this function keeps track of + * such configuration bits and is used to restore state if needed. + * ******************************************************************************/ -static void emuRestore(void) +typedef enum +{ + emState_Save, /* Save EMU and CMU state */ + emState_Restore, /* Restore and unlock */ +} emState_TypeDef; + +static void emState(emState_TypeDef action) { uint32_t oscEnCmd; uint32_t cmuLocked; - - /* Although we could use the CMU API for most of the below handling, we */ - /* would like this function to be as efficient as possible. */ - - /* CMU registers may be locked */ - cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; - CMU_Unlock(); - - /* AUXHFRCO are automatically disabled (except if using debugger). */ - /* HFRCO, USHFRCO and HFXO are automatically disabled. */ - /* LFRCO/LFXO may be disabled by SW in EM3. */ - /* Restore according to status prior to entering energy mode. */ - oscEnCmd = 0; - oscEnCmd |= ((cmuStatus & CMU_STATUS_HFRCOENS) ? CMU_OSCENCMD_HFRCOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_AUXHFRCOENS) ? CMU_OSCENCMD_AUXHFRCOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_LFRCOENS) ? CMU_OSCENCMD_LFRCOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_HFXOENS) ? CMU_OSCENCMD_HFXOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_LFXOENS) ? CMU_OSCENCMD_LFXOEN : 0); -#if defined( _CMU_STATUS_USHFRCOENS_MASK ) - oscEnCmd |= ((cmuStatus & CMU_STATUS_USHFRCOENS) ? CMU_OSCENCMD_USHFRCOEN : 0); + static uint32_t cmuStatus; + static CMU_Select_TypeDef hfClock; +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + static uint8_t vScaleStatus; #endif - CMU->OSCENCMD = oscEnCmd; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - /* Restore oscillator used for clocking core */ - switch (cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK) + /* Save or update state */ + if (action == emState_Save) { - case CMU_HFCLKSTATUS_SELECTED_LFRCO: - /* HFRCO could only be selected if the autostart HFXO feature is not - * enabled, otherwise the HFXO would be started and selected automatically. - * Note: this error hook helps catching erroneous oscillator configurations, - * when the AUTOSTARTSELEM0EM1 is set in CMU_HFXOCTRL. */ - if (!(CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1)) - { - /* Wait for LFRCO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFRCORDY)) - ; - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO; - } - else - { - EFM_ASSERT(0); - } - break; - - case CMU_HFCLKSTATUS_SELECTED_LFXO: - /* Wait for LFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFXORDY)) - ; - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO; - break; - - case CMU_HFCLKSTATUS_SELECTED_HFXO: - /* Wait for HFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_HFXORDY)) - ; -#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK ) - if (BUS_RegMaskedRead(&CMU->HFXOCTRL, - _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD) - { - while (BUS_RegMaskedRead(&CMU->STATUS, - _CMU_STATUS_HFXOSHUNTOPTRDY_MASK - | _CMU_STATUS_HFXOPEAKDETRDY_MASK) - != (CMU_STATUS_HFXOSHUNTOPTRDY | CMU_STATUS_HFXOPEAKDETRDY)) - ; - } + /* Save configuration. */ + cmuStatus = CMU->STATUS; + hfClock = CMU_ClockSelectGet(cmuClock_HF); +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Save vscale */ + EMU_VScaleWait(); + vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); #endif - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO; - break; - - default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */ - /* If core clock was HFRCO core clock, it is automatically restored to */ - /* state prior to entering energy mode. No need for further action. */ - break; } -#else - switch (cmuStatus & (CMU_STATUS_HFRCOSEL - | CMU_STATUS_HFXOSEL - | CMU_STATUS_LFRCOSEL -#if defined( CMU_STATUS_USHFRCODIV2SEL ) - | CMU_STATUS_USHFRCODIV2SEL -#endif - | CMU_STATUS_LFXOSEL)) - { - case CMU_STATUS_LFRCOSEL: - /* Wait for LFRCO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFRCORDY)) - ; - CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO; - break; - - case CMU_STATUS_LFXOSEL: - /* Wait for LFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFXORDY)) - ; - CMU->CMD = CMU_CMD_HFCLKSEL_LFXO; - break; - - case CMU_STATUS_HFXOSEL: - /* Wait for HFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_HFXORDY)) - ; - CMU->CMD = CMU_CMD_HFCLKSEL_HFXO; - break; + else if (action == emState_Restore) /* Restore state */ + { + /* Apply saved configuration. */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Restore EM0 and 1 voltage scaling level. EMU_VScaleWait() is called later, + just before HF clock select is set. */ + EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); +#endif + + /* CMU registers may be locked */ + cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; + CMU_Unlock(); + + /* AUXHFRCO are automatically disabled (except if using debugger). */ + /* HFRCO, USHFRCO and HFXO are automatically disabled. */ + /* LFRCO/LFXO may be disabled by SW in EM3. */ + /* Restore according to status prior to entering energy mode. */ + oscEnCmd = 0; + oscEnCmd |= ((cmuStatus & CMU_STATUS_HFRCOENS) ? CMU_OSCENCMD_HFRCOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_AUXHFRCOENS) ? CMU_OSCENCMD_AUXHFRCOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_LFRCOENS) ? CMU_OSCENCMD_LFRCOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_HFXOENS) ? CMU_OSCENCMD_HFXOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_LFXOENS) ? CMU_OSCENCMD_LFXOEN : 0); +#if defined( _CMU_STATUS_USHFRCOENS_MASK ) + oscEnCmd |= ((cmuStatus & CMU_STATUS_USHFRCOENS) ? CMU_OSCENCMD_USHFRCOEN : 0); +#endif + CMU->OSCENCMD = oscEnCmd; -#if defined( CMU_STATUS_USHFRCODIV2SEL ) - case CMU_STATUS_USHFRCODIV2SEL: - /* Wait for USHFRCO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_USHFRCORDY)) - ; - CMU->CMD = _CMU_CMD_HFCLKSEL_USHFRCODIV2; - break; +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* Wait for upscale to complete and then restore selected clock */ + EMU_VScaleWait(); #endif - default: /* CMU_STATUS_HFRCOSEL */ - /* If core clock was HFRCO core clock, it is automatically restored to */ - /* state prior to entering energy mode. No need for further action. */ - break; - } + if (hfClock != cmuSelect_HFRCO) + { + CMU_ClockSelectSet(cmuClock_HF, hfClock); + } - /* If HFRCO was disabled before entering Energy Mode, turn it off again */ - /* as it is automatically enabled by wake up */ - if ( ! (cmuStatus & CMU_STATUS_HFRCOENS) ) - { - CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; - } -#endif - /* Restore CMU register locking */ - if (cmuLocked) - { - CMU_Lock(); + /* If HFRCO was disabled before entering Energy Mode, turn it off again */ + /* as it is automatically enabled by wake up */ + if ( ! (cmuStatus & CMU_STATUS_HFRCOENS) ) + { + CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; + } + + /* Restore CMU register locking */ + if (cmuLocked) + { + CMU_Lock(); + } } } @@ -412,7 +377,49 @@ static void dcdcHsFixLnBlock(void) #endif +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) +/* Configure EMU and CMU for EM2 and 3 voltage downscale */ +static void vScaleDownEM23Setup(void) +{ + uint32_t hfSrcClockFrequency; + + EMU_VScaleEM23_TypeDef scaleEM23Voltage = + (EMU_VScaleEM23_TypeDef)((EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) + >> _EMU_CTRL_EM23VSCALE_SHIFT); + + EMU_VScaleEM01_TypeDef currentEM01Voltage = + (EMU_VScaleEM01_TypeDef)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); + + /* Wait until previous scaling is done. */ + EMU_VScaleWait(); + /* Inverse coding. */ + if ((uint32_t)scaleEM23Voltage > (uint32_t)currentEM01Voltage) + { + /* Set safe clock and wait-states. */ + if (scaleEM23Voltage == emuVScaleEM23_LowPower) + { + hfSrcClockFrequency = CMU_ClockDivGet(cmuClock_HF) * CMU_ClockFreqGet(cmuClock_HF); + /* Set default low power voltage HFRCO band as HF clock. */ + if (hfSrcClockFrequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX) + { + CMU_HFRCOBandSet(cmuHFRCOFreq_19M0Hz); + } + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + } + else + { + /* Other voltage scaling levels are not currently supported. */ + EFM_ASSERT(false); + } + } + else + { + /* Same voltage or hardware will scale to min(EMU_CTRL_EM23VSCALE, EMU_STATUS_VSCALE) */ + } +} +#endif /** @endcond */ @@ -458,9 +465,13 @@ static void dcdcHsFixLnBlock(void) * the starting and selecting of the core clocks will be identical to the user * independently of the value of the @p restore parameter when waking up on * the wakeup sources corresponding to the autostart and select setting. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM2 level, then the EM0 level is + * also restored. * * @param[in] restore - * @li true - restore oscillators and clocks, see function details. + * @li true - restore oscillators, clocks and voltage scaling, see function details. * @li false - do not restore oscillators and clocks, see function details. * @par * The @p restore option should only be used if all clock control is done @@ -473,11 +484,11 @@ void EMU_EnterEM2(bool restore) uint32_t nonWicIntEn[2]; #endif - /* Auto-update CMU status just in case before entering energy mode. */ - /* This variable is normally kept up-to-date by the CMU API. */ - cmuStatus = CMU->STATUS; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS); + /* Save EMU and CMU state requiring restore on EM2 exit. */ + emState(emState_Save); + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + vScaleDownEM23Setup(); #endif /* Enter Cortex deep sleep mode */ @@ -504,9 +515,6 @@ void EMU_EnterEM2(bool restore) #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN ) dcdcHsFixLnBlock(); #endif -#if defined( ERRATA_FIX_BYPLIMEN_TIMING_EN ) - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); -#endif __WFI(); @@ -525,21 +533,16 @@ void EMU_EnterEM2(bool restore) } #endif - /* Restore oscillators/clocks if specified */ + /* Restore oscillators/clocks and voltage scaling if supported. */ if (restore) { - emuRestore(); + emState(emState_Restore); } - /* If not restoring, and original clock was not HFRCO, we have to */ - /* update CMSIS core clock variable since core clock has changed */ - /* to using HFRCO. */ -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK) - != CMU_HFCLKSTATUS_SELECTED_HFRCO) -#else - else if (!(cmuStatus & CMU_STATUS_HFRCOSEL)) -#endif + else { + /* If not restoring, and original clock was not HFRCO, we have to */ + /* update CMSIS core clock variable since HF clock has changed */ + /* to HFRCO. */ SystemCoreClockUpdate(); } } @@ -579,9 +582,13 @@ void EMU_EnterEM2(bool restore) * If a debugger is attached, the AUXHFRCO will not be disabled if enabled * upon entering EM3. It will thus remain enabled when returning to EM0 * regardless of the @p restore parameter. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM3 level, then the EM0 level is + * also restored. * * @param[in] restore - * @li true - restore oscillators and clocks, see function details. + * @li true - restore oscillators, clocks and voltage scaling, see function details. * @li false - do not restore oscillators and clocks, see function details. * @par * The @p restore option should only be used if all clock control is done @@ -596,11 +603,11 @@ void EMU_EnterEM3(bool restore) uint32_t nonWicIntEn[2]; #endif - /* Auto-update CMU status just in case before entering energy mode. */ - /* This variable is normally kept up-to-date by the CMU API. */ - cmuStatus = CMU->STATUS; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS); + /* Save EMU and CMU state requiring restore on EM2 exit. */ + emState(emState_Save); + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + vScaleDownEM23Setup(); #endif /* CMU registers may be locked */ @@ -640,9 +647,6 @@ void EMU_EnterEM3(bool restore) #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN ) dcdcHsFixLnBlock(); #endif -#if defined( ERRATA_FIX_BYPLIMEN_TIMING_EN ) - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); -#endif __WFI(); @@ -661,26 +665,36 @@ void EMU_EnterEM3(bool restore) } #endif - /* Restore oscillators/clocks if specified */ + /* Restore oscillators/clocks and voltage scaling if supported. */ if (restore) { - emuRestore(); + emState(emState_Restore); } - /* If not restoring, and original clock was not HFRCO, we have to */ - /* update CMSIS core clock variable since core clock has changed */ - /* to using HFRCO. */ -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK) - != CMU_HFCLKSTATUS_SELECTED_HFRCO) -#else - else if (!(cmuStatus & CMU_STATUS_HFRCOSEL)) -#endif + else { + /* If not restoring, and original clock was not HFRCO, we have to */ + /* update CMSIS core clock variable since HF clock has changed */ + /* to HFRCO. */ SystemCoreClockUpdate(); } } +/***************************************************************************//** + * @brief + * Restore CMU HF clock select state, oscillator enable and voltage scaling + * (if available) after @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called + * with the restore parameter set to false. Calling this function is + * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the + * restore parameter set to true, but it allows the application to evaluate the + * wakeup reason before restoring state. + ******************************************************************************/ +void EMU_Restore(void) +{ + emState(emState_Restore); +} + + /***************************************************************************//** * @brief * Enter energy mode 4 (EM4). @@ -745,9 +759,6 @@ void EMU_EnterEM4(void) #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN ) dcdcHsFixLnBlock(); #endif -#if defined( ERRATA_FIX_BYPLIMEN_TIMING_EN ) - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); -#endif for (i = 0; i < 4; i++) { @@ -805,67 +816,256 @@ void EMU_EnterEM4S(void) * memory blocks for a device. * * @note - * Only a reset can make the specified memory block(s) available for use - * after having been powered down. Function will be void for devices not - * supporting this feature. + * Only a POR reset can power up the specified memory block(s) after powerdown. + * + * @deprecated + * This function is deprecated, use @ref EMU_RamPowerDown() instead which + * maps a user provided memory range into RAM blocks to power down. ******************************************************************************/ void EMU_MemPwrDown(uint32_t blocks) { -#if defined( _EMU_MEMCTRL_POWERDOWN_MASK ) - EFM_ASSERT(blocks <= (_EMU_MEMCTRL_POWERDOWN_MASK - >> _EMU_MEMCTRL_POWERDOWN_SHIFT)); - EMU->MEMCTRL = blocks; - -#elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK ) \ - && defined( _EMU_MEMCTRL_RAMHPOWERDOWN_MASK ) \ - && defined( _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK ) - EFM_ASSERT((blocks & (_EMU_MEMCTRL_RAMPOWERDOWN_MASK - | _EMU_MEMCTRL_RAMHPOWERDOWN_MASK - | _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK)) - == blocks); - EMU->MEMCTRL = blocks; - -#elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK ) - EFM_ASSERT((blocks & _EMU_MEMCTRL_RAMPOWERDOWN_MASK) == blocks); - EMU->MEMCTRL = blocks; - -#elif defined( _EMU_RAM0CTRL_RAMPOWERDOWN_MASK ) - EFM_ASSERT((blocks & _EMU_RAM0CTRL_RAMPOWERDOWN_MASK) == blocks); - EMU->RAM0CTRL = blocks; - +#if defined( _EMU_MEMCTRL_MASK ) + EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK; +#elif defined( _EMU_RAM0CTRL_MASK ) + EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK; #else (void)blocks; #endif } +/***************************************************************************//** + * @brief + * Power down RAM memory blocks. + * + * @details + * This function will power down all the RAM blocks that are within a given + * range. The RAM block layout is different between device families, so this + * function can be used in a generic way to power down a RAM memory region + * which is known to be unused. + * + * This function will only power down blocks which are completely enclosed + * by the memory range given by [start, end). + * + * Here is an example of how to power down all RAM blocks except the first + * one. The first RAM block is special in that it cannot be powered down + * by the hardware. The size of this first RAM block is device specific + * see the reference manual to find the RAM block sizes. + * + * @code + * EMU_RamPowerDown(SRAM_BASE, SRAM_BASE + SRAM_SIZE); + * @endcode + * + * @note + * Only a POR reset can power up the specified memory block(s) after powerdown. + * + * @param[in] start + * The start address of the RAM region to power down. This address is + * inclusive. + * + * @param[in] end + * The end address of the RAM region to power down. This address is + * exclusive. If this parameter is 0, then all RAM blocks contained in the + * region from start to the upper RAM address will be powered down. + ******************************************************************************/ +void EMU_RamPowerDown(uint32_t start, uint32_t end) +{ + uint32_t mask = 0; + + if (end == 0) + { + end = SRAM_BASE + SRAM_SIZE; + } + + // Check to see if something in RAM0 can be powered down + if (end > RAM0_END) + { +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) // EFM32xG12 and EFR32xG12 + // Block 0 is 16 kB and cannot be powered off + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000) << 0; // Block 1, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000) << 1; // Block 2, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x2000C000) << 2; // Block 3, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20010000) << 3; // Block 4, 64 kB +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) // EFM32xG1 and EFR32xG1 + // Block 0 is 4 kB and cannot be powered off + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20001000) << 0; // Block 1, 4 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20002000) << 1; // Block 2, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000) << 2; // Block 3, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000) << 3; // Block 4, 7 kB +#elif defined(RAM0_BLOCKS) + // These platforms have equally sized RAM blocks + for (int i = 1; i < RAM0_BLOCKS; i++) + { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i - 1); + } +#endif + } + + // Power down the selected blocks +#if defined( _EMU_MEMCTRL_MASK ) + EMU->MEMCTRL = EMU->MEMCTRL | mask; +#elif defined( _EMU_RAM0CTRL_MASK ) + EMU->RAM0CTRL = EMU->RAM0CTRL | mask; +#else + // These devices are unable to power down RAM blocks + (void) mask; + (void) start; +#endif + +#if defined(RAM1_MEM_END) + mask = 0; + if (end > RAM1_MEM_END) + { + for (int i = 0; i < RAM1_BLOCKS; i++) + { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM1_MEM_BASE + (i * RAM1_BLOCK_SIZE)) << i; + } + } + EMU->RAM1CTRL |= mask; +#endif +} + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/***************************************************************************//** + * @brief + * Set EM2 3 peripheral retention control. + * + * @param[in] periMask + * Peripheral select mask. Use | operator to select multiple peripheral, for example + * @ref emuPeripheralRetention_LEUART0 | @ref emuPeripheralRetention_VDAC0. + * @param[in] enable + * Peripheral retention enable (true) or disable (false). + * + * + * @note + * Only peripheral retention disable is currently supported. Peripherals are + * enabled by default, and can only be disabled. + ******************************************************************************/ +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable) +{ + EFM_ASSERT(!enable); + EMU->EM23PERNORETAINCTRL = periMask & emuPeripheralRetention_ALL; +} +#endif + /***************************************************************************//** * @brief * Update EMU module with CMU oscillator selection/enable status. * - * @details - * When entering EM2 and EM3, the HW may change the core clock oscillator - * used, as well as disabling some oscillators. The user may optionally select - * to restore the oscillators after waking up from EM2 and EM3 through the - * SW API. - * - * However, in order to support this in a safe way, the EMU module must - * be kept up-to-date on the actual selected configuration. The CMU - * module must keep the EMU module up-to-date. - * - * This function is mainly intended for internal use by the CMU module, - * but if the applications changes oscillator configurations without - * using the CMU API, this function can be used to keep the EMU module - * up-to-date. + * @deprecated + * Oscillator status is saved in @ref EMU_EnterEM2() and @ref EMU_EnterEM3(). ******************************************************************************/ void EMU_UpdateOscConfig(void) { - /* Fetch current configuration */ - cmuStatus = CMU->STATUS; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS); + emState(emState_Save); +} + + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/***************************************************************************//** + * @brief + * Voltage scale in EM0 and 1 by clock frequency. + * + * @param[in] clockFrequency + * Use CMSIS HF clock if 0, or override to custom clock. Providing a + * custom clock frequency is required if using a non-standard HFXO + * frequency. + * @param[in] wait + * Wait for scaling to complate. + * + * @note + * This function is primarely needed by the @ref CMU module. + ******************************************************************************/ +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait) +{ + uint32_t hfSrcClockFrequency; + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + + /* VSCALE frequency is HFSRCCLK */ + if (clockFrequency == 0) + { + hfSrcClockFrequency = SystemHFClockGet() * hfPresc; + } + else + { + hfSrcClockFrequency = clockFrequency; + } + + /* Apply EM0 and 1 voltage scaling command. */ + if (vScaleEM01Config.vScaleEM01LowPowerVoltageEnable + && (hfSrcClockFrequency < CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) + { + EMU->CMD = vScaleEM01Cmd(emuVScaleEM01_LowPower); + } + else + { + EMU->CMD = vScaleEM01Cmd(emuVScaleEM01_HighPerformance); + } + + if (wait) + { + EMU_VScaleWait(); + } +} +#endif + + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/***************************************************************************//** + * @brief + * Force voltage scaling in EM0 and 1 to a specific voltage level. + * + * @param[in] voltage + * Target VSCALE voltage level. + * @param[in] wait + * Wait for scaling to complate. + * + * @note + * This function is useful for upscaling before programming Flash from @ref MSC, + * and downscaling after programming is done. Flash programming is only supported + * at @ref emuVScaleEM01_HighPerformance. + * + * @note + * This function ignores @ref vScaleEM01LowPowerVoltageEnable set from @ref + * EMU_EM01Init(). + ******************************************************************************/ +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait) +{ + uint32_t hfSrcClockFrequency; + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + hfSrcClockFrequency = SystemHFClockGet() * hfPresc; + + if (voltage == emuVScaleEM01_LowPower) + { + EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); + } + + EMU->CMD = vScaleEM01Cmd(voltage); + if (wait) + { + EMU_VScaleWait(); + } +} #endif + + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/***************************************************************************//** + * @brief + * Update EMU module with Energy Mode 0 and 1 configuration + * + * @param[in] em01Init + * Energy Mode 0 and 1 configuration structure + ******************************************************************************/ +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init) +{ + vScaleEM01Config.vScaleEM01LowPowerVoltageEnable = + em01Init->vScaleEM01LowPowerVoltageEnable; + EMU_VScaleEM01ByClock(0, true); } +#endif /***************************************************************************//** @@ -875,7 +1075,7 @@ void EMU_UpdateOscConfig(void) * @param[in] em23Init * Energy Mode 2 and 3 configuration structure ******************************************************************************/ -void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init) +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init) { #if defined( _EMU_CTRL_EMVREG_MASK ) EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG) @@ -886,6 +1086,11 @@ void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init) #else (void)em23Init; #endif + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) + | (em23Init->vScaleEM23Voltage << _EMU_CTRL_EM23VSCALE_SHIFT); +#endif } @@ -897,7 +1102,7 @@ void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init) * @param[in] em4Init * Energy Mode 4 configuration structure ******************************************************************************/ -void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init) +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init) { #if defined( _EMU_EM4CONF_MASK ) /* Init for platforms with EMU->EM4CONF register */ @@ -937,6 +1142,11 @@ void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init) EMU->EM4CTRL = em4ctrl; #endif + +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK) + | (em4Init->vScaleEM4HVoltage << _EMU_CTRL_EM4HVSCALE_SHIFT); +#endif } #endif @@ -949,7 +1159,7 @@ void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init) * @param[in] bupdInit * Backup power domain initialization structure ******************************************************************************/ -void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit) +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit) { uint32_t reg; @@ -1055,8 +1265,8 @@ void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) #endif +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined( _EMU_DCDCCTRL_MASK ) - /* Translate fields with different names across platform generations to common names. */ #if defined( _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK ) #define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK @@ -1073,7 +1283,15 @@ void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) #define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT #endif -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Internal DCDC trim modes. */ +typedef enum +{ + dcdcTrimMode_EM234H_LP = 0, +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + dcdcTrimMode_EM01_LP, +#endif + dcdcTrimMode_LN, +} dcdcTrimMode_TypeDef; /***************************************************************************//** * @brief @@ -1083,9 +1301,9 @@ void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) * @return * False if calibration registers are locked ******************************************************************************/ -static bool ConstCalibrationLoad(void) +static bool dcdcConstCalibrationLoad(void) { -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) uint32_t val; volatile uint32_t *reg; @@ -1129,10 +1347,7 @@ static bool ConstCalibrationLoad(void) /* Return when assertions are disabled */ return false; -#elif defined( _SILICON_LABS_32B_PLATFORM_2_GEN_2 ) - return true; #else -#error "Undefined platform 2 generation." return true; #endif } @@ -1143,7 +1358,7 @@ static bool ConstCalibrationLoad(void) * Set recommended and validated current optimization and timing settings * ******************************************************************************/ -static void ValidatedConfigSet(void) +static void dcdcValidatedConfigSet(void) { /* Disable LP mode hysterysis in the state machine control */ #define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) @@ -1151,14 +1366,13 @@ static void ValidatedConfigSet(void) #define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) #define EMU_DCDCSMCTRL (* (volatile uint32_t *)(EMU_BASE + 0x44)) -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) + uint32_t lnForceCcm; + +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) uint32_t dcdcTiming; - SYSTEM_PartFamily_TypeDef family; SYSTEM_ChipRevision_TypeDef rev; #endif - uint32_t lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); - /* Enable duty cycling of the bias */ EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; @@ -1166,6 +1380,7 @@ static void ValidatedConfigSet(void) * LNFORCECCM is default 1 for EFR32 * LNFORCECCM is default 0 for EFM32 */ + lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); if (lnForceCcm) { /* 7MHz is recommended for LNFORCECCM = 1 */ @@ -1177,18 +1392,14 @@ static void ValidatedConfigSet(void) EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); } -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK; EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS | EMU_DCDCMISCCTRL_LPCMPHYSHI; - family = SYSTEM_GetFamily(); SYSTEM_ChipRevisionGet(&rev); - if ((((family >= systemPartFamilyMighty1P) - && (family <= systemPartFamilyFlex1V)) - || (family == systemPartFamilyEfm32Pearl1B) - || (family == systemPartFamilyEfm32Jade1B)) - && ((rev.major == 1) && (rev.minor < 3)) + if ((rev.major == 1) + && (rev.minor < 3) && (errataFixDcdcHsState == errataFixDcdcHsInit)) { /* LPCMPWAITDIS = 1 */ @@ -1315,16 +1526,14 @@ static void userCurrentLimitsSet(uint32_t maxCurrent_mA, ******************************************************************************/ static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) { -#define EMU_DCDCLNCOMPCTRL (*(volatile uint32_t *) (EMU_BASE + 0x58UL)) - switch (comp) { case emuDcdcLnCompCtrl_1u0F: - EMU_DCDCLNCOMPCTRL = 0x57204077UL; + EMU->DCDCLNCOMPCTRL = 0x57204077UL; break; case emuDcdcLnCompCtrl_4u7F: - EMU_DCDCLNCOMPCTRL = 0xB7102137UL; + EMU->DCDCLNCOMPCTRL = 0xB7102137UL; break; default: @@ -1338,21 +1547,29 @@ static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) * Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback * attenuation and DEVINFOREV. * - * @param[in] attSet + * @param[in] lpAttenuation * LP feedback attenuation. * @param[in] lpCmpBias - * lpCmpBias selection (unshifted) + * lpCmpBias selection. + * @param[in] trimMode + * DCDC trim mode. ******************************************************************************/ -static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias) +static bool lpCmpHystCalibrationLoad(bool lpAttenuation, + uint8_t lpCmpBias, + dcdcTrimMode_TypeDef trimMode) { - uint8_t devinfoRev; uint32_t lpcmpHystSel; /* Get calib data revision */ - devinfoRev = SYSTEM_GetDevinfoRev(); +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint8_t devinfoRev = SYSTEM_GetDevinfoRev(); /* Load LPATT indexed calibration data */ if (devinfoRev < 4) +#else + /* Format change not present of newer families. */ + if (false) +#endif { lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0; @@ -1378,17 +1595,17 @@ static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT; break; - case 1 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: + case 1: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT; break; - case 2 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: + case 2: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT; break; - case 3 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: + case 3: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT; break; @@ -1399,19 +1616,138 @@ static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias) return false; } } - /* Make sure the sel value is within the field range. */ - lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; - if (lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) + + /* Set trims */ + if (trimMode == dcdcTrimMode_EM234H_LP) { - EFM_ASSERT(false); - /* Return when assertions are disabled */ - return false; + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; + if (lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) + { + EFM_ASSERT(false); + /* Return when assertions are disabled */ + return false; + } + EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; } - EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; + +#if defined( _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK ) + if (trimMode == dcdcTrimMode_EM01_LP) + { + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT; + if (lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) + { + EFM_ASSERT(false); + /* Return when assertions are disabled */ + return false; + } + EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) | lpcmpHystSel; + } +#endif return true; } + +/***************************************************************************//** + * @brief + * Load LPVREF low and high from DEVINFO. + * + * @param[out] vrefL + * LPVREF low from DEVINFO. + * @param[out] vrefH + * LPVREF high from DEVINFO. + * @param[in] lpAttenuation + * LP feedback attenuation. + * @param[in] lpcmpBias + * lpcmpBias to lookup in DEVINFO. + ******************************************************************************/ +static void lpGetDevinfoVrefLowHigh(uint32_t *vrefL, + uint32_t *vrefH, + bool lpAttenuation, + uint8_t lpcmpBias) +{ + uint32_t vrefLow = 0; + uint32_t vrefHigh = 0; + + /* Find VREF high and low in DEVINFO indexed by LPCMPBIAS (lpcmpBias) + and LPATT (lpAttenuation) */ + uint32_t switchVal = (lpcmpBias << 8) | (lpAttenuation ? 1 : 0); + switch (switchVal) + { + case ((0 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; + break; + + case ((0 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; + break; + + default: + EFM_ASSERT(false); + break; + } + *vrefL = vrefLow; + *vrefH = vrefHigh; +} + /** @endcond */ /***************************************************************************//** @@ -1431,11 +1767,11 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) return; } -#if defined(_SILICON_LABS_32B_PLATFORM_2_GEN_1) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); /* Configure bypass current limiter */ - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1); + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1); /* Fix for errata DCDC_E203 */ if (((EMU_DcdcMode_TypeDef)currentDcdcMode == emuDcdcMode_Bypass) @@ -1444,8 +1780,9 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) errataFixDcdcHsState = errataFixDcdcHsBypassLn; } -#elif defined(_SILICON_LABS_32B_PLATFORM_2_GEN_2) +#else + /* Fix for errata DCDC_E204 */ if (((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_OFF) || (currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS)) && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise))) { @@ -1455,21 +1792,65 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE; while(!(EMU_IntGet() & EMU_IF_DCDCLNRUNNING)); } - else if (dcdcMode == emuDcdcMode_Bypass) - { - /* Enable limiter to remove current peak. Disable again in EMU_EnterEM2/3/4 */ - while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 1); - } -#else -#error "DCDC mode handling is undefined for this family." #endif /* Set user requested mode. */ + while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | dcdcMode; } +/***************************************************************************//** + * @brief + * Set DCDC LN regulator conduction mode + * + * @param[in] conductionMode + * DCDC LN conduction mode. + * @param[in] rcoDefaultSet + * The default DCDC RCO band for the conductionMode will be used if true. + * Otherwise the current RCO configuration is used. + ******************************************************************************/ +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet) +{ + EMU_DcdcMode_TypeDef currentDcdcMode + = (EMU_DcdcMode_TypeDef)(EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK); + EMU_DcdcLnRcoBand_TypeDef rcoBand + = (EMU_DcdcLnRcoBand_TypeDef)((EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT); + + /* Set bypass mode and wait for bypass mode to settle before + EMU_DCDCMISCCTRL_LNFORCECCM is set. Restore current DCDC mode. */ + EMU_IntClear(EMU_IFC_DCDCINBYPASS); + EMU_DCDCModeSet(emuDcdcMode_Bypass); + while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); + while(!(EMU_IntGet() & EMU_IF_DCDCINBYPASS)); + if (conductionMode == emuDcdcConductionMode_DiscontinuousLN) + { + EMU->DCDCMISCCTRL &= ~ EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) + { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); + } + else + { + /* emuDcdcConductionMode_DiscontinuousLN supports up to 4MHz LN RCO. */ + EFM_ASSERT(rcoBand <= emuDcdcLnRcoBand_4MHz); + } + } + else + { + EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) + { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); + } + } + EMU_DCDCModeSet(currentDcdcMode); + /* Update slice configuration as it depends on conduction mode and RCO band. */ + EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); +} + + /***************************************************************************//** * @brief * Configure DCDC regulator @@ -1485,20 +1866,18 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) * @return * True if initialization parameters are valid ******************************************************************************/ -bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) { -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - uint32_t lpCmpBiasSelEM01; -#endif uint32_t lpCmpBiasSelEM234H; +#if defined(_EMU_PWRCFG_MASK) /* Set external power configuration. This enables writing to the other DCDC registers. */ - EMU->PWRCFG = dcdcInit->powerConfig; + EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; /* EMU->PWRCFG is write-once and POR reset only. Check that we could set the desired power configuration. */ - if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != dcdcInit->powerConfig) + if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD) { /* If this assert triggers unexpectedly, please power cycle the kit to reset the power configuration. */ @@ -1506,23 +1885,25 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) /* Return when assertions are disabled */ return false; } +#endif /* Load DCDC calibration data from the DI page */ - ConstCalibrationLoad(); + dcdcConstCalibrationLoad(); /* Check current parameters */ EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200); EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA); EFM_ASSERT(dcdcInit->reverseCurrentControl <= 200); - /* DCDC low-noise supports max 200mA */ if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise) { + /* DCDC low-noise supports max 200mA */ EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200); } -#if (_SILICON_LABS_32B_PLATFORM_2_GEN > 1) +#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) { + /* Up to 10mA is supported for EM01-LP mode. */ EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 10); } #endif @@ -1530,22 +1911,6 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) /* EM2/3/4 current above 10mA is not supported */ EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 10000); - /* Decode LP comparator bias for EM0/1 and EM2/3 */ -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - lpCmpBiasSelEM01 = EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; - if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) - { - if (dcdcInit->em01LoadCurrent_mA <= 1) - { - lpCmpBiasSelEM01 = EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1; - } - else if (dcdcInit->em01LoadCurrent_mA <= 3) - { - lpCmpBiasSelEM01 = EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2; - } - } -#endif - if (dcdcInit->em234LoadCurrent_uA < 75) { lpCmpBiasSelEM234H = 0; @@ -1575,14 +1940,15 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) | (dcdcInit->reverseCurrentControl >= 0 ? EMU_DCDCMISCCTRL_LNFORCECCM : 0)); #if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* Only 10mA EM01-LP current is supported */ EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - | lpCmpBiasSelEM01; + | EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; #endif /* 2. Set recommended and validated current optimization settings <= Depends on LNFORCECCM => Updates DCDCLNFREQCTRL_RCOBAND */ - ValidatedConfigSet(); + dcdcValidatedConfigSet(); /* 3. Updated static currents and limits user data. Limiters are updated in EMU_DCDCOptimizeSlice() */ @@ -1611,27 +1977,28 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) return false; } -#if ( _SILICON_LABS_32B_PLATFORM_2_GEN == 1 ) +#if ( _SILICON_LABS_GECKO_INTERNAL_SDID == 80 ) /* Select analog peripheral power supply. This must be done before - DCDC mode is set for GEN_1. */ + DCDC mode is set for all EFM32xG1 and EFR32xG1 devices. */ BUS_RegBitWrite(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower ? 1 : 0); #endif +#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) + /* Select DVDD as input to the digital regulator. The switch to DVDD will take + effect once the DCDC output is stable. */ + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; +#endif + /* Set EM0 DCDC operating mode. Output voltage set in EMU_DCDCOutputVoltageSet() above takes effect if mode is changed from bypass/off mode. */ EMU_DCDCModeSet(dcdcInit->dcdcMode); - /* Select DVDD as input to the digital regulator */ -#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) - EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; -#endif - -#if ( _SILICON_LABS_32B_PLATFORM_2_GEN > 1 ) +#if ( _SILICON_LABS_GECKO_INTERNAL_SDID != 80 ) /* Select analog peripheral power supply. This must be done after - DCDC mode is set for GEN > 1. */ + DCDC mode is set for all devices other than EFM32xG1 and EFR32xG1. */ BUS_RegBitWrite(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower ? 1 : 0); @@ -1640,7 +2007,6 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) return true; } - /***************************************************************************//** * @brief * Set DCDC output voltage @@ -1657,27 +2023,21 @@ bool EMU_DCDCOutputVoltageSet(uint32_t mV, { #if defined( _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK ) +#define DCDC_TRIM_MODES ((uint8_t)dcdcTrimMode_LN + 1) bool validOutVoltage; - uint8_t lnMode; - bool attSet; - uint32_t attMask; - uint32_t vrefLow = 0; - uint32_t vrefHigh = 0; - uint32_t vrefVal = 0; + bool attenuationSet; uint32_t mVlow = 0; uint32_t mVhigh = 0; - uint32_t vrefShift; - uint32_t lpcmpBias; - volatile uint32_t* ctrlReg; + uint32_t mVdiff; + uint32_t vrefVal[DCDC_TRIM_MODES] = {0}; + uint32_t vrefLow[DCDC_TRIM_MODES] = {0}; + uint32_t vrefHigh[DCDC_TRIM_MODES] = {0}; + uint8_t lpcmpBias[DCDC_TRIM_MODES] = {0}; /* Check that the set voltage is within valid range. Voltages are obtained from the datasheet. */ - validOutVoltage = false; - if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) - { - validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN) - && (mV <= PWRCFG_DCDCTODVDD_VMAX)); - } + validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN) + && (mV <= PWRCFG_DCDCTODVDD_VMAX)); if (!validOutVoltage) { @@ -1686,167 +2046,127 @@ bool EMU_DCDCOutputVoltageSet(uint32_t mV, return false; } - /* Populate both LP and LN registers, set control reg pointer and VREF shift. */ - for (lnMode = 0; lnMode <= 1; lnMode++) + /* Set attenuation to use and low/high range. */ + attenuationSet = (mV > 1800); + if (attenuationSet) { - if (((lnMode == 0) && !setLpVoltage) - || ((lnMode == 1) && !setLnVoltage)) - { - continue; - } + mVlow = 1800; + mVhigh = 3000; + mVdiff = mVhigh - mVlow; + } + else + { + mVlow = 1200; + mVhigh = 1800; + mVdiff = mVhigh - mVlow; + } - ctrlReg = (lnMode ? &EMU->DCDCLNVCTRL : &EMU->DCDCLPVCTRL); - vrefShift = (lnMode ? _EMU_DCDCLNVCTRL_LNVREF_SHIFT - : _EMU_DCDCLPVCTRL_LPVREF_SHIFT); + /* Get 2-point calib data from DEVINFO */ - /* Set attenuation to use */ - attSet = (mV > 1800); - /* Always set mVlow different from mVhigh to avoid division by zero */ - /* further down. */ - if (attSet) + /* LN mode */ + if (attenuationSet) { - mVlow = 1800; - mVhigh = 3000; - attMask = (lnMode ? EMU_DCDCLNVCTRL_LNATT : EMU_DCDCLPVCTRL_LPATT); + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; } else { - mVlow = 1200; - mVhigh = 1800; - attMask = 0; + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; } - /* Get 2-point calib data from DEVINFO, calculate trimming and set voltege */ - if (lnMode) - { - /* Set low-noise DCDC output voltage tuning */ - if (attSet) - { - vrefLow = DEVINFO->DCDCLNVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) - >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; - } - else - { - vrefLow = DEVINFO->DCDCLNVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; - } - } - else - { - /* Set low-power DCDC output voltage tuning */ - /* Get LPCMPBIAS and make sure masks are not overlayed */ - lpcmpBias = EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK; - EFM_ASSERT(!(_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK & attMask)); - switch (attMask | lpcmpBias) - { - case EMU_DCDCLPVCTRL_LPATT: - vrefLow = DEVINFO->DCDCLPVCTRL2; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; - break; - - case EMU_DCDCLPVCTRL_LPATT | 1 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL2; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; - break; - - case EMU_DCDCLPVCTRL_LPATT | 2 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL3; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; - break; - - case EMU_DCDCLPVCTRL_LPATT | 3 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL3; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; - break; - - case 0: - vrefLow = DEVINFO->DCDCLPVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; - break; - - case 1 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; - break; - - case 2 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL1; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; - break; - - case 3 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL1; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; - break; - - default: - EFM_ASSERT(false); - break; - } + /* LP EM234H mode */ + lpcmpBias[dcdcTrimMode_EM234H_LP] = (EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) + >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP], + &vrefHigh[dcdcTrimMode_EM234H_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM234H_LP]); - /* Load LP comparator hysteresis calibration */ - if(!(LpCmpHystCalibrationLoad(attSet, lpcmpBias))) - { - EFM_ASSERT(false); - /* Return when assertions are disabled */ - return false; - } - } /* Low-nise / low-power mode */ +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + /* LP EM01 mode */ + lpcmpBias[dcdcTrimMode_EM01_LP] = (EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT; + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP], + &vrefHigh[dcdcTrimMode_EM01_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM01_LP]); +#endif + + + /* Calculate output voltage trims */ + vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN])) + / mVdiff; + vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN]; + + vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP]; + +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP]; +#endif + + /* Range checks */ + if ((vrefVal[dcdcTrimMode_LN] > vrefHigh[dcdcTrimMode_LN]) + || (vrefVal[dcdcTrimMode_LN] < vrefLow[dcdcTrimMode_LN]) +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + || (vrefVal[dcdcTrimMode_EM01_LP] > vrefHigh[dcdcTrimMode_EM01_LP]) + || (vrefVal[dcdcTrimMode_EM01_LP] < vrefLow[dcdcTrimMode_EM01_LP]) +#endif + || (vrefVal[dcdcTrimMode_EM234H_LP] > vrefHigh[dcdcTrimMode_EM234H_LP]) + || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP])) + { + EFM_ASSERT(false); + /* Return when assertions are disabled */ + return false; + } + /* Update output voltage tuning for LN and LP modes. */ + if (setLnVoltage) + { + EMU->DCDCLNVCTRL = (EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MASK)) + | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0); + } - /* Check for valid 2-point trim values */ - if (mVlow >= mVhigh) + if (setLpVoltage) + { + /* Load LP EM234H comparator hysteresis calibration */ + if(!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP))) { EFM_ASSERT(false); /* Return when assertions are disabled */ return false; } - /* Calculate and set voltage trim */ - vrefVal = ((mV - mVlow) * (vrefHigh - vrefLow)) / (mVhigh - mVlow); - vrefVal += vrefLow; - - /* Range check */ - if ((vrefVal > vrefHigh) || (vrefVal < vrefLow)) +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + /* Load LP EM234H comparator hysteresis calibration */ + if(!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP))) { EFM_ASSERT(false); /* Return when assertions are disabled */ return false; } - /* Update DCDCLNVCTRL/DCDCLPVCTRL */ - *ctrlReg = (vrefVal << vrefShift) | attMask; + /* LP VREF is that max of trims for EM01 and EM234H. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MAX(vrefVal[dcdcTrimMode_EM234H_LP], vrefVal[dcdcTrimMode_EM01_LP]); +#endif + + /* Don't exceed max available code as specified in the reference manual for EMU_DCDCLPVCTRL. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MIN(vrefVal[dcdcTrimMode_EM234H_LP], 0xE7U); + EMU->DCDCLPVCTRL = (EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MASK)) + | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0); } #endif return true; @@ -1969,11 +2289,15 @@ bool EMU_DCDCPowerOff(void) { bool dcdcModeSet; +#if defined(_EMU_PWRCFG_MASK) /* Set DCDCTODVDD only to enable write access to EMU->DCDCCTRL */ EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; +#endif /* Select DVDD as input to the digital regulator */ -#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) +#if defined(EMU_PWRCTRL_IMMEDIATEPWRSWITCH) + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; +#elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD) EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; #endif @@ -2015,7 +2339,7 @@ __STATIC_INLINE uint32_t vmonMilliVoltToFineThreshold(int mV, uint32_t coarseThr * @param[in] vmonInit * VMON initialization struct ******************************************************************************/ -void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit) +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit) { uint32_t thresholdCoarse, thresholdFine; EFM_ASSERT((vmonInit->threshold >= 1200) && (vmonInit->threshold <= 3980)); @@ -2073,7 +2397,7 @@ void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit) * @param[in] vmonInit * VMON Hysteresis initialization struct ******************************************************************************/ -void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit) +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit) { uint32_t riseThresholdCoarse, riseThresholdFine, fallThresholdCoarse, fallThresholdFine; /* VMON supports voltages between 1200 mV and 3980 mV (inclusive) in 20 mV increments */ @@ -2181,20 +2505,20 @@ bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel) } #endif /* EMU_STATUS_VMONRDY */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) -/** +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) +/***************************************************************************//** * @brief * Adjust the bias refresh rate * * @details * This function is only meant to be used under high-temperature operation on - * the first generation EFR32, Pearl and Jade. Adjusting the bias mode will + * EFR32xG1 and EFM32xG1 devices. Adjusting the bias mode will * increase the typical current consumption. See application note 1027 * and errata documents for further details. * * @param [in] mode * The new bias refresh rate - */ + ******************************************************************************/ void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) { #define EMU_TESTLOCK (*(volatile uint32_t *) (EMU_BASE + 0x190)) @@ -2202,37 +2526,37 @@ void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) #define EMU_BIASTESTCTRL (*(volatile uint32_t *) (EMU_BASE + 0x19C)) #define CMU_ULFRCOCTRL (*(volatile uint32_t *) (CMU_BASE + 0x03C)) - uint32_t freq = 0x2; + uint32_t freq = 0x2u; bool emuTestLocked = false; if (mode == emuBiasMode_1KHz) { - freq = 0x0; + freq = 0x0u; } - if (EMU_TESTLOCK == 0x1) + if (EMU_TESTLOCK == 0x1u) { emuTestLocked = true; - EMU_TESTLOCK = 0xADE8; + EMU_TESTLOCK = 0xADE8u; } if (mode == emuBiasMode_Continuous) { - EMU_BIASCONF &= ~0x74; + EMU_BIASCONF &= ~0x74u; } else { - EMU_BIASCONF |= 0x74; + EMU_BIASCONF |= 0x74u; } - EMU_BIASTESTCTRL |= 0x8; - CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00) - | ((freq & 0x3) << 10); - EMU_BIASTESTCTRL &= ~0x8; + EMU_BIASTESTCTRL |= 0x8u; + CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00u) + | ((freq & 0x3u) << 10u); + EMU_BIASTESTCTRL &= ~0x8u; if (emuTestLocked) { - EMU_TESTLOCK = 0; + EMU_TESTLOCK = 0u; } } #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c index 3914e87adf9..bee3af2ea83 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c index 599cfe414e1..15011e06f84 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c @@ -2,7 +2,7 @@ * @file em_gpio.c * @brief General Purpose IO (GPIO) peripheral API * devices. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -148,10 +148,10 @@ void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, * by this function. * * @note - * On platform 1 devices the pin number parameter is not used. The + * On series 0 devices the pin number parameter is not used. The * pin number used on these devices is hardwired to the interrupt with the * same number. @n - * On platform 2 devices, pin number can be selected freely within a group. + * On series 1 devices, pin number can be selected freely within a group. * Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin * number within the interrupt groups are: * 0: pins 0-3 @@ -185,7 +185,7 @@ void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, bool fallingEdge, bool enable) { - uint32_t tmp; + uint32_t tmp = 0; #if !defined(_GPIO_EXTIPINSELL_MASK) (void)pin; #endif @@ -291,12 +291,12 @@ void GPIO_PinModeSet(GPIO_Port_TypeDef port, * register controls pins 0-7 and MODEH controls pins 8-15. */ if (pin < 8) { - GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xF << (pin * 4))) + GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xFu << (pin * 4))) | (mode << (pin * 4)); } else { - GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xF << ((pin - 8) * 4))) + GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xFu << ((pin - 8) * 4))) | (mode << ((pin - 8) * 4)); } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c index d28873105a9..287e0315111 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_i2c.c * @brief Inter-integrated Circuit (I2C) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -77,9 +77,9 @@ #define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST) /* Max I2C transmission rate constant */ -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) #define I2C_CR_MAX 4 -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) #define I2C_CR_MAX 8 #else #warning "Max I2C transmission rate constant is not defined" @@ -257,21 +257,21 @@ void I2C_BusFreqSet(I2C_TypeDef *i2c, switch(i2cMode) { case i2cClockHLRStandard: -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) minFreq = 4200000; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) minFreq = 2000000; break; #endif case i2cClockHLRAsymetric: -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) minFreq = 11000000; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) minFreq = 5000000; break; #endif case i2cClockHLRFast: -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) minFreq = 24400000; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) minFreq = 14000000; break; #endif } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c index 1dfc2b6d5b2..7d6428eac94 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_idac.c * @brief Current Digital to Analog Converter (IDAC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -48,7 +48,8 @@ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Fix for errata IDAC_E101 - IDAC output current degradation */ -#if defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY) +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY)) #define ERRATA_FIX_IDAC_E101_EN #endif /** @endcond */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c index ed84185d642..32ef970104f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c @@ -1,7 +1,7 @@ /**************************************************************************//** * @file em_int.c * @brief Interrupt enable/disable unit API - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c index 99833a8d363..5a8b05893bc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lcd.c * @brief Liquid Crystal Display (LCD) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c index 9a1718016e8..1a2f8a1f159 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ldma.c * @brief Direct memory access (LDMA) module peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c index 88e7d65c21b..aee2ec75976 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lesense.c * @brief Low Energy Sensor (LESENSE) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -31,9 +31,8 @@ ******************************************************************************/ #include "em_lesense.h" -/* LESENSE is currently only supported on Platform 1. Full support for Platform 2 LESENSE - will be included in the next release. */ -#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) && defined(_SILICON_LABS_32B_PLATFORM_1) + +#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) #include "em_assert.h" #include "em_bus.h" #include "em_cmu.h" @@ -60,6 +59,22 @@ * @{ ******************************************************************************/ +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_LESENSE_ROUTE_MASK) +#define GENERIC_LESENSE_ROUTE LESENSE->ROUTE +#else +#define GENERIC_LESENSE_ROUTE LESENSE->ROUTEPEN +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) +/* DACOUT mode only available on channel 0,1,2,3,12,13,14,15 */ +#define DACOUT_SUPPORT 0xF00F +#else +/* DACOUT mode only available on channel 4,5,7,10,12,13 */ +#define DACOUT_SUPPORT 0x34B0 +#endif +/** @endcond */ + /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ @@ -100,11 +115,13 @@ * Request to call @ref LESENSE_Reset() first in order to initialize all * LESENSE registers with the default value. ******************************************************************************/ -void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) +void LESENSE_Init(const LESENSE_Init_TypeDef * init, bool reqReset) { /* Sanity check of initialization values */ EFM_ASSERT((uint32_t)init->timeCtrl.startDelay < 4U); +#if defined(_LESENSE_PERCTRL_DACPRESC_MASK) EFM_ASSERT((uint32_t)init->perCtrl.dacPresc < 32U); +#endif /* Reset LESENSE registers if requested. */ if (reqReset) @@ -114,6 +131,11 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) /* Set sensor start delay for each channel. */ LESENSE_StartDelaySet((uint32_t)init->timeCtrl.startDelay); +#if defined(_LESENSE_TIMCTRL_AUXSTARTUP_MASK) + /* Configure the AUXHRFCO startup delay. */ + LESENSE->TIMCTRL = (LESENSE->TIMCTRL & (~_LESENSE_TIMCTRL_AUXSTARTUP_MASK)) + | (init->timeCtrl.delayAuxStartup << _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT); +#endif /* LESENSE core control configuration. * Set PRS source, SCANCONF register usage strategy, interrupt and @@ -127,8 +149,10 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) | (uint32_t)init->coreCtrl.scanConfSel | (uint32_t)init->coreCtrl.bufTrigLevel | (uint32_t)init->coreCtrl.wakeupOnDMA +#if defined(_LESENSE_CTRL_ACMP0INV_MASK) | ((uint32_t)init->coreCtrl.invACMP0 << _LESENSE_CTRL_ACMP0INV_SHIFT) | ((uint32_t)init->coreCtrl.invACMP1 << _LESENSE_CTRL_ACMP1INV_SHIFT) +#endif | ((uint32_t)init->coreCtrl.dualSample << _LESENSE_CTRL_DUALSAMPLE_SHIFT) | ((uint32_t)init->coreCtrl.storeScanRes << _LESENSE_CTRL_STRSCANRES_SHIFT) | ((uint32_t)init->coreCtrl.bufOverWr << _LESENSE_CTRL_BUFOW_SHIFT) @@ -144,15 +168,24 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) * duty cycle (warm up) mode. */ LESENSE->PERCTRL = ((uint32_t)init->perCtrl.dacCh0Data << _LESENSE_PERCTRL_DACCH0DATA_SHIFT) + | ((uint32_t)init->perCtrl.dacCh1Data << _LESENSE_PERCTRL_DACCH1DATA_SHIFT) +#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK) | ((uint32_t)init->perCtrl.dacCh0ConvMode << _LESENSE_PERCTRL_DACCH0CONV_SHIFT) | ((uint32_t)init->perCtrl.dacCh0OutMode << _LESENSE_PERCTRL_DACCH0OUT_SHIFT) - | ((uint32_t)init->perCtrl.dacCh1Data << _LESENSE_PERCTRL_DACCH1DATA_SHIFT) | ((uint32_t)init->perCtrl.dacCh1ConvMode << _LESENSE_PERCTRL_DACCH1CONV_SHIFT) | ((uint32_t)init->perCtrl.dacCh1OutMode << _LESENSE_PERCTRL_DACCH1OUT_SHIFT) | ((uint32_t)init->perCtrl.dacPresc << _LESENSE_PERCTRL_DACPRESC_SHIFT) | (uint32_t)init->perCtrl.dacRef +#endif | ((uint32_t)init->perCtrl.acmp0Mode << _LESENSE_PERCTRL_ACMP0MODE_SHIFT) | ((uint32_t)init->perCtrl.acmp1Mode << _LESENSE_PERCTRL_ACMP1MODE_SHIFT) +#if defined(_LESENSE_PERCTRL_ACMP0INV_MASK) + | ((uint32_t)init->coreCtrl.invACMP0 << _LESENSE_PERCTRL_ACMP0INV_SHIFT) + | ((uint32_t)init->coreCtrl.invACMP1 << _LESENSE_PERCTRL_ACMP1INV_SHIFT) +#endif +#if defined(_LESENSE_PERCTRL_DACCONVTRIG_MASK) + | ((uint32_t)init->perCtrl.dacScan << _LESENSE_PERCTRL_DACCONVTRIG_SHIFT) +#endif | (uint32_t)init->perCtrl.warmupMode; /* LESENSE decoder general control configuration. @@ -211,7 +244,7 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) * Frequency in Hz calculated and set by this function. Users can use this to * compare the requested and set values. ******************************************************************************/ -uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t const scanFreq) +uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t scanFreq) { uint32_t tmp; uint32_t pcPresc = 0UL; /* Period counter prescaler. */ @@ -293,8 +326,8 @@ uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t const scanFreq) * @param[in] start * If true, LESENSE_ScanStart() is immediately issued after configuration. ******************************************************************************/ -void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef const scanMode, - bool const start) +void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef scanMode, + bool start) { uint32_t tmp; /* temporary storage of the CTRL register value */ @@ -335,7 +368,7 @@ void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef const scanMode, * @param[in] startDelay * Number of LFACLK cycles to delay. Valid range: 0-3 (2 bit). ******************************************************************************/ -void LESENSE_StartDelaySet(uint8_t const startDelay) +void LESENSE_StartDelaySet(uint8_t startDelay) { uint32_t tmp; /* temporary storage of the TIMCTRL register value */ @@ -378,8 +411,8 @@ void LESENSE_StartDelaySet(uint8_t const startDelay) * @param[in] clkDiv * Clock divisor value. Valid range depends on the @p clk value. ******************************************************************************/ -void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef const clk, - LESENSE_ClkPresc_TypeDef const clkDiv) +void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef clk, + LESENSE_ClkPresc_TypeDef clkDiv) { uint32_t tmp; @@ -440,12 +473,12 @@ void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef const clk, * @param[in] confChAll * Configuration structure for all (16) LESENSE sensor channels. ******************************************************************************/ -void LESENSE_ChannelAllConfig(LESENSE_ChAll_TypeDef const *confChAll) +void LESENSE_ChannelAllConfig(const LESENSE_ChAll_TypeDef * confChAll) { uint32_t i; /* Iterate through all the 16 channels */ - for (i = 0U; i < 16U; ++i) + for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i) { /* Configure scan channels. */ LESENSE_ChannelConfig(&confChAll->Ch[i], i); @@ -475,26 +508,31 @@ void LESENSE_ChannelAllConfig(LESENSE_ChAll_TypeDef const *confChAll) * @param[in] chIdx * Channel index to configure (0-15). ******************************************************************************/ -void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, - uint32_t const chIdx) +void LESENSE_ChannelConfig(const LESENSE_ChDesc_TypeDef * confCh, + uint32_t chIdx) { uint32_t tmp; /* Service variable. */ /* Sanity check of configuration parameters */ - EFM_ASSERT(chIdx < 16U); - EFM_ASSERT(confCh->exTime < 64U); - EFM_ASSERT(confCh->sampleDelay < 128U); - EFM_ASSERT(confCh->measDelay < 128U); + EFM_ASSERT(chIdx < LESENSE_NUM_CHANNELS); + EFM_ASSERT(confCh->exTime <= (_LESENSE_CH_TIMING_EXTIME_MASK >> _LESENSE_CH_TIMING_EXTIME_SHIFT)); + EFM_ASSERT(confCh->measDelay <= (_LESENSE_CH_TIMING_MEASUREDLY_MASK >> _LESENSE_CH_TIMING_MEASUREDLY_SHIFT)); +#if defined(_SILICON_LABS_32B_SERIES_0) + // Sample delay on other devices are 8 bits which fits perfectly in uint8_t + EFM_ASSERT(confCh->sampleDelay <= (_LESENSE_CH_TIMING_SAMPLEDLY_MASK >> _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT)); +#endif + /* Not a complete assert, as the max. value of acmpThres depends on other * configuration parameters, check the parameter description of acmpThres for * for more details! */ EFM_ASSERT(confCh->acmpThres < 4096U); - EFM_ASSERT(!(confCh->chPinExMode == lesenseChPinExDACOut - && (chIdx != 2U) - && (chIdx != 3U) - && (chIdx != 4U) - && (chIdx != 5U))); + if (confCh->chPinExMode == lesenseChPinExDACOut) + { + EFM_ASSERT((0x1 << chIdx) & DACOUT_SUPPORT); + } + +#if defined(_LESENSE_IDLECONF_CH0_DACCH0) EFM_ASSERT(!(confCh->chPinIdleMode == lesenseChPinIdleDACCh1 && ((chIdx != 12U) && (chIdx != 13U) @@ -505,6 +543,7 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, && (chIdx != 1U) && (chIdx != 2U) && (chIdx != 3U)))); +#endif /* Configure chIdx setup in LESENSE idle phase. * Read-modify-write in order to support reconfiguration during LESENSE @@ -516,9 +555,9 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, /* Channel specific timing configuration on scan channel chIdx. * Set excitation time, sampling delay, measurement delay. */ LESENSE_ChannelTimingSet(chIdx, - (uint32_t)confCh->exTime, - (uint32_t)confCh->sampleDelay, - (uint32_t)confCh->measDelay); + confCh->exTime, + confCh->sampleDelay, + confCh->measDelay); /* Channel specific configuration of clocks, sample mode, excitation pin mode * alternate excitation usage and interrupt mode on scan channel chIdx in @@ -538,22 +577,26 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, (uint32_t)confCh->compMode | ((uint32_t)confCh->shiftRes << _LESENSE_CH_EVAL_DECODE_SHIFT) | ((uint32_t)confCh->storeCntRes << _LESENSE_CH_EVAL_STRSAMPLE_SHIFT) - | ((uint32_t)confCh->invRes << _LESENSE_CH_EVAL_SCANRESINV_SHIFT); + | ((uint32_t)confCh->invRes << _LESENSE_CH_EVAL_SCANRESINV_SHIFT) +#if defined(_LESENSE_CH_EVAL_MODE_MASK) + | ((uint32_t)confCh->evalMode << _LESENSE_CH_EVAL_MODE_SHIFT) +#endif + ; /* Configure analog comparator (ACMP) threshold and decision threshold for * counter separately with the function provided for that. */ LESENSE_ChannelThresSet(chIdx, - (uint32_t)confCh->acmpThres, - (uint32_t)confCh->cntThres); + confCh->acmpThres, + confCh->cntThres); /* Enable/disable interrupts on channel */ - BUS_RegBitWrite(&(LESENSE->IEN), chIdx, confCh->enaInt); + BUS_RegBitWrite(&LESENSE->IEN, chIdx, confCh->enaInt); /* Enable/disable CHchIdx pin. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), chIdx, confCh->enaPin); + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, chIdx, confCh->enaPin); /* Enable/disable scan channel chIdx. */ - BUS_RegBitWrite(&(LESENSE->CHEN), chIdx, confCh->enaScanCh); + BUS_RegBitWrite(&LESENSE->CHEN, chIdx, confCh->enaScanCh); } @@ -574,7 +617,7 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, * @param[in] confAltEx * Configuration structure for LESENSE alternate excitation pins. ******************************************************************************/ -void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) +void LESENSE_AltExConfig(const LESENSE_ConfAltEx_TypeDef * confAltEx) { uint32_t i; uint32_t tmp; @@ -583,7 +626,7 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) /* Configure alternate excitation mapping. * Atomic read-modify-write using BUS_RegBitWrite function in order to * support reconfiguration during LESENSE operation. */ - BUS_RegBitWrite(&(LESENSE->CTRL), + BUS_RegBitWrite(&LESENSE->CTRL, _LESENSE_CTRL_ALTEXMAP_SHIFT, confAltEx->altExMap); @@ -596,7 +639,7 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) /* Enable/disable alternate excitation pin i. * Atomic read-modify-write using BUS_RegBitWrite function in order to * support reconfiguration during LESENSE operation. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, (16UL + i), confAltEx->AltEx[i].enablePin); @@ -608,20 +651,24 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) LESENSE->ALTEXCONF = tmp; /* Enable/disable always excite on channel i */ - BUS_RegBitWrite(&(LESENSE->ALTEXCONF), + BUS_RegBitWrite(&LESENSE->ALTEXCONF, (16UL + i), confAltEx->AltEx[i].alwaysEx); } break; +#if defined(_LESENSE_CTRL_ALTEXMAP_ACMP) case lesenseAltExMapACMP: +#else + case lesenseAltExMapCH: +#endif /* Iterate through all the 16 alternate excitation channels */ for (i = 0U; i < 16U; ++i) { /* Enable/disable alternate ACMP excitation channel pin i. */ /* Atomic read-modify-write using BUS_RegBitWrite function in order to * support reconfiguration during LESENSE operation. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, i, confAltEx->AltEx[i].enablePin); } @@ -658,18 +705,18 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) * @param[in] enaPin * Enable/disable the pin assigned to the channel selected by @p chIdx. ******************************************************************************/ -void LESENSE_ChannelEnable(uint8_t const chIdx, - bool const enaScanCh, - bool const enaPin) +void LESENSE_ChannelEnable(uint8_t chIdx, + bool enaScanCh, + bool enaPin) { /* Enable/disable the assigned pin of scan channel chIdx. * Note: BUS_RegBitWrite() function is used for setting/clearing single * bit peripheral register bitfields. Read the function description in * em_bus.h for more details. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), chIdx, enaPin); + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, chIdx, enaPin); /* Enable/disable scan channel chIdx. */ - BUS_RegBitWrite(&(LESENSE->CHEN), chIdx, enaScanCh); + BUS_RegBitWrite(&LESENSE->CHEN, chIdx, enaScanCh); } @@ -700,7 +747,7 @@ void LESENSE_ChannelEnableMask(uint16_t chMask, uint16_t pinMask) /* Enable/disable all channels at once according to the mask. */ LESENSE->CHEN = chMask; /* Enable/disable all channel pins at once according to the mask. */ - LESENSE->ROUTE = pinMask; + GENERIC_LESENSE_ROUTE = pinMask; } @@ -732,15 +779,18 @@ void LESENSE_ChannelEnableMask(uint16_t chMask, uint16_t pinMask) * Measure delay on chIdx. Sensor measuring is delayed for measDelay+1 * excitation clock cycles. Valid range: 0-127 (7 bits). ******************************************************************************/ -void LESENSE_ChannelTimingSet(uint8_t const chIdx, - uint8_t const exTime, - uint8_t const sampleDelay, - uint8_t const measDelay) +void LESENSE_ChannelTimingSet(uint8_t chIdx, + uint8_t exTime, + uint8_t sampleDelay, + uint16_t measDelay) { /* Sanity check of parameters. */ - EFM_ASSERT(exTime < 64U); - EFM_ASSERT(sampleDelay < 128U); - EFM_ASSERT(measDelay < 128U); + EFM_ASSERT(exTime <= (_LESENSE_CH_TIMING_EXTIME_MASK >> _LESENSE_CH_TIMING_EXTIME_SHIFT)); + EFM_ASSERT(measDelay <= (_LESENSE_CH_TIMING_MEASUREDLY_MASK >> _LESENSE_CH_TIMING_MEASUREDLY_SHIFT)); +#if defined(_SILICON_LABS_32B_SERIES_0) + // Sample delay on other devices are 8 bits which fits perfectly in uint8_t + EFM_ASSERT(sampleDelay <= (_LESENSE_CH_TIMING_SAMPLEDLY_MASK >> _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT)); +#endif /* Channel specific timing configuration on scan channel chIdx. * Setting excitation time, sampling delay, measurement delay. */ @@ -784,9 +834,9 @@ void LESENSE_ChannelTimingSet(uint8_t const chIdx, * Decision threshold for counter comparison. * Valid range: 0-65535 (16 bits). ******************************************************************************/ -void LESENSE_ChannelThresSet(uint8_t const chIdx, - uint16_t const acmpThres, - uint16_t const cntThres) +void LESENSE_ChannelThresSet(uint8_t chIdx, + uint16_t acmpThres, + uint16_t cntThres) { uint32_t tmp; /* temporary storage */ @@ -794,13 +844,13 @@ void LESENSE_ChannelThresSet(uint8_t const chIdx, /* Sanity check for acmpThres only, cntThres is 16bit value. */ EFM_ASSERT(acmpThres < 4096U); /* Sanity check for LESENSE channel id. */ - EFM_ASSERT(chIdx < 16); + EFM_ASSERT(chIdx < LESENSE_NUM_CHANNELS); /* Save the INTERACT register value of channel chIdx to tmp. * Please be aware the effects of the non-atomic Read-Modify-Write cycle! */ - tmp = LESENSE->CH[chIdx].INTERACT & ~(_LESENSE_CH_INTERACT_ACMPTHRES_MASK); + tmp = LESENSE->CH[chIdx].INTERACT & ~(0xFFF); /* Set the ACMP threshold value to the INTERACT register of channel chIdx. */ - tmp |= (uint32_t)acmpThres << _LESENSE_CH_INTERACT_ACMPTHRES_SHIFT; + tmp |= (uint32_t)acmpThres; /* Write the new value to the INTERACT register. */ LESENSE->CH[chIdx].INTERACT = tmp; @@ -813,6 +863,122 @@ void LESENSE_ChannelThresSet(uint8_t const chIdx, LESENSE->CH[chIdx].EVAL = tmp; } +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +/***************************************************************************//** + * @brief + * Configure Sliding Window evaluation mode for a specific channel + * + * @details + * This function will configure the evaluation mode, the initial + * sensor measurement (COMPTHRES) and the window size. For other channel + * related configuration see the @ref LESENSE_ChannelConfig() function. + * + * @warning + * Beware that the step size and window size configuration are global to all + * LESENSE channels and use the same register field in the hardware. This + * means that any windowSize configuration passed to this function will + * apply for all channels and override all other stepSize/windowSize + * configurations. + * + * @param[in] chIdx + * Identifier of the scan channel. Valid range: 0-15. + * + * @param[in] windowSize + * Window size to be used on all channels. + * + * @param[in] initValue + * The initial sensor value for the channel. + ******************************************************************************/ +void LESENSE_ChannelSlidingWindow(uint8_t chIdx, + uint32_t windowSize, + uint32_t initValue) +{ + LESENSE_CH_TypeDef * ch = &LESENSE->CH[chIdx]; + + LESENSE_WindowSizeSet(windowSize); + ch->EVAL = (ch->EVAL & ~(_LESENSE_CH_EVAL_COMPTHRES_MASK | _LESENSE_CH_EVAL_MODE_MASK)) + | (initValue << _LESENSE_CH_EVAL_COMPTHRES_SHIFT) + | LESENSE_CH_EVAL_MODE_SLIDINGWIN; +} + +/***************************************************************************//** + * @brief + * Configure step detection evaluation mode for a specific channel + * + * @details + * This function will configure the evaluation mode, the initial + * sensor measurement (COMPTHRES) and the window size. For other channel + * related configuration see the @ref LESENSE_ChannelConfig() function. + * + * @warning + * Beware that the step size and window size configuration are global to all + * LESENSE channels and use the same register field in the hardware. This + * means that any stepSize configuration passed to this function will + * apply for all channels and override all other stepSize/windowSize + * configurations. + * + * @param[in] chIdx + * Identifier of the scan channel. Valid range: 0-15. + * + * @param[in] stepSize + * Step size to be used on all channels. + * + * @param[in] initValue + * The initial sensor value for the channel. + ******************************************************************************/ +void LESENSE_ChannelStepDetection(uint8_t chIdx, + uint32_t stepSize, + uint32_t initValue) +{ + LESENSE_CH_TypeDef * ch = &LESENSE->CH[chIdx]; + + LESENSE_StepSizeSet(stepSize); + ch->EVAL = (ch->EVAL & ~(_LESENSE_CH_EVAL_COMPTHRES_MASK | _LESENSE_CH_EVAL_MODE_MASK)) + | (initValue << _LESENSE_CH_EVAL_COMPTHRES_SHIFT) + | LESENSE_CH_EVAL_MODE_STEPDET; +} + +/***************************************************************************//** + * @brief + * Set the window size for all LESENSE channels. + * + * @details + * The window size is used by all channels that are configured as + * @ref lesenseEvalModeSlidingWindow. + * + * @warning + * The window size configuration is using the same register field as the + * step detection size. So the window size configuration will have an + * effect on channels configured with the @ref lesenseEvalModeStepDetection + * evaluation mode as well. + * + * @param[in] windowSize + * The window size to use for all channels. + ******************************************************************************/ +void LESENSE_WindowSizeSet(uint32_t windowSize) +{ + LESENSE->EVALCTRL = (LESENSE->EVALCTRL & ~_LESENSE_EVALCTRL_WINSIZE_MASK) + | windowSize; +} + +/***************************************************************************//** + * @brief + * Set the step size for all LESENSE channels. + * + * @details + * The step size is configured using the same register field as use to + * configure window size. So calling this function will overwrite any + * previously configured window size as done by the + * @ref LESENSE_WindowSizeSet() function. + * + * @param[in] stepSize + * The step size to use for all channels. + ******************************************************************************/ +void LESENSE_StepSizeSet(uint32_t stepSize) +{ + LESENSE_WindowSizeSet(stepSize); +} +#endif /***************************************************************************//** * @brief @@ -828,14 +994,14 @@ void LESENSE_ChannelThresSet(uint8_t const chIdx, * LESENSE_DecoderStateConfig() function. * * @param[in] confDecStAll - * Configuration structure for all (16) LESENSE decoder states. + * Configuration structure for all (16 or 32) LESENSE decoder states. ******************************************************************************/ -void LESENSE_DecoderStateAllConfig(LESENSE_DecStAll_TypeDef const *confDecStAll) +void LESENSE_DecoderStateAllConfig(const LESENSE_DecStAll_TypeDef * confDecStAll) { uint32_t i; - /* Iterate through all the 16 decoder states. */ - for (i = 0U; i < 16U; ++i) + /* Iterate through all the 16 or 32 decoder states. */ + for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i) { /* Configure decoder state i. */ LESENSE_DecoderStateConfig(&confDecStAll->St[i], i); @@ -856,19 +1022,19 @@ void LESENSE_DecoderStateAllConfig(LESENSE_DecStAll_TypeDef const *confDecStAll) * Configuration structure for a single LESENSE decoder state. * * @param[in] decSt - * Decoder state index to configure (0-15). + * Decoder state index to configure (0-15) or (0-31) depending on device. ******************************************************************************/ -void LESENSE_DecoderStateConfig(LESENSE_DecStDesc_TypeDef const *confDecSt, - uint32_t const decSt) +void LESENSE_DecoderStateConfig(const LESENSE_DecStDesc_TypeDef * confDecSt, + uint32_t decSt) { /* Sanity check of configuration parameters */ - EFM_ASSERT(decSt < 16U); + EFM_ASSERT(decSt < LESENSE_NUM_DECODER_STATES); EFM_ASSERT((uint32_t)confDecSt->confA.compMask < 16U); EFM_ASSERT((uint32_t)confDecSt->confA.compVal < 16U); - EFM_ASSERT((uint32_t)confDecSt->confA.nextState < 16U); + EFM_ASSERT((uint32_t)confDecSt->confA.nextState < LESENSE_NUM_DECODER_STATES); EFM_ASSERT((uint32_t)confDecSt->confB.compMask < 16U); EFM_ASSERT((uint32_t)confDecSt->confB.compVal < 16U); - EFM_ASSERT((uint32_t)confDecSt->confB.nextState < 16U); + EFM_ASSERT((uint32_t)confDecSt->confB.nextState < LESENSE_NUM_DECODER_STATES); /* Configure state descriptor A (LESENSE_STi_TCONFA) for decoder state i. * Setting sensor compare value, sensor mask, next state index, @@ -907,11 +1073,12 @@ void LESENSE_DecoderStateConfig(LESENSE_DecStDesc_TypeDef const *confDecSt, * enabling the decoder! * * @param[in] decSt - * Decoder state to set as current state. Valid range: 0-15 + * Decoder state to set as current state. Valid range: 0-15 or 0-31 + * depending on device. ******************************************************************************/ void LESENSE_DecoderStateSet(uint32_t decSt) { - EFM_ASSERT(decSt < 16U); + EFM_ASSERT(decSt <= _LESENSE_DECSTATE_DECSTATE_MASK); LESENSE->DECSTATE = decSt & _LESENSE_DECSTATE_DECSTATE_MASK; } @@ -930,6 +1097,28 @@ uint32_t LESENSE_DecoderStateGet(void) return LESENSE->DECSTATE & _LESENSE_DECSTATE_DECSTATE_MASK; } +#if defined(_LESENSE_PRSCTRL_MASK) +/***************************************************************************//** + * @brief + * Enable or disable PRS output from the LESENSE decoder. + * + * @param[in] enable + * enable/disable the PRS output from the LESENSE decoder. true to enable and + * false to disable. + * + * @param[in] decMask + * Decoder state compare value mask + * + * @param[in] decVal + * Decoder state compare value. + ******************************************************************************/ +void LESENSE_DecoderPrsOut(bool enable, uint32_t decMask, uint32_t decVal) +{ + LESENSE->PRSCTRL = (enable << _LESENSE_PRSCTRL_DECCMPEN_SHIFT) + | (decMask << _LESENSE_PRSCTRL_DECCMPMASK_SHIFT) + | (decVal << _LESENSE_PRSCTRL_DECCMPVAL_SHIFT); +} +#endif /***************************************************************************//** * @brief @@ -1092,15 +1281,23 @@ void LESENSE_Reset(void) LESENSE->PERCTRL = _LESENSE_PERCTRL_RESETVALUE; LESENSE->DECCTRL = _LESENSE_DECCTRL_RESETVALUE; LESENSE->BIASCTRL = _LESENSE_BIASCTRL_RESETVALUE; +#if defined(_LESENSE_EVALCTRL_MASK) + LESENSE->EVALCTRL = _LESENSE_EVALCTRL_RESETVALUE; + LESENSE->PRSCTRL = _LESENSE_PRSCTRL_RESETVALUE; +#endif LESENSE->CHEN = _LESENSE_CHEN_RESETVALUE; LESENSE->IDLECONF = _LESENSE_IDLECONF_RESETVALUE; LESENSE->ALTEXCONF = _LESENSE_ALTEXCONF_RESETVALUE; /* Disable LESENSE to control GPIO pins */ - LESENSE->ROUTE = _LESENSE_ROUTE_RESETVALUE; +#if defined(_LESENSE_ROUTE_MASK) + LESENSE->ROUTE = _LESENSE_ROUTE_RESETVALUE; +#else + LESENSE->ROUTEPEN = _LESENSE_ROUTEPEN_RESETVALUE; +#endif /* Reset all channel configuration registers */ - for (i = 0U; i < 16U; ++i) + for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i) { LESENSE->CH[i].TIMING = _LESENSE_CH_TIMING_RESETVALUE; LESENSE->CH[i].INTERACT = _LESENSE_CH_INTERACT_RESETVALUE; @@ -1108,7 +1305,7 @@ void LESENSE_Reset(void) } /* Reset all decoder state configuration registers */ - for (i = 0U; i < 16U; ++i) + for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i) { LESENSE->ST[i].TCONFA = _LESENSE_ST_TCONFA_RESETVALUE; LESENSE->ST[i].TCONFB = _LESENSE_ST_TCONFB_RESETVALUE; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c index 666aa4a19b6..7281084139e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_letimer.c * @brief Low Energy Timer (LETIMER) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c index 30e6e68565e..b96dee30600 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c @@ -2,7 +2,7 @@ * @file em_leuart.c * @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) * Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c index acaad77aae5..066de510824 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_mpu.c * @brief Memory Protection Unit (MPU) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c index 30c14dc9711..6bc3975f04e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_msc.c * @brief Flash controller (MSC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -57,8 +57,8 @@ #define WORDS_PER_DATA_PHASE (1) #endif +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) /* Fix for errata FLASH_E201 - Potential program failure after Power On */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) #define ERRATA_FIX_FLASH_E201_EN #endif @@ -159,6 +159,13 @@ void MSC_Init(void) #if defined( _MSC_TIMEBASE_MASK ) uint32_t freq, cycles; #endif + +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* VSCALE must be done and flash erase and write requires VSCALE2 */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + /* Unlock the MSC */ MSC->LOCK = MSC_UNLOCK_CODE; /* Disable writing to the flash */ @@ -382,7 +389,7 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, { uint32_t timeOut; uint32_t wordIndex; - uint32_t wordsPerDataPhase; + bool useWDouble = false; MSC_Status_TypeDef retval = mscReturnOk; #if !defined( _EFM32_GECKO_FAMILY ) uint32_t irqState; @@ -392,6 +399,7 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, /* If LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word) */ if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE)) { +#if defined(_SILICON_LABS_32B_SERIES_0) /* If the number of words to be written are odd, we need to align by writing a single word first, before setting the WDOUBLE bit. */ if (numWords & 0x1) @@ -431,14 +439,11 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, } /* Now we can set the double word option in order to write two words per data phase. */ +#endif MSC->WRITECTRL |= MSC_WRITECTRL_WDOUBLE; - wordsPerDataPhase = 2; + useWDouble = true; } - else #endif /* defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) */ - { - wordsPerDataPhase = 1; - } /* Write the rest as double word write if wordsPerDataPhase == 2 */ if (numWords > 0) @@ -451,34 +456,34 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, wordIndex = 0; while(wordIndex < numWords) { - MSC->WDATA = *data++; - wordIndex++; - if (wordsPerDataPhase == 1) + if (!useWDouble) { + MSC->WDATA = *data++; + wordIndex++; MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; } - else if (wordsPerDataPhase == 2) + + else // useWDouble == true { + /* Trigger double write according to flash properties. */ +#if defined(_SILICON_LABS_32B_SERIES_0) + MSC->WDATA = *data++; while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)); MSC->WDATA = *data++; - wordIndex++; - - /* Trigger double write. Platform 1 and 2 - have different trigger behavior for - double word write as described in the - reference manual for MSC_WRITECMD_WRITEONCE - and WRITETRIG. */ -#if defined(_SILICON_LABS_32B_PLATFORM_1) + wordIndex += 2; MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; -#else + +#elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) + while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)); + do + { + MSC->WDATA = *data++; + wordIndex++; + } while ((MSC->STATUS & MSC_STATUS_WDATAREADY) + && (wordIndex < numWords)); MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; #endif } - else - { - /* Not supported. */ - EFM_ASSERT(false); - } /* Wait for the transaction to finish. */ timeOut = MSC_PROGRAM_TIMEOUT; @@ -539,14 +544,37 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; } } - MSC->WDATA = *data; - if ((wordsPerDataPhase == 1) - || ((wordsPerDataPhase == 2) && (wordIndex & 0x1))) + + if (!useWDouble) { + MSC->WDATA = *data; MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; + data++; + wordIndex++; + } + + else // useWDouble == true + { + /* Trigger double write according to flash properties. */ +#if defined(_SILICON_LABS_32B_SERIES_0) + MSC->WDATA = *data; + if (wordIndex & 0x1) + { + MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; + } + data++; + wordIndex++; + +#elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) + do + { + MSC->WDATA = *data++; + wordIndex++; + } while ((MSC->STATUS & MSC_STATUS_WDATAREADY) + && (wordIndex < numWords)); + MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; +#endif } - data++; - wordIndex++; } if (irqState == 0) @@ -587,8 +615,8 @@ MSC_RAMFUNC_DEFINITION_END * Write address * @param[in] data * Pointer to the first data word to load. - * @param[in] numWords - * Number of data words (32-bit) to load. + * @param[in] numBytes + * Number of data bytes to load, must be a multiple of 4 bytes. * @param[in] writeStrategy * Write strategy to apply. * @return @@ -612,6 +640,12 @@ MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address, /* Check number of bytes. Must be divisable by four */ EFM_ASSERT((numBytes & 0x3) == 0); +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* VSCALE must be done and flash write requires VSCALE2 */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + /* Enable writing to the MSC */ MSC->WRITECTRL |= MSC_WRITECTRL_WREN; @@ -717,6 +751,11 @@ MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) /* Address must be aligned to pages */ EFM_ASSERT((((uint32_t) startAddress) & (FLASH_PAGE_SIZE - 1)) == 0); +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* VSCALE must be done and flash erase requires VSCALE2 */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif /* Enable writing to the MSC */ MSC->WRITECTRL |= MSC_WRITECTRL_WREN; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c index 6963ab69f18..a342cd7bbdc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c @@ -1,7 +1,7 @@ /**************************************************************************//** * @file em_opamp.c * @brief Operational Amplifier (OPAMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -31,7 +31,8 @@ ******************************************************************************/ #include "em_opamp.h" -#if defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) +#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ + || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) #include "em_system.h" #include "em_assert.h" @@ -50,8 +51,13 @@ * @li OPAMP_Enable() Configure and enable an opamp. * @li OPAMP_Disable() Disable an opamp. * + * @if DOXYDOC_P1_DEVICE * All OPAMP functions assume that the DAC clock is running. If the DAC is not * used, the clock can be turned off when the opamp's are configured. + * @elseif DOXYDOC_P2_DEVICE + * All OPAMP functions assume that the VDAC clock is running. If the VDAC is not + * used, the clock can be turned off when the opamp's are configured. + * @endif * * If the available gain values dont suit the application at hand, the resistor * ladders can be disabled and external gain programming resistors used. @@ -64,8 +70,12 @@ * pads should be connected to a suitable signal ground. * * \nUnity gain voltage follower.\n + * @if DOXYDOC_P1_DEVICE * Use predefined macros @ref OPA_INIT_UNITY_GAIN and * @ref OPA_INIT_UNITY_GAIN_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_UNITY_GAIN. + * @endif * @verbatim |\ @@ -78,8 +88,12 @@ @endverbatim * * \nNon-inverting amplifier.\n + * @if DOXYDOC_P1_DEVICE * Use predefined macros @ref OPA_INIT_NON_INVERTING and * @ref OPA_INIT_NON_INVERTING_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_NON_INVERTING. + * @endif * @verbatim |\ @@ -95,8 +109,12 @@ NEGPAD @endverbatim * * \nInverting amplifier.\n + * @if DOXYDOC_P1_DEVICE * Use predefined macros @ref OPA_INIT_INVERTING and * @ref OPA_INIT_INVERTING_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_INVERTING. + * @endif * @verbatim _____R2____ @@ -185,6 +203,36 @@ |___________| @endverbatim * + * @if DOXYDOC_P2_DEVICE + * \nInstrumentation amplifier.\n + * Use predefined macros @ref OPA_INIT_INSTR_AMP_OPA0 and + * @ref OPA_INIT_INSTR_AMP_OPA0. + * @verbatim + + |\ + __________|+\ OPA1 + | \______________ + ___|_ / | + | | / | + | |/ R2 + |____________| + | + R1 + | + R1 + ____________| + | | + | R2 + | |\ | + |___|+\ OPA0 | + | \_____|________ + __________|_ / + | / + |/ + + @endverbatim + * @endif + * * @{ ******************************************************************************/ @@ -196,14 +244,27 @@ * @brief * Disable an Operational Amplifier. * + * @if DOXYDOC_P1_DEVICE * @param[in] dac * Pointer to DAC peripheral register block. + * @elseif DOXYDOC_P2_DEVICE + * @param[in] dac + * Pointer to VDAC peripheral register block. + * @endif + * * * @param[in] opa * Selects an OPA, valid vaules are @ref OPA0, @ref OPA1 and @ref OPA2. ******************************************************************************/ -void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) +void OPAMP_Disable( +#if defined(_SILICON_LABS_32B_SERIES_0) + DAC_TypeDef *dac, +#elif defined(_SILICON_LABS_32B_SERIES_1) + VDAC_TypeDef *dac, +#endif + OPAMP_TypeDef opa) { +#if defined(_SILICON_LABS_32B_SERIES_0) EFM_ASSERT(DAC_REF_VALID(dac)); EFM_ASSERT(DAC_OPA_VALID(opa)); @@ -221,6 +282,33 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) { dac->OPACTRL &= ~DAC_OPACTRL_OPA2EN; } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(VDAC_REF_VALID(dac)); + EFM_ASSERT(VDAC_OPA_VALID(opa)); + + if (opa == OPA0) + { + dac->CMD |= VDAC_CMD_OPA0DIS; + while (dac->STATUS & VDAC_STATUS_OPA0ENS) + { + } + } + else if (opa == OPA1) + { + dac->CMD |= VDAC_CMD_OPA1DIS; + while (dac->STATUS & VDAC_STATUS_OPA1ENS) + { + } + } + else /* OPA2 */ + { + dac->CMD |= VDAC_CMD_OPA2DIS; + while (dac->STATUS & VDAC_STATUS_OPA2ENS) + { + } + } +#endif } @@ -228,6 +316,7 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) * @brief * Configure and enable an Operational Amplifier. * + * @if DOXYDOC_P1_DEVICE * @note * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef * structure should consist of one or more of the @@ -256,6 +345,23 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) * * @param[in] dac * Pointer to DAC peripheral register block. + * @elseif DOXYDOC_P2_DEVICE + * @note + * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef + * structure should consist of one or more of the + * VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags + * (defined in \_vdac.h) OR'ed together. @n @n + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 + * + * E.g: @n + * init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | VDAC_OPA_OUT_ALTOUTPADEN_OUT4; + * @param[in] dac + * Pointer to VDAC peripheral register block. + * @endif * * @param[in] opa * Selects an OPA, valid vaules are @ref OPA0, @ref OPA1 and @ref OPA2. @@ -263,8 +369,16 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) * @param[in] init * Pointer to a structure containing OPAMP init information. ******************************************************************************/ -void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init) +void OPAMP_Enable( +#if defined(_SILICON_LABS_32B_SERIES_0) + DAC_TypeDef *dac, +#elif defined(_SILICON_LABS_32B_SERIES_1) + VDAC_TypeDef *dac, +#endif + OPAMP_TypeDef opa, + const OPAMP_Init_TypeDef *init) { +#if defined(_SILICON_LABS_32B_SERIES_0) uint32_t offset; EFM_ASSERT(DAC_REF_VALID(dac)); @@ -421,9 +535,172 @@ void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef | (init->hcmDisable ? DAC_OPACTRL_OPA2HCMDIS : 0) | DAC_OPACTRL_OPA2EN; } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + uint32_t calData = 0; + uint32_t warmupTime; + + EFM_ASSERT(VDAC_REF_VALID(dac)); + EFM_ASSERT(VDAC_OPA_VALID(opa)); + EFM_ASSERT(init->settleTime <= (_VDAC_OPA_TIMER_SETTLETIME_MASK + >> _VDAC_OPA_TIMER_SETTLETIME_SHIFT)); + EFM_ASSERT(init->startupDly <= (_VDAC_OPA_TIMER_STARTUPDLY_MASK + >> _VDAC_OPA_TIMER_STARTUPDLY_SHIFT)); + EFM_ASSERT((init->outPen & ~_VDAC_OPA_OUT_ALTOUTPADEN_MASK) == 0); + EFM_ASSERT(!((init->gain3xEn == true) + && ((init->negSel == opaNegSelResTap) + || (init->posSel == opaPosSelResTap)))); + EFM_ASSERT((init->drvStr == opaDrvStrLowerAccLowStr) + || (init->drvStr == opaDrvStrLowAccLowStr) + || (init->drvStr == opaDrvStrHighAccHighStr) + || (init->drvStr == opaDrvStrHigherAccHighStr)); + + /* Disable OPAMP before writing to registers. */ + OPAMP_Disable(dac, opa); + + /* Get the calibration value based on OPAMP, Drive Strength, and INCBW. */ + switch (opa) + { + case OPA0: + switch (init->drvStr) + { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL0 : DEVINFO->OPA0CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL1 : DEVINFO->OPA0CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL2 : DEVINFO->OPA0CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL3 : DEVINFO->OPA0CAL7); + break; + } + break; + + case OPA1: + switch (init->drvStr) + { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL0 : DEVINFO->OPA1CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL1 : DEVINFO->OPA1CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL2 : DEVINFO->OPA1CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL3 : DEVINFO->OPA1CAL7); + break; + } + break; + + case OPA2: + switch (init->drvStr) + { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL0 : DEVINFO->OPA2CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL1 : DEVINFO->OPA2CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL2 : DEVINFO->OPA2CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL3 : DEVINFO->OPA2CAL7); + break; + } + break; + } + if (!init->defaultOffsetN) + { + EFM_ASSERT(init->offsetN <= (_VDAC_OPA_CAL_OFFSETN_MASK + >> _VDAC_OPA_CAL_OFFSETN_SHIFT)); + calData = (calData & ~_VDAC_OPA_CAL_OFFSETN_MASK) + | (init->offsetN << _VDAC_OPA_CAL_OFFSETN_SHIFT); + } + if (!init->defaultOffsetP) + { + EFM_ASSERT(init->offsetP <= (_VDAC_OPA_CAL_OFFSETP_MASK + >> _VDAC_OPA_CAL_OFFSETP_SHIFT)); + calData = (calData & ~_VDAC_OPA_CAL_OFFSETP_MASK) + | (init->offsetP << _VDAC_OPA_CAL_OFFSETP_SHIFT); + } + + dac->OPA[opa].CAL = (calData & _VDAC_OPA_CAL_MASK); + + dac->OPA[opa].MUX = (uint32_t)init->resSel + | (init->gain3xEn ? VDAC_OPA_MUX_GAIN3X : 0) + | (uint32_t)init->resInMux + | (uint32_t)init->negSel + | (uint32_t)init->posSel; + + dac->OPA[opa].OUT = (uint32_t)init->outMode + | (uint32_t)init->outPen; + + switch (init->drvStr) + { + case opaDrvStrHigherAccHighStr: + warmupTime = 6; + break; + + case opaDrvStrHighAccHighStr: + warmupTime = 8; + break; + + case opaDrvStrLowAccLowStr: + warmupTime = 85; + break; + + case opaDrvStrLowerAccLowStr: + default: + warmupTime = 100; + break; + } + + dac->OPA[opa].TIMER = (uint32_t)(init->settleTime + << _VDAC_OPA_TIMER_SETTLETIME_SHIFT) + | (uint32_t)(warmupTime + << _VDAC_OPA_TIMER_WARMUPTIME_SHIFT) + | (uint32_t)(init->startupDly + << _VDAC_OPA_TIMER_STARTUPDLY_SHIFT); + + dac->OPA[opa].CTRL = (init->aportYMasterDisable + ? VDAC_OPA_CTRL_APORTYMASTERDIS : 0) + | (init->aportXMasterDisable + ? VDAC_OPA_CTRL_APORTXMASTERDIS : 0) + | (uint32_t)init->prsOutSel + | (uint32_t)init->prsSel + | (uint32_t)init->prsMode + | (init->prsEn ? VDAC_OPA_CTRL_PRSEN : 0) + | (init->halfDrvStr + ? VDAC_OPA_CTRL_OUTSCALE_HALF + : VDAC_OPA_CTRL_OUTSCALE_FULL) + | (init->hcmDisable ? VDAC_OPA_CTRL_HCMDIS : 0) + | (init->ugBwScale ? VDAC_OPA_CTRL_INCBW : 0) + | (uint32_t)init->drvStr; + + if (opa == OPA0) + { + dac->CMD |= VDAC_CMD_OPA0EN; + } + else if (opa == OPA1) + { + dac->CMD |= VDAC_CMD_OPA1EN; + } + else /* OPA2 */ + { + dac->CMD |= VDAC_CMD_OPA2EN; + } + +#endif } /** @} (end addtogroup OPAMP) */ /** @} (end addtogroup emlib) */ -#endif /* defined( OPAMP_PRESENT ) && ( OPAMP_COUNT == 1 ) */ +#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) + || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c index 44035ebf140..a71999b7d1f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_pcnt.c * @brief Pulse Counter (PCNT) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c index 3b1813423af..244d07c1d60 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_prs.c * @brief Peripheral Reflex System (PRS) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c index 9f467e72141..a8cd720863f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c @@ -2,7 +2,7 @@ * @file em_rmu.c * @brief Reset Management Unit (RMU) peripheral module peripheral API * - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -111,7 +111,7 @@ #define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL /** 0000000000000001 < Backup mode reset */ #define NUM_RSTCAUSES 16 -/* EFM32XG1X */ +/* EFM32xG1, EFM32xG12, EFM32xG13 */ #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL) #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ #define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ @@ -128,8 +128,8 @@ #error "RMU_RSTCAUSE XMASKs are not defined for this family." #endif +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) #define ERRATA_FIX_EMU_E208_EN #endif @@ -303,7 +303,7 @@ uint32_t RMU_ResetCauseGet(void) for (i = 0; i < NUM_RSTCAUSES; i++) { zeroXMask = resetCauseMasks[i].resetCauseZeroXMask; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /* Handle soft/hard pin reset */ if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) { diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c index c5ee6e79b73..0356bf2964b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_rtc.c * @brief Real Time Counter (RTC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c index 76e91979b20..3b5d3a10126 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief Real Time Counter with Calendar (RTCC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c index dcedb246291..4476b7f57f2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_system.c * @brief System Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -61,10 +61,10 @@ void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev) uint8_t tmp; EFM_ASSERT(rev); - - uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0)); - uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1)); - uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2)); + + uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0)); + uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1)); + uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2)); uint32_t pid3 = SECURE_READ(&(ROMTABLE->PID3)); /* CHIP FAMILY bit [5:2] */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c index 1182d7310b2..5c21e8d4e9d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_timer.c * @brief Timer/counter (TIMER) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c index 1e9bb632628..134519ca9cf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c @@ -2,7 +2,7 @@ * @file em_usart.c * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) * Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -110,14 +110,18 @@ #define USART_IRDA_VALID(ref) (0) #endif -#if defined(_EZR32_HAPPY_FAMILY) -#define USART_I2S_VALID(ref) ((ref) == USART0) -#elif defined(_EFM32_HAPPY_FAMILY) -#define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) -#elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) || defined(_SILICON_LABS_32B_PLATFORM_2) -#define USART_I2S_VALID(ref) ((ref) == USART1) -#elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) -#define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) +#if defined(_SILICON_LABS_32B_SERIES_1) + #define USART_I2S_VALID(ref) ((ref) == USART1) +#elif defined(_SILICON_LABS_32B_SERIES_0) + #if defined(_EZR32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART0) + #elif defined(_EFM32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART1) + #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) +#endif #endif #if (UART_COUNT == 1) @@ -475,11 +479,7 @@ uint32_t USART_BaudrateGet(USART_TypeDef *usart) ******************************************************************************/ void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate) { -#if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL) - uint64_t clkdiv; -#else uint32_t clkdiv; -#endif /* Inhibit divide by 0 */ EFM_ASSERT(baudrate); @@ -496,28 +496,8 @@ void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baud refFreq = CMU_ClockFreqGet(cmuClock_HFPER); } -#if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL) - /* Calculate CLKDIV with fractional bits */ - clkdiv = (128ULL*refFreq)/baudrate - 256; - - /* - * Make sure we dont use fractional bits, do normal integer rounding when - * discarding fractional bits. - */ - clkdiv = ((clkdiv + 128)/256) << 8; -#else - /* Calculate and set CLKDIV with fractional bits */ - clkdiv = 2 * refFreq; - clkdiv += baudrate - 1; - clkdiv /= baudrate; - clkdiv -= 4; - clkdiv *= 64; - /* Make sure we don't use fractional bits by rounding CLKDIV */ - /* up (and thus reducing baudrate, not increasing baudrate above */ - /* specified value). */ - clkdiv += 0xc0; - clkdiv &= 0xffffff00; -#endif + clkdiv = (refFreq - 1) / (2 * baudrate); + clkdiv = clkdiv << 8; /* Verify that resulting clock divider is within limits */ EFM_ASSERT(!(clkdiv & ~_USART_CLKDIV_DIV_MASK)); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c index 6198550c36c..03cf953c664 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_vcmp.c * @brief Voltage Comparator (VCMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c new file mode 100644 index 00000000000..634a6513d25 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c @@ -0,0 +1,437 @@ +/***************************************************************************//** + * @file em_vdac.c + * @brief Digital to Analog Converter (VDAC) Peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#include "em_vdac.h" +#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) +#include "em_cmu.h" + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup VDAC + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of VDAC channel for assert statements. */ +#define VDAC_CH_VALID(ch) ((ch) <= 1) + +/** Max VDAC clock */ +#define VDAC_MAX_CLOCK 1000000 + +/** Max clock frequency of internal clock oscillator, 10 MHz + 20%. */ +#define VDAC_INTERNAL_CLOCK_FREQ 12000000 + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable/disable VDAC channel. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] ch + * Channel to enable/disable. + * + * @param[in] enable + * true to enable VDAC channel, false to disable. + ******************************************************************************/ +void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable) +{ + EFM_ASSERT(VDAC_REF_VALID(vdac)); + EFM_ASSERT(VDAC_CH_VALID(ch)); + + if (ch == 0) + { + if (enable) + { + vdac->CMD = VDAC_CMD_CH0EN; + } + else + { + vdac->CMD = VDAC_CMD_CH0DIS; + while (vdac->STATUS & VDAC_STATUS_CH0ENS); + } + } + else + { + if (enable) + { + vdac->CMD = VDAC_CMD_CH1EN; + } + else + { + vdac->CMD = VDAC_CMD_CH1DIS; + while (vdac->STATUS & VDAC_STATUS_CH1ENS); + } + } +} + +/***************************************************************************//** + * @brief + * Initialize VDAC. + * + * @details + * Initializes common parts for both channels. This function will also load + * calibration values from the Device Information (DI) page into the VDAC + * calibration register. + * To complete a VDAC setup, channel control configuration must also be done, + * please refer to VDAC_InitChannel(). + * + * @note + * This function will disable both channels prior to configuration. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] init + * Pointer to VDAC initialization structure. + ******************************************************************************/ +void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init) +{ + uint32_t cal, tmp = 0; + uint32_t const volatile *calData; + + EFM_ASSERT(VDAC_REF_VALID(vdac)); + + /* Make sure both channels are disabled. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)); + + /* Get OFFSETTRIM calibration value. */ + cal = ((DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK) + >> _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT) + << _VDAC_CAL_OFFSETTRIM_SHIFT; + + if (init->mainCalibration) + { + calData = &DEVINFO->VDAC0MAINCAL; + } + else + { + calData = &DEVINFO->VDAC0ALTCAL; + } + + /* Get correct GAINERRTRIM calibration value. */ + switch (init->reference) + { + case vdacRef1V25Ln: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT; + break; + + case vdacRef2V5Ln: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT; + break; + + case vdacRef1V25: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT; + break; + + case vdacRef2V5: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT; + break; + + case vdacRefAvdd: + case vdacRefExtPin: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT; + break; + } + + /* Set GAINERRTRIM calibration value. */ + cal |= tmp << _VDAC_CAL_GAINERRTRIM_SHIFT; + + /* Get GAINERRTRIMCH1 calibration value. */ + switch (init->reference) + { + case vdacRef1V25Ln: + case vdacRef1V25: + case vdacRefAvdd: + case vdacRefExtPin: + tmp = (DEVINFO->VDAC0CH1CAL && _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK) + >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT; + break; + + case vdacRef2V5Ln: + case vdacRef2V5: + tmp = (DEVINFO->VDAC0CH1CAL && _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK) + >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT; + break; + } + + /* Set GAINERRTRIM calibration value. */ + cal |= tmp << _VDAC_CAL_GAINERRTRIMCH1_SHIFT; + + tmp = ((uint32_t)init->asyncClockMode << _VDAC_CTRL_DACCLKMODE_SHIFT) + | ((uint32_t)init->warmupKeepOn << _VDAC_CTRL_WARMUPMODE_SHIFT) + | ((uint32_t)init->refresh << _VDAC_CTRL_REFRESHPERIOD_SHIFT) + | (((uint32_t)init->prescaler << _VDAC_CTRL_PRESC_SHIFT) + & _VDAC_CTRL_PRESC_MASK) + | ((uint32_t)init->reference << _VDAC_CTRL_REFSEL_SHIFT) + | ((uint32_t)init->ch0ResetPre << _VDAC_CTRL_CH0PRESCRST_SHIFT) + | ((uint32_t)init->outEnablePRS << _VDAC_CTRL_OUTENPRS_SHIFT) + | ((uint32_t)init->sineEnable << _VDAC_CTRL_SINEMODE_SHIFT) + | ((uint32_t)init->diff << _VDAC_CTRL_DIFF_SHIFT); + + /* Write to VDAC registers. */ + vdac->CAL = cal; + vdac->CTRL = tmp; +} + +/***************************************************************************//** + * @brief + * Initialize a VDAC channel. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] init + * Pointer to VDAC channel initialization structure. + * + * @param[in] ch + * Channel number to initialize. + ******************************************************************************/ +void VDAC_InitChannel(VDAC_TypeDef *vdac, + const VDAC_InitChannel_TypeDef *init, + unsigned int ch) +{ + uint32_t vdacChCtrl, vdacStatus; + + EFM_ASSERT(VDAC_REF_VALID(vdac)); + EFM_ASSERT(VDAC_CH_VALID(ch)); + + /* Make sure both channels are disabled. */ + vdacStatus = vdac->STATUS; + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)); + + vdacChCtrl = ((uint32_t)init->prsSel << _VDAC_CH0CTRL_PRSSEL_SHIFT) + | ((uint32_t)init->prsAsync << _VDAC_CH0CTRL_PRSASYNC_SHIFT) + | ((uint32_t)init->trigMode << _VDAC_CH0CTRL_TRIGMODE_SHIFT) + | ((uint32_t)init->sampleOffMode << _VDAC_CH0CTRL_CONVMODE_SHIFT); + + if (ch == 0) + { + vdac->CH0CTRL = vdacChCtrl; + } + else + { + vdac->CH1CTRL = vdacChCtrl; + } + + /* Check if the channel must be enabled. */ + if (init->enable) + { + if (ch == 0) + { + vdac->CMD = VDAC_CMD_CH0EN; + } + else + { + vdac->CMD = VDAC_CMD_CH1EN; + } + } + + /* Check if the other channel had to be turned off above + * and needs to be turned on again. */ + if (ch == 0) + { + if (vdacStatus & VDAC_STATUS_CH1ENS) + { + vdac->CMD = VDAC_CMD_CH1EN; + } + } + else + { + if (vdacStatus & VDAC_STATUS_CH0ENS) + { + vdac->CMD = VDAC_CMD_CH0EN; + } + } +} + +/***************************************************************************//** + * @brief + * Set the output signal of a VDAC channel to a given value. + * + * @details + * This function sets the output signal of a VDAC channel by writing @p value + * to the corresponding CHnDATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] channel + * Channel number to set output of. + * + * @param[in] value + * Value to write to the channel output register CHnDATA. + ******************************************************************************/ +void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, + unsigned int channel, + uint32_t value) +{ + switch(channel) + { + case 0: + VDAC_Channel0OutputSet(vdac, value); + break; + case 1: + VDAC_Channel1OutputSet(vdac, value); + break; + default: + EFM_ASSERT(0); + break; + } +} + +/***************************************************************************//** + * @brief + * Calculate prescaler value used to determine VDAC clock. + * + * @details + * The VDAC clock is given by input clock divided by prescaler+1. + * + * VDAC_CLK = IN_CLK / (prescale + 1) + * + * Maximum VDAC clock is 1 MHz. Input clock is HFPERCLK when VDAC synchronous + * mode is selected, or an internal oscillator of 10 MHz +/- 20% when + * asynchronous mode is selected. + * + * @note + * If the requested VDAC frequency is low and the max prescaler value can not + * adjust the actual VDAC frequency lower than requested, the max prescaler + * value is returned, resulting in a higher VDAC frequency than requested. + * + * @param[in] vdacFreq VDAC frequency target. The frequency will automatically + * be adjusted to be below max allowed VDAC clock. + * + * @param[in] syncMode Set to true if you intend to use VDAC in synchronous + * mode. + * + * @param[in] hfperFreq Frequency in Hz of HFPERCLK oscillator. Set to 0 to + * use currently defined HFPERCLK clock setting. This parameter is only used + * when syncMode is set to true. + * + * @return + * Prescaler value to use for VDAC in order to achieve a clock value less than + * or equal to @p vdacFreq. + ******************************************************************************/ +uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq) +{ + uint32_t ret, refFreq; + + /* Make sure selected VDAC clock is below max value */ + if (vdacFreq > VDAC_MAX_CLOCK) + { + vdacFreq = VDAC_MAX_CLOCK; + } + + if (!syncMode) + { + refFreq = VDAC_INTERNAL_CLOCK_FREQ; + } + else + { + if (hfperFreq) + { + refFreq = hfperFreq; + } + else + { + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); + } + } + + /* Iterate in order to determine best prescale value. Start with lowest */ + /* prescaler value in order to get the first equal or less VDAC */ + /* frequency value. */ + for (ret = 0; ret <= _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; ret++) + { + if ((refFreq / (ret + 1)) <= vdacFreq) + { + break; + } + } + + /* If ret is higher than the max prescaler value, make sure to return + the max value. */ + if (ret > (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT)) + { + ret = _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Reset VDAC to same state as after a HW reset. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + ******************************************************************************/ +void VDAC_Reset(VDAC_TypeDef *vdac) +{ + /* Disable channels, before resetting other registers. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)); + vdac->CH0CTRL = _VDAC_CH0CTRL_RESETVALUE; + vdac->CH1CTRL = _VDAC_CH1CTRL_RESETVALUE; + vdac->CH0DATA = _VDAC_CH0DATA_RESETVALUE; + vdac->CH1DATA = _VDAC_CH1DATA_RESETVALUE; + vdac->CTRL = _VDAC_CTRL_RESETVALUE; + vdac->IEN = _VDAC_IEN_RESETVALUE; + vdac->IFC = _VDAC_IFC_MASK; + vdac->CAL = _VDAC_CAL_RESETVALUE; +} + +/** @} (end addtogroup VDAC) */ +/** @} (end addtogroup emlib) */ +#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c index 3e1024d35e0..55a66e44d2e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c @@ -2,7 +2,7 @@ * @file em_wdog.c * @brief Watchdog (WDOG) peripheral API * devices. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c index 78391c9c6ff..d112b4277a6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c @@ -9,7 +9,7 @@ #include "buffer_pool_allocator.h" -#include "em_int.h" +#include "em_core.h" #ifdef CONFIGURATION_HEADER #include CONFIGURATION_HEADER @@ -19,12 +19,11 @@ // Configuration Macros // ----------------------------------------------------------------------------- -// Default to a ping-pong buffer pool with a size of 128 (127 MTU + 1 length) bytes per buffer #ifndef BUFFER_POOL_SIZE -#define BUFFER_POOL_SIZE 2 +#define BUFFER_POOL_SIZE 8 #endif #ifndef MAX_BUFFER_SIZE -#define MAX_BUFFER_SIZE 128 +#define MAX_BUFFER_SIZE 160 #endif #define INVALID_BUFFER_OBJ ((void*)0xFFFFFFFF) @@ -46,7 +45,8 @@ void* memoryAllocate(uint32_t size) return INVALID_BUFFER_OBJ; } - INT_Disable(); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); for(i = 0; i < BUFFER_POOL_SIZE; i++) { if(memoryObjs[i].refCount == 0) @@ -56,7 +56,7 @@ void* memoryAllocate(uint32_t size) break; } } - INT_Enable(); + CORE_EXIT_CRITICAL(); return handle; } @@ -71,32 +71,35 @@ void *memoryPtrFromHandle(void *handle) return NULL; } - INT_Disable(); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); if(memoryObjs[(uint32_t)handle].refCount > 0) { ptr = memoryObjs[(uint32_t)handle].data; } - INT_Enable(); + CORE_EXIT_CRITICAL(); return ptr; } void memoryFree(void *handle) { - INT_Disable(); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); if(memoryPtrFromHandle(handle) != NULL) { memoryObjs[(uint32_t)handle].refCount--; } - INT_Enable(); + CORE_EXIT_CRITICAL(); } void memoryTakeReference(void *handle) { - INT_Disable(); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); if(memoryPtrFromHandle(handle) != NULL) { memoryObjs[(uint32_t)handle].refCount++; } - INT_Enable(); + CORE_EXIT_CRITICAL(); } diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/ieee802154_efr32xg1_configurator_out.c b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/ieee802154_efr32xg1_configurator_out.c deleted file mode 100644 index 213dac66fc0..00000000000 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/ieee802154_efr32xg1_configurator_out.c +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @brief RAIL Configuration - * @copyright Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com - ******************************************************************************/ -//============================================================================= -// -// WARNING: Auto-Generated Radio Config - DO NOT EDIT -// -//============================================================================= -#include - -const uint32_t ieee802154_config_base[] = { - 0x01010FF4UL, 0x00000000UL, - 0x01010FF8UL, 0x0003C000UL, - 0x01010FFCUL, 0x0003C00EUL, - 0x00010004UL, 0x00157001UL, - 0x00010008UL, 0x0000007FUL, - 0x00010018UL, 0x00000000UL, - 0x0001001CUL, 0x00000000UL, - 0x00010028UL, 0x00000000UL, - 0x0001002CUL, 0x00000000UL, - 0x00010030UL, 0x00000000UL, - 0x00010034UL, 0x00000000UL, - 0x0001003CUL, 0x00000000UL, - 0x00010040UL, 0x000007A0UL, - 0x00010048UL, 0x00000000UL, - 0x00010054UL, 0x00000000UL, - 0x00010058UL, 0x00000000UL, - 0x000100A0UL, 0x00004000UL, - 0x000100A4UL, 0x00004CFFUL, - 0x000100A8UL, 0x00004100UL, - 0x000100ACUL, 0x00004DFFUL, - 0x00012000UL, 0x00000704UL, - 0x00012010UL, 0x00000000UL, - 0x00012018UL, 0x00008408UL, - 0x00013008UL, 0x0000AC3FUL, - 0x0001302CUL, 0x01F50AAAUL, - 0x00013030UL, 0x00104924UL, - 0x00013034UL, 0x00000001UL, - 0x0001303CUL, 0x00010AABUL, - 0x00013040UL, 0x00000000UL, - 0x000140A0UL, 0x0F00277AUL, - 0x000140F4UL, 0x00001020UL, - 0x00014134UL, 0x00000880UL, - 0x00014138UL, 0x000087E6UL, - 0x00014140UL, 0x0088006DUL, - 0x00014144UL, 0x1153E6C0UL, - 0x00016014UL, 0x00000010UL, - 0x00016018UL, 0x0413F920UL, - 0x0001601CUL, 0x0052C007UL, - 0x00016020UL, 0x000000C8UL, - 0x00016024UL, 0x00000000UL, - 0x00016028UL, 0x03000000UL, - 0x0001602CUL, 0x00000000UL, - 0x00016030UL, 0x00FF0264UL, - 0x00016034UL, 0x000008A2UL, - 0x00016038UL, 0x00000001UL, - 0x0001603CUL, 0x000807B0UL, - 0x00016040UL, 0x000000A7UL, - 0x00016044UL, 0x00000000UL, - 0x00016048UL, 0x0AC00141UL, - 0x0001604CUL, 0x744AC39BUL, - 0x00016050UL, 0x000003F0UL, - 0x00016054UL, 0x00000000UL, - 0x00016058UL, 0x00000000UL, - 0x0001605CUL, 0x30100101UL, - 0x00016060UL, 0x7F7F7050UL, - 0x00016064UL, 0x00000000UL, - 0x00017014UL, 0x000270FAUL, - 0x00017018UL, 0x00001800UL, - 0x0001701CUL, 0x82840000UL, - 0x00017028UL, 0x01800000UL, - 0x00017048UL, 0x00003D3CUL, - 0x0001704CUL, 0x000019BCUL, - 0x00017070UL, 0x00010103UL, - 0x00017074UL, 0x00000442UL, - 0x00017078UL, 0x00552300UL, - 0xFFFFFFFFUL, -}; - -const uint32_t ieee802154_config_base_min[] = { - 0x01010FFCUL, 0x0003C00EUL, - 0x0001303CUL, 0x00010AABUL, - 0x00016034UL, 0x000008A2UL, - 0x00016038UL, 0x00000001UL, - 0x00017078UL, 0x00552300UL, - 0xFFFFFFFFUL, -}; - -const uint32_t ieee802154_config_2415MHz_min[] = { - 0x01010FFCUL, 0x0003C00AUL, - 0x0001303CUL, 0x00003555UL, - 0xFFFFFFFFUL, -}; - -const uint32_t ieee802154_config_2420MHz_min[] = { - 0x0001303CUL, 0x00003555UL, - 0x00016034UL, 0x000004A1UL, - 0x00016038UL, 0x00000009UL, - 0x00017078UL, 0x0049E006UL, - 0xFFFFFFFFUL, -}; - diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1.a deleted file mode 100644 index d505e1ccad6..00000000000 Binary files a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1.a and /dev/null differ diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a new file mode 100644 index 00000000000..bc0ab389b7e Binary files /dev/null and b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a differ diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.h b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.h new file mode 100644 index 00000000000..c6ba7e610fe --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.h @@ -0,0 +1,18 @@ + +/***************************************************************************//** + * @file ieee802154_config.h + * @brief IEEE802154 Configuration + * @copyright Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************/ + +#ifndef __IEEE802154_EFR32XG12_CONFIGURATOR_OUT_H__ +#define __IEEE802154_EFR32XG12_CONFIGURATOR_OUT_H__ + +#include + +extern const uint32_t ieee802154_config_base[]; +extern const uint32_t ieee802154_config_base_min[]; +extern const uint32_t ieee802154_config_2415MHz_min[]; +extern const uint32_t ieee802154_config_2420MHz_min[]; + +#endif // __IEEE802154_EFR32XG12_CONFIGURATOR_OUT_H__ diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12_gcc_release.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12_gcc_release.a new file mode 100644 index 00000000000..ac00f614cdb Binary files /dev/null and b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12_gcc_release.a differ diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32_iar_release.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32_iar_release.a deleted file mode 100644 index a089e35b1da..00000000000 Binary files a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32_iar_release.a and /dev/null differ diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a new file mode 100644 index 00000000000..bc0ab389b7e Binary files /dev/null and b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a differ diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG12/librail_efr32xg12_iar_release.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG12/librail_efr32xg12_iar_release.a new file mode 100644 index 00000000000..d5526f106dc Binary files /dev/null and b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG12/librail_efr32xg12_iar_release.a differ diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pa.h b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pa.h index faeefeca140..f8cd45ca4ce 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pa.h +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pa.h @@ -39,22 +39,22 @@ extern "C" { #endif /***************************************************************************//** - * @addtogroup RF_Library + * @addtogroup Chip_Specific * @{ ******************************************************************************/ /***************************************************************************//** - * @addtogroup PA + * @addtogroup EFR32xG1x_PA * @{ ******************************************************************************/ /******************************************************************************* **************************** CONFIGURATION ******************************** ******************************************************************************/ +/** Scaling factor applied to all dBm power level inputs and outputs * */ #define PA_SCALING_FACTOR 10 /** - * @struct RADIO_PASel_t * @brief Selection of the rf power amplifier (PA) to use */ typedef enum RADIO_PASel @@ -64,9 +64,15 @@ typedef enum RADIO_PASel /** Low power PA */ PA_SEL_2P4_LP, /** SubGig PA*/ - PA_SEL_SUBGIG + PA_SEL_SUBGIG, + /** Invalid PA Selection */ + PA_SEL_INVALID } RADIO_PASel_t; +/** + * @brief Selection should match the configuration of the voltage on the vPa pin + * of the chip. + */ typedef enum RADIO_PAVoltMode { /** Vpa = Vbat = 3.3V */ @@ -76,7 +82,6 @@ typedef enum RADIO_PAVoltMode } RADIO_PAVoltMode_t; /** - * @struct RADIO_PAInit_t * @brief Configuration structure for the rf power amplifier (PA) */ typedef struct RADIO_PAInit { @@ -84,9 +89,9 @@ typedef struct RADIO_PAInit { RADIO_PASel_t paSel; /** Power Amplifier vPA Voltage mode */ RADIO_PAVoltMode_t voltMode; - /** Desired output power in dBm * 10 */ + /** Desired output power in dBm * \ref PA_SCALING_FACTOR */ int16_t power; - /** Output power offset in dBm * 10 */ + /** Output power offset in dBm * \ref PA_SCALING_FACTOR */ int16_t offset; /** Desired ramp time in us */ uint16_t rampTime; @@ -96,16 +101,169 @@ typedef struct RADIO_PAInit { ****************************** PROTOTYPES ********************************* ******************************************************************************/ -bool RADIO_PA_Init(RADIO_PAInit_t * paInit); -int32_t PA_OutputPowerGet(void); -int32_t PA_OutputPowerSet(int32_t power); -int32_t PA_MaxOutputPowerSet(void); +/** + * @brief + * Initilize the PA settings based on the settings provided in the paInit + * structure. + * + * @param[in] paInit + * Pointer to a structure containing the desired PA configuration settings. + * + * @return + * True if the settings were accepted. + * False if settings were invalid. + * + * @warning + * The radio should not be transmitting when this function is called! +*/ +bool RADIO_PA_Init(RADIO_PAInit_t * paInit); + +/** + * @brief + * Returns the current power level of transmit power + * + * @return + * Current power level in dBm * \ref PA_SCALING_FACTOR + */ +int32_t PA_OutputPowerGet(void); + +/** + * @brief + * Sets the output power of the PA. + * + * Each PA has distinct maximum power, minimum power, and power step sizes. + * This API will calculate the best pa output power level setting to acheieve + * the desired output power. + * + * @note + * Board and chip variations will affect the accuracy of this API. Use + * of the RADIO_PAInit_t.offset paramter can help account for this variation. + * + * @param[in] power + * Power value in dBm * \ref PA_SCALING_FACTOR + * + * Examples with \ref PA_SCALING_FACTOR of 10: + * - 10 dBm --> 100 + * - 5.5 dBm --> 55 + * + * @return + * Returns the actual power that was set in dBm * \ref PA_SCALING_FACTOR + * + * @warning + * The radio should not be transmitting when this function is called! + */ +int32_t PA_OutputPowerSet(int32_t power); + +/** + * @brief + * Set the maximum possible output power for the selected PA. + * + * @return + * Returns the actual power that was set in dBm * \ref PA_SCALING_FACTOR + * + * @warning + * The radio should not be transmitting when this function is called! + */ +int32_t PA_MaxOutputPowerSet(void); + +/** + * @brief + * Return the current ramp time in microseconds + * + * @return + * Current ramp time in microseconds + */ uint32_t PA_RampTimeGet(void); + +/** + * @brief + * Sets up the ramp configuration so that it best matches the given ramp time + * + * @details + * Each PA has a distinct ramp level and ramp rate that can be used to + * achieve various ramp times. This API will pick the ramp rate that closest + * approximates the desired ramp time. + * + * @param[in] ramptime + * Desired ramp time in microseconds + * + * @return + * The actual ramp time that was set in microseconds. + * + * @warning + * The radio should not be transmitting when this function is called! + */ uint32_t PA_RampTimeSet(uint32_t ramptime); -void PA_CTuneSet(uint8_t txPaCtuneValue, uint8_t rxPaCtuneValue); -/** @} (end addtogroup PA) */ -/** @} (end addtogroup RF_Library) */ +/***************************************************************************//** + * @addtogroup EFR32xG1x_PA_Advanced + * @{ + ******************************************************************************/ + +/** + * @brief + * Set PACTUNE value for TX and RX mode. + * + * This value can vary depending on band and match and board design. + * + * @param[in] txPaCtuneValue + * Transmit value for pa ctune + * @param[in] rxPaCtuneValue + * Receive value for pa ctune + * + * @note PACTUNE will reset to default values when RADIO_PA_Init() or + * RAIL_RadioConfig() are called. + * + * @warning + * The radio should not be transmitting when this function is called! + */ +void PA_CTuneSet(uint8_t txPaCtuneValue, uint8_t rxPaCtuneValue); + +/** + * @brief + * Set the output power level based on power steps available in the chosen PA. + * + * @details + * Each PA has distinct maximum power, minimum power, and power step sizes. + * This API allows direct access to these power steps to tune between the + * maximum and minimum output power the selected PA is capable of. + * + * @param[in] pwrLevel + * Output power level. Note that the maximum power level will change + * depending on PA selection. + * @param[in] boostMode + * Output boost mode. Some PA selections have a mode that will increase the + * output power for each step if this is enabled. + * + * @return + * MSB Configured boost mode. \n + * LSB Configured power level + * + * @warning + * The radio should not be transmitting when this function is called! + */ +uint16_t PA_PowerLevelSet(uint8_t pwrLevel, uint8_t boostMode); + +/** + * @brief + * Optimize the PA settings based on expected output power level. + * + * @details + * This API optimizes the current consumption of the radio based on the + * provided output power. This is only necessary when output power is + * controlled by PA_PowerLevelSet(). + * + * @param[in] power + * Power value in dBm * \ref PA_SCALING_FACTOR + * + * @warning + * The radio should not be transmitting when this function is called! + */ +void PA_PowerLevelOptimize(int32_t power); + +/** @} (end addtogroup EFR32xG1x_PA_Advanced) */ +/** @} (end addtogroup EFR32xG1x_PA) */ +/** @} (end addtogroup Chip_Specific) */ #ifdef __cplusplus } diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail.h b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail.h index af1fb40699d..b5d858d6eef 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail.h +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail.h @@ -13,7 +13,7 @@ #include // Get the RAIL specific structures and types -#include "rail/rail_types.h" +#include "rail_types.h" /** * @addtogroup RAIL_API @@ -62,10 +62,9 @@ uint8_t RAIL_RfInit(const RAIL_Init_t *railInit); * @return Returns zero on success and an error code on error. * * The protocol is output via the Packet Trace Interface (PTI) for each packet. - * Before any protocol is set, the default value is \ref RAIL_PTI_PROTOCOL_CUSTOM. - * A custom value may be used if it does not conflict with one of the available - * \ref RAIL_PtiProtocol_t enum values, though values may only go up to \ref - * RAIL_PTI_PROTOCOL_MAX. + * Before any protocol is set, the default value is \ref + * RAIL_PTI_PROTOCOL_CUSTOM. One of the enum values should be used in order for + * Network Analyzer to be able to decode the packet. */ RAIL_Status_t RAIL_SetPtiProtocol(RAIL_PtiProtocol_t protocol); @@ -76,7 +75,7 @@ RAIL_Status_t RAIL_SetPtiProtocol(RAIL_PtiProtocol_t protocol); * @return void * * Callback that notifies the application when the radio is finished - * initializing and is ready for further configuration. This is callback is + * initializing and is ready for further configuration. This callback is * useful for potential transceiver products that require a power up sequence * before further configuration is available. After this callback fires, the * radio is ready for additional configuration before transmit and receive @@ -110,7 +109,8 @@ RAIL_RadioState_t RAIL_RfStateGet(void); * This function fails if unsupported transitions are passed in, or if the * radio is currently in the RX state. Success can transition to TX, RX, or * IDLE, while error can transition to RX or IDLE. The full list of options for - * the ignoreErrors parameter is any define that starts with RAIL_IGNORE_. + * the ignoreErrors parameter is any define that starts with + * \link RAIL_IGNORE_NO_ERRORS RAIL_IGNORE_\endlink. */ RAIL_Status_t RAIL_SetRxTransitions(RAIL_RadioState_t success, RAIL_RadioState_t error, @@ -209,6 +209,20 @@ uint32_t RAIL_RfSense(RAIL_RfSenseBand_t band, uint32_t senseTime, bool enableCb */ bool RAIL_RfSensed(void); +/** + * Modify the currently configured fixed length + * + * @param[in] length Expected fixed length; 0 is infinite + * @return Length configured; 0xFFFF if not in fixed length, 0 if in infinite + * + * Set the fixed length configuration for transmit and receive. Users should + * be careful when using this function in receive and transmit. This function + * returns \ref RAIL_SETFIXEDLENGTH_INVALID if the radio is not in fixed length + * mode. The function returns 0 if in infinite length mode. Otherwise it will + * return the length configured into the hardware. + */ +uint16_t RAIL_SetFixedLength(uint16_t length); + /***************************************************************************//** * Collect entropy from the radio if available. * @@ -288,6 +302,7 @@ uint16_t RAIL_GetRadioEntropy(uint8_t *buffer, uint16_t bytes); * { * int i = 0; * void *ptr = NULL; + * CORE_DECLARE_IRQ_STATE; * * // We can't support sizes greater than the maximum buffer size * if(size > (MAX_PACKET_SIZE + sizeof(RAIL_RxPacketInfo_t))) { @@ -295,23 +310,23 @@ uint16_t RAIL_GetRadioEntropy(uint8_t *buffer, uint16_t bytes); * } * * // Disable interrupts and attempt to grab the buffer - * INT_Disable(); + * CORE_ENTER_CRITICAL(); * if (isAllocated) { * ptr = NULL; * } else { * isAllocated = true; * ptr = buffer; * } - * INT_Enable(); + * CORE_EXIT_CRITICAL(); * * return ptr; * } * * void RAILCb_FreeMemory(void *ptr) * { - * INT_Disable(); - * isAllocated = false; - * INT_Enable(); + * CORE_CRITICAL_SECTION( + * isAllocated = false; + * ); * } * * void *RAILCb_BeginWriteMemory(void *handle, @@ -391,6 +406,380 @@ void *RAILCb_BeginWriteMemory(void *handle, */ void RAILCb_EndWriteMemory(void *handle, uint32_t offset, uint32_t size); +/** + * @} + */ + +/****************************************************************************** + * Data Management + *****************************************************************************/ +/** + * @addtogroup Data_Management + * @brief Data management functions + * + * These functions allow the application to choose how data is presented to the + * application. There are two methods for RAIL to provide data, in a packet + * based method leveraging \ref Memory_Management callbacks or in a FIFO based + * method which gives the application more granularity and responsibility in + * managing transmit and receive data. + * + * The application can configure RAIL data mangement through RAIL_DataConfig(); + * this function allows the application to specify the type of radio data (\ref + * RAIL_TxDataSource_t and \ref RAIL_RxDataSource_t) and the method of + * interacting with this data (\ref RAIL_DataMethod_t). By default, RAIL + * configures Tx and Rx both with packet data source and packet mode. + * + * In packet based data management: + * - Load transmit data with RAIL_TxDataLoad() + * - Received data is returned in RAILCb_RxPacketReceived() + * - Packet lengths are determined from the Radio Configurator configuration + * - \ref Memory_Management callbacks will fire to ask for pointers to store + * data + * + * In FIFO based data management: + * - Load transmit data with RAIL_WriteTxFifo() + * - Received data is retrieved through RAIL_ReadRxFifo() + * - Packet Lengths are determined from the Radio Configurator configuration + * - Set fifo thresholds through RAIL_SetTxFifoThreshold() and + * RAIL_SetRxFifoThreshold() which fires RAILCb_RxFifoAlmostFull() and + * RAILCb_TxFifoAlmostEmpty(). + * - Get fifo count information through RAIL_GetRxFifoBytesAvailable() + * and RAIL_GetTxFifoSpaceAvailable() + * - Reset fifos with RAIL_ResetFifo() + * - CRC Error acceptance is on by default + * + * Both transmit and receive fifos are the same size; when trying to determine + * an appropriate threshold, the application can use + * RAIL_GetTxFifoSpaceAvailable() to query the size of the fifo if it is empty + * and use that as the size of the receive fifo as well. The transmit fifo is edge + * based where it only provides an interrupt once when the threshold is + * crossed. The receive fifo is level based where the interrupt will constantly + * pend if the threshold is exceeded. This normally means that inside + * RAILCb_RxFifoAlmostFull(), the application should empty enough of the fifo + * to go under the threshold. If the application wishes to defer reading the + * fifo to main, it can disable the receive fifo threshold interrupt via + * RAIL_DisableRxFifoThreshold(). The application can reenable the interrupt + * via RAIL_EnableRxFifoThreshold(). + * + * In fifo mode, the fifos can store multiple packets. Depending on traffic, + * RAIL can receive multiple packets into the receive fifo before the + * application gets around to reading out the received data from the fifo. If + * appended info is enabled, make sure to read out the appended info with + * RAIL_ReadRxFifoAppendedInfo() before attempting to read out the next packet. + * If the application aborts during packet reception, appended info will not be + * present in the receive fifo. If a frame error occurs in fifo mode, the + * contents of the receive fifo is unreliable and should be flushed. + * + * When calling RAIL_DataConfig() for fifo mode, RAIL will set \ref + * RAIL_IGNORE_CRC_ERRORS. Otherwise for packet mode, RAIL will set \ref + * RAIL_IGNORE_NO_ERRORS. It is highly suggested that the application maintains + * \ref RAIL_IGNORE_CRC_ERRORS in fifo mode if using hardware crc checking. + * + * While RAIL defaults to packet mode, the application can explicitly + * initialize RAIL for packet mode in the following manner: + * @code{.c} + * static const RAIL_DataConfig_t railDataConfig = { + * .txSource = TX_PACKET_DATA, + * .rxSource = RX_PACKET_DATA, + * .txMethod = PACKET_MODE, + * .rxMethod = PACKET_MODE, + * }; + * + * status = RAIL_DataConfig(&railDataConfig); + * + * // Callbacks that occur in Packet Mode + * void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo); + * void RAILCb_RxPacketReceived(void *rxPacketHandle); + * void *RAILCb_AllocateMemory(uint32_t size); + * void RAILCb_FreeMemory(void *handle); + * void *RAILCb_BeginWriteMemory(void *handle, + * uint32_t offset, + * uint32_t *available); + * void RAILCb_EndWriteMemory(void *handle, uint32_t offset, uint32_t size); + * @endcode + * + * Initializing RAIL for Fifo Mode requires a few more function calls: + * @code{.c} + * static const RAIL_DataConfig_t railDataConfig = { + * .txSource = TX_PACKET_DATA, + * .rxSource = RX_PACKET_DATA, + * .txMethod = FIFO_MODE, + * .rxMethod = FIFO_MODE, + * }; + * + * status = RAIL_DataConfig(&railDataConfig); + * + * // Get the size of the fifos + * // The transmit and receive fifos are the same size + * uint16_t fifoSize = RAIL_GetTxFifoSpaceAvailable(); + * + * // Set the transmit and receive fifo thresholds + * // For this example, set the threshold in the middle of each fifo + * RAIL_SetRxFifoThreshold(fifoSize / 2); + * RAIL_SetTxFifoThreshold(fifoSize / 2); + * + * //Callbacks that occur in Fifo mode + * void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo); + * void RAILCb_RxPacketReceived(void *rxPacketHandle); + * void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable); + * void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable); + * @endcode + * + * On receive, there are multiple data sources that an application can use that + * are only compatible with the fifo method of data delivery. All that differs + * from the fifo mode example above is the RAIL_DataConfig_t::rxSource setting. + * IQ data samples are taken at the hardware's oversample rate and the amount + * of data can easily overwhelm CPU processing time. The sample rate depends on + * the chosen PHY as is determined by the data rate as well as the decimation + * chain. It is not recommended to use the IQ data source with sample + * rates above 300k samples/second as the CPU might not be able to keep up with + * the data. Depending on the application and needed CPU bandwidth, slower + * data rates may be required. + * @code{.c} + * // IQ data is provided into the receive fifo + * static const RAIL_DataConfig_t railDataConfig = { + * .txSource = TX_PACKET_DATA, + * .rxSource = RX_IQDATA_FILTLSB, + * .txMethod = FIFO_MODE, + * .rxMethod = FIFO_MODE, + * }; + * + * // When reading IQ data out of the fifo, it comes in the following format: + * //------------------------------------ + * // I[LSB] | I[MSB] | Q[LSB] | Q[MSB] | + * //------------------------------------ + * @endcode + * + * @note \ref RAIL_DataConfig_t.txMethod and \ref RAIL_DataConfig_t.rxMethod + * must have the same \ref RAIL_DataMethod_t configuration. + * + * @warning Do not call RAIL fifo functions while in \ref + * RAIL_DataMethod_t::PACKET_MODE. + * @{ + */ + +/** + * RAIL data management configuration + * + * @param[in] dataConfig RAIL data configuration structure + * @return RAIL Status of configuration + * + * This function configures how RAIL manages data. The application can + * configure RAIL to receive data in a packet based or FIFO based format. When + * configuring tx or rx for fifo mode, this function will reset the configured + * fifos. + * + * If \ref RAIL_DataConfig_t.rxMethod is set to \ref + * RAIL_DataMethod_t.PACKET_MODE, the radio will filter packets with invalid + * CRCs by default. This is similar to setting the ignoreErrors + * parameter in RAIL_SetRxTransitions() to \ref RAIL_IGNORE_NO_ERRORS. + * + * If \ref RAIL_DataConfig_t.rxMethod is set to \ref + * RAIL_DataMethod_t.FIFO_MODE, the radio will accept packets with CRCs as + * 'valid' packets by default. This is meant to treat 'fully received' packets + * the same way regardless if CRC passes or fails. The application can parse + * CRC errors via appended info obtained from RAIL_ReadRxFifoAppendedInfo(). + * This is similar to setting the ignoreErrors parameter in + * RAIL_SetRxTransitions() to \ref RAIL_IGNORE_CRC_ERRORS. + * + * In either situation, the application can set ignoreErrors as needed; + * in fifo mode, appended info will not be present for frame errors. The + * defaults defined above are the recommended setting. + */ +RAIL_Status_t RAIL_DataConfig(RAIL_DataConfig_t *dataConfig); + +/** + * Write data to the transmit fifo + * + * @param[in] dataPtr Application provided pointer to transmit data + * @param[in] writeLength Number of bytes to write to the transmit fifo + * + * @return The number of bytes written to the transmit fifo + * + * This function reads data from the provided dataPtr and writes it to the TX + * Fifo. If the requested writeLength exceeds the current number of bytes open + * in the transmit fifo, the function will only write until the transmit fifo + * is full. The function returns the number of bytes written to the transmit + * fifo. + * + * @note This function does not create a critical section but depending on the + * application a critical section could be appropriate. + */ +uint16_t RAIL_WriteTxFifo(uint8_t *dataPtr, uint16_t writeLength); + +/** + * Read data from the receive fifo + * + * @param[out] dataPtr Application provided pointer to store data + * @param[in] readLength Number of bytes to read from the fifo + * + * @return The number of bytes read from the receive fifo + * + * This function reads data from the receive fifo and writes it to the provided + * dataPtr. If the requested readLength exceeds the current number of bytes in + * the receive fifo, the function will only read the current amount of bytes + * available. + * + * This function does not have a critical section, so either use it only in one + * context or make sure function calls are protected to prevent buffer + * corruption. + */ +uint16_t RAIL_ReadRxFifo(uint8_t *dataPtr, uint16_t readLength); + +/** + * Read appended info from the receive fifo + * + * @param[out] appendedInfo Application provided pointer to store RAIL_AppendedInfo_t + * @return void + * + * This function reads appended info from the receive fifo and writes it to the + * provided pointer; appended info is added to the receive fifo once a packet is + * received. Using this function while not at the end of a packet can corrupt + * your buffer by processing receive data as appended info. + * + * @note The following fields in appended info are not implemented in fifo mode and + * do not contain valid info: + * - RAIL_AppendedInfo_t.isAck + * - RAIL_AppendedInfo_t.lqi + * - RAIL_AppendedInfo_t.frameCodingStatus (will reflect the last received packet) + */ +void RAIL_ReadRxFifoAppendedInfo(RAIL_AppendedInfo_t *appendedInfo); + +/** + * Configure the RAIL transmit fifo almost empty threshold + * + * @param[in] txThreshold Threshold once fallen under + * will fire RAILCb_TxFifoAlmostEmpty() + * @return Configured transmit fifo threshold value + * + * This function configures the threshold for the transmit fifo. When the count + * of the transmit fifo is less than the configured threshold, + * RAILCb_TxFifoAlmostEmpty() will fire. A value of 0 is invalid and will not + * change the current configuration. + */ +uint16_t RAIL_SetTxFifoThreshold(uint16_t txThreshold); + +/** + * Configure the RAIL receive fifo almost full threshold + * + * @param[in] rxThreshold Threshold once exceeded will fire + * RAILCb_RxFifoAlmostFull() + * @return Configured receive fifo threshold value + * + * This function configures the threshold for the transmit fifo. When the count + * of the receive fifo is greater than the configured threshold, + * RAILCb_RxFifoAlmostFull() will fire. A value of 0xFFFF is invalid and will + * not change the current configuration. Depending on the hardware the maximum + * value can vary. If the rxThreshold value exceeds the capability of the + * hardware, the rx threshold will be configured so that it fires only when the + * FIFO is one byte away from being full. + * + */ +uint16_t RAIL_SetRxFifoThreshold(uint16_t rxThreshold); + +/** + * Get the RAIL transmit fifo almost empty threshold value + * + * @return Configured Tx Threshold value + * + * Retrieve the configured tx threshold value + */ +uint16_t RAIL_GetTxFifoThreshold(void); + +/** + * Get the RAIL receive fifo almost full threshold value + * + * @return Configured Rx Threshold value + * + * Retrieve the configured rx threshold value + */ +uint16_t RAIL_GetRxFifoThreshold(void); + +/** + * Enable the RAIL receive fifo threshold interrupt + * + * @return void + * + * Enable the RAIL receive fifo threshold interrupt. + */ +void RAIL_EnableRxFifoThreshold(void); + +/** + * Disable the RAIL receive fifo threshold interrupt + * + * @return void + * + * Disable the RAIL receive fifo threshold interrupt. This is useful if the + * application wishes to defer reading the receive fifo into another context. + */ +void RAIL_DisableRxFifoThreshold(void); + +/** + * Reset the RAIL Fifos + * + * @param[in] txFifo If true, reset the transmit fifo + * @param[in] rxFifo If true, reset the receive fifo + * @return void + * + * This function can reset each fifo. The application should not reset the Rx + * Fifo while receiving a frame. + */ +//@TODO interrupt protect when clearing; need to check race conditions with hw team +void RAIL_ResetFifo(bool txFifo, bool rxFifo); + +/** + * Get the number of bytes in the receive fifo + * + * @return Number of bytes in the receive fifo + * + * Get the number of bytes in the receive fifo + */ +uint16_t RAIL_GetRxFifoBytesAvailable(void); + +/** + * Get the number of bytes open in the transmit fifo + * + * @return Number of bytes open in the transmit fifo + * + * Get the number of bytes open in the transmit fifo + */ +uint16_t RAIL_GetTxFifoSpaceAvailable(void); + +/** + * Callback that fires when the receive fifo exceeds the configured threshold + * value + * + * @param[in] bytesAvailable Number of bytes available in the receive fifo at + * the time of the callback dispatch + * + * @return void + * @warning You must implement a stub for this in your RAIL application. + * + * Callback that fires when the receive fifo exceeds the configured threshold + * value. Provides the number of bytes available in the receive fifo at the + * time of the callback dispatch. + */ +void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable); + +/** + * Callback that fires when the transmit fifo falls under the configured + * threshold value + * + * @param[in] spaceAvailable Number of bytes open in the transmit fifo at the + * time of the callback dispatch + * + * @return void + * @warning You must implement a stub for this in your RAIL application. + * + * Callback that fires when the transmit fifo falls under the configured + * threshold value. It only fires if a rising edge occurs across this + * threshold. This callback will not fire on initailization nor after resetting + * the transmit fifo with RAIL_ResetFifo(). + * + * Provides the number of bytes open in the transmit fifo at the time of the + * callback dispatch. + */ +void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable); /** * @} */ @@ -564,7 +953,9 @@ uint8_t RAIL_RadioConfig(void *radioConfig); * * @param[in] frameType Frame type configuration structure. * - * Currently the frame type passed in only handles packet length decoding. + * Currently the frame type passed in only handles packet length decoding. If + * NULL is passed into this function, it will clear any currently configured + * frame type settings. */ void RAIL_PacketLengthConfigFrameType(const RAIL_FrameType_t *frameType); @@ -598,7 +989,7 @@ RAIL_Status_t RAIL_ChannelExists(uint8_t channel); * * @return The symbol rate in symbols per second * - * The symbol rate is the number of symbol changes over the air. For non DSSS + * The symbol rate is the rate of symbol changes over the air. For non-DSSS * PHYs this is the same as the baudrate. For DSSS PHYs it is the baudrate * divided by the length of a chipping sequence. For more information on this * consult the modem calculator documentation. @@ -647,8 +1038,8 @@ RAIL_Status_t RAIL_PaCtuneSet(uint8_t txPaCtuneValue, uint8_t rxPaCtuneValue); /** * Set the radio transmit power level * - * @param[in] powerLevel TX Power Level defined in deci dBm (0.0 dBm) - * @return TX Power Level in deci dBm (0.0 dBm) + * @param[in] powerLevel TX Power Level defined in deci dBm (10 * dBm) + * @return TX Power Level in deci dBm (10 * dBm) * * Not all values of powerLevel are achievable, but this function will set the * power output to be close to the given powerLevel, and return the value that @@ -659,7 +1050,7 @@ int32_t RAIL_TxPowerSet(int32_t powerLevel); /** * Get the radio transmit power level * - * @return TX Power Level defined in deci dBm (0.0 dBm) + * @return TX Power Level defined in deci dBm (10 * dBm) * * This will return what the power output was actually set to, not just the * value passed into RAIL_TxPowerSet. @@ -667,19 +1058,39 @@ int32_t RAIL_TxPowerSet(int32_t powerLevel); int32_t RAIL_TxPowerGet(void); /** - * Load payload to send. + * Configure which radio transmit actions trigger callbacks + * + * @param[in] cbToEnable Define which callbacks to trigger for transmit events. + * The full list of available callabcks can be found by looking at the + * RAIL_TX_CONFIG_* set of defines. + * @return Return 0 for success or an error code + * + * Setup which receive interrupts will generate a RAILCb_TxRadioStatus() + * callback. The full list of options is any define that starts with + * RAIL_TX_CONFIG_. Before this function is called, the actions which will + * generate callbacks are: + * - \ref RAIL_TX_CONFIG_BUFFER_UNDERFLOW + * - \ref RAIL_TX_CONFIG_CHANNEL_BUSY + * - \ref RAIL_TX_CONFIG_TX_ABORTED + * - \ref RAIL_TX_CONFIG_TX_BLOCKED + */ +RAIL_Status_t RAIL_TxConfig(uint32_t cbToEnable); + +/** + * Load payload to transmit. * * @param[in] txData Pointer to a RAIL_TxData_t structure which defines the - * payload bytes and length to transmit. If the fields are configured for - * fixed length. + * payload bytes and the number of bytes to write into the transmit buffer. * @return Returns 0 on success and an error code on fail. * - * This function may overwrite current TX data held by RAIL, and should not be - * called repetitively or during TX. The recommended way to use this is to call - * RAIL_TxDataLoad() and RAIL_TxStart() almost immediately in succession. + * This function will overwrite current TX data held by RAIL, and will return + * an error if called during transmit operations. RAIL_TxData_t.dataLength + * defines the number of bytes to load into the transmit buffer from + * RAIL_TxData_t.dataPtr while the number of bytes transmitted is determined by + * the packet configuration defined in the radio configuration. * - * Will return \ref RAIL_STATUS_INVALID_CALL if the Tx buffer is in use by the - * radio and cannot be updated. + * @note This function creates a critical section while writing to the transmit + * buffer. */ uint8_t RAIL_TxDataLoad(RAIL_TxData_t *txData); @@ -692,12 +1103,14 @@ uint8_t RAIL_TxDataLoad(RAIL_TxData_t *txData); * @param[in] preTxOpParams Pointer to the pre-transmit operation's * configuration parameters, or NULL if none. * @return Returns 0 on successfully initiating the transmit process, or an - * error code on failure. If successfully initiated, transmit completion + * error code on failure. If successfully initiated, transmit completion * or failure will be reported by later callbacks RAILCb_TxPacketSent() * (success) or RAILCb_TxRadioStatus() (failure). * * Begins transmission of the payload previously loaded via RAIL_TxDataLoad(). - * Return error if currently transmitting or receiving. + * Will begin transmitting after a received packet if currently receiving a + * packet. Returns error if the radio is active and the channel needs to be + * changed. */ uint8_t RAIL_TxStart(uint8_t channel, RAIL_PreTxOp_t preTxOp, @@ -722,7 +1135,9 @@ uint8_t RAIL_TxStart(uint8_t channel, * transmit options will only be configured if the preTxOp is successful. * * Begins transmission of the payload previously loaded via RAIL_TxDataLoad(). - * Return error if currently transmitting or receiving. + * Will begin transmitting after a received packet if currently receiving a + * packet. Returns error if the radio is active and the channel needs to be + * changed. */ uint8_t RAIL_TxStartWithOptions(uint8_t channel, RAIL_TxOptions_t *options, @@ -754,6 +1169,9 @@ void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo); * - \ref RAIL_TX_CONFIG_CHANNEL_BUSY * - \ref RAIL_TX_CONFIG_TX_ABORTED * - \ref RAIL_TX_CONFIG_TX_BLOCKED + * - \ref RAIL_TX_CONFIG_CHANNEL_CLEAR + * - \ref RAIL_TX_CONFIG_CCA_RETRY + * - \ref RAIL_TX_CONFIG_START_CCA */ void RAILCb_TxRadioStatus(uint8_t status); @@ -792,7 +1210,9 @@ void RAILCb_TxRadioStatus(uint8_t status); * * A RAIL_PreTxOp_t function that schedules the transmit to occur at the * specified absolute or relative time within a RAIL_TxStart() transmit - * operation. + * operation. If RAIL is receiving a packet at the scheduled time, the transmit + * will be delayed until after the packet is received. To guarantee the time of + * the outgoing transmit, only call this function while the radio is idle. */ uint8_t RAIL_ScheduleTx(void *params); @@ -804,8 +1224,15 @@ uint8_t RAIL_ScheduleTx(void *params); * @return - Returns 0 on success and anything else on error. * * A RAIL_PreTxOp_t function that performs the CSMA algorithm when specified - * within a RAIL_TxStart() transmit operation. + * within a RAIL_TxStart() transmit operation. Packets can be received during + * CSMA backoff periods if receive is active throughout the CSMA process. This + * will happen either by starting the CSMA process while receive is already + * active, or if the ccaBackoff time in the RAIL_CsmaConfig_t is less than the + * idleToRx time (set by RAIL_SetStateTimings). If the ccaBackoff time is + * greater than the idleToRx time, then receive will only be active during the + * clear channel assessments. */ + uint8_t RAIL_CcaCsma(void *params); /** @@ -816,10 +1243,32 @@ uint8_t RAIL_CcaCsma(void *params); * @return Returns 0 on success and anything else on error. * * A RAIL_PreTxOp_t function that performs the LBT algorithm when specified - * within a RAIL_TxStart() transmit operation. + * within a RAIL_TxStart() transmit operation. Packets can be received during + * CSMA backoff periods if receive is active throughout the LBT process. This + * will happen either by starting the LBT process while receive is already + * active, or if the lbtBackoff time in the RAIL_LbtConfig_t is less than the + * idleToRx time (set by RAIL_SetStateTimings). If the lbtBackoff time is + * greater than the idleToRx time, then receive will only be active during the + * clear channel assessments. */ uint8_t RAIL_CcaLbt(void *params); +/** + * Sets the CCA threshold in dBm + * + * @param[in] ccaThresholdDbm CCA threshold in dBm. + * @return \ref RAIL_STATUS_NO_ERROR on success. + * + * A RAIL_PreTxOp_t function will normally set CCA threshold, assuming it is + * enabled either in LBT or CSMA mode. Unlike RAIL_CcaCsma and RAIL_CcaLbt, + * which are called as RAIL_PreTxOp_t functions, this function only modifies + * CCA threshold. A possible usecase for this function is to set CCA threshold + * to invalid RSSI of -128 which disables transmission by canceling + * the current CCA check. + * + */ +RAIL_Status_t RAIL_SetCcaThreshold(int8_t ccaThresholdDbm); + /** * end of group Pre-Transmit * @} @@ -850,10 +1299,23 @@ uint8_t RAIL_CcaLbt(void *params); * * Setup which receive interrupts will generate a RAILCb_RxRadioStatus() * callback. The full list of options is any define that starts with - * RAIL_RX_CONFIG_. This function cannot be called while receiving. + * RAIL_RX_CONFIG_. */ uint8_t RAIL_RxConfig(uint32_t cbToEnable, bool appendedInfoEnable); +/** + * Configure receive options + * + * @param[in] options Bitfield of options which affect recieve. The available + * options begin with RAIL_RX_OPTION. + * @return Return 0 for success or an error code + * + * Configure the radio receive flow, based on the list of available options. + * This will fail with RAIL_STATUS_INVALID_STATE if a packet is being received + * during this configuration. + */ +RAIL_Status_t RAIL_SetRxOptions(uint32_t options); + /** * Listen on a channel for a packet * @@ -861,7 +1323,7 @@ uint8_t RAIL_RxConfig(uint32_t cbToEnable, bool appendedInfoEnable); * @return Return 0 for success or an error code * * This is a non-blocking function. RAILCb_RxPacketReceived() will be called - * when a packet has been received. Returns an error is currently transmitting + * when a packet has been received. Returns an error if currently transmitting * or receiving. */ uint8_t RAIL_RxStart(uint8_t channel); @@ -878,7 +1340,7 @@ uint8_t RAIL_RxStart(uint8_t channel); * end time then you may call this API later with an end time as long as you set * the start time to disabled. You can also terminate the whole receive * operation immediately using the RAIL_RfIdle() function. Note that relative - * end times are always relative to the start unless there is not start + * end times are always relative to the start unless there is no start time * specified. */ uint8_t RAIL_ScheduleRx(uint8_t channel, RAIL_ScheduleRxConfig_t *cfg); @@ -899,6 +1361,71 @@ uint8_t RAIL_ScheduleRx(uint8_t channel, RAIL_ScheduleRxConfig_t *cfg); */ int16_t RAIL_RxGetRSSI(void); +/** + * Compute the average RSSI over a specified time in us + * + * @param[in] averageTimeUs Averaging time in microseconds. + * @return Return \ref RAIL_RSSI_INVALID if the receiver is disabled and we are + * unable to get an RSSI value, otherwise, return the RSSI in quarter dBm, + * dbm*4. + * + * This blocking function will poll the hardware for RSSI values and compute + * the average RSSI over the requested time period. If no valid readings have + * been made function will return \ref RAIL_RSSI_INVALID reading. Receiving a + * packet during the averaging will cause invalid reading(s). However, invalid + * readings during the averaging will not be included in the average. Number of + * RSSI readings per baud depends on the phy. + */ +int16_t RAIL_PollAverageRSSI(uint32_t averageTimeUs); + +/** + * Start the RSSI averaging over specified time in us + * + * @param[in] channel The physical channel to set + * @param[in] averagingTimeUs Averaging time in microseconds. + * @return Returns 0 on success, error code on error. + * + * Start a non-blocking hardware based RSSI averaging mechanism. Only a single + * instance of RSSI averaging can be run at any time and the radio must be idle + * to start. + */ +RAIL_Status_t RAIL_StartAverageRSSI(uint8_t channel, uint32_t averagingTimeUs); + +/** + * Queries whether the RSSI averaging is done + * + * @return Returns true if done and false otherwise. + * + * This function can be used to poll for completion of the RSSI averaging so + * that you do not have to rely on an interrupt based callback. + */ +bool RAIL_AverageRSSIReady(void); + +/** + * Get the RSSI averaged over specified time in us + * + * @return Return \ref RAIL_RSSI_INVALID if the receiver is disabled and we are + * unable to get an RSSI value, otherwise, return the RSSI in quarter dBm, + * dbm*4. + * + * Get the hardware RSSI average after issuing RAIL_StartAverageRSSI. Should be + * used after RAIL_StartAverageRSSI. + */ +int16_t RAIL_GetAverageRSSI(void); + +/** + * Callback for when AGC averaged RSSI is done + * + * @param avgRssi Contains the the RSSI in quarter dBm (dbm*4) on success and + * returns \ref RAIL_RSSI_INVALID if there was a problem computing the result. + * + * Called in response to RAIL_StartAverageRSSI() to indicate that the hardware + * has completed averaging. If you would like you can instead use the + * RAIL_AverageRSSIReady() to wait for completion and RAIL_GetAverageRSSI() to + * get the result. + */ +void RAILCb_RssiAverageDone(int16_t avgRssi); + /** * Receive packet callback. * @@ -912,6 +1439,9 @@ int16_t RAIL_RxGetRSSI(void); * stored. After this callback is done we will release the memory handle so you * must somehow increment a reference count or copy the data out within this * function. + * + * If \ref RAIL_IGNORE_CRC_ERRORS is set, this callback will fire for packets + * with crc errors as well. */ void RAILCb_RxPacketReceived(void *rxPacketHandle); @@ -965,6 +1495,7 @@ void RAILCb_RxRadioStatus(uint8_t status); * - \ref RAIL_RX_CONFIG_RF_SENSED * - \ref RAIL_RX_CONFIG_TIMEOUT * - \ref RAIL_RX_CONFIG_SCHEDULED_RX_END + * - \ref RAIL_RX_CONFIG_PACKET_ABORTED */ void RAILCb_RxRadioStatusExt(uint32_t status); @@ -1031,8 +1562,9 @@ void RAILCb_RxRadioStatusExt(uint32_t status); * ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD. For more complex systems you'll have to * create a valid table on your own. * - * @note When using a 38.4 MHz crystal, address filtering will not function with - * any data rate greater than 1Mbps. + * @note Address filtering does not function properly with PHYs that use a data + * rate greater than 500kbps. If you require this you must filter in software + * for the time being. * * @{ */ @@ -1139,7 +1671,7 @@ bool RAIL_AddressFilterDisableAddress(uint8_t field, uint8_t index); * * @param validFrames The frames on which to enable address filtering. Each bit * corresponds to a frame, where a 1 means to enable address filtering during - * that frame, and a 0 means to ignore addresses during that frame.. The least + * that frame, and a 0 means to ignore addresses during that frame. The least * significant bit corresponds to frame 0, and the most significant bit to * frame 7. * @return True if configuration was set properly, false otherwise @@ -1216,6 +1748,8 @@ bool RAIL_AddressFilterByFrameType(uint8_t validFrames); * @code{.c} * void RAILCb_RxPacketReceived(void *rxPacketHandle) * { + * RAIL_RxPacketInfo_t rxPacketInfo = (RAIL_RxPacketInfo_t)rxPacketHandle; + * * // If we have just received an ACK, don't respond with an ACK * if (rxPacketInfo->dataPtr[2] == 0xF1) * { @@ -1589,6 +2123,7 @@ uint8_t RAIL_TxStreamStop(void); * During BER test mode, this device will expect to receive a standard PN9 * signal (x^9 + x^5 + 1). In order to use this BER test, the selection * for BER mode should be enabled from the radio configurator. + * This function has been deprecated. */ void RAIL_BerConfigSet(RAIL_BerConfig_t *berConfig); @@ -1599,6 +2134,7 @@ void RAIL_BerConfigSet(RAIL_BerConfig_t *berConfig); * * Enter BER receive with the settings specified by RAIL_BerConfigSet(). * This also resets the BER status. + * This function has been deprecated. */ void RAIL_BerRxStart(void); @@ -1608,6 +2144,7 @@ void RAIL_BerRxStart(void); * @return void * * Halt a test early, or exit infinite BER receive mode. + * This function has been deprecated. */ void RAIL_BerRxStop(void); @@ -1618,6 +2155,7 @@ void RAIL_BerRxStop(void); * @return void * * Get status of latest BER test. + * This function has been deprecated. */ void RAIL_BerStatusGet(RAIL_BerStatus_t *status); @@ -1658,7 +2196,7 @@ uint32_t RAIL_DebugModeGet(void); * * @param[in] freq Desired frequency in Hz * - * Sets the radio to transmit at a the frequency given. This function can only + * Sets the radio to transmit at the frequency given. This function can only * be used while in RAIL_DEBUG_MODE_FREQ_OVERRIDE. The given frequency needs * to be close to the base frequency of the current PHY. */ @@ -1666,24 +2204,21 @@ RAIL_Status_t RAIL_DebugFrequencyOverride(uint32_t freq); #endif /** - * Interrupt level callback to signify when the radio changes state. This is - * for debug and __NOT__ for application use. It is not called by default but - * is required for the linking process. + * Callback function to signify when the radio changes state. + * + * @param[in] state Current state of the radio. Exact values are for internal + * use only. * - * Create an empty function for this callback. + * This is for debug and __NOT__ for application use. It is not called by + * default but is required for the linking process. + * + * Create an empty function for this callback as shown below. * * @code{.c} * RAILCb_RadioStateChanged(uint8_t state) { * } * @endcode */ -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * @param[in] state Current state of the radio, as defined by EFR32 data sheet - * TODO: Unify these states with the RAIL_RadioState_t type? (There are much - * more than just TX, RX, and IDLE) - */ -#endif void RAILCb_RadioStateChanged(uint8_t state); /** diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_chip_specific.h b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_chip_specific.h index fad46dab6c7..dfe2c87305f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_chip_specific.h +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_chip_specific.h @@ -31,13 +31,16 @@ * something that can be computed once and stored off or computed each time at * startup. It is PHY specific and provides sensitivity improvements so we * highly recommend using it. The IR calibration should only be run when the - * radio is IDLE. The temperature dependent calibrations are used to - * recalibrate the synth if the temperature falls below 0 or changes by a - * certain amount while sitting in receive. We will do this automatically upon - * entering the receive state so you may omit this calibration if you feel that - * your stack will turn receive on and off frequently enough. If you do not - * calibrate for temperature it's possible to miss receive packets due to drift - * in the carrier frequency. + * radio is IDLE. + * + * The temperature dependent calibrations are used to recalibrate the synth if + * the temperature crosses 0C or the temperature delta since the last + * calibration exceeds 70C while sitting in receive. RAIL will run VCO + * calibration automatically upon entering receive state so the application can + * omit this calibration if the stack will re-enter receive with enough + * frequency to not hit this temperature delta. If the application does not + * calibrate for temperature, it's possible to miss receive packets due to + * drift in the carrier frequency. */ /** diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_types.h b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_types.h index 75de9d0e98a..8578404bb74 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_types.h +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_types.h @@ -13,7 +13,7 @@ #include #include -#include "rail/rail_chip_specific.h" +#include "rail_chip_specific.h" /** * @addtogroup RAIL_API @@ -77,7 +77,7 @@ typedef struct RAIL_Version { * @brief Initialization structure for the RAIL library. */ typedef struct RAIL_Init { - uint16_t maxPacketLength; /**< The maximum number of bytes in a packet. */ + uint16_t maxPacketLength; /**< The maximum number of bytes in a packet. UNUSED! */ const uint32_t rfXtalFreq; /**< The xtal frequency of the radio. */ RAIL_CalMask_t calEnable; /**< Mask that defines calibrations to perform in RAIL. */ } RAIL_Init_t; @@ -88,11 +88,10 @@ typedef struct RAIL_Init { */ typedef enum RAIL_PtiProtocol { RAIL_PTI_PROTOCOL_CUSTOM = 0, /**< PTI output for a custom protocol */ - RAIL_PTI_PROTOCOL_ZIGBEE = 1, /**< PTI output for the Zigbee protocol */ RAIL_PTI_PROTOCOL_THREAD = 2, /**< PTI output for the Thread protocol */ RAIL_PTI_PROTOCOL_BLE = 3, /**< PTI output for the Bluetooth Smart protocol */ RAIL_PTI_PROTOCOL_CONNECT = 4, /**< PTI output for the Connect protocol */ - RAIL_PTI_PROTOCOL_MAX = 0xF /**< Maximum possible protocol value for PTI */ + RAIL_PTI_PROTOCOL_ZIGBEE = 5, /**< PTI output for the Zigbee protocol */ } RAIL_PtiProtocol_t; /** @@ -150,9 +149,80 @@ typedef enum { * abort all current operations and cancel any pending scheduled operations. * It may also corrupt receive or transmit buffers and end up clearing them. */ - RAIL_IDLE_FORCE_SHUTDOWN + RAIL_IDLE_FORCE_SHUTDOWN, + /** + * Similar to the \ref RAIL_IDLE_FORCE_SHUTDOWN command this will quickly + * put the radio into the idle state. In addition to this it will clear any + * pending receive or transmit callbacks and clear both the receive and + * transmit storage. + */ + RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS } RAIL_RfIdleMode_t; +/** + * @} + */ + +// ----------------------------------------------------------------------------- +// Data Management Structures +// ----------------------------------------------------------------------------- + +/** + * @addtogroup Data_Management + * @{ + */ + +/** + * @enum RAIL_TxDataSource_t + * @brief Transmit data sources supported by RAIL. + */ +typedef enum{ + TX_PACKET_DATA, /**< Use the frame hardware to packetize data */ +} RAIL_TxDataSource_t; + +/** + * @enum RAIL_RxDataSource_t + * @brief Receive data sources supported by RAIL. + */ +typedef enum{ + RX_PACKET_DATA, /**< Use the frame hardware to packetize data */ + RX_DEMOD_DATA, /**< Get 8-bit data output from the demodulator */ + RX_IQDATA_FILTLSB, /**< Get lower 16 bits of I/Q data provided to demodulator */ + RX_IQDATA_FILTMSB /**< Get highest 16 bits of I/Q data provided to demodulator */ +} RAIL_RxDataSource_t; + +/** + * @enum RAIL_DataMethod_t + * @brief Methods for the application to provide and retreive data from RAIL. + */ +typedef enum{ + PACKET_MODE, /**< Packet based data method */ + FIFO_MODE, /**< FIFO based data method */ +} RAIL_DataMethod_t; + +/** + * @struct RAIL_DataConfig_t + * @brief RAIL data configuration structure + * + * This structure is used to select the transmit/receive data sources, and the + * method the application uses to provide/retreive data from RAIL. + */ +typedef struct { + RAIL_TxDataSource_t txSource; /**< Source of TX Data */ + RAIL_RxDataSource_t rxSource; /**< Source of RX Data */ + RAIL_DataMethod_t txMethod; /**< Method of providing transmit data */ + RAIL_DataMethod_t rxMethod; /**< Method of retrieving receive data */ +} RAIL_DataConfig_t; + +/** + * @def RAIL_SETFIXEDLENGTH_INVALID + * @brief Invalid return value when calling RAIL_SetFixedLength() + * + * Invalid return value when calling RAIL_SetFixedLength() while the radio is + * not in fixed length mode. + */ +#define RAIL_SETFIXEDLENGTH_INVALID (0xFFFF) + /** * @} */ @@ -203,6 +273,8 @@ typedef struct RAIL_FrameType { * channel space and the channel indexes that are valid within this range. * * * frequency = baseFrequency + channelSpacing * (channel - channelNumberStart); + * + * Each RAIL_ChannelConfigEntry_t should not span more than 64 channels. */ typedef struct RAIL_ChannelConfigEntry { uint16_t channelNumberStart; /**< RAIL Channel number in which this channel set begins.*/ @@ -214,7 +286,47 @@ typedef struct RAIL_ChannelConfigEntry { /** * @struct RAIL_ChannelConfig_t * @brief Channel configuration structure which defines the channel meaning when - * passed into RAIL functions, eg. RAIL_TxStart(), RAIL_RxStart() + * a channel number is passed into a RAIL function, eg. RAIL_TxStart(), RAIL_RxStart() + * + * A RAIL_ChannelConfig_t structure defines the channel scheme that an + * application uses when registered in RAIL_ChannelConfig(). A channel scheme + * must be in the same band, it can not span across frequencies that would + * change the divider. + * + * A few examples of different channel schemes: + * @code{.c} + * // Ten channels starting a 915 Mhz with a channel spacing of 1 Mhz + * RAIL_ChannelConfigEntry_t channels = { + * 0, 9, 1000000, 915000000 + * }; + * RAIL_ChannelConfig_t channelScheme = { + * channels, + * 1 + * }; + * + * // 120 channels starting at 915Mhz with channel spacing of 100KHz + * RAIL_ChannelConfigEntry_t channels[] = { + * {0, 63, 100000, 910000000}, + * {64, 119, 100000, 916400000}, + * }; + * RAIL_ChannelConfig_t channelScheme = { + * channels, + * 2 + * }; + * + * // 5 nonlinear channels + * RAIL_ChannelConfigEntry_t channels[] = { + * {0, 0, 0, 910123456}, + * {1, 1, 0, 911654789}, + * {2, 2, 0, 912321456}, + * {3, 3, 0, 913147852}, + * {4, 4, 0, 914567890} + * }; + * RAIL_ChannelConfig_t channelScheme = { + * channels, + * 5 + * }; + * @endcode */ typedef struct RAIL_ChannelConfig { RAIL_ChannelConfigEntry_t *configs; /**< Pointer to an array of RAIL_ChannelConfigEntry_t entries.*/ @@ -314,13 +426,39 @@ typedef struct RAIL_AddrConfig { /** * @enum RAIL_TimeMode_t - * @brief Enumeration for specifying timing offsets in RAIL for any APIs that - * use them. + * @brief This type is used to specifying a time offset in RAIL APIs. + * + * Different APIs use these same constants and may provide more specifics of how + * they're used but the general philosophy for each is described below. */ typedef enum RAIL_TimeMode { - RAIL_TIME_ABSOLUTE, /**< The time specified is an exact time in the RAIL timebase */ - RAIL_TIME_DELAY, /**< The time specified is relative to now */ - RAIL_TIME_DISABLED /**< The time specified is not intended to be used */ + /** + * The time specified is an exact time in the RAIL timebase and the given + * event should happen at exactly that time. If this time is already in the + * past we will return an error and fail. Since the RAIL timebase wraps at 32 + * bits there is no real 'past' so we instead consider any event greater than + * 3/4 of the way into the future to be in the past. + */ + RAIL_TIME_ABSOLUTE, + /** + * The time specified is relative to now and the event should occur that many + * ticks in the future. Delays are only guaranteed to be at least as long as + * the value specified. There may be some overhead between when the API is + * called and when the delay starts so we _do not_ recommend using this for + * operations that must happen at exactly a given time. For that you must use + * \ref RAIL_TIME_ABSOLUTE delays. + * + * Note that if you specify a delay of 0 we will trigger that event as soon as + * possible. This is different than specifying an absolute time of now which + * would return an error unless it was possible. + */ + RAIL_TIME_DELAY, + /** + * The specified time is invalid and should be ignored. For some APIs this can + * also indicate that any previously stored delay should be invalidated and + * disabled. + */ + RAIL_TIME_DISABLED } RAIL_TimeMode_t; /** @@ -350,8 +488,17 @@ typedef uint8_t (*RAIL_PreTxOp_t)(void *params); * must be passed as its argument. */ typedef struct RAIL_ScheduleTxConfig { - uint32_t when; /**< When to transmit this packet in the RAIL timebase. */ - RAIL_TimeMode_t mode; /**< Specifies whether when is an absolute time or an offset from now. */ + /** + * When to transmit this packet. The exact interpretation of this value + * depends on the mode specified below. + */ + uint32_t when; + /** + * They type of delay to use. See the \ref RAIL_TimeMode_t documentation for + * more information. Be sure to use \ref RAIL_TIME_ABSOLUTE delays for time + * critical protocols. + */ + RAIL_TimeMode_t mode; } RAIL_ScheduleTxConfig_t; /** @@ -368,8 +515,14 @@ typedef struct RAIL_ScheduleTxConfig { * argument. */ typedef struct RAIL_CsmaConfig { - uint8_t csmaMinBoExp; /**< Minimum (starting) exponent for CSMA backoff (2^exp - 1) */ - uint8_t csmaMaxBoExp; /**< Maximum exponent for CSMA backoff */ + /** + * Minimum (starting) exponent for CSMA backoff (2^exp - 1) + */ + uint8_t csmaMinBoExp; + /** + * Maximum exponent for CSMA backoff + */ + uint8_t csmaMaxBoExp; /** * Number of CCA failures before report CCA_FAIL. With a maximum value defined * in @ref RAIL_MAX_LBT_TRIES). A value of 0 will perform no CCA assessments, @@ -383,15 +536,16 @@ typedef struct RAIL_CsmaConfig { int8_t ccaThreshold; /** * The backoff unit period, in RAIL's microsecond time base. This is - * mulitiplied by the random backoff multiplier controlled by @ref + * mulitiplied by the random backoff exponential controlled by @ref * csmaMinBoExp and @ref csmaMaxBoExp to determine the overall backoff - * period. This value must be at least the idleToRx time (set by - * RAIL_SetStateTimings). For random backoffs, any value above 511 - * microseconds will be truncated; for fixed backoffs it can go up to 65535 - * microseconds. + * period. For random backoffs, any value above 511 microseconds will + * be truncated; for fixed backoffs it can go up to 65535 microseconds. */ uint16_t ccaBackoff; - uint16_t ccaDuration; /**< CCA check duration, in microseconds */ + /** + * CCA check duration in microseconds. + */ + uint16_t ccaDuration; /** * An overall timeout, in RAIL's microsecond time base, for the operation. If * transmission doesn't start before this timeout expires, the transmission @@ -442,14 +596,20 @@ typedef struct RAIL_CsmaConfig { * argument. */ typedef struct RAIL_LbtConfig { - uint8_t lbtMinBoRand; /**< Minimum backoff random multiplier */ - uint8_t lbtMaxBoRand; /**< Maximum backoff random multiplier */ + /** + * Maximum backoff random multiplier + */ + uint8_t lbtMinBoRand; + /** + * Maximum backoff random multiplier + */ + uint8_t lbtMaxBoRand; /** * Number of CCA failures before report CCA_FAIL. With a maximum value defined * in @ref RAIL_MAX_LBT_TRIES). A value of 0 will perform no CCA assessments, * and always transmit immediately. */ - uint8_t lbtTries; /**< Number of LBT failures before report CCA_FAIL */ + uint8_t lbtTries; /** * The CCA RSSI threshold, in dBm, above which the channel is * considered 'busy'. @@ -458,13 +618,15 @@ typedef struct RAIL_LbtConfig { /** * The backoff unit period, in RAIL's microsecond time base. This is * mulitiplied by the random backoff multiplier controlled by @ref - * csmaMinBoExp and @ref csmaMaxBoExp to determine the overall backoff - * period. For random backoffs, this value must be in the range from - * idleToRx time (set by RAIL_SetStateTimings) to 511 microseconds; for fixed - * backoffs it can go up to 65535 microseconds. + * lbtMinBoRand and @ref lbtMaxBoRand to determine the overall backoff + * period. For random backoffs, any value above 511 microseconds will + * be truncated; for fixed backoffs it can go up to 65535 microseconds. */ uint16_t lbtBackoff; - uint16_t lbtDuration; /**< LBT check duration, in microseconds */ + /** + * LBT check duration in microseconds. + */ + uint16_t lbtDuration; /** * An overall timeout, in RAIL's microsecond time base, for the * operation. If transmission doesn't start before this timeout expires, the @@ -508,6 +670,8 @@ typedef struct RAIL_LbtConfig { */ // Tx Config Callback Defines +/** Callback for a transmit buffer overflow event */ +#define RAIL_TX_CONFIG_BUFFER_OVERFLOW (0x01 << 0) /** Callback for a transmit buffer underflow event */ #define RAIL_TX_CONFIG_BUFFER_UNDERFLOW (0x01 << 1) /** Callback for CCA/CSMA/LBT failure */ @@ -516,6 +680,12 @@ typedef struct RAIL_LbtConfig { #define RAIL_TX_CONFIG_TX_ABORTED (0x01 << 3) /** Callback for when a Tx is blocked by something like PTA or RHO */ #define RAIL_TX_CONFIG_TX_BLOCKED (0x01 << 4) +/** Callback for CCA/CSMA/LBT success */ +#define RAIL_TX_CONFIG_CHANNEL_CLEAR (0x01 << 5) +/** Callback for when an CCA check is being retried */ +#define RAIL_TX_CONFIG_CCA_RETRY (0x01 << 6) +/** Callback for when a clear channel assessment (CCA) is begun */ +#define RAIL_TX_CONFIG_START_CCA (0x01 << 7) /** * @struct RAIL_TxData_t @@ -525,7 +695,7 @@ typedef struct RAIL_LbtConfig { */ typedef struct RAIL_TxData { uint8_t *dataPtr; /**< Pointer to data to transmit */ - uint16_t dataLength; /**< Number of bytes to transmit */ + uint16_t dataLength; /**< Number of bytes to load into transmit buffer */ } RAIL_TxData_t; /** @@ -534,7 +704,8 @@ typedef struct RAIL_TxData { */ typedef struct RAIL_TxPacketInfo { /** - * Time recorded when the last bit is transmitted out of the modulator. + * Timestamp of the transmitted packet in the RAIL timebase of microseconds. + * The time is the end of the last bit of the transmitted packet. */ uint32_t timeUs; } RAIL_TxPacketInfo_t; @@ -562,13 +733,21 @@ typedef struct RAIL_TxOptions { */ // Rx Config Callback Defines +/** Callback for when more is read from the Rx buffer than is available */ +#define RAIL_RX_CONFIG_BUFFER_UNDERFLOW (0x01 << 0) /** Callback for preamble detection */ #define RAIL_RX_CONFIG_PREAMBLE_DETECT (0x01 << 1) /** Callback for detection of the first sync word */ #define RAIL_RX_CONFIG_SYNC1_DETECT (0x01 << 2) /** Callback for detection of the second sync word */ #define RAIL_RX_CONFIG_SYNC2_DETECT (0x01 << 3) -/** Callback for detection of frame errors */ +/** Callback for detection of frame errors + * + * For efr32xg1x parts, frame errors include violations of variable length + * min/max limits, frame coding errors, and crc errors. If \ref + * RAIL_IGNORE_CRC_ERRORS are set, \ref RAIL_RX_CONFIG_FRAME_ERROR will not be + * asserted for crc errors. + */ #define RAIL_RX_CONFIG_FRAME_ERROR (0x01 << 4) /** Callback for when we run out of Rx buffer space */ #define RAIL_RX_CONFIG_BUFFER_OVERFLOW (0x01 << 5) @@ -580,16 +759,42 @@ typedef struct RAIL_TxOptions { #define RAIL_RX_CONFIG_TIMEOUT (0x01 << 8) /** Callback for when the scheduled Rx window ends */ #define RAIL_RX_CONFIG_SCHEDULED_RX_END (0x01 << 9) +/** Callback for an aborted packet. This is triggered when a more specific + * reason the packet was aborted, such as RAIL_RX_CONFIG_ADDRESS_FILTERED, is + * not known. */ +#define RAIL_RX_CONFIG_PACKET_ABORTED (0x01 << 10) +/** + * Callback for when the packet has passed any configured address and frame + * filtering options. + */ +#define RAIL_RX_CONFIG_FILTER_PASSED (0x01 << 11) /** To maintain backwards compatibility with RAIL 1.1, * RAIL_RX_CONFIG_INVALID_CRC is the same as RAIL_RX_CONFIG_FRAME_ERROR */ #define RAIL_RX_CONFIG_INVALID_CRC RAIL_RX_CONFIG_FRAME_ERROR +// Rx Option Defines +/** Option to configure whether the CRC portion of the packet is included in + * the dataPtr field of the RAIL_RxPacketInfo_t passed via + * RAILCb_RxPacketReceived(). Defaults to false. */ +#define RAIL_RX_OPTION_STORE_CRC (1 << 0) + // Rx Config Ignore Error Defines -/** Ignore no errors. Drop all packets with errors */ +/** + * Ignore no errors. + * + * Drop all packets with errors. With this setting, crc errors will generate a + * RAILCb_RxRadioStatus() with \ref RAIL_RX_CONFIG_FRAME_ERROR. + */ #define RAIL_IGNORE_NO_ERRORS (0x00) -/** Ignore CRC errors. Receive packets with CRC errors */ +/** + * Hardware ignores CRC errors. + * + * When this setting is enabled and a CRC error occurs, RAILCb_RxRadioStatus() + * with \ref RAIL_RX_CONFIG_FRAME_ERROR will not occur. Instead packets with crc + * errors will generate RAILCb_RxPacketReceived(). + */ #define RAIL_IGNORE_CRC_ERRORS (0x01 << 0) /** Ignore all possible errors. Receive all possible packets */ #define RAIL_IGNORE_ALL_ERRORS (0xFF) @@ -606,8 +811,8 @@ typedef struct RAIL_TxOptions { */ typedef struct RAIL_AppendedInfo { /** - * Timestamp of the received packet in the RAIL timebase of microseconds. - * This time is recorded at sync detect. + * Timestamp of the received packet in the RAIL timebase of microseconds. The + * time is the end of the sync word of the received packet. */ uint32_t timeUs; /** @@ -623,7 +828,8 @@ typedef struct RAIL_AppendedInfo { /** * Indicates if the received packet is an ack. An 'ack' is defined as a * packet received during the rx ack window when autoack is enabled. - * Set to 0 for not an ack, and 1 for is an ack. + * Set to 0 for not an ack, and 1 for is an ack. Will always be 0 if + * autoack is not enabled. */ bool isAck:1; /** @@ -632,8 +838,8 @@ typedef struct RAIL_AppendedInfo { */ int8_t rssiLatch; /** - * Link quality indicator of the received packet. This is not currently - * implemented. + * Link quality indicator of the received packet. This is calculated as the + * average correlation for the first 8 symbols in a frame. */ uint8_t lqi; /** @@ -645,26 +851,35 @@ typedef struct RAIL_AppendedInfo { /** * @struct RAIL_RxPacketInfo_t - * @brief Rx Packet Information structure passed into RAILCb_RxPacketReceived - * after a packet has been received. Contains a pointer to the data recieved, - * as well as other packet information. + * @brief Receive packet information structure + * + * The structure used to pass an over the air packet and some associated + * information up to the application code. The memory handle that you receive + * in the call to RAILCb_RxPacketReceived() will contain this data structure. */ typedef struct RAIL_RxPacketInfo { - RAIL_AppendedInfo_t appendedInfo; /**< A structure containing various extra information about the received packet. */ - uint16_t dataLength; /**< The number of bytes in the dataPtr array. */ - uint8_t dataPtr[]; /**< A variable length array holding the packet contents. */ + /** + * A structure containing the extra information associated with this received + * packet. + */ + RAIL_AppendedInfo_t appendedInfo; + /** + * The number of bytes that are in the dataPtr array. + */ + uint16_t dataLength; + /** + * A variable length array holding the receive packet data bytes. + */ + uint8_t dataPtr[]; } RAIL_RxPacketInfo_t; /** * @struct RAIL_ScheduleRxConfig_t - * @brief This structure is used to configure the Scheduled Rx algorithm. It - * allows you to define the start and end times of the window in either absolute - * or relative times. If start is set to \ref RAIL_TIME_DISABLED it will be - * assumed that we should start receive now. If end is set to \ref - * RAIL_TIME_DISABLED then the only way to end this scheduled receive is with an - * explicit call to RAIL_RfIdle(). If end is relative it is relative to the - * start time not the current time. All times are assumed to be specified in the - * RAIL timebase. + * @brief This structure is used to configure the Scheduled Rx algorithm. + * + * It allows you to define the start and end times of the receive window created + * for scheduled receive. If either start or end times are disabled then they + * will be ignored. */ typedef struct RAIL_ScheduleRxConfig { /** @@ -672,15 +887,12 @@ typedef struct RAIL_ScheduleRxConfig { * types of start times that you can specify. */ uint32_t start; - /** - * The type of time value specified in the start parameter. If this is - * \ref RAIL_TIME_ABSOLUTE then it's an exact time, if it's \ref - * RAIL_TIME_DELAY then it's an offset relative to the current time. If you - * specify \ref RAIL_TIME_DISABLED for this then the start event will be - * ignored. + * How to interpret the time value specified in the start parameter. See the + * \ref RAIL_TimeMode_t documentation for more information. Use + * \ref RAIL_TIME_ABSOLUTE for absolute times, \ref RAIL_TIME_DELAY for times + * relative to now, and \ref RAIL_TIME_DISABLED to ignore the start time. */ - RAIL_TimeMode_t startMode; /** * The time to end receive. See endMode for more information about the types @@ -688,11 +900,13 @@ typedef struct RAIL_ScheduleRxConfig { */ uint32_t end; /** - * The type of time value specified in the end parameter. If this is - * \ref RAIL_TIME_ABSOLUTE then it's an exact time, if it's \ref RAIL_TIME_DELAY then - * it's an offset relative to the start time as long as the startMode isn't - * \ref RAIL_TIME_DISABLED and if it's \ref RAIL_TIME_DISABLED we will not configure the - * end event so that this can run indefinitely. + * How to interpret the time value specified in the end parameter. See the + * \ref RAIL_TimeMode_t documentation for more information. Note that in this + * API if you specify a \ref RAIL_TIME_DELAY it will be relative to the start + * time if given and relative to now if none is specified. Also, using \ref + * RAIL_TIME_DISABLED means that this window will not end unless you + * explicitly call RAIL_RfIdle() or add an end event through a future update + * to this configuration. */ RAIL_TimeMode_t endMode; /** diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/mbed_lib.json b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/mbed_lib.json index fc7c7e08227..1725bc8fd7e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/mbed_lib.json +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/mbed_lib.json @@ -1,6 +1,35 @@ { "name": "sl-rail", "config": { - "band": 2400 + "band": { + "help" : "Configure this to 2400, 915 or 868 depending on which band you want to run on (and have available on the board)", + "value" : 2400 + }, + "PTI": true, + "has-2p4": false, + "has-subgig": false, + "pti-mode": "RADIO_PTI_MODE_UART", + "pti-baudrate" : 1600000, + "pti-dout-location": 6, + "pti-dout-port": "gpioPortB", + "pti-dout-pin": 12, + "pti-dclk-location": 6, + "pti-dclk-port": "gpioPortB", + "pti-dclk-pin": 11, + "pti-dframe-location": 6, + "pti-dframe-port": "gpioPortB", + "pti-dframe-pin": 13 + }, + "target_overrides": { + "THUNDERBOARD_SENSE": { + "sl-rail.has-2p4": true + }, + "THUNDERBOARD_SENSE_12": { + "sl-rail.has-2p4": true + }, + "EFR32MG1_BRD4150": { + "sl-rail.has-2p4": true, + "sl-rail.has-subgig": true + } } } diff --git a/targets/TARGET_Silicon_Labs/mbed_rtx.h b/targets/TARGET_Silicon_Labs/mbed_rtx.h index 1a8c5a2ab99..51dfdbb16db 100644 --- a/targets/TARGET_Silicon_Labs/mbed_rtx.h +++ b/targets/TARGET_Silicon_Labs/mbed_rtx.h @@ -115,6 +115,19 @@ extern uint32_t STACK$$Base; #define OS_MAINSTKSIZE 256 #endif +#elif defined(TARGET_EFR32MG12) || defined(TARGET_EFM32PG12) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20040000UL) +#endif + +#ifndef OS_TASKCNT +#define OS_TASKCNT 14 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 256 +#endif + #endif #endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index ee38b950b9c..a08f523ac58 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -903,7 +903,7 @@ "extra_labels": ["STM", "STM32F4", "STM32F439", "STM32F439ZI", "STM32F439xx", "STM32F439xI", "FLASH_CMSIS_ALGO"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "progen": {"target": "nucleo-f439zi"}, - "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"], + "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "MBEDTLS_CONFIG_HW_SUPPORT"], "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"], "detect_code": ["0797"], "features": ["LWIP"], @@ -1920,7 +1920,7 @@ }, "EFM32GG990F1024": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32GG", "1024K"], + "extra_labels_add": ["EFM32GG", "1024K", "SL_AES"], "core": "Cortex-M3", "macros": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -1973,7 +1973,7 @@ }, "EFM32LG990F256": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32LG", "256K"], + "extra_labels_add": ["EFM32LG", "256K", "SL_AES"], "core": "Cortex-M3", "macros": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2026,7 +2026,7 @@ }, "EFM32WG990F256": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32WG", "256K"], + "extra_labels_add": ["EFM32WG", "256K", "SL_AES"], "core": "Cortex-M4F", "macros": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2079,7 +2079,7 @@ }, "EFM32ZG222F32": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32ZG", "32K"], + "extra_labels_add": ["EFM32ZG", "32K", "SL_AES"], "core": "Cortex-M0+", "default_toolchain": "uARM", "macros": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"], @@ -2133,7 +2133,7 @@ }, "EFM32HG322F64": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32HG", "64K"], + "extra_labels_add": ["EFM32HG", "64K", "SL_AES"], "core": "Cortex-M0+", "default_toolchain": "uARM", "macros": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"], @@ -2187,7 +2187,7 @@ }, "EFM32PG1B100F256GM32": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32PG", "256K"], + "extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"], "core": "Cortex-M4F", "macros": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2239,7 +2239,7 @@ }, "EFR32MG1P132F256GM48": { "inherits": ["EFM32"], - "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL"], + "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"], "core": "Cortex-M4F", "macros": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2249,7 +2249,7 @@ }, "EFR32MG1P233F256GM48": { "inherits": ["EFM32"], - "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL"], + "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"], "core": "Cortex-M4F", "macros": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2258,7 +2258,7 @@ }, "EFR32MG1_BRD4150": { "inherits": ["EFR32MG1P132F256GM48"], - "device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "RF_SUBGHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 2, "config": { "hf_clock_src": { @@ -2301,7 +2301,104 @@ }, "THUNDERBOARD_SENSE": { "inherits": ["EFR32MG1P233F256GM48"], - "device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], + "forced_reset_timeout": 5, + "config": { + "hf_clock_src": { + "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator", + "value": "HFXO", + "macro_name": "CORE_CLOCK_SOURCE" + }, + "hfxo_clock_freq": { + "help": "Value: External crystal frequency in hertz", + "value": "38400000", + "macro_name": "HFXO_FREQUENCY" + }, + "lf_clock_src": { + "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator", + "value": "LFXO", + "macro_name": "LOW_ENERGY_CLOCK_SOURCE" + }, + "lfxo_clock_freq": { + "help": "Value: External crystal frequency in hertz", + "value": "32768", + "macro_name": "LFXO_FREQUENCY" + }, + "hfrco_clock_freq": { + "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select", + "value": "32000000", + "macro_name": "HFRCO_FREQUENCY" + }, + "hfrco_band_select": { + "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!", + "value": "cmuHFRCOFreq_32M0Hz", + "macro_name": "HFRCO_FREQUENCY_ENUM" + } + } + }, + "EFM32PG12B500F1024GL125": { + "inherits": ["EFM32"], + "extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"], + "core": "Cortex-M4F", + "macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], + "release_versions": ["2", "5"], + "public": false + }, + "EFM32PG12_STK3402": { + "inherits": ["EFM32PG12B500F1024GL125"], + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], + "forced_reset_timeout": 2, + "config": { + "hf_clock_src": { + "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator", + "value": "HFXO", + "macro_name": "CORE_CLOCK_SOURCE" + }, + "hfxo_clock_freq": { + "help": "Value: External crystal frequency in hertz", + "value": "40000000", + "macro_name": "HFXO_FREQUENCY" + }, + "lf_clock_src": { + "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator", + "value": "LFXO", + "macro_name": "LOW_ENERGY_CLOCK_SOURCE" + }, + "lfxo_clock_freq": { + "help": "Value: External crystal frequency in hertz", + "value": "32768", + "macro_name": "LFXO_FREQUENCY" + }, + "hfrco_clock_freq": { + "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select", + "value": "32000000", + "macro_name": "HFRCO_FREQUENCY" + }, + "hfrco_band_select": { + "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!", + "value": "cmuHFRCOFreq_32M0Hz", + "macro_name": "HFRCO_FREQUENCY_ENUM" + }, + "board_controller_enable": { + "help": "Pin to pull high for enabling the USB serial port", + "value": "PA5", + "macro_name": "EFM_BC_EN" + } + } + }, + "EFR32MG12P332F1024GL125": { + "inherits": ["EFM32"], + "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL", "SL_CRYPTO"], + "core": "Cortex-M4F", + "macros": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], + "release_versions": ["2", "5"], + "public": false + }, + "THUNDERBOARD_SENSE_12": { + "inherits": ["EFR32MG12P332F1024GL125"], + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 5, "config": { "hf_clock_src": { @@ -2545,6 +2642,16 @@ "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], "release_versions": ["2", "5"], "overrides": {"lf_clock_src": "NRF_LF_SRC_RC"}, + "config": { + "lf_clock_rc_calib_timer_interval": { + "value": 16, + "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL" + }, + "lf_clock_rc_calib_mode_config": { + "value": 0, + "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG" + } + }, "device_name": "nRF52832_xxAA" }, "BLUEPILL_F103C8": { diff --git a/tools/arm_pack_manager/__init__.py b/tools/arm_pack_manager/__init__.py index 963377dc04d..d297f063b8e 100644 --- a/tools/arm_pack_manager/__init__.py +++ b/tools/arm_pack_manager/__init__.py @@ -13,6 +13,7 @@ from zipfile import ZipFile from tempfile import gettempdir import warnings +from distutils.version import LooseVersion warnings.filterwarnings("ignore") @@ -31,7 +32,7 @@ def strip_protocol(url) : def largest_version(content) : return sorted([t['version'] for t in content.package.releases('release')], - reverse=True, key=lambda v: map(int, v.split(".")))[0] + reverse=True, key=lambda v: LooseVersion(v))[0] def do_queue(Class, function, interable) : q = Queue() @@ -246,19 +247,23 @@ def _generate_aliases_helper(self, d) : self.counter += 1 self.display_counter("Scanning for Aliases") - def get_flash_algorthim_binary(self, device_name) : + def get_flash_algorthim_binary(self, device_name, all=False) : """Retrieve the flash algorithm file for a particular part. Assumes that both the PDSC and the PACK file associated with that part are in the cache. :param device_name: The exact name of a device + :param all: Return an iterator of all flash algos for this device :type device_name: str :return: A file-like object that, when read, is the ELF file that describes the flashing algorithm - :rtype: ZipExtFile + :return: A file-like object that, when read, is the ELF file that describes the flashing algorithm. + When "all" is set to True then an iterator for file-like objects is returned + :rtype: ZipExtFile or ZipExtFile iterator if all is True """ device = self.index[device_name] pack = self.pack_from_cache(device) - return pack.open(device['algorithm'].keys()[0]) + algo_itr = (pack.open(path) for path in device['algorithm'].keys()) + return algo_itr if all else algo_itr.next() def get_svd_file(self, device_name) : """Retrieve the flash algorithm file for a particular part. @@ -352,7 +357,7 @@ def aliases(self) : """ if not self._aliases : - with open(join(self.data_path, "aliases.json")) as i : + with open(LocalPackAliases) as i : self._aliases = load(i) return self._aliases diff --git a/tools/arm_pack_manager/aliases.json b/tools/arm_pack_manager/aliases.json index 49acef43f53..ea57e415814 100644 --- a/tools/arm_pack_manager/aliases.json +++ b/tools/arm_pack_manager/aliases.json @@ -1 +1 @@ -{"nRF51 PCA10028": "nRF51422_xxAC", "SAM4L-EK": "ATSAM4LC4C", "NuTiny-SDK-M451": "M453VG6AE", "STM32L073Z-EVAL": "STM32L073VZ", "TLE9879 EvalKit": "TLE9879QXA40", "STM32F401C-Discovery": "STM32F401VC", "NuTiny-SDK-M051": "M0516LDE", "MCB11C14": "LPC11C14FBD48/301", "XMC4500 Relax Kit": "XMC4500-F100x1024", "TWR-K22F120M": "MK22FN512xxx12", "MCB1200": "LPC1227FBD64/301", "DB-MAX71637": "MAX71637", "XMC 2Go": "XMC1100-Q024x0064", "FRDM-KL43Z": "MKL43Z256xxx4", "NUCLEO-L152RE": "STM32L152RE", "TWR-KV10Z32": "MKV10Z32xxx7", "EFM32ZG-STK3200": "EFM32ZG222F32", "FRDM-KW40Z": "MKW40Z160xxx4", "NuTiny-SDK-NM1200": "NM1200LBAE", "TWR-K70F120M": "MK70FN1M0xxx12", "MCBSTM32F400": "STM32F407IG", "SAML21-XPRO": "ATSAML21J18A", "STM32F030-Discovery": "STM32F030R8", "STM32756G-EVAL": "STM32F756NGHx", "Apollo EVK": "Apollo_512_BGA", "NuTiny-SDK-NUC505": "NUC505YO13Y", "NuTiny-SDK-M058S": "M058SSAN", "TRK-KEA8": "SKEAZN8xxx4", "MCB1700": "LPC1758", "V2M-MPS2": "CMSDK_CM7", "MCB54110": "LPC54114J256BD64", "Z32F1280100KITG": "Z32F12811ARS", "NuTiny-SDK-NUC472": "NUC472HI8AE", "EFM32GG-DK3750": "EFM32GG990F1024", "MCBSTM32F200": "STM32F207IG", "EVAL-ADuCM322EBZ": "ADuCM322", "MCBTMPM360": "TMPM362F10FG", "SN32F707B Starter Kit Rev1_0": "SN32F70*B", "NUCLEO-F446RE": "STM32F446RE", "NuTiny-SDK-NANO103": "NANO103SD3AE", "MCBNUC1xx": "NUC140VE3AN", "Z32F0640100KITG": "Z32F06410AES", "FRDM-KL02Z": "MKL02Z32xxx4", "Colibri-iMX7": "MCIMX7D", "SAM3S-EK": "ATSAM3S4C", "NuTiny-SDK-Mini51": "Mini54LDE", "NuTiny-SDK-NANO100BN": "NANO130KE3BN", "NuTiny-SDK-Mini58": "Mini58LDE", "XMC1400 Boot Kit": "XMC1402-Q040x0128", "TRK-KEA64": "SKEAZN64xxx2", "XMC1200 Boot Kit": "XMC1201-T038x0200", "N5 Starter Kit": "nRF51422_xxAA", "Core031C_Board": "MM32x031", "EFM32HG-SLSTK3400A": "EFM32HG322F64", "ADSP-CM419F EZ-BOARD M4": "ADSP-CM419F-BCZ_M4", "ADSP-CM419F EZ-BOARD M0": "ADSP-CM419F-BCZ_M0", "NuTiny-SDK-NUC200": "NUC220VE3AN", "FRDM-KE06Z": "MKE06Z128xxx4", "NUCLEO-F072RB": "STM32F072RB", "NuTiny-SDK-NUC100": "NUC100VE3DN", "FRDM-KL25Z": "MKL25Z128xxx4", "FRDM-K20D50M": "MK20DX128xxx5", "TS-R-IN32M3-CEC": "R-IN32M3-EC", "SAM4L-XPRO": "ATSAM4LC4C", "EVAL-ADuCM360MKZ": "ADuCM360", "nRF52 PCA10036": "nRF52832_xxAA", "TWR-KV11Z75M": "MKV11Z128xxx7", "LPCXpresso54102": "LPC54102J512BD64", "SF2_STARTER_KIT": "M2S010", "STM32L-Discovery": "STM32L152RB", "IMX7-PHYBOARD-ZETA": "MCIMX7D", "nRF51 PCA20006": "nRF51822_xxaa", "TWR-KV46F150M": "MKV46F256xxx16", "Koala EVM": "STM32F429II", "EFM32WG-STK3800": "EFM32WG990F256", "MCB1313": "LPC1313FBD48", "TWR-K65F180M": "MK65FN2M0xxx18", "EB_TMPM369FDFG": "TMPM369FDFG", "TS-R-IN32M3-EC": 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Purpose (CPU_45B)": "XMC4500-E144x1024", "EVAL-ADuCM320iQSPZ": "ADuCM320i", "SN32F100 Starter Kit": "SN32F10*", "SAM3U-EK": "ATSAM3U4E", "SAMG55-XPRO": "ATSAMG55J19", "FRDM-KL82Z": "MKL81Z128xxx7", "XMC1300 Boot Kit": "XMC1302-T038x0200", "LPC1788-32 Developers Kit": "LPC1788", "MCBTMPM395": "TMPM395FWAXBG", "STM32F072-Discovery": "STM32F072RB", "BMSKTOPASM369": "TMPM369FDFG", "uVision Simulator": "ARMCM0", "NuTiny-SDK-NANO100AN": "NANO100VD3AN", "TWR-K60D100M": "MK60DN512xxx10", "TWR-K20D72M": "MK20DX256xxx7", "nRF51 PCA10031": "nRF51422_xxAC", "XMC4700 Relax Kit": "XMC4700-F144x2048", "SK-FM3-176PMC-ETHERNET": "MB9BFD18T", "LPC4088-32 Developers Kit": "LPC4088FET208", "TLE984x Eval.Board": "TLE9844QX", "XMC4500 Relax Lite Kit": "XMC4500-F100x1024", "STM32L053-Discovery": "STM32L053C8", "LPCXpresso11U68": "LPC11U68JBD100", "XMC4400 CPU Board - General Purpose (CPU_44A)": "XMC4400-F100x512", "NUCLEO-F103RB": "STM32F103RB", "NuTiny-SDK-NUC029AE": "NUC029FAE", "NuTiny-SDK-NUC029AN": "NUC029TAN", "MCBSTM32E": "STM32F103ZG", "XMC4300 Relax Kit": "XMC4300-F100x256", "TWR-KL82Z72M": "MKL82Z128xxx7", "NuTiny-SDK-M0518": "M0518SD2AE", "NuTiny-SDK-M0519": "M0519VE3AE", "TWR-K64F120M": "MK64FN1M0xxx12", "MCB4300": "LPC4350", "XMC4200 CPU Board - Actuator (CPU_42A)": "XMC4200-F64x256"} \ No newline at end of file +{"nRF51 PCA10028": "nRF51422_xxAC", "SAM4L-EK": "ATSAM4LC4C", "NuTiny-SDK-M451": "M453VG6AE", "NuTiny-SDK-M0518": "M0518SD2AE", "STM32L073Z-EVAL": "STM32L073VZ", "TLE9879 EvalKit": "TLE9879QXA40", "STM32F401C-Discovery": "STM32F401VC", "NuTiny-SDK-M051": "M0516LDE", "MCB11C14": "LPC11C14FBD48/301", "XMC4500 Relax Kit": "XMC4500-F100x1024", "TWR-K22F120M": "MK22FN512xxx12", "MCB1200": "LPC1227FBD64/301", "DB-MAX71637": "MAX71637", "XMC 2Go": "XMC1100-Q024x0064", "NUCLEO-L152RE": "STM32L152RE", "TWR-KV10Z32": "MKV10Z32xxx7", "NuTiny-SDK-NUC029AE": "NUC029FAE", "FRDM-KW40Z": "MKW40Z160xxx4", "NuTiny-SDK-NM1200": "NM1200LBAE", "TWR-K70F120M": "MK70FN1M0xxx12", "STM32F769I-Discovery": "STM32F769NIHx", "TWR-KE18F": "MKE18F512xxx16", "MCBSTM32F400": "STM32F407IG", "LPCXpresso54608": "LPC54608J512BD208", "STM32F030-Discovery": "STM32F030R8", "Apollo EVK": "Apollo_512_BGA", "NuTiny-SDK-NUC505": "NUC505YO13Y", "NuTiny-SDK-M058S": "M058SSAN", "TRK-KEA8": "SKEAZN8xxx4", "MCB1313": "LPC1313FBD48", "NUCLEO-F446RE": "STM32F446RE", "V2M-MPS2": "CMSDK_CM7", "MCB54110": "LPC54114J256BD64", "Z32F1280100KITG": "Z32F12811ARS", "NuTiny-SDK-NUC472": "NUC472HI8AE", "EFM32GG-DK3750": "EFM32GG990F1024", "MCBSTM32F200": "STM32F207IG", "EVAL-ADuCM322EBZ": "ADuCM322", "FRDM-KL25Z": "MKL25Z128xxx4", "SN32F707B Starter Kit Rev1_0": "SN32F70*B", "NuTiny-SDK-NANO103": "NANO103SD3AE", "MCBNUC1xx": "NUC140VE3AN", "Z32F0640100KITG": "Z32F06410AES", "LPCXpresso54114": "LPC54114J256BD64", "Colibri-iMX7": "MCIMX7D", "ADuCM3029 EZ-BOARD": "ADuCM3029", "SAM3S-EK": "ATSAM3S4C", "SF2_DEV_KIT": "M2S050", "NuTiny-SDK-NANO100BN": "NANO130KE3BN", "NuTiny-SDK-Mini58": "Mini58LDE", "XMC1400 Boot Kit": "XMC1402-Q040x0128", "FRDM-K28F": "MK28FN2M0xxx15", "TRK-KEA64": "SKEAZN64xxx2", "XMC1200 Boot Kit": "XMC1201-T038x0200", "N5 Starter Kit": "nRF51422_xxAA", "Core031C_Board": "MM32x031", "EFM32HG-SLSTK3400A": "EFM32HG322F64", "ADSP-CM419F EZ-BOARD M4": "ADSP-CM419F-BCZ_M4", "XMC4700 Relax Kit": "XMC4700-F144x2048", "SAMG55-XPRO": "ATSAMG55J19", "NuTiny-SDK-NUC200": "NUC220VE3AN", "TWR-K60D100M": "MK60DN512xxx10", "FRDM-KE06Z": "MKE06Z128xxx4", "SF2_ADV_DEV_KIT": "M2S150", "NuTiny-SDK-NUC100": "NUC100VE3DN", "MCB1700": "LPC1758", "MCBTMPM360": "TMPM362F10FG", "FRDM-K20D50M": "MK20DX128xxx5", "STM32756G-EVAL": "STM32F756NGHx", "SAM4L-XPRO": "ATSAM4LC4C", "FRDM-KL43Z": "MKL43Z256xxx4", "nRF52 PCA10036": "nRF52832_xxAA", "TWR-KV11Z75M": "MKV11Z128xxx7", "LPCXpresso54102": "LPC54102J512BD64", "TWR-KM34Z50": "MKM34Z128xxx5", "STM32L-Discovery": "STM32L152RB", "XMC1100 Boot Kit": "XMC1100-T038x0064", "TWR-KV46F150M": "MKV46F256xxx16", "Koala EVM": "STM32F429II", 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"0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2410.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NUC100RD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.0.9.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S6110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}} \ No newline at end of file diff --git a/tools/check_release.json b/tools/check_release.json index f791bbef3c5..9db3fb6d458 100644 --- a/tools/check_release.json +++ b/tools/check_release.json @@ -11,6 +11,8 @@ "name" : "test_compile_mbed_dev", "lib" : "mbed-dev" } - ] + ], + "target_list" : [], + "ignore_list" : [] } diff --git a/tools/check_release.py b/tools/check_release.py index c3f1bc1bc3a..4d940fbb2db 100644 --- a/tools/check_release.py +++ b/tools/check_release.py @@ -31,7 +31,8 @@ # "name" : "test_compile_mbed_dev", # "lib" : "mbed-dev" # } -# ] +# ], +# "target_list" : [] #} # # The mbed_repo_path field should be changed to point to where your local @@ -41,6 +42,10 @@ # "test_compile_mbed_lib" and "test_compile_mbed_dev" # The lib field in each says which type of mbed 2 library the app contains. # These test apps MUST be available as repos in the user's online Mercurial area. +# The target_list allows the user to override the set of targets/platforms used +# for the compilation. +# E.g to just compile for 2 targets, K64F and K22F : +# "target_list" : ["K64F", "K22F"] # # Run the script from the mbed-os directory as follows: # > python tools/check_release.py @@ -51,8 +56,8 @@ # The lib files within the test apps are then updated to the corresponding version in # the associated lib itself. The test apps are then committed and pushed back to the users # fork. -# The test apps will then be compiled for all supported targets and a % result output at the -# end. +# The test apps will then be compiled for all supported targets and a % result output at +# the end. # # Uses the online compiler API at https://mbed.org/handbook/Compile-API # Based on the example from https://mbed.org/teams/mbed/code/mbed-API-helper/ @@ -76,21 +81,39 @@ def get_compilation_failure(messages): """ Reads the json formatted 'messages' and checks for compilation errors. - If there is a genuine compilation error then there should be a new message containing - a severity field = Error and an accompanying message with the compile error text. - Any other combination is considered an internal compile engine failure + If there is a genuine compilation error then there should be a new + message containing a severity field = Error and an accompanying message + with the compile error text. Any other combination is considered an + internal compile engine failure Args: messages - json formatted text returned by the online compiler API. Returns: - Either a string containing a compilation error or "Internal" to indicate an error with - the online IDE API itself. + Either "Error" or "Internal" to indicate an actual compilation error or an + internal IDE API fault. """ for m in messages: - if 'severity' in m and 'message' in m: - if m['severity'] == 'error': - return m['message'] + # Get message text if it exists + try: + message = m['message'] + message = message + "\n" + except KeyError: + # Skip this message as it has no 'message' field + continue + + # Get type of message text + try: + msg_type = m['type'] + except KeyError: + # Skip this message as it has no 'type' field + continue + + if msg_type == 'error' or msg_type == 'tool_error': + rel_log.error(message) + return "Error" + else: + rel_log.debug(message) return "Internal" @@ -111,48 +134,56 @@ def invoke_api(payload, url, auth, polls, begin="start/"): """ # send task to api - logging.debug(url + begin + "| data: " + str(payload)) + rel_log.debug(url + begin + "| data: " + str(payload)) r = requests.post(url + begin, data=payload, auth=auth) - logging.debug(r.request.body) + rel_log.debug(r.request.body) if r.status_code != 200: - logging.error("HTTP code %d reported.", r.status_code) + rel_log.error("HTTP code %d reported.", r.status_code) return False, "Internal" response = r.json() - logging.debug(response) + rel_log.debug(response) uuid = response['result']['data']['task_id'] - logging.debug("Task accepted and given ID: %s", uuid) + rel_log.debug("Task accepted and given ID: %s", uuid) result = False fail_type = None - # It currently seems to take the onlide IDE API ~30s to process the compile request and - # provide a response. Set the poll time to half that in case it does manage to compile - # quicker. + # It currently seems to take the onlide IDE API ~30s to process the compile + # request and provide a response. Set the poll time to half that in case it + # does manage to compile quicker. poll_delay = 15 - logging.debug("Running with a poll for response delay of: %ss", poll_delay) + rel_log.debug("Running with a poll for response delay of: %ss", poll_delay) # poll for output for check in range(polls): time.sleep(poll_delay) - r = requests.get(url + "output/%s" % uuid, auth=auth) - response = r.json() - if response['result']['data']['task_complete']: + + try: + r = requests.get(url + "output/%s" % uuid, auth=auth) + except ConnectionError: + return "Internal" + + response = r.json() + + data = response['result']['data'] + if data['task_complete']: # Task completed. Now determine the result. Should be one of : # 1) Successful compilation # 2) Failed compilation with an error message # 3) Internal failure of the online compiler - result = bool(response['result']['data']['compilation_success']) + result = bool(data['compilation_success']) if result: - logging.info("\t\tCompilation SUCCESSFUL\n") + rel_log.info("COMPILATION SUCCESSFUL\n") else: - # Did this fail due to a genuine compilation error or a failue of the api itself ? - logging.info("\t\tCompilation FAILURE\n") - fail_type = get_compilation_failure(response['result']['data']['new_messages']) + # Did this fail due to a genuine compilation error or a failue of + # the api itself ? + rel_log.info("COMPILATION FAILURE\n") + fail_type = get_compilation_failure(data['new_messages']) break else: - logging.info("\t\tCompilation FAILURE\n") + rel_log.info("COMPILATION FAILURE\n") if not result and fail_type == None: fail_type = "Internal" @@ -160,8 +191,10 @@ def invoke_api(payload, url, auth, polls, begin="start/"): return result, fail_type -def build_repo(target, program, user, pw, polls=25, url="https://developer.mbed.org/api/v2/tasks/compiler/"): - """ Wrapper for sending an API command request to the online IDE. Sends a build request. +def build_repo(target, program, user, pw, polls=25, + url="https://developer.mbed.org/api/v2/tasks/compiler/"): + """ Wrapper for sending an API command request to the online IDE. Sends a + build request. Args: target - Target to be built @@ -192,11 +225,12 @@ def run_cmd(command, exit_on_failure=False): Returns: result - True/False indicating the success/failure of the command """ - logging.debug('[Exec] %s', ' '.join(command)) + rel_log.debug('[Exec] %s', ' '.join(command)) return_code = subprocess.call(command, shell=True) if return_code: - logging.warning("The command '%s' failed with return code: %s", (' '.join(command), return_code)) + rel_log.warning("The command '%s' failed with return code: %s", + (' '.join(command), return_code)) if exit_on_failure: sys.exit(1) @@ -217,22 +251,24 @@ def run_cmd_with_output(command, exit_on_failure=False): result - True/False indicating the success/failure of the command output - The output of the command if it was successful, else empty string """ - logging.debug('[Exec] %s', ' '.join(command)) + rel_log.debug('[Exec] %s', ' '.join(command)) returncode = 0 output = "" try: output = subprocess.check_output(command, shell=True) except subprocess.CalledProcessError as e: - logging.warning("The command '%s' failed with return code: %s", (' '.join(command), e.returncode)) + rel_log.warning("The command '%s' failed with return code: %s", + (' '.join(command), e.returncode)) returncode = e.returncode if exit_on_failure: sys.exit(1) return returncode, output def upgrade_test_repo(test, user, library, ref, repo_path): - """ Upgrades a local version of a test repo to the latest version of its embedded library. - If the test repo is not present in the user area specified in the json config file, then - it will first be cloned. + """ Upgrades a local version of a test repo to the latest version of its + embedded library. + If the test repo is not present in the user area specified in the json + config file, then it will first be cloned. Args: test - Mercurial test repo name user - Mercurial user name @@ -243,7 +279,7 @@ def upgrade_test_repo(test, user, library, ref, repo_path): Returns: updated - True if library was updated, False otherwise """ - logging.info("Updating test repo: '%s' to SHA: %s", test, ref) + rel_log.info("Updating test repo: '%s' to SHA: %s", test, ref) cwd = os.getcwd() repo = "https://" + user + '@developer.mbed.org/users/' + user + '/code/' + test @@ -251,7 +287,7 @@ def upgrade_test_repo(test, user, library, ref, repo_path): # Clone the repo if it doesn't already exist path = abspath(repo_path + '/' + test) if not os.path.exists(path): - logging.info("Test repo doesn't exist, cloning...") + rel_log.info("Test repo doesn't exist, cloning...") os.chdir(abspath(repo_path)) clone_cmd = ['hg', 'clone', repo] run_cmd(clone_cmd, exit_on_failure=True) @@ -270,7 +306,7 @@ def upgrade_test_repo(test, user, library, ref, repo_path): os.rename(lib_file, bak_file) else: - logging.error("!! Error trying to backup lib file prior to updating.") + rel_log.error("Failure to backup lib file prior to updating.") return False # mbed 2 style lib file contains one line with the following format @@ -279,7 +315,8 @@ def upgrade_test_repo(test, user, library, ref, repo_path): lib_re = re.compile(exp) updated = False - # Scan through mbed-os.lib line by line, looking for lib version and update it if found + # Scan through mbed-os.lib line by line, looking for lib version and update + # it if found with open(bak_file, 'r') as ip, open(lib_file, 'w') as op: for line in ip: @@ -297,8 +334,9 @@ def upgrade_test_repo(test, user, library, ref, repo_path): # Setup the default commit message commit_message = '"Updating ' + library + ' to ' + ref + '"' - # Setup and run the commit command. Need to use the rawcommand in the hglib for this in order to pass - # the string value to the -m option. run_cmd using subprocess does not like this syntax. + # Setup and run the commit command. Need to use the rawcommand in the hglib + # for this in order to pass the string value to the -m option. run_cmd using + # subprocess does not like this syntax. try: client.rawcommand(['commit','-m '+commit_message, lib_file]) @@ -306,7 +344,7 @@ def upgrade_test_repo(test, user, library, ref, repo_path): run_cmd(cmd, exit_on_failure=True) except: - logging.info("Lib file already up to date and thus nothing to commit") + rel_log.info("Lib file already up to date and thus nothing to commit") os.chdir(cwd) return updated @@ -362,11 +400,21 @@ def get_latest_library_versions(repo_path): return mbed, mbed_dev +def log_results(lst, title): + if len(lst) == 0: + rel_log.info("%s - None", title) + else: + for entry in lst: + rel_log.info("%s - Test: %s, Target: %s", title, entry[0], entry[1]) + + if __name__ == '__main__': parser = argparse.ArgumentParser(description=__doc__, formatter_class=argparse.RawDescriptionHelpFormatter) - parser.add_argument('-l', '--log-level', help="Level for providing logging output", default='INFO') + parser.add_argument('-l', '--log-level', + help="Level for providing logging output", + default='INFO') args = parser.parse_args() default = getattr(logging, 'INFO') @@ -374,17 +422,28 @@ def get_latest_library_versions(repo_path): # Set logging level logging.basicConfig(level=level) + rel_log = logging.getLogger("check-release") # Read configuration data - json_data = json.load(open(os.path.join(os.path.dirname(__file__), "check_release.json"))) - - + with open(os.path.join(os.path.dirname(__file__), "check_release.json")) as config: + json_data = json.load(config) + supported_targets = [] - - # Get a list of the officially supported mbed-os 2 targets - for tgt in OFFICIAL_MBED_LIBRARY_BUILD: - supported_targets.append(tgt[0]) - + + if len(json_data["target_list"]) > 0: + # Compile user supplied subset of targets + supported_targets = json_data["target_list"] + else: + # Get a list of the officially supported mbed-os 2 targets + for tgt in OFFICIAL_MBED_LIBRARY_BUILD: + supported_targets.append(tgt[0]) + + ignore_list = [] + + if len(json_data["ignore_list"]) > 0: + # List of tuples of (test, target) to be ignored in this test + ignore_list = json_data["ignore_list"] + config = json_data["config"] test_list = json_data["test_list"] repo_path = config["mbed_repo_path"] @@ -405,44 +464,67 @@ def get_latest_library_versions(repo_path): mbed, mbed_dev = get_latest_library_versions(repo_path) if not mbed or not mbed_dev: - logging.error("Could not obtain latest versions of library files!!") + rel_log.error("Could not obtain latest versions of library files!!") exit(1) - logging.info("Latest mbed lib version = %s", mbed) - logging.info("Latest mbed-dev lib version = %s", mbed_dev) + rel_log.info("Latest mbed lib version = %s", mbed) + rel_log.info("Latest mbed-dev lib version = %s", mbed_dev) # First update test repos to latest versions of their embedded libraries for test in test_list: tests.append(test['name']) - upgrade_test_repo(test['name'], user, test['lib'], mbed if test['lib'] == "mbed" else mbed_dev, repo_path) - - total = len(supported_targets)*len(tests) + upgrade_test_repo(test['name'], user, test['lib'], + mbed if test['lib'] == "mbed" else mbed_dev, + repo_path) + + total = len(supported_targets) * len(tests) + current = 0 retries = 10 passes = 0 + failures = [] + skipped = [] # Compile each test for each supported target for test in tests: - logging.info("Test compiling program: %s\n", test) for target in supported_targets: + + combo = [test, target] + + if combo in ignore_list: + rel_log.info("SKIPPING TEST: %s, TARGET: %s", test, target) + total -= 1 + skipped.append(combo) + continue + + current += 1 for retry in range(0, retries): - logging.info("\tCompiling target: %s , attempt %u\n", target, retry) + rel_log.info("COMPILING (%d/%d): TEST %s, TARGET: %s , attempt %u\n", current, total, test, target, retry) result, mesg = build_repo(target, test, user, password) if not result: if mesg == 'Internal': # Internal compiler error thus retry continue else: - # Genuine compilation error, thus print it out - logging.error("\t\tError: %s\n", mesg) + # Actual error thus move on to next compilation + failures.append(combo) + break passes += (int)(result) break else: - logging.error("\t\tProgram/Target compilation failed due to internal errors. Removing from considered list!\n") + rel_log.error("Compilation failed due to internal errors.") + rel_log.error("Skipping test/target combination.") total -= 1 + skipped.append(combo) + rel_log.info(" SUMMARY OF COMPILATION RESULTS") + rel_log.info(" ------------------------------") + rel_log.info(" NUMBER OF TEST APPS: %d, NUMBER OF TARGETS: %d", + len(tests), len(supported_targets)) + log_results(failures, " FAILED") + log_results(skipped, " SKIPPED") + # Output a % pass rate, indicate a failure if not 100% successful - pass_rate = int(passes/total) * 100 - logging.info("Pass percentage = %d\n", pass_rate) + pass_rate = (float(passes) / float(total)) * 100.0 + rel_log.info(" PASS RATE %.1f %%\n", pass_rate) sys.exit(not (pass_rate == 100)) - \ No newline at end of file diff --git a/tools/export/e2studio/rz_a1h_cproject.tmpl b/tools/export/e2studio/rz_a1h_cproject.tmpl index 85dcd994245..d54ad2f337b 100644 --- a/tools/export/e2studio/rz_a1h_cproject.tmpl +++ b/tools/export/e2studio/rz_a1h_cproject.tmpl @@ -76,6 +76,9 @@ {% endfor %} + @@ -92,6 +95,9 @@ diff --git a/tools/export/gnuarmeclipse/__init__.py b/tools/export/gnuarmeclipse/__init__.py index 9f7eb4e72db..30b4b6eb1ec 100644 --- a/tools/export/gnuarmeclipse/__init__.py +++ b/tools/export/gnuarmeclipse/__init__.py @@ -207,7 +207,7 @@ def generate(self): src_paths = [''] target_name = self.toolchain.target.name toolchain = prepare_toolchain( - src_paths, target_name, self.TOOLCHAIN, build_profile=profile_toolchain) + src_paths, "", target_name, self.TOOLCHAIN, build_profile=profile_toolchain) # Hack to fill in build_dir toolchain.build_dir = self.toolchain.build_dir diff --git a/tools/project_api.py b/tools/project_api.py index 728f61ee4f5..6373bd6beec 100644 --- a/tools/project_api.py +++ b/tools/project_api.py @@ -187,7 +187,7 @@ def export_project(src_paths, export_path, target, ide, libraries_paths=None, # Pass all params to the unified prepare_resources() toolchain = prepare_toolchain( - paths, export_path, target, toolchain_name, macros=macros, jobs=jobs, + paths, "", target, toolchain_name, macros=macros, jobs=jobs, notify=notify, silent=silent, verbose=verbose, extra_verbose=extra_verbose, config=config, build_profile=build_profile) # The first path will give the name to the library diff --git a/tools/test/toolchains/api.py b/tools/test/toolchains/api.py index 31ced9d0c9b..01a684fae8a 100644 --- a/tools/test/toolchains/api.py +++ b/tools/test/toolchains/api.py @@ -4,15 +4,15 @@ from string import printable from copy import deepcopy from mock import MagicMock, patch -from hypothesis import given -from hypothesis.strategies import text, lists, fixed_dictionaries +from hypothesis import given, settings +from hypothesis.strategies import text, lists, fixed_dictionaries, booleans ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", "..")) sys.path.insert(0, ROOT) from tools.toolchains import TOOLCHAIN_CLASSES, LEGACY_TOOLCHAIN_NAMES,\ - Resources + Resources, TOOLCHAIN_PATHS from tools.targets import TARGET_MAP def test_instantiation(): @@ -125,3 +125,21 @@ def test_detect_duplicates(filenames): assert "dupe.s" in notification["message"] assert "dupe.c" in notification["message"] assert "dupe.cpp" in notification["message"] + +@given(text(alphabet=ALPHABET + ["/"], min_size=1)) +@given(booleans()) +@given(booleans()) +@settings(max_examples=20) +def test_path_specified_gcc(gcc_loc, exists_at_loc, exists_in_path): + with patch('tools.toolchains.gcc.exists') as _exists: + with patch('tools.toolchains.gcc.find_executable') as _find: + _exists.return_value = exists_at_loc + _find.return_value = exists_in_path + TOOLCHAIN_PATHS['GCC_ARM'] = gcc_loc + toolchain_class = TOOLCHAIN_CLASSES["GCC_ARM"] + found_p = toolchain_class.check_executable() + assert found_p == (exists_at_loc or exists_in_path) + if exists_at_loc: + assert TOOLCHAIN_PATHS['GCC_ARM'] == gcc_loc + elif exists_in_path: + assert TOOLCHAIN_PATHS['GCC_ARM'] == '' diff --git a/tools/toolchains/gcc.py b/tools/toolchains/gcc.py index 1211d2aa27b..9b6cbd8b15c 100644 --- a/tools/toolchains/gcc.py +++ b/tools/toolchains/gcc.py @@ -15,7 +15,8 @@ limitations under the License. """ import re -from os.path import join, basename, splitext, dirname +from os.path import join, basename, splitext, dirname, exists +from distutils.spawn import find_executable from tools.toolchains import mbedToolchain, TOOLCHAIN_PATHS from tools.hooks import hook_tool @@ -286,7 +287,15 @@ def check_executable(): """Returns True if the executable (arm-none-eabi-gcc) location specified by the user exists OR the executable can be found on the PATH. Returns False otherwise.""" - return mbedToolchain.generic_check_executable("GCC_ARM", 'arm-none-eabi-gcc', 1) + if not TOOLCHAIN_PATHS['GCC_ARM'] or not exists(TOOLCHAIN_PATHS['GCC_ARM']): + if find_executable('arm-none-eabi-gcc'): + TOOLCHAIN_PATHS['GCC_ARM'] = '' + return True + else: + return False + else: + exec_name = join(TOOLCHAIN_PATHS['GCC_ARM'], 'arm-none-eabi-gcc') + return exists(exec_name) or exists(exec_name + '.exe') class GCC_ARM(GCC): pass